4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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14 * notice, this list of conditions and the following disclaimer in
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
42 #include <rte_ether.h>
43 #include <rte_ethdev.h>
45 #include <rte_memzone.h>
46 #include <rte_malloc.h>
52 #include "i40e_logs.h"
53 #include "i40e/i40e_type.h"
54 #include "i40e_ethdev.h"
55 #include "i40e_rxtx.h"
57 #define I40E_FDIR_MZ_NAME "FDIR_MEMZONE"
59 #define IPV6_ADDR_LEN 16
62 #define I40E_FDIR_PKT_LEN 512
63 #define I40E_FDIR_IP_DEFAULT_LEN 420
64 #define I40E_FDIR_IP_DEFAULT_TTL 0x40
65 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL 0x45
66 #define I40E_FDIR_TCP_DEFAULT_DATAOFF 0x50
67 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW 0x60300000
68 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS 0xFF
69 #define I40E_FDIR_IPv6_PAYLOAD_LEN 380
70 #define I40E_FDIR_UDP_DEFAULT_LEN 400
72 /* Wait count and interval for fdir filter programming */
73 #define I40E_FDIR_WAIT_COUNT 10
74 #define I40E_FDIR_WAIT_INTERVAL_US 1000
76 /* Wait count and interval for fdir filter flush */
77 #define I40E_FDIR_FLUSH_RETRY 50
78 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
80 #define I40E_COUNTER_PF 2
81 /* Statistic counter index for one pf */
82 #define I40E_COUNTER_INDEX_FDIR(pf_id) (0 + (pf_id) * I40E_COUNTER_PF)
83 #define I40E_MAX_FLX_SOURCE_OFF 480
84 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
86 #define NONUSE_FLX_PIT_DEST_OFF 63
87 #define NONUSE_FLX_PIT_FSIZE 1
88 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
89 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
90 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
91 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
92 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
93 ((((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR) << \
94 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
95 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
97 #define I40E_FDIR_FLOW_TYPES ( \
98 (1 << RTE_ETH_FLOW_TYPE_UDPV4) | \
99 (1 << RTE_ETH_FLOW_TYPE_TCPV4) | \
100 (1 << RTE_ETH_FLOW_TYPE_SCTPV4) | \
101 (1 << RTE_ETH_FLOW_TYPE_IPV4_OTHER) | \
102 (1 << RTE_ETH_FLOW_TYPE_FRAG_IPV4) | \
103 (1 << RTE_ETH_FLOW_TYPE_UDPV6) | \
104 (1 << RTE_ETH_FLOW_TYPE_TCPV6) | \
105 (1 << RTE_ETH_FLOW_TYPE_SCTPV6) | \
106 (1 << RTE_ETH_FLOW_TYPE_IPV6_OTHER) | \
107 (1 << RTE_ETH_FLOW_TYPE_FRAG_IPV6))
109 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
111 static int i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq);
112 static int i40e_check_fdir_flex_conf(
113 const struct rte_eth_fdir_flex_conf *conf);
114 static void i40e_set_flx_pld_cfg(struct i40e_pf *pf,
115 const struct rte_eth_flex_payload_cfg *cfg);
116 static void i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
117 enum i40e_filter_pctype pctype,
118 const struct rte_eth_fdir_flex_mask *mask_cfg);
119 static int i40e_fdir_construct_pkt(struct i40e_pf *pf,
120 const struct rte_eth_fdir_input *fdir_input,
121 unsigned char *raw_pkt);
122 static int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
123 const struct rte_eth_fdir_filter *filter,
125 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
126 enum i40e_filter_pctype pctype,
127 const struct rte_eth_fdir_filter *filter,
129 static int i40e_fdir_flush(struct rte_eth_dev *dev);
130 static void i40e_fdir_info_get(struct rte_eth_dev *dev,
131 struct rte_eth_fdir_info *fdir);
132 static void i40e_fdir_stats_get(struct rte_eth_dev *dev,
133 struct rte_eth_fdir_stats *stat);
136 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
138 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
139 struct i40e_hmc_obj_rxq rx_ctx;
140 int err = I40E_SUCCESS;
142 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
143 /* Init the RX queue in hardware */
144 rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
146 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
147 rx_ctx.qlen = rxq->nb_rx_desc;
148 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
151 rx_ctx.dtype = i40e_header_split_none;
152 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
153 rx_ctx.rxmax = ETHER_MAX_LEN;
154 rx_ctx.tphrdesc_ena = 1;
155 rx_ctx.tphwdesc_ena = 1;
156 rx_ctx.tphdata_ena = 1;
157 rx_ctx.tphhead_ena = 1;
158 rx_ctx.lrxqthresh = 2;
164 err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
165 if (err != I40E_SUCCESS) {
166 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
169 err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
170 if (err != I40E_SUCCESS) {
171 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
174 rxq->qrx_tail = hw->hw_addr +
175 I40E_QRX_TAIL(rxq->vsi->base_queue);
178 /* Init the RX tail regieter. */
179 I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
180 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
186 * i40e_fdir_setup - reserve and initialize the Flow Director resources
187 * @pf: board private structure
190 i40e_fdir_setup(struct i40e_pf *pf)
192 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
193 struct i40e_vsi *vsi;
194 int err = I40E_SUCCESS;
195 char z_name[RTE_MEMZONE_NAMESIZE];
196 const struct rte_memzone *mz = NULL;
197 struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
199 if ((pf->flags & I40E_FLAG_FDIR) == 0) {
200 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
201 return I40E_NOT_SUPPORTED;
204 PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
205 " num_filters_best_effort = %u.",
206 hw->func_caps.fd_filters_guaranteed,
207 hw->func_caps.fd_filters_best_effort);
209 vsi = pf->fdir.fdir_vsi;
211 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
214 /* make new FDIR VSI */
215 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
217 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
218 return I40E_ERR_NO_AVAILABLE_VSI;
220 pf->fdir.fdir_vsi = vsi;
222 /*Fdir tx queue setup*/
223 err = i40e_fdir_setup_tx_resources(pf);
225 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
229 /*Fdir rx queue setup*/
230 err = i40e_fdir_setup_rx_resources(pf);
232 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
236 err = i40e_tx_queue_init(pf->fdir.txq);
238 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
242 /* need switch on before dev start*/
243 err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
245 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
249 /* Init the rx queue in hardware */
250 err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
252 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
256 /* switch on rx queue */
257 err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
259 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
263 /* reserve memory for the fdir programming packet */
264 snprintf(z_name, sizeof(z_name), "%s_%s_%d",
265 eth_dev->driver->pci_drv.name,
267 eth_dev->data->port_id);
268 mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
270 PMD_DRV_LOG(ERR, "Cannot init memzone for "
271 "flow director program packet.");
272 err = I40E_ERR_NO_MEMORY;
275 pf->fdir.prg_pkt = mz->addr;
276 #ifdef RTE_LIBRTE_XEN_DOM0
277 pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
279 pf->fdir.dma_addr = (uint64_t)mz->phys_addr;
281 pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
282 PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
287 i40e_dev_rx_queue_release(pf->fdir.rxq);
290 i40e_dev_tx_queue_release(pf->fdir.txq);
293 i40e_vsi_release(vsi);
294 pf->fdir.fdir_vsi = NULL;
299 * i40e_fdir_teardown - release the Flow Director resources
300 * @pf: board private structure
303 i40e_fdir_teardown(struct i40e_pf *pf)
305 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
306 struct i40e_vsi *vsi;
308 vsi = pf->fdir.fdir_vsi;
311 i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
312 i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
313 i40e_dev_rx_queue_release(pf->fdir.rxq);
315 i40e_dev_tx_queue_release(pf->fdir.txq);
317 i40e_vsi_release(vsi);
318 pf->fdir.fdir_vsi = NULL;
321 /* check whether the flow director table in empty */
323 i40e_fdir_empty(struct i40e_hw *hw)
325 uint32_t guarant_cnt, best_cnt;
327 guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
328 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
329 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
330 best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
331 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
332 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
333 if (best_cnt + guarant_cnt > 0)
340 * Initialize the configuration about bytes stream extracted as flexible payload
344 i40e_init_flx_pld(struct i40e_pf *pf)
346 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
351 * Define the bytes stream extracted as flexible payload in
352 * field vector. By default, select 8 words from the beginning
353 * of payload as flexible payload.
355 for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
356 index = i * I40E_MAX_FLXPLD_FIED;
357 pf->fdir.flex_set[index].src_offset = 0;
358 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
359 pf->fdir.flex_set[index].dst_offset = 0;
360 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
362 I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
364 I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
367 /* initialize the masks */
368 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
369 pctype <= I40E_FILTER_PCTYPE_FRAG_IPV6; pctype++) {
370 pf->fdir.flex_mask[pctype].word_mask = 0;
371 I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
372 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
373 pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
374 pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
375 I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
380 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
382 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
383 if ((flex_pit2).src_offset < \
384 (flex_pit1).src_offset + (flex_pit1).size) { \
385 PMD_DRV_LOG(ERR, "src_offset should be not" \
386 " less than than previous offset" \
387 " + previous FSIZE."); \
393 * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
394 * and the flex_pit will be sorted by it's src_offset value
396 static inline uint16_t
397 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
398 struct i40e_fdir_flex_pit *flex_pit)
400 uint16_t src_tmp, size, num = 0;
401 uint16_t i, k, j = 0;
403 while (j < I40E_FDIR_MAX_FLEX_LEN) {
405 for (; j < I40E_FDIR_MAX_FLEX_LEN; j++) {
406 if (src_offset[j + 1] == src_offset[j] + 1)
409 src_tmp = src_offset[j] + 1 - size;
410 /* the flex_pit need to be sort by scr_offset */
411 for (i = 0; i < num; i++) {
412 if (src_tmp < flex_pit[i].src_offset)
415 /* if insert required, move backward */
416 for (k = num; k > i; k--)
417 flex_pit[k] = flex_pit[k - 1];
419 flex_pit[i].dst_offset = j + 1 - size;
420 flex_pit[i].src_offset = src_tmp;
421 flex_pit[i].size = size;
431 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
433 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
435 struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
438 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
439 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
440 PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
445 memset(flex_pit, 0, sizeof(flex_pit));
446 num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
447 if (num > I40E_MAX_FLXPLD_FIED) {
448 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
451 for (i = 0; i < num; i++) {
452 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
453 flex_pit[i].src_offset & 0x01) {
454 PMD_DRV_LOG(ERR, "flexpayload should be measured"
459 I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
465 * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
466 * arguments are valid
469 i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
471 const struct rte_eth_flex_payload_cfg *flex_cfg;
472 const struct rte_eth_fdir_flex_mask *flex_mask;
479 PMD_DRV_LOG(INFO, "NULL pointer.");
482 /* check flexible payload setting configuration */
483 if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
484 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
487 for (i = 0; i < conf->nb_payloads; i++) {
488 flex_cfg = &conf->flex_set[i];
489 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
490 PMD_DRV_LOG(ERR, "invalid payload type.");
493 ret = i40e_check_fdir_flex_payload(flex_cfg);
495 PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
500 /* check flex mask setting configuration */
501 if (conf->nb_flexmasks > RTE_ETH_FLOW_TYPE_FRAG_IPV6) {
502 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
505 for (i = 0; i < conf->nb_flexmasks; i++) {
506 flex_mask = &conf->flex_mask[i];
507 if (!I40E_VALID_FLOW_TYPE(flex_mask->flow_type)) {
508 PMD_DRV_LOG(WARNING, "invalid flow type.");
512 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
513 mask_tmp = I40E_WORD(flex_mask->mask[j],
514 flex_mask->mask[j + 1]);
515 if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
517 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
518 PMD_DRV_LOG(ERR, " exceed maximal"
519 " number of bitmasks.");
529 * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
530 * @pf: board private structure
531 * @cfg: the rule how bytes stream is extracted as flexible payload
534 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
535 const struct rte_eth_flex_payload_cfg *cfg)
537 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
538 struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
540 uint16_t num, min_next_off; /* in words */
541 uint8_t field_idx = 0;
542 uint8_t layer_idx = 0;
545 if (cfg->type == RTE_ETH_L2_PAYLOAD)
546 layer_idx = I40E_FLXPLD_L2_IDX;
547 else if (cfg->type == RTE_ETH_L3_PAYLOAD)
548 layer_idx = I40E_FLXPLD_L3_IDX;
549 else if (cfg->type == RTE_ETH_L4_PAYLOAD)
550 layer_idx = I40E_FLXPLD_L4_IDX;
552 memset(flex_pit, 0, sizeof(flex_pit));
553 num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
555 for (i = 0; i < num; i++) {
556 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
557 /* record the info in fdir structure */
558 pf->fdir.flex_set[field_idx].src_offset =
559 flex_pit[i].src_offset / sizeof(uint16_t);
560 pf->fdir.flex_set[field_idx].size =
561 flex_pit[i].size / sizeof(uint16_t);
562 pf->fdir.flex_set[field_idx].dst_offset =
563 flex_pit[i].dst_offset / sizeof(uint16_t);
564 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
565 pf->fdir.flex_set[field_idx].size,
566 pf->fdir.flex_set[field_idx].dst_offset);
568 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
570 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
571 pf->fdir.flex_set[field_idx].size;
573 for (; i < I40E_MAX_FLXPLD_FIED; i++) {
574 /* set the non-used register obeying register's constrain */
575 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
576 NONUSE_FLX_PIT_DEST_OFF);
578 I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
585 * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
586 * @pf: board private structure
587 * @pctype: packet classify type
588 * @flex_masks: mask for flexible payload
591 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
592 enum i40e_filter_pctype pctype,
593 const struct rte_eth_fdir_flex_mask *mask_cfg)
595 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
596 struct i40e_fdir_flex_mask *flex_mask;
597 uint32_t flxinset, fd_mask;
599 uint8_t i, nb_bitmask = 0;
601 flex_mask = &pf->fdir.flex_mask[pctype];
602 memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
603 for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
604 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
605 if (mask_tmp != 0x0) {
606 flex_mask->word_mask |=
607 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
608 if (mask_tmp != UINT16_MAX) {
610 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
611 flex_mask->bitmask[nb_bitmask].offset =
612 i / sizeof(uint16_t);
617 /* write mask to hw */
618 flxinset = (flex_mask->word_mask <<
619 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
620 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
621 I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
623 for (i = 0; i < nb_bitmask; i++) {
624 fd_mask = (flex_mask->bitmask[i].mask <<
625 I40E_PRTQF_FD_MSK_MASK_SHIFT) &
626 I40E_PRTQF_FD_MSK_MASK_MASK;
627 fd_mask |= ((flex_mask->bitmask[i].offset +
628 I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
629 I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
630 I40E_PRTQF_FD_MSK_OFFSET_MASK;
631 I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
636 * Configure flow director related setting
639 i40e_fdir_configure(struct rte_eth_dev *dev)
641 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
642 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
643 struct rte_eth_fdir_flex_conf *conf;
644 enum i40e_filter_pctype pctype;
650 * configuration need to be done before
651 * flow director filters are added
652 * If filters exist, flush them.
654 if (i40e_fdir_empty(hw) < 0) {
655 ret = i40e_fdir_flush(dev);
657 PMD_DRV_LOG(ERR, "failed to flush fdir table.");
662 /* enable FDIR filter */
663 val = I40E_READ_REG(hw, I40E_PFQF_CTL_0);
664 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
665 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val);
667 i40e_init_flx_pld(pf); /* set flex config to default value */
669 conf = &dev->data->dev_conf.fdir_conf.flex_conf;
670 ret = i40e_check_fdir_flex_conf(conf);
672 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
675 /* configure flex payload */
676 for (i = 0; i < conf->nb_payloads; i++)
677 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
678 /* configure flex mask*/
679 for (i = 0; i < conf->nb_flexmasks; i++) {
680 pctype = i40e_flowtype_to_pctype(
681 conf->flex_mask[i].flow_type);
682 i40e_set_flex_mask_on_pctype(pf,
684 &conf->flex_mask[i]);
691 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
692 unsigned char *raw_pkt)
694 struct ether_hdr *ether = (struct ether_hdr *)raw_pkt;
696 struct ipv6_hdr *ip6;
697 static const uint8_t next_proto[] = {
698 [RTE_ETH_FLOW_TYPE_UDPV4] = IPPROTO_UDP,
699 [RTE_ETH_FLOW_TYPE_TCPV4] = IPPROTO_TCP,
700 [RTE_ETH_FLOW_TYPE_SCTPV4] = IPPROTO_SCTP,
701 [RTE_ETH_FLOW_TYPE_IPV4_OTHER] = IPPROTO_IP,
702 [RTE_ETH_FLOW_TYPE_FRAG_IPV4] = IPPROTO_IP,
703 [RTE_ETH_FLOW_TYPE_UDPV6] = IPPROTO_UDP,
704 [RTE_ETH_FLOW_TYPE_TCPV6] = IPPROTO_TCP,
705 [RTE_ETH_FLOW_TYPE_SCTPV6] = IPPROTO_SCTP,
706 [RTE_ETH_FLOW_TYPE_IPV6_OTHER] = IPPROTO_NONE,
707 [RTE_ETH_FLOW_TYPE_FRAG_IPV6] = IPPROTO_NONE,
710 switch (fdir_input->flow_type) {
711 case RTE_ETH_FLOW_TYPE_UDPV4:
712 case RTE_ETH_FLOW_TYPE_TCPV4:
713 case RTE_ETH_FLOW_TYPE_SCTPV4:
714 case RTE_ETH_FLOW_TYPE_IPV4_OTHER:
715 case RTE_ETH_FLOW_TYPE_FRAG_IPV4:
716 ip = (struct ipv4_hdr *)(raw_pkt + sizeof(struct ether_hdr));
718 ether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
719 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
720 /* set len to by default */
721 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
722 ip->time_to_live = I40E_FDIR_IP_DEFAULT_TTL;
724 * The source and destination fields in the transmitted packet
725 * need to be presented in a reversed order with respect
726 * to the expected received packets.
728 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
729 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
730 ip->next_proto_id = next_proto[fdir_input->flow_type];
732 case RTE_ETH_FLOW_TYPE_UDPV6:
733 case RTE_ETH_FLOW_TYPE_TCPV6:
734 case RTE_ETH_FLOW_TYPE_SCTPV6:
735 case RTE_ETH_FLOW_TYPE_IPV6_OTHER:
736 case RTE_ETH_FLOW_TYPE_FRAG_IPV6:
737 ip6 = (struct ipv6_hdr *)(raw_pkt + sizeof(struct ether_hdr));
739 ether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
741 rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW);
743 rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
744 ip6->hop_limits = I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
747 * The source and destination fields in the transmitted packet
748 * need to be presented in a reversed order with respect
749 * to the expected received packets.
751 rte_memcpy(&(ip6->src_addr),
752 &(fdir_input->flow.ipv6_flow.dst_ip),
754 rte_memcpy(&(ip6->dst_addr),
755 &(fdir_input->flow.ipv6_flow.src_ip),
757 ip6->proto = next_proto[fdir_input->flow_type];
760 PMD_DRV_LOG(ERR, "unknown flow type %u.",
761 fdir_input->flow_type);
768 * i40e_fdir_construct_pkt - construct packet based on fields in input
769 * @pf: board private structure
770 * @fdir_input: input set of the flow director entry
771 * @raw_pkt: a packet to be constructed
774 i40e_fdir_construct_pkt(struct i40e_pf *pf,
775 const struct rte_eth_fdir_input *fdir_input,
776 unsigned char *raw_pkt)
778 unsigned char *payload, *ptr;
781 struct sctp_hdr *sctp;
782 uint8_t size, dst = 0;
783 uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
785 /* fill the ethernet and IP head */
786 i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt);
788 /* fill the L4 head */
789 switch (fdir_input->flow_type) {
790 case RTE_ETH_FLOW_TYPE_UDPV4:
791 udp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
792 sizeof(struct ipv4_hdr));
793 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
795 * The source and destination fields in the transmitted packet
796 * need to be presented in a reversed order with respect
797 * to the expected received packets.
799 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
800 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
801 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
804 case RTE_ETH_FLOW_TYPE_TCPV4:
805 tcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
806 sizeof(struct ipv4_hdr));
807 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
809 * The source and destination fields in the transmitted packet
810 * need to be presented in a reversed order with respect
811 * to the expected received packets.
813 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
814 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
815 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
818 case RTE_ETH_FLOW_TYPE_SCTPV4:
819 sctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
820 sizeof(struct ipv4_hdr));
821 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
822 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
825 case RTE_ETH_FLOW_TYPE_IPV4_OTHER:
826 case RTE_ETH_FLOW_TYPE_FRAG_IPV4:
827 payload = raw_pkt + sizeof(struct ether_hdr) +
828 sizeof(struct ipv4_hdr);
829 set_idx = I40E_FLXPLD_L3_IDX;
832 case RTE_ETH_FLOW_TYPE_UDPV6:
833 udp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
834 sizeof(struct ipv6_hdr));
835 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
837 * The source and destination fields in the transmitted packet
838 * need to be presented in a reversed order with respect
839 * to the expected received packets.
841 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
842 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
843 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
846 case RTE_ETH_FLOW_TYPE_TCPV6:
847 tcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
848 sizeof(struct ipv6_hdr));
849 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
851 * The source and destination fields in the transmitted packet
852 * need to be presented in a reversed order with respect
853 * to the expected received packets.
855 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
856 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
857 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
860 case RTE_ETH_FLOW_TYPE_SCTPV6:
861 sctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
862 sizeof(struct ipv6_hdr));
863 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
864 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
867 case RTE_ETH_FLOW_TYPE_IPV6_OTHER:
868 case RTE_ETH_FLOW_TYPE_FRAG_IPV6:
869 payload = raw_pkt + sizeof(struct ether_hdr) +
870 sizeof(struct ipv6_hdr);
871 set_idx = I40E_FLXPLD_L3_IDX;
874 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
878 /* fill the flexbytes to payload */
879 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
880 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
881 size = pf->fdir.flex_set[pit_idx].size;
884 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
886 pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
887 (void)rte_memcpy(ptr,
888 &fdir_input->flow_ext.flexbytes[dst],
889 size * sizeof(uint16_t));
895 /* Construct the tx flags */
896 static inline uint64_t
897 i40e_build_ctob(uint32_t td_cmd,
902 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
903 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
904 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
905 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
906 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
910 * check the programming status descriptor in rx queue.
911 * done after Programming Flow Director is programmed on
915 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
917 volatile union i40e_rx_desc *rxdp;
924 rxdp = &rxq->rx_ring[rxq->rx_tail];
925 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
926 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
927 >> I40E_RXD_QW1_STATUS_SHIFT;
929 if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
930 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
931 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
932 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
934 if (len == I40E_RX_PROG_STATUS_DESC_LENGTH &&
935 id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
937 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
938 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
940 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
941 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
942 " (FD_ID %u): programming status"
944 rxdp->wb.qword0.hi_dword.fd_id);
946 } else if (error == (0x1 <<
947 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
948 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
949 " (FD_ID %u): programming status"
951 rxdp->wb.qword0.hi_dword.fd_id);
954 PMD_DRV_LOG(ERR, "invalid programming status"
955 " reported, error = %u.", error);
957 PMD_DRV_LOG(ERR, "unknown programming status"
958 " reported, len = %d, id = %u.", len, id);
959 rxdp->wb.qword1.status_error_len = 0;
961 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
968 * i40e_add_del_fdir_filter - add or remove a flow director filter.
969 * @pf: board private structure
970 * @filter: fdir filter entry
971 * @add: 0 - delete, 1 - add
974 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
975 const struct rte_eth_fdir_filter *filter,
978 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
979 unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
980 enum i40e_filter_pctype pctype;
983 if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
984 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
985 " check the mode in fdir_conf.");
989 if (!I40E_VALID_FLOW_TYPE(filter->input.flow_type)) {
990 PMD_DRV_LOG(ERR, "invalid flow_type input.");
993 if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
994 PMD_DRV_LOG(ERR, "Invalid queue ID");
998 memset(pkt, 0, I40E_FDIR_PKT_LEN);
1000 ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1002 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1005 pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
1006 ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1008 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1016 * i40e_fdir_filter_programming - Program a flow director filter rule.
1017 * Is done by Flow Director Programming Descriptor followed by packet
1018 * structure that contains the filter fields need to match.
1019 * @pf: board private structure
1021 * @filter: fdir filter entry
1022 * @add: 0 - delelet, 1 - add
1025 i40e_fdir_filter_programming(struct i40e_pf *pf,
1026 enum i40e_filter_pctype pctype,
1027 const struct rte_eth_fdir_filter *filter,
1030 struct i40e_tx_queue *txq = pf->fdir.txq;
1031 struct i40e_rx_queue *rxq = pf->fdir.rxq;
1032 const struct rte_eth_fdir_action *fdir_action = &filter->action;
1033 volatile struct i40e_tx_desc *txdp;
1034 volatile struct i40e_filter_program_desc *fdirdp;
1039 PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1040 fdirdp = (volatile struct i40e_filter_program_desc *)
1041 (&(txq->tx_ring[txq->tx_tail]));
1043 fdirdp->qindex_flex_ptype_vsi =
1044 rte_cpu_to_le_32((fdir_action->rx_queue <<
1045 I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1046 I40E_TXD_FLTR_QW0_QINDEX_MASK);
1048 fdirdp->qindex_flex_ptype_vsi |=
1049 rte_cpu_to_le_32((fdir_action->flex_off <<
1050 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1051 I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1053 fdirdp->qindex_flex_ptype_vsi |=
1054 rte_cpu_to_le_32((pctype <<
1055 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1056 I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1058 /* Use LAN VSI Id by default */
1059 fdirdp->qindex_flex_ptype_vsi |=
1060 rte_cpu_to_le_32((pf->main_vsi->vsi_id <<
1061 I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1062 I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1064 fdirdp->dtype_cmd_cntindex =
1065 rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1068 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1069 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1070 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1072 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1073 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1074 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1076 if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1077 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1079 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1080 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1081 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1082 I40E_TXD_FLTR_QW1_DEST_MASK);
1084 fdirdp->dtype_cmd_cntindex |=
1085 rte_cpu_to_le_32((fdir_action->report_status<<
1086 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1087 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1089 fdirdp->dtype_cmd_cntindex |=
1090 rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1091 fdirdp->dtype_cmd_cntindex |=
1092 rte_cpu_to_le_32((pf->fdir.match_counter_index <<
1093 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1094 I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1096 fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1098 PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1099 txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1100 txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1101 td_cmd = I40E_TX_DESC_CMD_EOP |
1102 I40E_TX_DESC_CMD_RS |
1103 I40E_TX_DESC_CMD_DUMMY;
1105 txdp->cmd_type_offset_bsz =
1106 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1108 txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1109 if (txq->tx_tail >= txq->nb_tx_desc)
1111 /* Update the tx tail register */
1113 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1115 for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {
1116 rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
1117 if (txdp->cmd_type_offset_bsz &
1118 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1121 if (i >= I40E_FDIR_WAIT_COUNT) {
1122 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1123 " time out to get DD on tx queue.");
1126 /* totally delay 10 ms to check programming status*/
1127 rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);
1128 if (i40e_check_fdir_programming_status(rxq) < 0) {
1129 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1130 " programming status reported.");
1138 * i40e_fdir_flush - clear all filters of Flow Director table
1139 * @pf: board private structure
1142 i40e_fdir_flush(struct rte_eth_dev *dev)
1144 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1145 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1147 uint16_t guarant_cnt, best_cnt;
1150 I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1151 I40E_WRITE_FLUSH(hw);
1153 for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1154 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1155 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1156 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1159 if (i >= I40E_FDIR_FLUSH_RETRY) {
1160 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1163 guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1164 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1165 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1166 best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1167 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1168 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1169 if (guarant_cnt != 0 || best_cnt != 0) {
1170 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1173 PMD_DRV_LOG(INFO, "FD table Flush success.");
1178 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1179 struct rte_eth_flex_payload_cfg *flex_set,
1182 struct i40e_fdir_flex_pit *flex_pit;
1183 struct rte_eth_flex_payload_cfg *ptr = flex_set;
1184 uint16_t src, dst, size, j, k;
1185 uint8_t i, layer_idx;
1187 for (layer_idx = I40E_FLXPLD_L2_IDX;
1188 layer_idx <= I40E_FLXPLD_L4_IDX;
1190 if (layer_idx == I40E_FLXPLD_L2_IDX)
1191 ptr->type = RTE_ETH_L2_PAYLOAD;
1192 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1193 ptr->type = RTE_ETH_L3_PAYLOAD;
1194 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1195 ptr->type = RTE_ETH_L4_PAYLOAD;
1197 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1198 flex_pit = &pf->fdir.flex_set[layer_idx *
1199 I40E_MAX_FLXPLD_FIED + i];
1200 if (flex_pit->size == 0)
1202 src = flex_pit->src_offset * sizeof(uint16_t);
1203 dst = flex_pit->dst_offset * sizeof(uint16_t);
1204 size = flex_pit->size * sizeof(uint16_t);
1205 for (j = src, k = dst; j < src + size; j++, k++)
1206 ptr->src_offset[k] = j;
1214 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1215 struct rte_eth_fdir_flex_mask *flex_mask,
1218 struct i40e_fdir_flex_mask *mask;
1219 struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1220 enum rte_eth_flow_type flow_type;
1222 uint16_t off_bytes, mask_tmp;
1224 for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1225 i <= I40E_FILTER_PCTYPE_FRAG_IPV6;
1227 mask = &pf->fdir.flex_mask[i];
1228 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
1230 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
1231 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1232 if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1233 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1234 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1236 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1237 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1240 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1241 off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1242 mask_tmp = ~mask->bitmask[j].mask;
1243 ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1244 ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1246 ptr->flow_type = flow_type;
1253 * i40e_fdir_info_get - get information of Flow Director
1254 * @pf: ethernet device to get info from
1255 * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1256 * the flow director information.
1259 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1261 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1262 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1263 uint16_t num_flex_set = 0;
1264 uint16_t num_flex_mask = 0;
1266 if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1267 fdir->mode = RTE_FDIR_MODE_PERFECT;
1269 fdir->mode = RTE_FDIR_MODE_NONE;
1272 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1274 (uint32_t)hw->func_caps.fd_filters_best_effort;
1275 fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1276 fdir->flow_types_mask[0] = I40E_FDIR_FLOW_TYPES;
1277 fdir->flex_payload_unit = sizeof(uint16_t);
1278 fdir->flex_bitmask_unit = sizeof(uint16_t);
1279 fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1280 fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1281 fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1283 i40e_fdir_info_get_flex_set(pf,
1284 fdir->flex_conf.flex_set,
1286 i40e_fdir_info_get_flex_mask(pf,
1287 fdir->flex_conf.flex_mask,
1290 fdir->flex_conf.nb_payloads = num_flex_set;
1291 fdir->flex_conf.nb_flexmasks = num_flex_mask;
1295 * i40e_fdir_stat_get - get statistics of Flow Director
1296 * @pf: ethernet device to get info from
1297 * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1298 * the flow director statistics.
1301 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1303 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1304 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1307 fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1309 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1310 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1312 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1313 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1317 * i40e_fdir_ctrl_func - deal with all operations on flow director.
1318 * @pf: board private structure
1319 * @filter_op:operation will be taken.
1320 * @arg: a pointer to specific structure corresponding to the filter_op
1323 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1324 enum rte_filter_op filter_op,
1327 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1330 if ((pf->flags & I40E_FLAG_FDIR) == 0)
1333 if (filter_op == RTE_ETH_FILTER_NOP)
1336 if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1339 switch (filter_op) {
1340 case RTE_ETH_FILTER_ADD:
1341 ret = i40e_add_del_fdir_filter(dev,
1342 (struct rte_eth_fdir_filter *)arg,
1345 case RTE_ETH_FILTER_DELETE:
1346 ret = i40e_add_del_fdir_filter(dev,
1347 (struct rte_eth_fdir_filter *)arg,
1350 case RTE_ETH_FILTER_FLUSH:
1351 ret = i40e_fdir_flush(dev);
1353 case RTE_ETH_FILTER_INFO:
1354 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1356 case RTE_ETH_FILTER_STATS:
1357 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1360 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);