lib/librte_pmd_i40e/i40e_fdir.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41
  42 #include <rte_ether.h>
  43 #include <rte_ethdev.h>
  44 #include <rte_log.h>
  45 #include <rte_memzone.h>
  46 #include <rte_malloc.h>
  47 #include <rte_ip.h>
  48 #include <rte_udp.h>
  49 #include <rte_tcp.h>
  50 #include <rte_sctp.h>
  51
  52 #include "i40e_logs.h"
  53 #include "i40e/i40e_type.h"
  54 #include "i40e_ethdev.h"
  55 #include "i40e_rxtx.h"
  56
  57 #define I40E_FDIR_MZ_NAME          "FDIR_MEMZONE"
  58 #ifndef IPV6_ADDR_LEN
  59 #define IPV6_ADDR_LEN              16
  60 #endif
  61
  62 #define I40E_FDIR_PKT_LEN                   512
  63 #define I40E_FDIR_IP_DEFAULT_LEN            420
  64 #define I40E_FDIR_IP_DEFAULT_TTL            0x40
  65 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL    0x45
  66 #define I40E_FDIR_TCP_DEFAULT_DATAOFF       0x50
  67 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW     0x60300000
  68 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS   0xFF
  69 #define I40E_FDIR_IPv6_PAYLOAD_LEN          380
  70 #define I40E_FDIR_UDP_DEFAULT_LEN           400
  71
  72 /* Wait count and interval for fdir filter programming */
  73 #define I40E_FDIR_WAIT_COUNT       10
  74 #define I40E_FDIR_WAIT_INTERVAL_US 1000
  75
  76 /* Wait count and interval for fdir filter flush */
  77 #define I40E_FDIR_FLUSH_RETRY       50
  78 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
  79
  80 #define I40E_COUNTER_PF           2
  81 /* Statistic counter index for one pf */
  82 #define I40E_COUNTER_INDEX_FDIR(pf_id)   (0 + (pf_id) * I40E_COUNTER_PF)
  83 #define I40E_MAX_FLX_SOURCE_OFF           480
  84 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR   50
  85
  86 #define NONUSE_FLX_PIT_DEST_OFF 63
  87 #define NONUSE_FLX_PIT_FSIZE    1
  88 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
  89         (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
  90                 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
  91         (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
  92                         I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
  93         ((((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR) << \
  94                         I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
  95                         I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
  96
  97 #define I40E_FDIR_FLOW_TYPES ( \
  98         (1 << RTE_ETH_FLOW_TYPE_UDPV4) | \
  99         (1 << RTE_ETH_FLOW_TYPE_TCPV4) | \
 100         (1 << RTE_ETH_FLOW_TYPE_SCTPV4) | \
 101         (1 << RTE_ETH_FLOW_TYPE_IPV4_OTHER) | \
 102         (1 << RTE_ETH_FLOW_TYPE_FRAG_IPV4) | \
 103         (1 << RTE_ETH_FLOW_TYPE_UDPV6) | \
 104         (1 << RTE_ETH_FLOW_TYPE_TCPV6) | \
 105         (1 << RTE_ETH_FLOW_TYPE_SCTPV6) | \
 106         (1 << RTE_ETH_FLOW_TYPE_IPV6_OTHER) | \
 107         (1 << RTE_ETH_FLOW_TYPE_FRAG_IPV6))
 108
 109 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
 110
 111 static int i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq);
 112 static int i40e_check_fdir_flex_conf(
 113         const struct rte_eth_fdir_flex_conf *conf);
 114 static void i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 115                          const struct rte_eth_flex_payload_cfg *cfg);
 116 static void i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
 117                 enum i40e_filter_pctype pctype,
 118                 const struct rte_eth_fdir_flex_mask *mask_cfg);
 119 static int i40e_fdir_construct_pkt(struct i40e_pf *pf,
 120                                      const struct rte_eth_fdir_input *fdir_input,
 121                                      unsigned char *raw_pkt);
 122 static int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
 123                             const struct rte_eth_fdir_filter *filter,
 124                             bool add);
 125 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
 126                         enum i40e_filter_pctype pctype,
 127                         const struct rte_eth_fdir_filter *filter,
 128                         bool add);
 129 static int i40e_fdir_flush(struct rte_eth_dev *dev);
 130 static void i40e_fdir_info_get(struct rte_eth_dev *dev,
 131                            struct rte_eth_fdir_info *fdir);
 132 static void i40e_fdir_stats_get(struct rte_eth_dev *dev,
 133                            struct rte_eth_fdir_stats *stat);
 134
 135 static int
 136 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
 137 {
 138         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
 139         struct i40e_hmc_obj_rxq rx_ctx;
 140         int err = I40E_SUCCESS;
 141
 142         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
 143         /* Init the RX queue in hardware */
 144         rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
 145         rx_ctx.hbuff = 0;
 146         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 147         rx_ctx.qlen = rxq->nb_rx_desc;
 148 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 149         rx_ctx.dsize = 1;
 150 #endif
 151         rx_ctx.dtype = i40e_header_split_none;
 152         rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
 153         rx_ctx.rxmax = ETHER_MAX_LEN;
 154         rx_ctx.tphrdesc_ena = 1;
 155         rx_ctx.tphwdesc_ena = 1;
 156         rx_ctx.tphdata_ena = 1;
 157         rx_ctx.tphhead_ena = 1;
 158         rx_ctx.lrxqthresh = 2;
 159         rx_ctx.crcstrip = 0;
 160         rx_ctx.l2tsel = 1;
 161         rx_ctx.showiv = 1;
 162         rx_ctx.prefena = 1;
 163
 164         err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
 165         if (err != I40E_SUCCESS) {
 166                 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
 167                 return err;
 168         }
 169         err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
 170         if (err != I40E_SUCCESS) {
 171                 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
 172                 return err;
 173         }
 174         rxq->qrx_tail = hw->hw_addr +
 175                 I40E_QRX_TAIL(rxq->vsi->base_queue);
 176
 177         rte_wmb();
 178         /* Init the RX tail regieter. */
 179         I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
 180         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 181
 182         return err;
 183 }
 184
 185 /*
 186  * i40e_fdir_setup - reserve and initialize the Flow Director resources
 187  * @pf: board private structure
 188  */
 189 int
 190 i40e_fdir_setup(struct i40e_pf *pf)
 191 {
 192         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 193         struct i40e_vsi *vsi;
 194         int err = I40E_SUCCESS;
 195         char z_name[RTE_MEMZONE_NAMESIZE];
 196         const struct rte_memzone *mz = NULL;
 197         struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
 198
 199         PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
 200                         " num_filters_best_effort = %u.",
 201                         hw->func_caps.fd_filters_guaranteed,
 202                         hw->func_caps.fd_filters_best_effort);
 203
 204         vsi = pf->fdir.fdir_vsi;
 205         if (vsi) {
 206                 PMD_DRV_LOG(ERR, "FDIR vsi pointer needs "
 207                                  "to be null before creation.");
 208                 return I40E_ERR_BAD_PTR;
 209         }
 210         /* make new FDIR VSI */
 211         vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
 212         if (!vsi) {
 213                 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
 214                 return I40E_ERR_NO_AVAILABLE_VSI;
 215         }
 216         pf->fdir.fdir_vsi = vsi;
 217
 218         /*Fdir tx queue setup*/
 219         err = i40e_fdir_setup_tx_resources(pf);
 220         if (err) {
 221                 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
 222                 goto fail_setup_tx;
 223         }
 224
 225         /*Fdir rx queue setup*/
 226         err = i40e_fdir_setup_rx_resources(pf);
 227         if (err) {
 228                 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
 229                 goto fail_setup_rx;
 230         }
 231
 232         err = i40e_tx_queue_init(pf->fdir.txq);
 233         if (err) {
 234                 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
 235                 goto fail_mem;
 236         }
 237
 238         /* need switch on before dev start*/
 239         err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
 240         if (err) {
 241                 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
 242                 goto fail_mem;
 243         }
 244
 245         /* Init the rx queue in hardware */
 246         err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
 247         if (err) {
 248                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
 249                 goto fail_mem;
 250         }
 251
 252         /* switch on rx queue */
 253         err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
 254         if (err) {
 255                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
 256                 goto fail_mem;
 257         }
 258
 259         /* reserve memory for the fdir programming packet */
 260         snprintf(z_name, sizeof(z_name), "%s_%s_%d",
 261                         eth_dev->driver->pci_drv.name,
 262                         I40E_FDIR_MZ_NAME,
 263                         eth_dev->data->port_id);
 264         mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
 265         if (!mz) {
 266                 PMD_DRV_LOG(ERR, "Cannot init memzone for "
 267                                  "flow director program packet.");
 268                 err = I40E_ERR_NO_MEMORY;
 269                 goto fail_mem;
 270         }
 271         pf->fdir.prg_pkt = mz->addr;
 272 #ifdef RTE_LIBRTE_XEN_DOM0
 273         pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
 274 #else
 275         pf->fdir.dma_addr = (uint64_t)mz->phys_addr;
 276 #endif
 277         pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
 278         PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
 279                     vsi->base_queue);
 280         return I40E_SUCCESS;
 281
 282 fail_mem:
 283         i40e_dev_rx_queue_release(pf->fdir.rxq);
 284         pf->fdir.rxq = NULL;
 285 fail_setup_rx:
 286         i40e_dev_tx_queue_release(pf->fdir.txq);
 287         pf->fdir.txq = NULL;
 288 fail_setup_tx:
 289         i40e_vsi_release(vsi);
 290         pf->fdir.fdir_vsi = NULL;
 291         return err;
 292 }
 293
 294 /*
 295  * i40e_fdir_teardown - release the Flow Director resources
 296  * @pf: board private structure
 297  */
 298 void
 299 i40e_fdir_teardown(struct i40e_pf *pf)
 300 {
 301         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 302         struct i40e_vsi *vsi;
 303
 304         vsi = pf->fdir.fdir_vsi;
 305         i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
 306         i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
 307         i40e_dev_rx_queue_release(pf->fdir.rxq);
 308         pf->fdir.rxq = NULL;
 309         i40e_dev_tx_queue_release(pf->fdir.txq);
 310         pf->fdir.txq = NULL;
 311         i40e_vsi_release(vsi);
 312         pf->fdir.fdir_vsi = NULL;
 313 }
 314
 315 /* check whether the flow director table in empty */
 316 static inline int
 317 i40e_fdir_empty(struct i40e_hw *hw)
 318 {
 319         uint32_t guarant_cnt, best_cnt;
 320
 321         guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 322                                  I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
 323                                  I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
 324         best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 325                               I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
 326                               I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
 327         if (best_cnt + guarant_cnt > 0)
 328                 return -1;
 329
 330         return 0;
 331 }
 332
 333 /*
 334  * Initialize the configuration about bytes stream extracted as flexible payload
 335  * and mask setting
 336  */
 337 static inline void
 338 i40e_init_flx_pld(struct i40e_pf *pf)
 339 {
 340         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 341         uint8_t pctype;
 342         int i, index;
 343
 344         /*
 345          * Define the bytes stream extracted as flexible payload in
 346          * field vector. By default, select 8 words from the beginning
 347          * of payload as flexible payload.
 348          */
 349         for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
 350                 index = i * I40E_MAX_FLXPLD_FIED;
 351                 pf->fdir.flex_set[index].src_offset = 0;
 352                 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
 353                 pf->fdir.flex_set[index].dst_offset = 0;
 354                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
 355                 I40E_WRITE_REG(hw,
 356                         I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
 357                 I40E_WRITE_REG(hw,
 358                         I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
 359         }
 360
 361         /* initialize the masks */
 362         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 363              pctype <= I40E_FILTER_PCTYPE_FRAG_IPV6; pctype++) {
 364                 pf->fdir.flex_mask[pctype].word_mask = 0;
 365                 I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
 366                 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
 367                         pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
 368                         pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
 369                         I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
 370                 }
 371         }
 372 }
 373
 374 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
 375
 376 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
 377         if ((flex_pit2).src_offset < \
 378                 (flex_pit1).src_offset + (flex_pit1).size) { \
 379                 PMD_DRV_LOG(ERR, "src_offset should be not" \
 380                         " less than than previous offset" \
 381                         " + previous FSIZE."); \
 382                 return -EINVAL; \
 383         } \
 384 } while (0)
 385
 386 /*
 387  * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
 388  * and the flex_pit will be sorted by it's src_offset value
 389  */
 390 static inline uint16_t
 391 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
 392                         struct i40e_fdir_flex_pit *flex_pit)
 393 {
 394         uint16_t src_tmp, size, num = 0;
 395         uint16_t i, k, j = 0;
 396
 397         while (j < I40E_FDIR_MAX_FLEX_LEN) {
 398                 size = 1;
 399                 for (; j < I40E_FDIR_MAX_FLEX_LEN; j++) {
 400                         if (src_offset[j + 1] == src_offset[j] + 1)
 401                                 size++;
 402                         else {
 403                                 src_tmp = src_offset[j] + 1 - size;
 404                                 /* the flex_pit need to be sort by scr_offset */
 405                                 for (i = 0; i < num; i++) {
 406                                         if (src_tmp < flex_pit[i].src_offset)
 407                                                 break;
 408                                 }
 409                                 /* if insert required, move backward */
 410                                 for (k = num; k > i; k--)
 411                                         flex_pit[k] = flex_pit[k - 1];
 412                                 /* insert */
 413                                 flex_pit[i].dst_offset = j + 1 - size;
 414                                 flex_pit[i].src_offset = src_tmp;
 415                                 flex_pit[i].size = size;
 416                                 j++;
 417                                 num++;
 418                                 break;
 419                         }
 420                 }
 421         }
 422         return num;
 423 }
 424
 425 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
 426 static inline int
 427 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
 428 {
 429         struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
 430         uint16_t num, i;
 431
 432         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
 433                 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
 434                         PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
 435                         return -EINVAL;
 436                 }
 437         }
 438
 439         memset(flex_pit, 0, sizeof(flex_pit));
 440         num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
 441         if (num > I40E_MAX_FLXPLD_FIED) {
 442                 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
 443                 return -EINVAL;
 444         }
 445         for (i = 0; i < num; i++) {
 446                 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
 447                         flex_pit[i].src_offset & 0x01) {
 448                         PMD_DRV_LOG(ERR, "flexpayload should be measured"
 449                                 " in word");
 450                         return -EINVAL;
 451                 }
 452                 if (i != num - 1)
 453                         I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
 454         }
 455         return 0;
 456 }
 457
 458 /*
 459  * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
 460  * arguments are valid
 461  */
 462 static int
 463 i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
 464 {
 465         const struct rte_eth_flex_payload_cfg *flex_cfg;
 466         const struct rte_eth_fdir_flex_mask *flex_mask;
 467         uint16_t mask_tmp;
 468         uint8_t nb_bitmask;
 469         uint16_t i, j;
 470         int ret = 0;
 471
 472         if (conf == NULL) {
 473                 PMD_DRV_LOG(INFO, "NULL pointer.");
 474                 return -EINVAL;
 475         }
 476         /* check flexible payload setting configuration */
 477         if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
 478                 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
 479                 return -EINVAL;
 480         }
 481         for (i = 0; i < conf->nb_payloads; i++) {
 482                 flex_cfg = &conf->flex_set[i];
 483                 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
 484                         PMD_DRV_LOG(ERR, "invalid payload type.");
 485                         return -EINVAL;
 486                 }
 487                 ret = i40e_check_fdir_flex_payload(flex_cfg);
 488                 if (ret < 0) {
 489                         PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
 490                         return -EINVAL;
 491                 }
 492         }
 493
 494         /* check flex mask setting configuration */
 495         if (conf->nb_flexmasks > RTE_ETH_FLOW_TYPE_FRAG_IPV6) {
 496                 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
 497                 return -EINVAL;
 498         }
 499         for (i = 0; i < conf->nb_flexmasks; i++) {
 500                 flex_mask = &conf->flex_mask[i];
 501                 if (!I40E_VALID_FLOW_TYPE(flex_mask->flow_type)) {
 502                         PMD_DRV_LOG(WARNING, "invalid flow type.");
 503                         return -EINVAL;
 504                 }
 505                 nb_bitmask = 0;
 506                 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
 507                         mask_tmp = I40E_WORD(flex_mask->mask[j],
 508                                              flex_mask->mask[j + 1]);
 509                         if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
 510                                 nb_bitmask++;
 511                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
 512                                         PMD_DRV_LOG(ERR, " exceed maximal"
 513                                                 " number of bitmasks.");
 514                                         return -EINVAL;
 515                                 }
 516                         }
 517                 }
 518         }
 519         return 0;
 520 }
 521
 522 /*
 523  * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
 524  * @pf: board private structure
 525  * @cfg: the rule how bytes stream is extracted as flexible payload
 526  */
 527 static void
 528 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 529                          const struct rte_eth_flex_payload_cfg *cfg)
 530 {
 531         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 532         struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
 533         uint32_t flx_pit;
 534         uint16_t num, min_next_off;  /* in words */
 535         uint8_t field_idx = 0;
 536         uint8_t layer_idx = 0;
 537         uint16_t i;
 538
 539         if (cfg->type == RTE_ETH_L2_PAYLOAD)
 540                 layer_idx = I40E_FLXPLD_L2_IDX;
 541         else if (cfg->type == RTE_ETH_L3_PAYLOAD)
 542                 layer_idx = I40E_FLXPLD_L3_IDX;
 543         else if (cfg->type == RTE_ETH_L4_PAYLOAD)
 544                 layer_idx = I40E_FLXPLD_L4_IDX;
 545
 546         memset(flex_pit, 0, sizeof(flex_pit));
 547         num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
 548
 549         for (i = 0; i < num; i++) {
 550                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
 551                 /* record the info in fdir structure */
 552                 pf->fdir.flex_set[field_idx].src_offset =
 553                         flex_pit[i].src_offset / sizeof(uint16_t);
 554                 pf->fdir.flex_set[field_idx].size =
 555                         flex_pit[i].size / sizeof(uint16_t);
 556                 pf->fdir.flex_set[field_idx].dst_offset =
 557                         flex_pit[i].dst_offset / sizeof(uint16_t);
 558                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
 559                                 pf->fdir.flex_set[field_idx].size,
 560                                 pf->fdir.flex_set[field_idx].dst_offset);
 561
 562                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
 563         }
 564         min_next_off = pf->fdir.flex_set[field_idx].src_offset +
 565                                 pf->fdir.flex_set[field_idx].size;
 566
 567         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
 568                 /* set the non-used register obeying register's constrain */
 569                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
 570                            NONUSE_FLX_PIT_DEST_OFF);
 571                 I40E_WRITE_REG(hw,
 572                         I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
 573                         flx_pit);
 574                 min_next_off++;
 575         }
 576 }
 577
 578 /*
 579  * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
 580  * @pf: board private structure
 581  * @pctype: packet classify type
 582  * @flex_masks: mask for flexible payload
 583  */
 584 static void
 585 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
 586                 enum i40e_filter_pctype pctype,
 587                 const struct rte_eth_fdir_flex_mask *mask_cfg)
 588 {
 589         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 590         struct i40e_fdir_flex_mask *flex_mask;
 591         uint32_t flxinset, fd_mask;
 592         uint16_t mask_tmp;
 593         uint8_t i, nb_bitmask = 0;
 594
 595         flex_mask = &pf->fdir.flex_mask[pctype];
 596         memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
 597         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
 598                 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
 599                 if (mask_tmp != 0x0) {
 600                         flex_mask->word_mask |=
 601                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
 602                         if (mask_tmp != UINT16_MAX) {
 603                                 /* set bit mask */
 604                                 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
 605                                 flex_mask->bitmask[nb_bitmask].offset =
 606                                         i / sizeof(uint16_t);
 607                                 nb_bitmask++;
 608                         }
 609                 }
 610         }
 611         /* write mask to hw */
 612         flxinset = (flex_mask->word_mask <<
 613                 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
 614                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
 615         I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
 616
 617         for (i = 0; i < nb_bitmask; i++) {
 618                 fd_mask = (flex_mask->bitmask[i].mask <<
 619                         I40E_PRTQF_FD_MSK_MASK_SHIFT) &
 620                         I40E_PRTQF_FD_MSK_MASK_MASK;
 621                 fd_mask |= ((flex_mask->bitmask[i].offset +
 622                         I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
 623                         I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
 624                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
 625                 I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
 626         }
 627 }
 628
 629 /*
 630  * Configure flow director related setting
 631  */
 632 int
 633 i40e_fdir_configure(struct rte_eth_dev *dev)
 634 {
 635         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 636         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 637         struct rte_eth_fdir_flex_conf *conf;
 638         enum i40e_filter_pctype pctype;
 639         uint32_t val;
 640         uint8_t i;
 641         int ret = 0;
 642
 643         /*
 644         * configuration need to be done before
 645         * flow director filters are added
 646         * If filters exist, flush them.
 647         */
 648         if (i40e_fdir_empty(hw) < 0) {
 649                 ret = i40e_fdir_flush(dev);
 650                 if (ret) {
 651                         PMD_DRV_LOG(ERR, "failed to flush fdir table.");
 652                         return ret;
 653                 }
 654         }
 655
 656         val = I40E_READ_REG(hw, I40E_PFQF_CTL_0);
 657         if ((pf->flags & I40E_FLAG_FDIR) &&
 658                 dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 659                 /* enable FDIR filter */
 660                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
 661                 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val);
 662
 663                 i40e_init_flx_pld(pf); /* set flex config to default value */
 664
 665                 conf = &dev->data->dev_conf.fdir_conf.flex_conf;
 666                 ret = i40e_check_fdir_flex_conf(conf);
 667                 if (ret < 0) {
 668                         PMD_DRV_LOG(ERR, " invalid configuration arguments.");
 669                         return -EINVAL;
 670                 }
 671                 /* configure flex payload */
 672                 for (i = 0; i < conf->nb_payloads; i++)
 673                         i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
 674                 /* configure flex mask*/
 675                 for (i = 0; i < conf->nb_flexmasks; i++) {
 676                         pctype = i40e_flowtype_to_pctype(
 677                                 conf->flex_mask[i].flow_type);
 678                         i40e_set_flex_mask_on_pctype(pf,
 679                                         pctype,
 680                                         &conf->flex_mask[i]);
 681                 }
 682         } else {
 683                 /* disable FDIR filter */
 684                 val &= ~I40E_PFQF_CTL_0_FD_ENA_MASK;
 685                 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val);
 686                 pf->flags &= ~I40E_FLAG_FDIR;
 687         }
 688
 689         return ret;
 690 }
 691
 692 static inline void
 693 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 694                                unsigned char *raw_pkt)
 695 {
 696         struct ether_hdr *ether = (struct ether_hdr *)raw_pkt;
 697         struct ipv4_hdr *ip;
 698         struct ipv6_hdr *ip6;
 699         static const uint8_t next_proto[] = {
 700                 [RTE_ETH_FLOW_TYPE_UDPV4] = IPPROTO_UDP,
 701                 [RTE_ETH_FLOW_TYPE_TCPV4] = IPPROTO_TCP,
 702                 [RTE_ETH_FLOW_TYPE_SCTPV4] = IPPROTO_SCTP,
 703                 [RTE_ETH_FLOW_TYPE_IPV4_OTHER] = IPPROTO_IP,
 704                 [RTE_ETH_FLOW_TYPE_FRAG_IPV4] = IPPROTO_IP,
 705                 [RTE_ETH_FLOW_TYPE_UDPV6] = IPPROTO_UDP,
 706                 [RTE_ETH_FLOW_TYPE_TCPV6] = IPPROTO_TCP,
 707                 [RTE_ETH_FLOW_TYPE_SCTPV6] = IPPROTO_SCTP,
 708                 [RTE_ETH_FLOW_TYPE_IPV6_OTHER] = IPPROTO_NONE,
 709                 [RTE_ETH_FLOW_TYPE_FRAG_IPV6] = IPPROTO_NONE,
 710         };
 711
 712         switch (fdir_input->flow_type) {
 713         case RTE_ETH_FLOW_TYPE_UDPV4:
 714         case RTE_ETH_FLOW_TYPE_TCPV4:
 715         case RTE_ETH_FLOW_TYPE_SCTPV4:
 716         case RTE_ETH_FLOW_TYPE_IPV4_OTHER:
 717         case RTE_ETH_FLOW_TYPE_FRAG_IPV4:
 718                 ip = (struct ipv4_hdr *)(raw_pkt + sizeof(struct ether_hdr));
 719
 720                 ether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
 721                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
 722                 /* set len to by default */
 723                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
 724                 ip->time_to_live = I40E_FDIR_IP_DEFAULT_TTL;
 725                 /*
 726                  * The source and destination fields in the transmitted packet
 727                  * need to be presented in a reversed order with respect
 728                  * to the expected received packets.
 729                  */
 730                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
 731                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
 732                 ip->next_proto_id = next_proto[fdir_input->flow_type];
 733                 break;
 734         case RTE_ETH_FLOW_TYPE_UDPV6:
 735         case RTE_ETH_FLOW_TYPE_TCPV6:
 736         case RTE_ETH_FLOW_TYPE_SCTPV6:
 737         case RTE_ETH_FLOW_TYPE_IPV6_OTHER:
 738         case RTE_ETH_FLOW_TYPE_FRAG_IPV6:
 739                 ip6 = (struct ipv6_hdr *)(raw_pkt + sizeof(struct ether_hdr));
 740
 741                 ether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
 742                 ip6->vtc_flow =
 743                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW);
 744                 ip6->payload_len =
 745                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 746                 ip6->hop_limits = I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
 747
 748                 /*
 749                  * The source and destination fields in the transmitted packet
 750                  * need to be presented in a reversed order with respect
 751                  * to the expected received packets.
 752                  */
 753                 rte_memcpy(&(ip6->src_addr),
 754                            &(fdir_input->flow.ip6_flow.dst_ip),
 755                            IPV6_ADDR_LEN);
 756                 rte_memcpy(&(ip6->dst_addr),
 757                            &(fdir_input->flow.ip6_flow.src_ip),
 758                            IPV6_ADDR_LEN);
 759                 ip6->proto = next_proto[fdir_input->flow_type];
 760                 break;
 761         default:
 762                 PMD_DRV_LOG(ERR, "unknown flow type %u.",
 763                             fdir_input->flow_type);
 764                 break;
 765         }
 766 }
 767
 768
 769 /*
 770  * i40e_fdir_construct_pkt - construct packet based on fields in input
 771  * @pf: board private structure
 772  * @fdir_input: input set of the flow director entry
 773  * @raw_pkt: a packet to be constructed
 774  */
 775 static int
 776 i40e_fdir_construct_pkt(struct i40e_pf *pf,
 777                              const struct rte_eth_fdir_input *fdir_input,
 778                              unsigned char *raw_pkt)
 779 {
 780         unsigned char *payload, *ptr;
 781         struct udp_hdr *udp;
 782         struct tcp_hdr *tcp;
 783         struct sctp_hdr *sctp;
 784         uint8_t size, dst = 0;
 785         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
 786
 787         /* fill the ethernet and IP head */
 788         i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt);
 789
 790         /* fill the L4 head */
 791         switch (fdir_input->flow_type) {
 792         case RTE_ETH_FLOW_TYPE_UDPV4:
 793                 udp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 794                                 sizeof(struct ipv4_hdr));
 795                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 796                 /*
 797                  * The source and destination fields in the transmitted packet
 798                  * need to be presented in a reversed order with respect
 799                  * to the expected received packets.
 800                  */
 801                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
 802                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
 803                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
 804                 break;
 805
 806         case RTE_ETH_FLOW_TYPE_TCPV4:
 807                 tcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 808                                          sizeof(struct ipv4_hdr));
 809                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 810                 /*
 811                  * The source and destination fields in the transmitted packet
 812                  * need to be presented in a reversed order with respect
 813                  * to the expected received packets.
 814                  */
 815                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
 816                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
 817                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 818                 break;
 819
 820         case RTE_ETH_FLOW_TYPE_SCTPV4:
 821                 sctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 822                                            sizeof(struct ipv4_hdr));
 823                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 824                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
 825                 break;
 826
 827         case RTE_ETH_FLOW_TYPE_IPV4_OTHER:
 828         case RTE_ETH_FLOW_TYPE_FRAG_IPV4:
 829                 payload = raw_pkt + sizeof(struct ether_hdr) +
 830                           sizeof(struct ipv4_hdr);
 831                 set_idx = I40E_FLXPLD_L3_IDX;
 832                 break;
 833
 834         case RTE_ETH_FLOW_TYPE_UDPV6:
 835                 udp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 836                                          sizeof(struct ipv6_hdr));
 837                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 838                 /*
 839                  * The source and destination fields in the transmitted packet
 840                  * need to be presented in a reversed order with respect
 841                  * to the expected received packets.
 842                  */
 843                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
 844                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
 845                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 846                 break;
 847
 848         case RTE_ETH_FLOW_TYPE_TCPV6:
 849                 tcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 850                                          sizeof(struct ipv6_hdr));
 851                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 852                 /*
 853                  * The source and destination fields in the transmitted packet
 854                  * need to be presented in a reversed order with respect
 855                  * to the expected received packets.
 856                  */
 857                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 858                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
 859                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
 860                 break;
 861
 862         case RTE_ETH_FLOW_TYPE_SCTPV6:
 863                 sctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 864                                            sizeof(struct ipv6_hdr));
 865                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 866                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
 867                 break;
 868
 869         case RTE_ETH_FLOW_TYPE_IPV6_OTHER:
 870         case RTE_ETH_FLOW_TYPE_FRAG_IPV6:
 871                 payload = raw_pkt + sizeof(struct ether_hdr) +
 872                           sizeof(struct ipv6_hdr);
 873                 set_idx = I40E_FLXPLD_L3_IDX;
 874                 break;
 875         default:
 876                 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
 877                 return -EINVAL;
 878         }
 879
 880         /* fill the flexbytes to payload */
 881         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
 882                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
 883                 size = pf->fdir.flex_set[pit_idx].size;
 884                 if (size == 0)
 885                         continue;
 886                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
 887                 ptr = payload +
 888                         pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
 889                 (void)rte_memcpy(ptr,
 890                                  &fdir_input->flow_ext.flexbytes[dst],
 891                                  size * sizeof(uint16_t));
 892         }
 893
 894         return 0;
 895 }
 896
 897 /* Construct the tx flags */
 898 static inline uint64_t
 899 i40e_build_ctob(uint32_t td_cmd,
 900                 uint32_t td_offset,
 901                 unsigned int size,
 902                 uint32_t td_tag)
 903 {
 904         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 905                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 906                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 907                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 908                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 909 }
 910
 911 /*
 912  * check the programming status descriptor in rx queue.
 913  * done after Programming Flow Director is programmed on
 914  * tx queue
 915  */
 916 static inline int
 917 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
 918 {
 919         volatile union i40e_rx_desc *rxdp;
 920         uint64_t qword1;
 921         uint32_t rx_status;
 922         uint32_t len, id;
 923         uint32_t error;
 924         int ret = 0;
 925
 926         rxdp = &rxq->rx_ring[rxq->rx_tail];
 927         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 928         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 929                         >> I40E_RXD_QW1_STATUS_SHIFT;
 930
 931         if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
 932                 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
 933                 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
 934                             I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
 935
 936                 if (len  == I40E_RX_PROG_STATUS_DESC_LENGTH &&
 937                     id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
 938                         error = (qword1 &
 939                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
 940                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
 941                         if (error == (0x1 <<
 942                                 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
 943                                 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
 944                                             " (FD_ID %u): programming status"
 945                                             " reported.",
 946                                             rxdp->wb.qword0.hi_dword.fd_id);
 947                                 ret = -1;
 948                         } else if (error == (0x1 <<
 949                                 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
 950                                 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
 951                                             " (FD_ID %u): programming status"
 952                                             " reported.",
 953                                             rxdp->wb.qword0.hi_dword.fd_id);
 954                                 ret = -1;
 955                         } else
 956                                 PMD_DRV_LOG(ERR, "invalid programming status"
 957                                             " reported, error = %u.", error);
 958                 } else
 959                         PMD_DRV_LOG(ERR, "unknown programming status"
 960                                     " reported, len = %d, id = %u.", len, id);
 961                 rxdp->wb.qword1.status_error_len = 0;
 962                 rxq->rx_tail++;
 963                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
 964                         rxq->rx_tail = 0;
 965         }
 966         return ret;
 967 }
 968
 969 /*
 970  * i40e_add_del_fdir_filter - add or remove a flow director filter.
 971  * @pf: board private structure
 972  * @filter: fdir filter entry
 973  * @add: 0 - delete, 1 - add
 974  */
 975 static int
 976 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
 977                             const struct rte_eth_fdir_filter *filter,
 978                             bool add)
 979 {
 980         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 981         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
 982         enum i40e_filter_pctype pctype;
 983         int ret = 0;
 984
 985         if (!(pf->flags & I40E_FLAG_FDIR)) {
 986                 PMD_DRV_LOG(ERR, "FDIR is not enabled.");
 987                 return -ENOTSUP;
 988         }
 989         if (!I40E_VALID_FLOW_TYPE(filter->input.flow_type)) {
 990                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
 991                 return -EINVAL;
 992         }
 993         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
 994                 PMD_DRV_LOG(ERR, "Invalid queue ID");
 995                 return -EINVAL;
 996         }
 997
 998         memset(pkt, 0, I40E_FDIR_PKT_LEN);
 999
1000         ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1001         if (ret < 0) {
1002                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1003                 return ret;
1004         }
1005         pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
1006         ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1007         if (ret < 0) {
1008                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1009                             pctype);
1010                 return ret;
1011         }
1012         return ret;
1013 }
1014
1015 /*
1016  * i40e_fdir_filter_programming - Program a flow director filter rule.
1017  * Is done by Flow Director Programming Descriptor followed by packet
1018  * structure that contains the filter fields need to match.
1019  * @pf: board private structure
1020  * @pctype: pctype
1021  * @filter: fdir filter entry
1022  * @add: 0 - delelet, 1 - add
1023  */
1024 static int
1025 i40e_fdir_filter_programming(struct i40e_pf *pf,
1026                         enum i40e_filter_pctype pctype,
1027                         const struct rte_eth_fdir_filter *filter,
1028                         bool add)
1029 {
1030         struct i40e_tx_queue *txq = pf->fdir.txq;
1031         struct i40e_rx_queue *rxq = pf->fdir.rxq;
1032         const struct rte_eth_fdir_action *fdir_action = &filter->action;
1033         volatile struct i40e_tx_desc *txdp;
1034         volatile struct i40e_filter_program_desc *fdirdp;
1035         uint32_t td_cmd;
1036         uint16_t i;
1037         uint8_t dest;
1038
1039         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1040         fdirdp = (volatile struct i40e_filter_program_desc *)
1041                         (&(txq->tx_ring[txq->tx_tail]));
1042
1043         fdirdp->qindex_flex_ptype_vsi =
1044                         rte_cpu_to_le_32((fdir_action->rx_queue <<
1045                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1046                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
1047
1048         fdirdp->qindex_flex_ptype_vsi |=
1049                         rte_cpu_to_le_32((fdir_action->flex_off <<
1050                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1051                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1052
1053         fdirdp->qindex_flex_ptype_vsi |=
1054                         rte_cpu_to_le_32((pctype <<
1055                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1056                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1057
1058         /* Use LAN VSI Id by default */
1059         fdirdp->qindex_flex_ptype_vsi |=
1060                 rte_cpu_to_le_32((pf->main_vsi->vsi_id <<
1061                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1062                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1063
1064         fdirdp->dtype_cmd_cntindex =
1065                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1066
1067         if (add)
1068                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1069                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1070                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1071         else
1072                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1073                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1074                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1075
1076         if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1077                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1078         else
1079                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1080         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1081                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1082                                 I40E_TXD_FLTR_QW1_DEST_MASK);
1083
1084         fdirdp->dtype_cmd_cntindex |=
1085                 rte_cpu_to_le_32((fdir_action->report_status<<
1086                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1087                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1088
1089         fdirdp->dtype_cmd_cntindex |=
1090                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1091         fdirdp->dtype_cmd_cntindex |=
1092                         rte_cpu_to_le_32((pf->fdir.match_counter_index <<
1093                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1094                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1095
1096         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1097
1098         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1099         txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1100         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1101         td_cmd = I40E_TX_DESC_CMD_EOP |
1102                  I40E_TX_DESC_CMD_RS  |
1103                  I40E_TX_DESC_CMD_DUMMY;
1104
1105         txdp->cmd_type_offset_bsz =
1106                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1107
1108         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1109         if (txq->tx_tail >= txq->nb_tx_desc)
1110                 txq->tx_tail = 0;
1111         /* Update the tx tail register */
1112         rte_wmb();
1113         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1114
1115         for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {
1116                 rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
1117                 if (txdp->cmd_type_offset_bsz &
1118                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1119                         break;
1120         }
1121         if (i >= I40E_FDIR_WAIT_COUNT) {
1122                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1123                             " time out to get DD on tx queue.");
1124                 return -ETIMEDOUT;
1125         }
1126         /* totally delay 10 ms to check programming status*/
1127         rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);
1128         if (i40e_check_fdir_programming_status(rxq) < 0) {
1129                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1130                             " programming status reported.");
1131                 return -ENOSYS;
1132         }
1133
1134         return 0;
1135 }
1136
1137 /*
1138  * i40e_fdir_flush - clear all filters of Flow Director table
1139  * @pf: board private structure
1140  */
1141 static int
1142 i40e_fdir_flush(struct rte_eth_dev *dev)
1143 {
1144         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1145         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1146         uint32_t reg;
1147         uint16_t guarant_cnt, best_cnt;
1148         uint16_t i;
1149
1150         I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1151         I40E_WRITE_FLUSH(hw);
1152
1153         for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1154                 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1155                 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1156                 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1157                         break;
1158         }
1159         if (i >= I40E_FDIR_FLUSH_RETRY) {
1160                 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1161                 return -ETIMEDOUT;
1162         }
1163         guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1164                                 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1165                                 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1166         best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1167                                 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1168                                 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1169         if (guarant_cnt != 0 || best_cnt != 0) {
1170                 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1171                 return -ENOSYS;
1172         } else
1173                 PMD_DRV_LOG(INFO, "FD table Flush success.");
1174         return 0;
1175 }
1176
1177 static inline void
1178 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1179                         struct rte_eth_flex_payload_cfg *flex_set,
1180                         uint16_t *num)
1181 {
1182         struct i40e_fdir_flex_pit *flex_pit;
1183         struct rte_eth_flex_payload_cfg *ptr = flex_set;
1184         uint16_t src, dst, size, j, k;
1185         uint8_t i, layer_idx;
1186
1187         for (layer_idx = I40E_FLXPLD_L2_IDX;
1188              layer_idx <= I40E_FLXPLD_L4_IDX;
1189              layer_idx++) {
1190                 if (layer_idx == I40E_FLXPLD_L2_IDX)
1191                         ptr->type = RTE_ETH_L2_PAYLOAD;
1192                 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1193                         ptr->type = RTE_ETH_L3_PAYLOAD;
1194                 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1195                         ptr->type = RTE_ETH_L4_PAYLOAD;
1196
1197                 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1198                         flex_pit = &pf->fdir.flex_set[layer_idx *
1199                                 I40E_MAX_FLXPLD_FIED + i];
1200                         if (flex_pit->size == 0)
1201                                 continue;
1202                         src = flex_pit->src_offset * sizeof(uint16_t);
1203                         dst = flex_pit->dst_offset * sizeof(uint16_t);
1204                         size = flex_pit->size * sizeof(uint16_t);
1205                         for (j = src, k = dst; j < src + size; j++, k++)
1206                                 ptr->src_offset[k] = j;
1207                 }
1208                 (*num)++;
1209                 ptr++;
1210         }
1211 }
1212
1213 static inline void
1214 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1215                         struct rte_eth_fdir_flex_mask *flex_mask,
1216                         uint16_t *num)
1217 {
1218         struct i40e_fdir_flex_mask *mask;
1219         struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1220         enum rte_eth_flow_type flow_type;
1221         uint8_t i, j;
1222         uint16_t off_bytes, mask_tmp;
1223
1224         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1225              i <= I40E_FILTER_PCTYPE_FRAG_IPV6;
1226              i++) {
1227                 mask =  &pf->fdir.flex_mask[i];
1228                 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
1229                         continue;
1230                 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
1231                 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1232                         if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1233                                 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1234                                 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1235                         } else {
1236                                 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1237                                 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1238                         }
1239                 }
1240                 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1241                         off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1242                         mask_tmp = ~mask->bitmask[j].mask;
1243                         ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1244                         ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1245                 }
1246                 ptr->flow_type = flow_type;
1247                 ptr++;
1248                 (*num)++;
1249         }
1250 }
1251
1252 /*
1253  * i40e_fdir_info_get - get information of Flow Director
1254  * @pf: ethernet device to get info from
1255  * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1256  *    the flow director information.
1257  */
1258 static void
1259 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1260 {
1261         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1262         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1263         uint16_t num_flex_set = 0;
1264         uint16_t num_flex_mask = 0;
1265
1266         fdir->mode = (pf->flags & I40E_FLAG_FDIR) ?
1267                         RTE_FDIR_MODE_PERFECT : RTE_FDIR_MODE_NONE;
1268         fdir->guarant_spc =
1269                 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1270         fdir->best_spc =
1271                 (uint32_t)hw->func_caps.fd_filters_best_effort;
1272         fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1273         fdir->flow_types_mask[0] = I40E_FDIR_FLOW_TYPES;
1274         fdir->flex_payload_unit = sizeof(uint16_t);
1275         fdir->flex_bitmask_unit = sizeof(uint16_t);
1276         fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1277         fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1278         fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1279
1280         i40e_fdir_info_get_flex_set(pf,
1281                                 fdir->flex_conf.flex_set,
1282                                 &num_flex_set);
1283         i40e_fdir_info_get_flex_mask(pf,
1284                                 fdir->flex_conf.flex_mask,
1285                                 &num_flex_mask);
1286
1287         fdir->flex_conf.nb_payloads = num_flex_set;
1288         fdir->flex_conf.nb_flexmasks = num_flex_mask;
1289 }
1290
1291 /*
1292  * i40e_fdir_stat_get - get statistics of Flow Director
1293  * @pf: ethernet device to get info from
1294  * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1295  *    the flow director statistics.
1296  */
1297 static void
1298 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1299 {
1300         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1301         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1302         uint32_t fdstat;
1303
1304         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1305         stat->guarant_cnt =
1306                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1307                             I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1308         stat->best_cnt =
1309                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1310                             I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1311 }
1312
1313 /*
1314  * i40e_fdir_ctrl_func - deal with all operations on flow director.
1315  * @pf: board private structure
1316  * @filter_op:operation will be taken.
1317  * @arg: a pointer to specific structure corresponding to the filter_op
1318  */
1319 int
1320 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1321                        enum rte_filter_op filter_op,
1322                        void *arg)
1323 {
1324         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1325         int ret = 0;
1326
1327         if (filter_op == RTE_ETH_FILTER_NOP) {
1328                 if (!(pf->flags & I40E_FLAG_FDIR))
1329                         ret = -ENOTSUP;
1330                 return ret;
1331         }
1332
1333         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1334                 return -EINVAL;
1335
1336         switch (filter_op) {
1337         case RTE_ETH_FILTER_ADD:
1338                 ret = i40e_add_del_fdir_filter(dev,
1339                         (struct rte_eth_fdir_filter *)arg,
1340                         TRUE);
1341                 break;
1342         case RTE_ETH_FILTER_DELETE:
1343                 ret = i40e_add_del_fdir_filter(dev,
1344                         (struct rte_eth_fdir_filter *)arg,
1345                         FALSE);
1346                 break;
1347         case RTE_ETH_FILTER_FLUSH:
1348                 ret = i40e_fdir_flush(dev);
1349                 break;
1350         case RTE_ETH_FILTER_INFO:
1351                 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1352                 break;
1353         case RTE_ETH_FILTER_STATS:
1354                 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1355                 break;
1356         default:
1357                 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
1358                 ret = -EINVAL;
1359                 break;
1360         }
1361         return ret;
1362 }