lib/librte_pmd_i40e/i40e_fdir.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41
  42 #include <rte_ether.h>
  43 #include <rte_ethdev.h>
  44 #include <rte_log.h>
  45 #include <rte_memzone.h>
  46 #include <rte_malloc.h>
  47 #include <rte_ip.h>
  48 #include <rte_udp.h>
  49 #include <rte_tcp.h>
  50 #include <rte_sctp.h>
  51
  52 #include "i40e_logs.h"
  53 #include "i40e/i40e_type.h"
  54 #include "i40e_ethdev.h"
  55 #include "i40e_rxtx.h"
  56
  57 #define I40E_FDIR_MZ_NAME          "FDIR_MEMZONE"
  58 #ifndef IPV6_ADDR_LEN
  59 #define IPV6_ADDR_LEN              16
  60 #endif
  61
  62 #define I40E_FDIR_PKT_LEN                   512
  63 #define I40E_FDIR_IP_DEFAULT_LEN            420
  64 #define I40E_FDIR_IP_DEFAULT_TTL            0x40
  65 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL    0x45
  66 #define I40E_FDIR_TCP_DEFAULT_DATAOFF       0x50
  67 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW     0x60300000
  68 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS   0xFF
  69 #define I40E_FDIR_IPv6_PAYLOAD_LEN          380
  70 #define I40E_FDIR_UDP_DEFAULT_LEN           400
  71
  72 /* Wait count and interval for fdir filter programming */
  73 #define I40E_FDIR_WAIT_COUNT       10
  74 #define I40E_FDIR_WAIT_INTERVAL_US 1000
  75
  76 /* Wait count and interval for fdir filter flush */
  77 #define I40E_FDIR_FLUSH_RETRY       50
  78 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
  79
  80 #define I40E_COUNTER_PF           2
  81 /* Statistic counter index for one pf */
  82 #define I40E_COUNTER_INDEX_FDIR(pf_id)   (0 + (pf_id) * I40E_COUNTER_PF)
  83 #define I40E_MAX_FLX_SOURCE_OFF           480
  84 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR   50
  85
  86 #define NONUSE_FLX_PIT_DEST_OFF 63
  87 #define NONUSE_FLX_PIT_FSIZE    1
  88 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
  89         (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
  90                 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
  91         (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
  92                         I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
  93         ((((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR) << \
  94                         I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
  95                         I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
  96
  97 #define I40E_FDIR_FLOW_TYPES ( \
  98         (1 << RTE_ETH_FLOW_TYPE_UDPV4) | \
  99         (1 << RTE_ETH_FLOW_TYPE_TCPV4) | \
 100         (1 << RTE_ETH_FLOW_TYPE_SCTPV4) | \
 101         (1 << RTE_ETH_FLOW_TYPE_IPV4_OTHER) | \
 102         (1 << RTE_ETH_FLOW_TYPE_FRAG_IPV4) | \
 103         (1 << RTE_ETH_FLOW_TYPE_UDPV6) | \
 104         (1 << RTE_ETH_FLOW_TYPE_TCPV6) | \
 105         (1 << RTE_ETH_FLOW_TYPE_SCTPV6) | \
 106         (1 << RTE_ETH_FLOW_TYPE_IPV6_OTHER) | \
 107         (1 << RTE_ETH_FLOW_TYPE_FRAG_IPV6))
 108
 109 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
 110
 111 static int i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq);
 112 static int i40e_fdir_construct_pkt(struct i40e_pf *pf,
 113                                      const struct rte_eth_fdir_input *fdir_input,
 114                                      unsigned char *raw_pkt);
 115 static int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
 116                             const struct rte_eth_fdir_filter *filter,
 117                             bool add);
 118 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
 119                         enum i40e_filter_pctype pctype,
 120                         const struct rte_eth_fdir_filter *filter,
 121                         bool add);
 122 static int i40e_fdir_flush(struct rte_eth_dev *dev);
 123 static void i40e_fdir_info_get(struct rte_eth_dev *dev,
 124                            struct rte_eth_fdir_info *fdir);
 125
 126 static int
 127 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
 128 {
 129         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
 130         struct i40e_hmc_obj_rxq rx_ctx;
 131         int err = I40E_SUCCESS;
 132
 133         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
 134         /* Init the RX queue in hardware */
 135         rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
 136         rx_ctx.hbuff = 0;
 137         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 138         rx_ctx.qlen = rxq->nb_rx_desc;
 139 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 140         rx_ctx.dsize = 1;
 141 #endif
 142         rx_ctx.dtype = i40e_header_split_none;
 143         rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
 144         rx_ctx.rxmax = ETHER_MAX_LEN;
 145         rx_ctx.tphrdesc_ena = 1;
 146         rx_ctx.tphwdesc_ena = 1;
 147         rx_ctx.tphdata_ena = 1;
 148         rx_ctx.tphhead_ena = 1;
 149         rx_ctx.lrxqthresh = 2;
 150         rx_ctx.crcstrip = 0;
 151         rx_ctx.l2tsel = 1;
 152         rx_ctx.showiv = 1;
 153         rx_ctx.prefena = 1;
 154
 155         err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
 156         if (err != I40E_SUCCESS) {
 157                 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
 158                 return err;
 159         }
 160         err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
 161         if (err != I40E_SUCCESS) {
 162                 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
 163                 return err;
 164         }
 165         rxq->qrx_tail = hw->hw_addr +
 166                 I40E_QRX_TAIL(rxq->vsi->base_queue);
 167
 168         rte_wmb();
 169         /* Init the RX tail regieter. */
 170         I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
 171         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 172
 173         return err;
 174 }
 175
 176 /*
 177  * i40e_fdir_setup - reserve and initialize the Flow Director resources
 178  * @pf: board private structure
 179  */
 180 int
 181 i40e_fdir_setup(struct i40e_pf *pf)
 182 {
 183         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 184         struct i40e_vsi *vsi;
 185         int err = I40E_SUCCESS;
 186         char z_name[RTE_MEMZONE_NAMESIZE];
 187         const struct rte_memzone *mz = NULL;
 188         struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
 189
 190         PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
 191                         " num_filters_best_effort = %u.",
 192                         hw->func_caps.fd_filters_guaranteed,
 193                         hw->func_caps.fd_filters_best_effort);
 194
 195         vsi = pf->fdir.fdir_vsi;
 196         if (vsi) {
 197                 PMD_DRV_LOG(ERR, "FDIR vsi pointer needs "
 198                                  "to be null before creation.");
 199                 return I40E_ERR_BAD_PTR;
 200         }
 201         /* make new FDIR VSI */
 202         vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
 203         if (!vsi) {
 204                 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
 205                 return I40E_ERR_NO_AVAILABLE_VSI;
 206         }
 207         pf->fdir.fdir_vsi = vsi;
 208
 209         /*Fdir tx queue setup*/
 210         err = i40e_fdir_setup_tx_resources(pf);
 211         if (err) {
 212                 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
 213                 goto fail_setup_tx;
 214         }
 215
 216         /*Fdir rx queue setup*/
 217         err = i40e_fdir_setup_rx_resources(pf);
 218         if (err) {
 219                 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
 220                 goto fail_setup_rx;
 221         }
 222
 223         err = i40e_tx_queue_init(pf->fdir.txq);
 224         if (err) {
 225                 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
 226                 goto fail_mem;
 227         }
 228
 229         /* need switch on before dev start*/
 230         err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
 231         if (err) {
 232                 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
 233                 goto fail_mem;
 234         }
 235
 236         /* Init the rx queue in hardware */
 237         err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
 238         if (err) {
 239                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
 240                 goto fail_mem;
 241         }
 242
 243         /* switch on rx queue */
 244         err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
 245         if (err) {
 246                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
 247                 goto fail_mem;
 248         }
 249
 250         /* reserve memory for the fdir programming packet */
 251         snprintf(z_name, sizeof(z_name), "%s_%s_%d",
 252                         eth_dev->driver->pci_drv.name,
 253                         I40E_FDIR_MZ_NAME,
 254                         eth_dev->data->port_id);
 255         mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
 256         if (!mz) {
 257                 PMD_DRV_LOG(ERR, "Cannot init memzone for "
 258                                  "flow director program packet.");
 259                 err = I40E_ERR_NO_MEMORY;
 260                 goto fail_mem;
 261         }
 262         pf->fdir.prg_pkt = mz->addr;
 263 #ifdef RTE_LIBRTE_XEN_DOM0
 264         pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
 265 #else
 266         pf->fdir.dma_addr = (uint64_t)mz->phys_addr;
 267 #endif
 268         pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
 269         PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
 270                     vsi->base_queue);
 271         return I40E_SUCCESS;
 272
 273 fail_mem:
 274         i40e_dev_rx_queue_release(pf->fdir.rxq);
 275         pf->fdir.rxq = NULL;
 276 fail_setup_rx:
 277         i40e_dev_tx_queue_release(pf->fdir.txq);
 278         pf->fdir.txq = NULL;
 279 fail_setup_tx:
 280         i40e_vsi_release(vsi);
 281         pf->fdir.fdir_vsi = NULL;
 282         return err;
 283 }
 284
 285 /*
 286  * i40e_fdir_teardown - release the Flow Director resources
 287  * @pf: board private structure
 288  */
 289 void
 290 i40e_fdir_teardown(struct i40e_pf *pf)
 291 {
 292         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 293         struct i40e_vsi *vsi;
 294
 295         vsi = pf->fdir.fdir_vsi;
 296         i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
 297         i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
 298         i40e_dev_rx_queue_release(pf->fdir.rxq);
 299         pf->fdir.rxq = NULL;
 300         i40e_dev_tx_queue_release(pf->fdir.txq);
 301         pf->fdir.txq = NULL;
 302         i40e_vsi_release(vsi);
 303         pf->fdir.fdir_vsi = NULL;
 304 }
 305
 306 /* check whether the flow director table in empty */
 307 static inline int
 308 i40e_fdir_empty(struct i40e_hw *hw)
 309 {
 310         uint32_t guarant_cnt, best_cnt;
 311
 312         guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 313                                  I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
 314                                  I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
 315         best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 316                               I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
 317                               I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
 318         if (best_cnt + guarant_cnt > 0)
 319                 return -1;
 320
 321         return 0;
 322 }
 323
 324 /*
 325  * Initialize the configuration about bytes stream extracted as flexible payload
 326  * and mask setting
 327  */
 328 static inline void
 329 i40e_init_flx_pld(struct i40e_pf *pf)
 330 {
 331         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 332         uint8_t pctype;
 333         int i, index;
 334
 335         /*
 336          * Define the bytes stream extracted as flexible payload in
 337          * field vector. By default, select 8 words from the beginning
 338          * of payload as flexible payload.
 339          */
 340         for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
 341                 index = i * I40E_MAX_FLXPLD_FIED;
 342                 pf->fdir.flex_set[index].src_offset = 0;
 343                 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
 344                 pf->fdir.flex_set[index].dst_offset = 0;
 345                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
 346                 I40E_WRITE_REG(hw,
 347                         I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
 348                 I40E_WRITE_REG(hw,
 349                         I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
 350         }
 351
 352         /* initialize the masks */
 353         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 354              pctype <= I40E_FILTER_PCTYPE_FRAG_IPV6; pctype++) {
 355                 pf->fdir.flex_mask[pctype].word_mask = 0;
 356                 I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
 357                 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
 358                         pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
 359                         pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
 360                         I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
 361                 }
 362         }
 363 }
 364
 365 /*
 366  * Configure flow director related setting
 367  */
 368 int
 369 i40e_fdir_configure(struct rte_eth_dev *dev)
 370 {
 371         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 372         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 373         uint32_t val;
 374         int ret = 0;
 375
 376         /*
 377         * configuration need to be done before
 378         * flow director filters are added
 379         * If filters exist, flush them.
 380         */
 381         if (i40e_fdir_empty(hw) < 0) {
 382                 ret = i40e_fdir_flush(dev);
 383                 if (ret) {
 384                         PMD_DRV_LOG(ERR, "failed to flush fdir table.");
 385                         return ret;
 386                 }
 387         }
 388
 389         val = I40E_READ_REG(hw, I40E_PFQF_CTL_0);
 390         if ((pf->flags & I40E_FLAG_FDIR) &&
 391                 dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 392                 /* enable FDIR filter */
 393                 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
 394                 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val);
 395
 396                 i40e_init_flx_pld(pf); /* set flex config to default value */
 397         } else {
 398                 /* disable FDIR filter */
 399                 val &= ~I40E_PFQF_CTL_0_FD_ENA_MASK;
 400                 I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val);
 401                 pf->flags &= ~I40E_FLAG_FDIR;
 402         }
 403
 404         return ret;
 405 }
 406
 407 static inline void
 408 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 409                                unsigned char *raw_pkt)
 410 {
 411         struct ether_hdr *ether = (struct ether_hdr *)raw_pkt;
 412         struct ipv4_hdr *ip;
 413         struct ipv6_hdr *ip6;
 414         static const uint8_t next_proto[] = {
 415                 [RTE_ETH_FLOW_TYPE_UDPV4] = IPPROTO_UDP,
 416                 [RTE_ETH_FLOW_TYPE_TCPV4] = IPPROTO_TCP,
 417                 [RTE_ETH_FLOW_TYPE_SCTPV4] = IPPROTO_SCTP,
 418                 [RTE_ETH_FLOW_TYPE_IPV4_OTHER] = IPPROTO_IP,
 419                 [RTE_ETH_FLOW_TYPE_FRAG_IPV4] = IPPROTO_IP,
 420                 [RTE_ETH_FLOW_TYPE_UDPV6] = IPPROTO_UDP,
 421                 [RTE_ETH_FLOW_TYPE_TCPV6] = IPPROTO_TCP,
 422                 [RTE_ETH_FLOW_TYPE_SCTPV6] = IPPROTO_SCTP,
 423                 [RTE_ETH_FLOW_TYPE_IPV6_OTHER] = IPPROTO_NONE,
 424                 [RTE_ETH_FLOW_TYPE_FRAG_IPV6] = IPPROTO_NONE,
 425         };
 426
 427         switch (fdir_input->flow_type) {
 428         case RTE_ETH_FLOW_TYPE_UDPV4:
 429         case RTE_ETH_FLOW_TYPE_TCPV4:
 430         case RTE_ETH_FLOW_TYPE_SCTPV4:
 431         case RTE_ETH_FLOW_TYPE_IPV4_OTHER:
 432         case RTE_ETH_FLOW_TYPE_FRAG_IPV4:
 433                 ip = (struct ipv4_hdr *)(raw_pkt + sizeof(struct ether_hdr));
 434
 435                 ether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
 436                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
 437                 /* set len to by default */
 438                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
 439                 ip->time_to_live = I40E_FDIR_IP_DEFAULT_TTL;
 440                 /*
 441                  * The source and destination fields in the transmitted packet
 442                  * need to be presented in a reversed order with respect
 443                  * to the expected received packets.
 444                  */
 445                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
 446                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
 447                 ip->next_proto_id = next_proto[fdir_input->flow_type];
 448                 break;
 449         case RTE_ETH_FLOW_TYPE_UDPV6:
 450         case RTE_ETH_FLOW_TYPE_TCPV6:
 451         case RTE_ETH_FLOW_TYPE_SCTPV6:
 452         case RTE_ETH_FLOW_TYPE_IPV6_OTHER:
 453         case RTE_ETH_FLOW_TYPE_FRAG_IPV6:
 454                 ip6 = (struct ipv6_hdr *)(raw_pkt + sizeof(struct ether_hdr));
 455
 456                 ether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
 457                 ip6->vtc_flow =
 458                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW);
 459                 ip6->payload_len =
 460                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 461                 ip6->hop_limits = I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
 462
 463                 /*
 464                  * The source and destination fields in the transmitted packet
 465                  * need to be presented in a reversed order with respect
 466                  * to the expected received packets.
 467                  */
 468                 rte_memcpy(&(ip6->src_addr),
 469                            &(fdir_input->flow.ip6_flow.dst_ip),
 470                            IPV6_ADDR_LEN);
 471                 rte_memcpy(&(ip6->dst_addr),
 472                            &(fdir_input->flow.ip6_flow.src_ip),
 473                            IPV6_ADDR_LEN);
 474                 ip6->proto = next_proto[fdir_input->flow_type];
 475                 break;
 476         default:
 477                 PMD_DRV_LOG(ERR, "unknown flow type %u.",
 478                             fdir_input->flow_type);
 479                 break;
 480         }
 481 }
 482
 483
 484 /*
 485  * i40e_fdir_construct_pkt - construct packet based on fields in input
 486  * @pf: board private structure
 487  * @fdir_input: input set of the flow director entry
 488  * @raw_pkt: a packet to be constructed
 489  */
 490 static int
 491 i40e_fdir_construct_pkt(struct i40e_pf *pf,
 492                              const struct rte_eth_fdir_input *fdir_input,
 493                              unsigned char *raw_pkt)
 494 {
 495         unsigned char *payload, *ptr;
 496         struct udp_hdr *udp;
 497         struct tcp_hdr *tcp;
 498         struct sctp_hdr *sctp;
 499         uint8_t size, dst = 0;
 500         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
 501
 502         /* fill the ethernet and IP head */
 503         i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt);
 504
 505         /* fill the L4 head */
 506         switch (fdir_input->flow_type) {
 507         case RTE_ETH_FLOW_TYPE_UDPV4:
 508                 udp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 509                                 sizeof(struct ipv4_hdr));
 510                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 511                 /*
 512                  * The source and destination fields in the transmitted packet
 513                  * need to be presented in a reversed order with respect
 514                  * to the expected received packets.
 515                  */
 516                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
 517                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
 518                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
 519                 break;
 520
 521         case RTE_ETH_FLOW_TYPE_TCPV4:
 522                 tcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 523                                          sizeof(struct ipv4_hdr));
 524                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 525                 /*
 526                  * The source and destination fields in the transmitted packet
 527                  * need to be presented in a reversed order with respect
 528                  * to the expected received packets.
 529                  */
 530                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
 531                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
 532                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 533                 break;
 534
 535         case RTE_ETH_FLOW_TYPE_SCTPV4:
 536                 sctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 537                                            sizeof(struct ipv4_hdr));
 538                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 539                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
 540                 break;
 541
 542         case RTE_ETH_FLOW_TYPE_IPV4_OTHER:
 543         case RTE_ETH_FLOW_TYPE_FRAG_IPV4:
 544                 payload = raw_pkt + sizeof(struct ether_hdr) +
 545                           sizeof(struct ipv4_hdr);
 546                 set_idx = I40E_FLXPLD_L3_IDX;
 547                 break;
 548
 549         case RTE_ETH_FLOW_TYPE_UDPV6:
 550                 udp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 551                                          sizeof(struct ipv6_hdr));
 552                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 553                 /*
 554                  * The source and destination fields in the transmitted packet
 555                  * need to be presented in a reversed order with respect
 556                  * to the expected received packets.
 557                  */
 558                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
 559                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
 560                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 561                 break;
 562
 563         case RTE_ETH_FLOW_TYPE_TCPV6:
 564                 tcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 565                                          sizeof(struct ipv6_hdr));
 566                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 567                 /*
 568                  * The source and destination fields in the transmitted packet
 569                  * need to be presented in a reversed order with respect
 570                  * to the expected received packets.
 571                  */
 572                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 573                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
 574                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
 575                 break;
 576
 577         case RTE_ETH_FLOW_TYPE_SCTPV6:
 578                 sctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 579                                            sizeof(struct ipv6_hdr));
 580                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 581                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
 582                 break;
 583
 584         case RTE_ETH_FLOW_TYPE_IPV6_OTHER:
 585         case RTE_ETH_FLOW_TYPE_FRAG_IPV6:
 586                 payload = raw_pkt + sizeof(struct ether_hdr) +
 587                           sizeof(struct ipv6_hdr);
 588                 set_idx = I40E_FLXPLD_L3_IDX;
 589                 break;
 590         default:
 591                 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
 592                 return -EINVAL;
 593         }
 594
 595         /* fill the flexbytes to payload */
 596         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
 597                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
 598                 size = pf->fdir.flex_set[pit_idx].size;
 599                 if (size == 0)
 600                         continue;
 601                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
 602                 ptr = payload +
 603                         pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
 604                 (void)rte_memcpy(ptr,
 605                                  &fdir_input->flow_ext.flexbytes[dst],
 606                                  size * sizeof(uint16_t));
 607         }
 608
 609         return 0;
 610 }
 611
 612 /* Construct the tx flags */
 613 static inline uint64_t
 614 i40e_build_ctob(uint32_t td_cmd,
 615                 uint32_t td_offset,
 616                 unsigned int size,
 617                 uint32_t td_tag)
 618 {
 619         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 620                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 621                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 622                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 623                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 624 }
 625
 626 /*
 627  * check the programming status descriptor in rx queue.
 628  * done after Programming Flow Director is programmed on
 629  * tx queue
 630  */
 631 static inline int
 632 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
 633 {
 634         volatile union i40e_rx_desc *rxdp;
 635         uint64_t qword1;
 636         uint32_t rx_status;
 637         uint32_t len, id;
 638         uint32_t error;
 639         int ret = 0;
 640
 641         rxdp = &rxq->rx_ring[rxq->rx_tail];
 642         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 643         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 644                         >> I40E_RXD_QW1_STATUS_SHIFT;
 645
 646         if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
 647                 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
 648                 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
 649                             I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
 650
 651                 if (len  == I40E_RX_PROG_STATUS_DESC_LENGTH &&
 652                     id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
 653                         error = (qword1 &
 654                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
 655                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
 656                         if (error == (0x1 <<
 657                                 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
 658                                 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
 659                                             " (FD_ID %u): programming status"
 660                                             " reported.",
 661                                             rxdp->wb.qword0.hi_dword.fd_id);
 662                                 ret = -1;
 663                         } else if (error == (0x1 <<
 664                                 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
 665                                 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
 666                                             " (FD_ID %u): programming status"
 667                                             " reported.",
 668                                             rxdp->wb.qword0.hi_dword.fd_id);
 669                                 ret = -1;
 670                         } else
 671                                 PMD_DRV_LOG(ERR, "invalid programming status"
 672                                             " reported, error = %u.", error);
 673                 } else
 674                         PMD_DRV_LOG(ERR, "unknown programming status"
 675                                     " reported, len = %d, id = %u.", len, id);
 676                 rxdp->wb.qword1.status_error_len = 0;
 677                 rxq->rx_tail++;
 678                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
 679                         rxq->rx_tail = 0;
 680         }
 681         return ret;
 682 }
 683
 684 /*
 685  * i40e_add_del_fdir_filter - add or remove a flow director filter.
 686  * @pf: board private structure
 687  * @filter: fdir filter entry
 688  * @add: 0 - delete, 1 - add
 689  */
 690 static int
 691 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
 692                             const struct rte_eth_fdir_filter *filter,
 693                             bool add)
 694 {
 695         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 696         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
 697         enum i40e_filter_pctype pctype;
 698         int ret = 0;
 699
 700         if (!(pf->flags & I40E_FLAG_FDIR)) {
 701                 PMD_DRV_LOG(ERR, "FDIR is not enabled.");
 702                 return -ENOTSUP;
 703         }
 704         if (!I40E_VALID_FLOW_TYPE(filter->input.flow_type)) {
 705                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
 706                 return -EINVAL;
 707         }
 708         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
 709                 PMD_DRV_LOG(ERR, "Invalid queue ID");
 710                 return -EINVAL;
 711         }
 712
 713         memset(pkt, 0, I40E_FDIR_PKT_LEN);
 714
 715         ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
 716         if (ret < 0) {
 717                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
 718                 return ret;
 719         }
 720         pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
 721         ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
 722         if (ret < 0) {
 723                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
 724                             pctype);
 725                 return ret;
 726         }
 727         return ret;
 728 }
 729
 730 /*
 731  * i40e_fdir_filter_programming - Program a flow director filter rule.
 732  * Is done by Flow Director Programming Descriptor followed by packet
 733  * structure that contains the filter fields need to match.
 734  * @pf: board private structure
 735  * @pctype: pctype
 736  * @filter: fdir filter entry
 737  * @add: 0 - delelet, 1 - add
 738  */
 739 static int
 740 i40e_fdir_filter_programming(struct i40e_pf *pf,
 741                         enum i40e_filter_pctype pctype,
 742                         const struct rte_eth_fdir_filter *filter,
 743                         bool add)
 744 {
 745         struct i40e_tx_queue *txq = pf->fdir.txq;
 746         struct i40e_rx_queue *rxq = pf->fdir.rxq;
 747         const struct rte_eth_fdir_action *fdir_action = &filter->action;
 748         volatile struct i40e_tx_desc *txdp;
 749         volatile struct i40e_filter_program_desc *fdirdp;
 750         uint32_t td_cmd;
 751         uint16_t i;
 752         uint8_t dest;
 753
 754         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
 755         fdirdp = (volatile struct i40e_filter_program_desc *)
 756                         (&(txq->tx_ring[txq->tx_tail]));
 757
 758         fdirdp->qindex_flex_ptype_vsi =
 759                         rte_cpu_to_le_32((fdir_action->rx_queue <<
 760                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
 761                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
 762
 763         fdirdp->qindex_flex_ptype_vsi |=
 764                         rte_cpu_to_le_32((fdir_action->flex_off <<
 765                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
 766                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
 767
 768         fdirdp->qindex_flex_ptype_vsi |=
 769                         rte_cpu_to_le_32((pctype <<
 770                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
 771                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
 772
 773         /* Use LAN VSI Id by default */
 774         fdirdp->qindex_flex_ptype_vsi |=
 775                 rte_cpu_to_le_32((pf->main_vsi->vsi_id <<
 776                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
 777                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
 778
 779         fdirdp->dtype_cmd_cntindex =
 780                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
 781
 782         if (add)
 783                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
 784                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
 785                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
 786         else
 787                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
 788                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
 789                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
 790
 791         if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
 792                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
 793         else
 794                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
 795         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
 796                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
 797                                 I40E_TXD_FLTR_QW1_DEST_MASK);
 798
 799         fdirdp->dtype_cmd_cntindex |=
 800                 rte_cpu_to_le_32((fdir_action->report_status<<
 801                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
 802                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
 803
 804         fdirdp->dtype_cmd_cntindex |=
 805                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
 806         fdirdp->dtype_cmd_cntindex |=
 807                         rte_cpu_to_le_32((pf->fdir.match_counter_index <<
 808                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
 809                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
 810
 811         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
 812
 813         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
 814         txdp = &(txq->tx_ring[txq->tx_tail + 1]);
 815         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
 816         td_cmd = I40E_TX_DESC_CMD_EOP |
 817                  I40E_TX_DESC_CMD_RS  |
 818                  I40E_TX_DESC_CMD_DUMMY;
 819
 820         txdp->cmd_type_offset_bsz =
 821                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
 822
 823         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
 824         if (txq->tx_tail >= txq->nb_tx_desc)
 825                 txq->tx_tail = 0;
 826         /* Update the tx tail register */
 827         rte_wmb();
 828         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
 829
 830         for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {
 831                 rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
 832                 if (txdp->cmd_type_offset_bsz &
 833                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
 834                         break;
 835         }
 836         if (i >= I40E_FDIR_WAIT_COUNT) {
 837                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
 838                             " time out to get DD on tx queue.");
 839                 return -ETIMEDOUT;
 840         }
 841         /* totally delay 10 ms to check programming status*/
 842         rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);
 843         if (i40e_check_fdir_programming_status(rxq) < 0) {
 844                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
 845                             " programming status reported.");
 846                 return -ENOSYS;
 847         }
 848
 849         return 0;
 850 }
 851
 852 /*
 853  * i40e_fdir_flush - clear all filters of Flow Director table
 854  * @pf: board private structure
 855  */
 856 static int
 857 i40e_fdir_flush(struct rte_eth_dev *dev)
 858 {
 859         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 860         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 861         uint32_t reg;
 862         uint16_t guarant_cnt, best_cnt;
 863         uint16_t i;
 864
 865         I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
 866         I40E_WRITE_FLUSH(hw);
 867
 868         for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
 869                 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
 870                 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
 871                 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
 872                         break;
 873         }
 874         if (i >= I40E_FDIR_FLUSH_RETRY) {
 875                 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
 876                 return -ETIMEDOUT;
 877         }
 878         guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 879                                 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
 880                                 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
 881         best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 882                                 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
 883                                 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
 884         if (guarant_cnt != 0 || best_cnt != 0) {
 885                 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
 886                 return -ENOSYS;
 887         } else
 888                 PMD_DRV_LOG(INFO, "FD table Flush success.");
 889         return 0;
 890 }
 891
 892 static inline void
 893 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
 894                         struct rte_eth_flex_payload_cfg *flex_set,
 895                         uint16_t *num)
 896 {
 897         struct i40e_fdir_flex_pit *flex_pit;
 898         struct rte_eth_flex_payload_cfg *ptr = flex_set;
 899         uint16_t src, dst, size, j, k;
 900         uint8_t i, layer_idx;
 901
 902         for (layer_idx = I40E_FLXPLD_L2_IDX;
 903              layer_idx <= I40E_FLXPLD_L4_IDX;
 904              layer_idx++) {
 905                 if (layer_idx == I40E_FLXPLD_L2_IDX)
 906                         ptr->type = RTE_ETH_L2_PAYLOAD;
 907                 else if (layer_idx == I40E_FLXPLD_L3_IDX)
 908                         ptr->type = RTE_ETH_L3_PAYLOAD;
 909                 else if (layer_idx == I40E_FLXPLD_L4_IDX)
 910                         ptr->type = RTE_ETH_L4_PAYLOAD;
 911
 912                 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
 913                         flex_pit = &pf->fdir.flex_set[layer_idx *
 914                                 I40E_MAX_FLXPLD_FIED + i];
 915                         if (flex_pit->size == 0)
 916                                 continue;
 917                         src = flex_pit->src_offset * sizeof(uint16_t);
 918                         dst = flex_pit->dst_offset * sizeof(uint16_t);
 919                         size = flex_pit->size * sizeof(uint16_t);
 920                         for (j = src, k = dst; j < src + size; j++, k++)
 921                                 ptr->src_offset[k] = j;
 922                 }
 923                 (*num)++;
 924                 ptr++;
 925         }
 926 }
 927
 928 static inline void
 929 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
 930                         struct rte_eth_fdir_flex_mask *flex_mask,
 931                         uint16_t *num)
 932 {
 933         struct i40e_fdir_flex_mask *mask;
 934         struct rte_eth_fdir_flex_mask *ptr = flex_mask;
 935         enum rte_eth_flow_type flow_type;
 936         uint8_t i, j;
 937         uint16_t off_bytes, mask_tmp;
 938
 939         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 940              i <= I40E_FILTER_PCTYPE_FRAG_IPV6;
 941              i++) {
 942                 mask =  &pf->fdir.flex_mask[i];
 943                 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
 944                         continue;
 945                 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
 946                 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
 947                         if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
 948                                 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
 949                                 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
 950                         } else {
 951                                 ptr->mask[j * sizeof(uint16_t)] = 0x0;
 952                                 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
 953                         }
 954                 }
 955                 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
 956                         off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
 957                         mask_tmp = ~mask->bitmask[j].mask;
 958                         ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
 959                         ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
 960                 }
 961                 ptr->flow_type = flow_type;
 962                 ptr++;
 963                 (*num)++;
 964         }
 965 }
 966
 967 /*
 968  * i40e_fdir_info_get - get information of Flow Director
 969  * @pf: ethernet device to get info from
 970  * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
 971  *    the flow director information.
 972  */
 973 static void
 974 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
 975 {
 976         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 977         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 978         uint16_t num_flex_set = 0;
 979         uint16_t num_flex_mask = 0;
 980
 981         fdir->mode = (pf->flags & I40E_FLAG_FDIR) ?
 982                         RTE_FDIR_MODE_PERFECT : RTE_FDIR_MODE_NONE;
 983         fdir->guarant_spc =
 984                 (uint32_t)hw->func_caps.fd_filters_guaranteed;
 985         fdir->best_spc =
 986                 (uint32_t)hw->func_caps.fd_filters_best_effort;
 987         fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
 988         fdir->flow_types_mask[0] = I40E_FDIR_FLOW_TYPES;
 989         fdir->flex_payload_unit = sizeof(uint16_t);
 990         fdir->flex_bitmask_unit = sizeof(uint16_t);
 991         fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
 992         fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
 993         fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
 994
 995         i40e_fdir_info_get_flex_set(pf,
 996                                 fdir->flex_conf.flex_set,
 997                                 &num_flex_set);
 998         i40e_fdir_info_get_flex_mask(pf,
 999                                 fdir->flex_conf.flex_mask,
1000                                 &num_flex_mask);
1001
1002         fdir->flex_conf.nb_payloads = num_flex_set;
1003         fdir->flex_conf.nb_flexmasks = num_flex_mask;
1004 }
1005
1006 /*
1007  * i40e_fdir_ctrl_func - deal with all operations on flow director.
1008  * @pf: board private structure
1009  * @filter_op:operation will be taken.
1010  * @arg: a pointer to specific structure corresponding to the filter_op
1011  */
1012 int
1013 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1014                        enum rte_filter_op filter_op,
1015                        void *arg)
1016 {
1017         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1018         int ret = 0;
1019
1020         if (filter_op == RTE_ETH_FILTER_NOP) {
1021                 if (!(pf->flags & I40E_FLAG_FDIR))
1022                         ret = -ENOTSUP;
1023                 return ret;
1024         }
1025
1026         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1027                 return -EINVAL;
1028
1029         switch (filter_op) {
1030         case RTE_ETH_FILTER_ADD:
1031                 ret = i40e_add_del_fdir_filter(dev,
1032                         (struct rte_eth_fdir_filter *)arg,
1033                         TRUE);
1034                 break;
1035         case RTE_ETH_FILTER_DELETE:
1036                 ret = i40e_add_del_fdir_filter(dev,
1037                         (struct rte_eth_fdir_filter *)arg,
1038                         FALSE);
1039                 break;
1040         case RTE_ETH_FILTER_FLUSH:
1041                 ret = i40e_fdir_flush(dev);
1042                 break;
1043         case RTE_ETH_FILTER_INFO:
1044                 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1045                 break;
1046         default:
1047                 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
1048                 ret = -EINVAL;
1049                 break;
1050         }
1051         return ret;
1052 }