4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 #include <sys/queue.h>
43 #include <rte_string_fns.h>
45 #include <rte_ether.h>
46 #include <rte_ethdev.h>
47 #include <rte_memzone.h>
48 #include <rte_malloc.h>
49 #include <rte_memcpy.h>
51 #include "i40e_logs.h"
52 #include "i40e/i40e_prototype.h"
53 #include "i40e/i40e_adminq_cmd.h"
54 #include "i40e/i40e_type.h"
55 #include "i40e_ethdev.h"
56 #include "i40e_rxtx.h"
60 i40e_pf_host_switch_queues(struct i40e_pf_vf *vf,
61 struct i40e_virtchnl_queue_select *qsel,
65 * Bind PF queues with VSI and VF.
68 i40e_pf_vf_queues_mapping(struct i40e_pf_vf *vf)
71 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
72 uint16_t vsi_id = vf->vsi->vsi_id;
73 uint16_t vf_id = vf->vf_idx;
74 uint16_t nb_qps = vf->vsi->nb_qps;
75 uint16_t qbase = vf->vsi->base_queue;
80 * VF should use scatter range queues. So, it needn't
81 * to set QBASE in this register.
83 I40E_WRITE_REG(hw, I40E_VSILAN_QBASE(vsi_id),
84 I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
86 /* Set to enable VFLAN_QTABLE[] registers valid */
87 I40E_WRITE_REG(hw, I40E_VPLAN_MAPENA(vf_id),
88 I40E_VPLAN_MAPENA_TXRX_ENA_MASK);
90 /* map PF queues to VF */
91 for (i = 0; i < nb_qps; i++) {
92 val = ((qbase + i) & I40E_VPLAN_QTABLE_QINDEX_MASK);
93 I40E_WRITE_REG(hw, I40E_VPLAN_QTABLE(i, vf_id), val);
96 /* map PF queues to VSI */
97 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF / 2; i++) {
98 if (2 * i > nb_qps - 1)
99 q1 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;
103 if (2 * i + 1 > nb_qps - 1)
104 q2 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;
106 q2 = qbase + 2 * i + 1;
108 val = (q2 << I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) + q1;
109 I40E_WRITE_REG(hw, I40E_VSILAN_QTABLE(i, vsi_id), val);
111 I40E_WRITE_FLUSH(hw);
118 * Proceed VF reset operation.
121 i40e_pf_host_vf_reset(struct i40e_pf_vf *vf, bool do_hw_reset)
124 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
125 uint16_t vf_id, abs_vf_id, vf_msix_num;
127 struct i40e_virtchnl_queue_select qsel;
133 abs_vf_id = vf_id + hw->func_caps.vf_base_id;
135 /* Notify VF that we are in VFR progress */
136 I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), I40E_PF_VFR_INPROGRESS);
139 * If require a SW VF reset, a VFLR interrupt will be generated,
140 * this function will be called again. To avoid it,
141 * disable interrupt first.
144 vf->state = I40E_VF_INRESET;
145 val = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));
146 val |= I40E_VPGEN_VFRTRIG_VFSWR_MASK;
147 I40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);
148 I40E_WRITE_FLUSH(hw);
151 #define VFRESET_MAX_WAIT_CNT 100
152 /* Wait until VF reset is done */
153 for (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {
155 val = I40E_READ_REG(hw, I40E_VPGEN_VFRSTAT(vf_id));
156 if (val & I40E_VPGEN_VFRSTAT_VFRD_MASK)
160 if (i >= VFRESET_MAX_WAIT_CNT) {
161 PMD_DRV_LOG(ERR, "VF reset timeout");
165 /* This is not first time to do reset, do cleanup job first */
168 memset(&qsel, 0, sizeof(qsel));
169 for (i = 0; i < vf->vsi->nb_qps; i++)
170 qsel.rx_queues |= 1 << i;
171 qsel.tx_queues = qsel.rx_queues;
172 ret = i40e_pf_host_switch_queues(vf, &qsel, false);
173 if (ret != I40E_SUCCESS) {
174 PMD_DRV_LOG(ERR, "Disable VF queues failed");
178 /* Disable VF interrupt setting */
179 vf_msix_num = hw->func_caps.num_msix_vectors_vf;
180 for (i = 0; i < vf_msix_num; i++) {
182 val = I40E_VFINT_DYN_CTL0(vf_id);
184 val = I40E_VFINT_DYN_CTLN(((vf_msix_num - 1) *
186 I40E_WRITE_REG(hw, val, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
188 I40E_WRITE_FLUSH(hw);
191 ret = i40e_vsi_release(vf->vsi);
192 if (ret != I40E_SUCCESS) {
193 PMD_DRV_LOG(ERR, "Release VSI failed");
198 #define I40E_VF_PCI_ADDR 0xAA
199 #define I40E_VF_PEND_MASK 0x20
200 /* Check the pending transactions of this VF */
201 /* Use absolute VF id, refer to datasheet for details */
202 I40E_WRITE_REG(hw, I40E_PF_PCI_CIAA, I40E_VF_PCI_ADDR |
203 (abs_vf_id << I40E_PF_PCI_CIAA_VF_NUM_SHIFT));
204 for (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {
206 val = I40E_READ_REG(hw, I40E_PF_PCI_CIAD);
207 if ((val & I40E_VF_PEND_MASK) == 0)
211 if (i >= VFRESET_MAX_WAIT_CNT) {
212 PMD_DRV_LOG(ERR, "Wait VF PCI transaction end timeout");
216 /* Reset done, Set COMPLETE flag and clear reset bit */
217 I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), I40E_PF_VFR_COMPLETED);
218 val = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));
219 val &= ~I40E_VPGEN_VFRTRIG_VFSWR_MASK;
220 I40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);
222 I40E_WRITE_FLUSH(hw);
224 /* Allocate resource again */
225 vf->vsi = i40e_vsi_setup(vf->pf, I40E_VSI_SRIOV,
226 vf->pf->main_vsi, vf->vf_idx);
227 if (vf->vsi == NULL) {
228 PMD_DRV_LOG(ERR, "Add vsi failed");
232 ret = i40e_pf_vf_queues_mapping(vf);
233 if (ret != I40E_SUCCESS) {
234 PMD_DRV_LOG(ERR, "queue mapping error");
235 i40e_vsi_release(vf->vsi);
243 i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf,
249 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
250 uint16_t abs_vf_id = hw->func_caps.vf_base_id + vf->vf_idx;
253 ret = i40e_aq_send_msg_to_vf(hw, abs_vf_id, opcode, retval,
256 PMD_INIT_LOG(ERR, "Fail to send message to VF, err %u",
257 hw->aq.asq_last_status);
264 i40e_pf_host_process_cmd_version(struct i40e_pf_vf *vf)
266 struct i40e_virtchnl_version_info info;
268 info.major = I40E_DPDK_VERSION_MAJOR;
269 info.minor = I40E_DPDK_VERSION_MINOR;
270 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_VERSION,
271 I40E_SUCCESS, (uint8_t *)&info, sizeof(info));
275 i40e_pf_host_process_cmd_reset_vf(struct i40e_pf_vf *vf)
277 i40e_pf_host_vf_reset(vf, 1);
279 /* No feedback will be sent to VF for VFLR */
284 i40e_pf_host_process_cmd_get_vf_resource(struct i40e_pf_vf *vf)
286 struct i40e_virtchnl_vf_resource *vf_res = NULL;
287 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
289 int ret = I40E_SUCCESS;
291 /* only have 1 VSI by default */
292 len = sizeof(struct i40e_virtchnl_vf_resource) +
293 I40E_DEFAULT_VF_VSI_NUM *
294 sizeof(struct i40e_virtchnl_vsi_resource);
296 vf_res = rte_zmalloc("i40e_vf_res", len, 0);
297 if (vf_res == NULL) {
298 PMD_DRV_LOG(ERR, "failed to allocate mem");
299 ret = I40E_ERR_NO_MEMORY;
305 vf_res->vf_offload_flags = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
306 I40E_VIRTCHNL_VF_OFFLOAD_VLAN;
307 vf_res->max_vectors = hw->func_caps.num_msix_vectors_vf;
308 vf_res->num_queue_pairs = vf->vsi->nb_qps;
309 vf_res->num_vsis = I40E_DEFAULT_VF_VSI_NUM;
311 /* Change below setting if PF host can support more VSIs for VF */
312 vf_res->vsi_res[0].vsi_type = I40E_VSI_SRIOV;
313 /* As assume Vf only has single VSI now, always return 0 */
314 vf_res->vsi_res[0].vsi_id = 0;
315 vf_res->vsi_res[0].num_queue_pairs = vf->vsi->nb_qps;
318 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_GET_VF_RESOURCES,
319 ret, (uint8_t *)vf_res, len);
326 i40e_pf_host_hmc_config_rxq(struct i40e_hw *hw,
327 struct i40e_pf_vf *vf,
328 struct i40e_virtchnl_rxq_info *rxq)
330 int err = I40E_SUCCESS;
331 struct i40e_hmc_obj_rxq rx_ctx;
332 uint16_t abs_queue_id = vf->vsi->base_queue + rxq->queue_id;
334 /* Clear the context structure first */
335 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
336 rx_ctx.dbuff = rxq->databuffer_size >> I40E_RXQ_CTX_DBUFF_SHIFT;
337 rx_ctx.hbuff = rxq->hdr_size >> I40E_RXQ_CTX_HBUFF_SHIFT;
338 rx_ctx.base = rxq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;
339 rx_ctx.qlen = rxq->ring_len;
340 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
344 if (rxq->splithdr_enabled) {
345 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
346 rx_ctx.dtype = i40e_header_split_enabled;
348 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
349 rx_ctx.dtype = i40e_header_split_none;
351 rx_ctx.rxmax = rxq->max_pkt_size;
352 rx_ctx.tphrdesc_ena = 1;
353 rx_ctx.tphwdesc_ena = 1;
354 rx_ctx.tphdata_ena = 1;
355 rx_ctx.tphhead_ena = 1;
356 rx_ctx.lrxqthresh = 2;
361 err = i40e_clear_lan_rx_queue_context(hw, abs_queue_id);
362 if (err != I40E_SUCCESS)
364 err = i40e_set_lan_rx_queue_context(hw, abs_queue_id, &rx_ctx);
370 i40e_pf_host_hmc_config_txq(struct i40e_hw *hw,
371 struct i40e_pf_vf *vf,
372 struct i40e_virtchnl_txq_info *txq)
374 int err = I40E_SUCCESS;
375 struct i40e_hmc_obj_txq tx_ctx;
377 uint16_t abs_queue_id = vf->vsi->base_queue + txq->queue_id;
380 /* clear the context structure first */
381 memset(&tx_ctx, 0, sizeof(tx_ctx));
382 tx_ctx.new_context = 1;
383 tx_ctx.base = txq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;
384 tx_ctx.qlen = txq->ring_len;
385 tx_ctx.rdylist = rte_le_to_cpu_16(vf->vsi->info.qs_handle[0]);
386 err = i40e_clear_lan_tx_queue_context(hw, abs_queue_id);
387 if (err != I40E_SUCCESS)
390 err = i40e_set_lan_tx_queue_context(hw, abs_queue_id, &tx_ctx);
391 if (err != I40E_SUCCESS)
394 /* bind queue with VF function, since TX/QX will appear in pair,
395 * so only has QTX_CTL to set.
397 qtx_ctl = (I40E_QTX_CTL_VF_QUEUE << I40E_QTX_CTL_PFVF_Q_SHIFT) |
398 ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
399 I40E_QTX_CTL_PF_INDX_MASK) |
400 (((vf->vf_idx + hw->func_caps.vf_base_id) <<
401 I40E_QTX_CTL_VFVM_INDX_SHIFT) &
402 I40E_QTX_CTL_VFVM_INDX_MASK);
403 I40E_WRITE_REG(hw, I40E_QTX_CTL(abs_queue_id), qtx_ctl);
404 I40E_WRITE_FLUSH(hw);
410 i40e_pf_host_process_cmd_config_vsi_queues(struct i40e_pf_vf *vf,
414 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
415 struct i40e_vsi *vsi = vf->vsi;
416 int ret = I40E_SUCCESS;
417 struct i40e_virtchnl_vsi_queue_config_info *qconfig =
418 (struct i40e_virtchnl_vsi_queue_config_info *)msg;
420 struct i40e_virtchnl_queue_pair_info *qpair;
422 if (msg == NULL || msglen <= sizeof(*qconfig) ||
423 qconfig->num_queue_pairs > vsi->nb_qps) {
424 PMD_DRV_LOG(ERR, "vsi_queue_config_info argument wrong");
425 ret = I40E_ERR_PARAM;
429 qpair = qconfig->qpair;
430 for (i = 0; i < qconfig->num_queue_pairs; i++) {
431 if (qpair[i].rxq.queue_id > vsi->nb_qps - 1 ||
432 qpair[i].txq.queue_id > vsi->nb_qps - 1) {
433 ret = I40E_ERR_PARAM;
437 /* Apply VF RX queue setting to HMC */
438 if (i40e_pf_host_hmc_config_rxq(hw, vf, &qpair[i].rxq)
440 PMD_DRV_LOG(ERR, "Configure RX queue HMC failed");
441 ret = I40E_ERR_PARAM;
445 /* Apply VF TX queue setting to HMC */
446 if (i40e_pf_host_hmc_config_txq(hw, vf, &qpair[i].txq)
448 PMD_DRV_LOG(ERR, "Configure TX queue HMC failed");
449 ret = I40E_ERR_PARAM;
455 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES,
461 i40e_pf_host_process_cmd_config_irq_map(struct i40e_pf_vf *vf,
462 uint8_t *msg, uint16_t msglen)
464 int ret = I40E_SUCCESS;
465 struct i40e_virtchnl_irq_map_info *irqmap =
466 (struct i40e_virtchnl_irq_map_info *)msg;
468 if (msg == NULL || msglen < sizeof(struct i40e_virtchnl_irq_map_info)) {
469 PMD_DRV_LOG(ERR, "buffer too short");
470 ret = I40E_ERR_PARAM;
474 /* Assume VF only have 1 vector to bind all queues */
475 if (irqmap->num_vectors != 1) {
476 PMD_DRV_LOG(ERR, "DKDK host only support 1 vector");
477 ret = I40E_ERR_PARAM;
481 if (irqmap->vecmap[0].vector_id == 0) {
482 PMD_DRV_LOG(ERR, "DPDK host don't support use IRQ0");
483 ret = I40E_ERR_PARAM;
486 /* This MSIX intr store the intr in VF range */
487 vf->vsi->msix_intr = irqmap->vecmap[0].vector_id;
489 /* Don't care how the TX/RX queue mapping with this vector.
490 * Link all VF RX queues together. Only did mapping work.
491 * VF can disable/enable the intr by itself.
493 i40e_vsi_queues_bind_intr(vf->vsi);
495 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP,
502 i40e_pf_host_switch_queues(struct i40e_pf_vf *vf,
503 struct i40e_virtchnl_queue_select *qsel,
506 int ret = I40E_SUCCESS;
508 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
509 uint16_t baseq = vf->vsi->base_queue;
511 if (qsel->rx_queues + qsel->tx_queues == 0)
512 return I40E_ERR_PARAM;
514 /* always enable RX first and disable last */
515 /* Enable RX if it's enable */
517 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
518 if (qsel->rx_queues & (1 << i)) {
519 ret = i40e_switch_rx_queue(hw, baseq + i, on);
520 if (ret != I40E_SUCCESS)
525 /* Enable/Disable TX */
526 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
527 if (qsel->tx_queues & (1 << i)) {
528 ret = i40e_switch_tx_queue(hw, baseq + i, on);
529 if (ret != I40E_SUCCESS)
533 /* disable RX last if it's disable */
536 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
537 if (qsel->rx_queues & (1 << i)) {
538 ret = i40e_switch_rx_queue(hw, baseq + i, on);
539 if (ret != I40E_SUCCESS)
548 i40e_pf_host_process_cmd_enable_queues(struct i40e_pf_vf *vf,
552 int ret = I40E_SUCCESS;
553 struct i40e_virtchnl_queue_select *q_sel =
554 (struct i40e_virtchnl_queue_select *)msg;
556 if (msg == NULL || msglen != sizeof(*q_sel)) {
557 ret = I40E_ERR_PARAM;
560 ret = i40e_pf_host_switch_queues(vf, q_sel, true);
563 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES,
570 i40e_pf_host_process_cmd_disable_queues(struct i40e_pf_vf *vf,
574 int ret = I40E_SUCCESS;
575 struct i40e_virtchnl_queue_select *q_sel =
576 (struct i40e_virtchnl_queue_select *)msg;
578 if (msg == NULL || msglen != sizeof(*q_sel)) {
579 ret = I40E_ERR_PARAM;
582 ret = i40e_pf_host_switch_queues(vf, q_sel, false);
585 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES,
593 i40e_pf_host_process_cmd_add_ether_address(struct i40e_pf_vf *vf,
597 int ret = I40E_SUCCESS;
598 struct i40e_virtchnl_ether_addr_list *addr_list =
599 (struct i40e_virtchnl_ether_addr_list *)msg;
600 struct i40e_mac_filter_info filter;
602 struct ether_addr *mac;
604 memset(&filter, 0 , sizeof(struct i40e_mac_filter_info));
606 if (msg == NULL || msglen <= sizeof(*addr_list)) {
607 PMD_DRV_LOG(ERR, "add_ether_address argument too short");
608 ret = I40E_ERR_PARAM;
612 for (i = 0; i < addr_list->num_elements; i++) {
613 mac = (struct ether_addr *)(addr_list->list[i].addr);
614 (void)rte_memcpy(&filter.mac_addr, mac, ETHER_ADDR_LEN);
615 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
616 if(!is_valid_assigned_ether_addr(mac) ||
617 i40e_vsi_add_mac(vf->vsi, &filter)) {
618 ret = I40E_ERR_INVALID_MAC_ADDR;
624 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS,
631 i40e_pf_host_process_cmd_del_ether_address(struct i40e_pf_vf *vf,
635 int ret = I40E_SUCCESS;
636 struct i40e_virtchnl_ether_addr_list *addr_list =
637 (struct i40e_virtchnl_ether_addr_list *)msg;
639 struct ether_addr *mac;
641 if (msg == NULL || msglen <= sizeof(*addr_list)) {
642 PMD_DRV_LOG(ERR, "delete_ether_address argument too short");
643 ret = I40E_ERR_PARAM;
647 for (i = 0; i < addr_list->num_elements; i++) {
648 mac = (struct ether_addr *)(addr_list->list[i].addr);
649 if(!is_valid_assigned_ether_addr(mac) ||
650 i40e_vsi_delete_mac(vf->vsi, mac)) {
651 ret = I40E_ERR_INVALID_MAC_ADDR;
657 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS,
665 i40e_pf_host_process_cmd_add_vlan(struct i40e_pf_vf *vf,
666 uint8_t *msg, uint16_t msglen)
668 int ret = I40E_SUCCESS;
669 struct i40e_virtchnl_vlan_filter_list *vlan_filter_list =
670 (struct i40e_virtchnl_vlan_filter_list *)msg;
674 if (msg == NULL || msglen <= sizeof(*vlan_filter_list)) {
675 PMD_DRV_LOG(ERR, "add_vlan argument too short");
676 ret = I40E_ERR_PARAM;
680 vid = vlan_filter_list->vlan_id;
682 for (i = 0; i < vlan_filter_list->num_elements; i++) {
683 ret = i40e_vsi_add_vlan(vf->vsi, vid[i]);
684 if(ret != I40E_SUCCESS)
689 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_ADD_VLAN,
696 i40e_pf_host_process_cmd_del_vlan(struct i40e_pf_vf *vf,
700 int ret = I40E_SUCCESS;
701 struct i40e_virtchnl_vlan_filter_list *vlan_filter_list =
702 (struct i40e_virtchnl_vlan_filter_list *)msg;
706 if (msg == NULL || msglen <= sizeof(*vlan_filter_list)) {
707 PMD_DRV_LOG(ERR, "delete_vlan argument too short");
708 ret = I40E_ERR_PARAM;
712 vid = vlan_filter_list->vlan_id;
713 for (i = 0; i < vlan_filter_list->num_elements; i++) {
714 ret = i40e_vsi_delete_vlan(vf->vsi, vid[i]);
715 if(ret != I40E_SUCCESS)
720 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_DEL_VLAN,
727 i40e_pf_host_process_cmd_config_promisc_mode(
728 struct i40e_pf_vf *vf,
732 int ret = I40E_SUCCESS;
733 struct i40e_virtchnl_promisc_info *promisc =
734 (struct i40e_virtchnl_promisc_info *)msg;
735 struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
736 bool unicast = FALSE, multicast = FALSE;
738 if (msg == NULL || msglen != sizeof(*promisc)) {
739 ret = I40E_ERR_PARAM;
743 if (promisc->flags & I40E_FLAG_VF_UNICAST_PROMISC)
745 ret = i40e_aq_set_vsi_unicast_promiscuous(hw,
746 vf->vsi->seid, unicast, NULL);
747 if (ret != I40E_SUCCESS)
750 if (promisc->flags & I40E_FLAG_VF_MULTICAST_PROMISC)
752 ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vf->vsi->seid,
756 i40e_pf_host_send_msg_to_vf(vf,
757 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, ret, NULL, 0);
763 i40e_pf_host_process_cmd_get_stats(struct i40e_pf_vf *vf)
765 i40e_update_vsi_stats(vf->vsi);
767 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_GET_STATS,
768 I40E_SUCCESS, (uint8_t *)&vf->vsi->eth_stats,
769 sizeof(vf->vsi->eth_stats));
775 i40e_pf_host_process_cmd_get_link_status(struct i40e_pf_vf *vf)
777 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vf->pf->main_vsi);
779 /* Update link status first to acquire latest link change */
780 i40e_dev_link_update(dev, 1);
781 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_GET_LINK_STAT,
782 I40E_SUCCESS, (uint8_t *)&dev->data->dev_link,
783 sizeof(struct rte_eth_link));
787 i40e_pf_host_process_cmd_cfg_vlan_offload(
788 struct i40e_pf_vf *vf,
792 int ret = I40E_SUCCESS;
793 struct i40e_virtchnl_vlan_offload_info *offload =
794 (struct i40e_virtchnl_vlan_offload_info *)msg;
796 if (msg == NULL || msglen != sizeof(*offload)) {
797 ret = I40E_ERR_PARAM;
801 ret = i40e_vsi_config_vlan_stripping(vf->vsi,
802 !!offload->enable_vlan_strip);
804 PMD_DRV_LOG(ERR, "Failed to configure vlan stripping");
807 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD,
814 i40e_pf_host_process_cmd_cfg_pvid(struct i40e_pf_vf *vf,
818 int ret = I40E_SUCCESS;
819 struct i40e_virtchnl_pvid_info *tpid_info =
820 (struct i40e_virtchnl_pvid_info *)msg;
822 if (msg == NULL || msglen != sizeof(*tpid_info)) {
823 ret = I40E_ERR_PARAM;
827 ret = i40e_vsi_vlan_pvid_set(vf->vsi, &tpid_info->info);
830 i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CFG_VLAN_PVID,
837 i40e_pf_host_handle_vf_msg(struct rte_eth_dev *dev,
838 uint16_t abs_vf_id, uint32_t opcode,
839 __rte_unused uint32_t retval,
843 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
844 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
845 struct i40e_pf_vf *vf;
846 /* AdminQ will pass absolute VF id, transfer to internal vf id */
847 uint16_t vf_id = abs_vf_id - hw->func_caps.vf_base_id;
849 if (!dev || vf_id > pf->vf_num - 1 || !pf->vfs) {
850 PMD_DRV_LOG(ERR, "invalid argument");
854 vf = &pf->vfs[vf_id];
856 PMD_DRV_LOG(ERR, "NO VSI associated with VF found");
857 i40e_pf_host_send_msg_to_vf(vf, opcode,
858 I40E_ERR_NO_AVAILABLE_VSI, NULL, 0);
863 case I40E_VIRTCHNL_OP_VERSION :
864 PMD_DRV_LOG(INFO, "OP_VERSION received");
865 i40e_pf_host_process_cmd_version(vf);
867 case I40E_VIRTCHNL_OP_RESET_VF :
868 PMD_DRV_LOG(INFO, "OP_RESET_VF received");
869 i40e_pf_host_process_cmd_reset_vf(vf);
871 case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
872 PMD_DRV_LOG(INFO, "OP_GET_VF_RESOURCES received");
873 i40e_pf_host_process_cmd_get_vf_resource(vf);
875 case I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES:
876 PMD_DRV_LOG(INFO, "OP_CONFIG_VSI_QUEUES received");
877 i40e_pf_host_process_cmd_config_vsi_queues(vf,
880 case I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP:
881 PMD_DRV_LOG(INFO, "OP_CONFIG_IRQ_MAP received");
882 i40e_pf_host_process_cmd_config_irq_map(vf, msg, msglen);
884 case I40E_VIRTCHNL_OP_ENABLE_QUEUES:
885 PMD_DRV_LOG(INFO, "OP_ENABLE_QUEUES received");
886 i40e_pf_host_process_cmd_enable_queues(vf,
889 case I40E_VIRTCHNL_OP_DISABLE_QUEUES:
890 PMD_DRV_LOG(INFO, "OP_DISABLE_QUEUE received");
891 i40e_pf_host_process_cmd_disable_queues(vf,
894 case I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS:
895 PMD_DRV_LOG(INFO, "OP_ADD_ETHER_ADDRESS received");
896 i40e_pf_host_process_cmd_add_ether_address(vf,
899 case I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS:
900 PMD_DRV_LOG(INFO, "OP_DEL_ETHER_ADDRESS received");
901 i40e_pf_host_process_cmd_del_ether_address(vf,
904 case I40E_VIRTCHNL_OP_ADD_VLAN:
905 PMD_DRV_LOG(INFO, "OP_ADD_VLAN received");
906 i40e_pf_host_process_cmd_add_vlan(vf, msg, msglen);
908 case I40E_VIRTCHNL_OP_DEL_VLAN:
909 PMD_DRV_LOG(INFO, "OP_DEL_VLAN received");
910 i40e_pf_host_process_cmd_del_vlan(vf, msg, msglen);
912 case I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE:
913 PMD_DRV_LOG(INFO, "OP_CONFIG_PROMISCUOUS_MODE received");
914 i40e_pf_host_process_cmd_config_promisc_mode(vf, msg, msglen);
916 case I40E_VIRTCHNL_OP_GET_STATS:
917 PMD_DRV_LOG(INFO, "OP_GET_STATS received");
918 i40e_pf_host_process_cmd_get_stats(vf);
920 case I40E_VIRTCHNL_OP_GET_LINK_STAT:
921 PMD_DRV_LOG(INFO, "OP_GET_LINK_STAT received");
922 i40e_pf_host_process_cmd_get_link_status(vf);
924 case I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD:
925 PMD_DRV_LOG(INFO, "OP_CFG_VLAN_OFFLOAD received");
926 i40e_pf_host_process_cmd_cfg_vlan_offload(vf, msg, msglen);
928 case I40E_VIRTCHNL_OP_CFG_VLAN_PVID:
929 PMD_DRV_LOG(INFO, "OP_CFG_VLAN_PVID received");
930 i40e_pf_host_process_cmd_cfg_pvid(vf, msg, msglen);
932 /* Don't add command supported below, which will
933 * return an error code.
935 case I40E_VIRTCHNL_OP_FCOE:
936 PMD_DRV_LOG(ERR, "OP_FCOE received, not supported");
938 PMD_DRV_LOG(ERR, "%u received, not supported", opcode);
939 i40e_pf_host_send_msg_to_vf(vf, opcode,
940 I40E_ERR_PARAM, NULL, 0);
946 i40e_pf_host_init(struct rte_eth_dev *dev)
948 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
949 struct i40e_hw *hw = I40E_PF_TO_HW(pf);
953 PMD_INIT_FUNC_TRACE();
956 * return if SRIOV not enabled, VF number not configured or
959 if(!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 || pf->vf_nb_qps == 0)
962 /* Allocate memory to store VF structure */
963 pf->vfs = rte_zmalloc("i40e_pf_vf",sizeof(*pf->vfs) * pf->vf_num, 0);
967 /* Disable irq0 for VFR event */
968 i40e_pf_disable_irq0(hw);
970 /* Disable VF link status interrupt */
971 val = I40E_READ_REG(hw, I40E_PFGEN_PORTMDIO_NUM);
972 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
973 I40E_WRITE_REG(hw, I40E_PFGEN_PORTMDIO_NUM, val);
974 I40E_WRITE_FLUSH(hw);
976 for (i = 0; i < pf->vf_num; i++) {
978 pf->vfs[i].state = I40E_VF_INACTIVE;
979 pf->vfs[i].vf_idx = i;
980 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
981 if (ret != I40E_SUCCESS)
986 i40e_pf_enable_irq0(hw);
992 i40e_pf_enable_irq0(hw);