lib/librte_pmd_i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define I40E_MIN_RING_DESC     64
  61 #define I40E_MAX_RING_DESC     4096
  62 #define I40E_ALIGN             128
  63 #define DEFAULT_TX_RS_THRESH   32
  64 #define DEFAULT_TX_FREE_THRESH 32
  65 #define I40E_MAX_PKT_TYPE      256
  66
  67 #define I40E_VLAN_TAG_SIZE 4
  68 #define I40E_TX_MAX_BURST  32
  69
  70 #define I40E_DMA_MEM_ALIGN 4096
  71
  72 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  73                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  74
  75 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  76
  77 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
  78         (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
  79
  80 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
  81         ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
  82
  83 static const struct rte_memzone *
  84 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
  85                            const char *ring_name,
  86                            uint16_t queue_id,
  87                            uint32_t ring_size,
  88                            int socket_id);
  89 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  90                                       struct rte_mbuf **tx_pkts,
  91                                       uint16_t nb_pkts);
  92
  93 /* Translate the rx descriptor status to pkt flags */
  94 static inline uint64_t
  95 i40e_rxd_status_to_pkt_flags(uint64_t qword)
  96 {
  97         uint64_t flags;
  98
  99         /* Check if VLAN packet */
 100         flags = qword & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
 101                                                         PKT_RX_VLAN_PKT : 0;
 102
 103         /* Check if RSS_HASH */
 104         flags |= (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 105                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 106                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 107
 108         return flags;
 109 }
 110
 111 static inline uint64_t
 112 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 113 {
 114         uint64_t flags = 0;
 115         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 116
 117 #define I40E_RX_ERR_BITS 0x3f
 118         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 119                 return flags;
 120         /* If RXE bit set, all other status bits are meaningless */
 121         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 122                 flags |= PKT_RX_MAC_ERR;
 123                 return flags;
 124         }
 125
 126         /* If RECIPE bit set, all other status indications should be ignored */
 127         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
 128                 flags |= PKT_RX_RECIP_ERR;
 129                 return flags;
 130         }
 131         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
 132                 flags |= PKT_RX_HBUF_OVERFLOW;
 133         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 134                 flags |= PKT_RX_IP_CKSUM_BAD;
 135         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 136                 flags |= PKT_RX_L4_CKSUM_BAD;
 137         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 138                 flags |= PKT_RX_EIP_CKSUM_BAD;
 139         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
 140                 flags |= PKT_RX_OVERSIZE;
 141
 142         return flags;
 143 }
 144
 145 /* Translate pkt types to pkt flags */
 146 static inline uint64_t
 147 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
 148 {
 149         uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
 150                                         I40E_RXD_QW1_PTYPE_SHIFT);
 151         static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
 152                 0, /* PTYPE 0 */
 153                 0, /* PTYPE 1 */
 154                 0, /* PTYPE 2 */
 155                 0, /* PTYPE 3 */
 156                 0, /* PTYPE 4 */
 157                 0, /* PTYPE 5 */
 158                 0, /* PTYPE 6 */
 159                 0, /* PTYPE 7 */
 160                 0, /* PTYPE 8 */
 161                 0, /* PTYPE 9 */
 162                 0, /* PTYPE 10 */
 163                 0, /* PTYPE 11 */
 164                 0, /* PTYPE 12 */
 165                 0, /* PTYPE 13 */
 166                 0, /* PTYPE 14 */
 167                 0, /* PTYPE 15 */
 168                 0, /* PTYPE 16 */
 169                 0, /* PTYPE 17 */
 170                 0, /* PTYPE 18 */
 171                 0, /* PTYPE 19 */
 172                 0, /* PTYPE 20 */
 173                 0, /* PTYPE 21 */
 174                 PKT_RX_IPV4_HDR, /* PTYPE 22 */
 175                 PKT_RX_IPV4_HDR, /* PTYPE 23 */
 176                 PKT_RX_IPV4_HDR, /* PTYPE 24 */
 177                 0, /* PTYPE 25 */
 178                 PKT_RX_IPV4_HDR, /* PTYPE 26 */
 179                 PKT_RX_IPV4_HDR, /* PTYPE 27 */
 180                 PKT_RX_IPV4_HDR, /* PTYPE 28 */
 181                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
 182                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
 183                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
 184                 0, /* PTYPE 32 */
 185                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
 186                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
 187                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
 188                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
 189                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
 190                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
 191                 0, /* PTYPE 39 */
 192                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
 193                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
 194                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
 195                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
 196                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
 197                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
 198                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
 199                 0, /* PTYPE 47 */
 200                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
 201                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
 202                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
 203                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
 204                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
 205                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
 206                 0, /* PTYPE 54 */
 207                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
 208                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
 209                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
 210                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
 211                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 59 */
 212                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 60 */
 213                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 61 */
 214                 0, /* PTYPE 62 */
 215                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 63 */
 216                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 64 */
 217                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 65 */
 218                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 66 */
 219                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 67 */
 220                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 68 */
 221                 0, /* PTYPE 69 */
 222                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 70 */
 223                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 71 */
 224                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 72 */
 225                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 73 */
 226                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 74 */
 227                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 75 */
 228                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 76 */
 229                 0, /* PTYPE 77 */
 230                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 78 */
 231                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 79 */
 232                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 80 */
 233                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 81 */
 234                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 82 */
 235                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 83 */
 236                 0, /* PTYPE 84 */
 237                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 85 */
 238                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 86 */
 239                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
 240                 PKT_RX_IPV6_HDR, /* PTYPE 88 */
 241                 PKT_RX_IPV6_HDR, /* PTYPE 89 */
 242                 PKT_RX_IPV6_HDR, /* PTYPE 90 */
 243                 0, /* PTYPE 91 */
 244                 PKT_RX_IPV6_HDR, /* PTYPE 92 */
 245                 PKT_RX_IPV6_HDR, /* PTYPE 93 */
 246                 PKT_RX_IPV6_HDR, /* PTYPE 94 */
 247                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
 248                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
 249                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
 250                 0, /* PTYPE 98 */
 251                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
 252                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
 253                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
 254                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
 255                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
 256                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
 257                 0, /* PTYPE 105 */
 258                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
 259                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
 260                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
 261                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
 262                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
 263                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
 264                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
 265                 0, /* PTYPE 113 */
 266                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
 267                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
 268                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
 269                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
 270                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
 271                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
 272                 0, /* PTYPE 120 */
 273                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
 274                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
 275                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
 276                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
 277                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 125 */
 278                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 126 */
 279                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 127 */
 280                 0, /* PTYPE 128 */
 281                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 129 */
 282                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 130 */
 283                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 131 */
 284                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 132 */
 285                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 133 */
 286                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 134 */
 287                 0, /* PTYPE 135 */
 288                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 136 */
 289                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 137 */
 290                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 138 */
 291                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 139 */
 292                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 140 */
 293                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 141 */
 294                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 142 */
 295                 0, /* PTYPE 143 */
 296                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 144 */
 297                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 145 */
 298                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 146 */
 299                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 147 */
 300                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 148 */
 301                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 149 */
 302                 0, /* PTYPE 150 */
 303                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 151 */
 304                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 152 */
 305                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
 306                 0, /* PTYPE 154 */
 307                 0, /* PTYPE 155 */
 308                 0, /* PTYPE 156 */
 309                 0, /* PTYPE 157 */
 310                 0, /* PTYPE 158 */
 311                 0, /* PTYPE 159 */
 312                 0, /* PTYPE 160 */
 313                 0, /* PTYPE 161 */
 314                 0, /* PTYPE 162 */
 315                 0, /* PTYPE 163 */
 316                 0, /* PTYPE 164 */
 317                 0, /* PTYPE 165 */
 318                 0, /* PTYPE 166 */
 319                 0, /* PTYPE 167 */
 320                 0, /* PTYPE 168 */
 321                 0, /* PTYPE 169 */
 322                 0, /* PTYPE 170 */
 323                 0, /* PTYPE 171 */
 324                 0, /* PTYPE 172 */
 325                 0, /* PTYPE 173 */
 326                 0, /* PTYPE 174 */
 327                 0, /* PTYPE 175 */
 328                 0, /* PTYPE 176 */
 329                 0, /* PTYPE 177 */
 330                 0, /* PTYPE 178 */
 331                 0, /* PTYPE 179 */
 332                 0, /* PTYPE 180 */
 333                 0, /* PTYPE 181 */
 334                 0, /* PTYPE 182 */
 335                 0, /* PTYPE 183 */
 336                 0, /* PTYPE 184 */
 337                 0, /* PTYPE 185 */
 338                 0, /* PTYPE 186 */
 339                 0, /* PTYPE 187 */
 340                 0, /* PTYPE 188 */
 341                 0, /* PTYPE 189 */
 342                 0, /* PTYPE 190 */
 343                 0, /* PTYPE 191 */
 344                 0, /* PTYPE 192 */
 345                 0, /* PTYPE 193 */
 346                 0, /* PTYPE 194 */
 347                 0, /* PTYPE 195 */
 348                 0, /* PTYPE 196 */
 349                 0, /* PTYPE 197 */
 350                 0, /* PTYPE 198 */
 351                 0, /* PTYPE 199 */
 352                 0, /* PTYPE 200 */
 353                 0, /* PTYPE 201 */
 354                 0, /* PTYPE 202 */
 355                 0, /* PTYPE 203 */
 356                 0, /* PTYPE 204 */
 357                 0, /* PTYPE 205 */
 358                 0, /* PTYPE 206 */
 359                 0, /* PTYPE 207 */
 360                 0, /* PTYPE 208 */
 361                 0, /* PTYPE 209 */
 362                 0, /* PTYPE 210 */
 363                 0, /* PTYPE 211 */
 364                 0, /* PTYPE 212 */
 365                 0, /* PTYPE 213 */
 366                 0, /* PTYPE 214 */
 367                 0, /* PTYPE 215 */
 368                 0, /* PTYPE 216 */
 369                 0, /* PTYPE 217 */
 370                 0, /* PTYPE 218 */
 371                 0, /* PTYPE 219 */
 372                 0, /* PTYPE 220 */
 373                 0, /* PTYPE 221 */
 374                 0, /* PTYPE 222 */
 375                 0, /* PTYPE 223 */
 376                 0, /* PTYPE 224 */
 377                 0, /* PTYPE 225 */
 378                 0, /* PTYPE 226 */
 379                 0, /* PTYPE 227 */
 380                 0, /* PTYPE 228 */
 381                 0, /* PTYPE 229 */
 382                 0, /* PTYPE 230 */
 383                 0, /* PTYPE 231 */
 384                 0, /* PTYPE 232 */
 385                 0, /* PTYPE 233 */
 386                 0, /* PTYPE 234 */
 387                 0, /* PTYPE 235 */
 388                 0, /* PTYPE 236 */
 389                 0, /* PTYPE 237 */
 390                 0, /* PTYPE 238 */
 391                 0, /* PTYPE 239 */
 392                 0, /* PTYPE 240 */
 393                 0, /* PTYPE 241 */
 394                 0, /* PTYPE 242 */
 395                 0, /* PTYPE 243 */
 396                 0, /* PTYPE 244 */
 397                 0, /* PTYPE 245 */
 398                 0, /* PTYPE 246 */
 399                 0, /* PTYPE 247 */
 400                 0, /* PTYPE 248 */
 401                 0, /* PTYPE 249 */
 402                 0, /* PTYPE 250 */
 403                 0, /* PTYPE 251 */
 404                 0, /* PTYPE 252 */
 405                 0, /* PTYPE 253 */
 406                 0, /* PTYPE 254 */
 407                 0, /* PTYPE 255 */
 408         };
 409
 410         return ip_ptype_map[ptype];
 411 }
 412
 413 static inline void
 414 i40e_txd_enable_checksum(uint32_t ol_flags,
 415                         uint32_t *td_cmd,
 416                         uint32_t *td_offset,
 417                         uint8_t l2_len,
 418                         uint8_t l3_len)
 419 {
 420         if (!l2_len) {
 421                 PMD_DRV_LOG(DEBUG, "L2 length set to 0");
 422                 return;
 423         }
 424         *td_offset |= (l2_len >> 1) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 425
 426         if (!l3_len) {
 427                 PMD_DRV_LOG(DEBUG, "L3 length set to 0");
 428                 return;
 429         }
 430
 431         /* Enable L3 checksum offloads */
 432         if (ol_flags & PKT_TX_IPV4_CSUM) {
 433                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 434                 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 435         } else if (ol_flags & PKT_TX_IPV4) {
 436                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 437                 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 438         } else if (ol_flags & PKT_TX_IPV6) {
 439                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 440                 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 441         }
 442
 443         /* Enable L4 checksum offloads */
 444         switch (ol_flags & PKT_TX_L4_MASK) {
 445         case PKT_TX_TCP_CKSUM:
 446                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 447                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 448                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 449                 break;
 450         case PKT_TX_SCTP_CKSUM:
 451                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 452                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 453                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 454                 break;
 455         case PKT_TX_UDP_CKSUM:
 456                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 457                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 458                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 459                 break;
 460         default:
 461                 break;
 462         }
 463 }
 464
 465 static inline struct rte_mbuf *
 466 rte_rxmbuf_alloc(struct rte_mempool *mp)
 467 {
 468         struct rte_mbuf *m;
 469
 470         m = __rte_mbuf_raw_alloc(mp);
 471         __rte_mbuf_sanity_check_raw(m, 0);
 472
 473         return m;
 474 }
 475
 476 /* Construct the tx flags */
 477 static inline uint64_t
 478 i40e_build_ctob(uint32_t td_cmd,
 479                 uint32_t td_offset,
 480                 unsigned int size,
 481                 uint32_t td_tag)
 482 {
 483         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 484                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 485                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 486                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 487                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 488 }
 489
 490 static inline int
 491 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 492 {
 493         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 494         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 495         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 496         uint16_t nb_tx_desc = txq->nb_tx_desc;
 497         uint16_t desc_to_clean_to;
 498         uint16_t nb_tx_to_clean;
 499
 500         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 501         if (desc_to_clean_to >= nb_tx_desc)
 502                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 503
 504         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 505         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
 506                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) {
 507                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 508                         "(port=%d queue=%d)", desc_to_clean_to,
 509                                 txq->port_id, txq->queue_id);
 510                 return -1;
 511         }
 512
 513         if (last_desc_cleaned > desc_to_clean_to)
 514                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 515                                                         desc_to_clean_to);
 516         else
 517                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 518                                         last_desc_cleaned);
 519
 520         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 521
 522         txq->last_desc_cleaned = desc_to_clean_to;
 523         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 524
 525         return 0;
 526 }
 527
 528 static inline int
 529 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 530 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 531 #else
 532 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 533 #endif
 534 {
 535         int ret = 0;
 536
 537 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 538         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 539                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 540                              "rxq->rx_free_thresh=%d, "
 541                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 542                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 543                 ret = -EINVAL;
 544         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 545                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 546                              "rxq->rx_free_thresh=%d, "
 547                              "rxq->nb_rx_desc=%d",
 548                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 549                 ret = -EINVAL;
 550         } else if (!(rxq->nb_rx_desc % rxq->rx_free_thresh) == 0) {
 551                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 552                              "rxq->nb_rx_desc=%d, "
 553                              "rxq->rx_free_thresh=%d",
 554                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 555                 ret = -EINVAL;
 556         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 557                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 558                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 559                              "rxq->nb_rx_desc=%d, "
 560                              "I40E_MAX_RING_DESC=%d, "
 561                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 562                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 563                              RTE_PMD_I40E_RX_MAX_BURST);
 564                 ret = -EINVAL;
 565         }
 566 #else
 567         ret = -EINVAL;
 568 #endif
 569
 570         return ret;
 571 }
 572
 573 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 574 #define I40E_LOOK_AHEAD 8
 575 #if (I40E_LOOK_AHEAD != 8)
 576 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 577 #endif
 578 static inline int
 579 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 580 {
 581         volatile union i40e_rx_desc *rxdp;
 582         struct i40e_rx_entry *rxep;
 583         struct rte_mbuf *mb;
 584         uint16_t pkt_len;
 585         uint64_t qword1;
 586         uint32_t rx_status;
 587         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 588         int32_t i, j, nb_rx = 0;
 589         uint64_t pkt_flags;
 590
 591         rxdp = &rxq->rx_ring[rxq->rx_tail];
 592         rxep = &rxq->sw_ring[rxq->rx_tail];
 593
 594         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 595         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 596                                 I40E_RXD_QW1_STATUS_SHIFT;
 597
 598         /* Make sure there is at least 1 packet to receive */
 599         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 600                 return 0;
 601
 602         /**
 603          * Scan LOOK_AHEAD descriptors at a time to determine which
 604          * descriptors reference packets that are ready to be received.
 605          */
 606         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 607                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 608                 /* Read desc statuses backwards to avoid race condition */
 609                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 610                         qword1 = rte_le_to_cpu_64(\
 611                                 rxdp[j].wb.qword1.status_error_len);
 612                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 613                                         I40E_RXD_QW1_STATUS_SHIFT;
 614                 }
 615
 616                 /* Compute how many status bits were set */
 617                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 618                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 619
 620                 nb_rx += nb_dd;
 621
 622                 /* Translate descriptor info to mbuf parameters */
 623                 for (j = 0; j < nb_dd; j++) {
 624                         mb = rxep[j].mbuf;
 625                         qword1 = rte_le_to_cpu_64(\
 626                                 rxdp[j].wb.qword1.status_error_len);
 627                         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 628                                                 I40E_RXD_QW1_STATUS_SHIFT;
 629                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 630                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 631                         mb->data_len = pkt_len;
 632                         mb->pkt_len = pkt_len;
 633                         mb->vlan_tci = rx_status &
 634                                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
 635                         rte_le_to_cpu_16(\
 636                                 rxdp[j].wb.qword0.lo_dword.l2tag1) : 0;
 637                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 638                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 639                         pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
 640                         mb->ol_flags = pkt_flags;
 641
 642                         mb->packet_type = (uint16_t)((qword1 &
 643                                         I40E_RXD_QW1_PTYPE_MASK) >>
 644                                         I40E_RXD_QW1_PTYPE_SHIFT);
 645                         if (pkt_flags & PKT_RX_RSS_HASH)
 646                                 mb->hash.rss = rte_le_to_cpu_32(\
 647                                         rxdp->wb.qword0.hi_dword.rss);
 648                 }
 649
 650                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 651                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 652
 653                 if (nb_dd != I40E_LOOK_AHEAD)
 654                         break;
 655         }
 656
 657         /* Clear software ring entries */
 658         for (i = 0; i < nb_rx; i++)
 659                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 660
 661         return nb_rx;
 662 }
 663
 664 static inline uint16_t
 665 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 666                         struct rte_mbuf **rx_pkts,
 667                         uint16_t nb_pkts)
 668 {
 669         uint16_t i;
 670         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 671
 672         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 673
 674         for (i = 0; i < nb_pkts; i++)
 675                 rx_pkts[i] = stage[i];
 676
 677         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 678         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 679
 680         return nb_pkts;
 681 }
 682
 683 static inline int
 684 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 685 {
 686         volatile union i40e_rx_desc *rxdp;
 687         struct i40e_rx_entry *rxep;
 688         struct rte_mbuf *mb;
 689         uint16_t alloc_idx, i;
 690         uint64_t dma_addr;
 691         int diag;
 692
 693         /* Allocate buffers in bulk */
 694         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 695                                 (rxq->rx_free_thresh - 1));
 696         rxep = &(rxq->sw_ring[alloc_idx]);
 697         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 698                                         rxq->rx_free_thresh);
 699         if (unlikely(diag != 0)) {
 700                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 701                 return -ENOMEM;
 702         }
 703
 704         rxdp = &rxq->rx_ring[alloc_idx];
 705         for (i = 0; i < rxq->rx_free_thresh; i++) {
 706                 mb = rxep[i].mbuf;
 707                 rte_mbuf_refcnt_set(mb, 1);
 708                 mb->next = NULL;
 709                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 710                 mb->nb_segs = 1;
 711                 mb->port = rxq->port_id;
 712                 dma_addr = rte_cpu_to_le_64(\
 713                         RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
 714                 rxdp[i].read.hdr_addr = dma_addr;
 715                 rxdp[i].read.pkt_addr = dma_addr;
 716         }
 717
 718         /* Update rx tail regsiter */
 719         rte_wmb();
 720         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 721
 722         rxq->rx_free_trigger =
 723                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 724         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 725                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 726
 727         return 0;
 728 }
 729
 730 static inline uint16_t
 731 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 732 {
 733         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 734         uint16_t nb_rx = 0;
 735
 736         if (!nb_pkts)
 737                 return 0;
 738
 739         if (rxq->rx_nb_avail)
 740                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 741
 742         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 743         rxq->rx_next_avail = 0;
 744         rxq->rx_nb_avail = nb_rx;
 745         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 746
 747         if (rxq->rx_tail > rxq->rx_free_trigger) {
 748                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 749                         uint16_t i, j;
 750
 751                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
 752                                    "port_id=%u, queue_id=%u",
 753                                    rxq->port_id, rxq->queue_id);
 754                         rxq->rx_nb_avail = 0;
 755                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 756                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 757                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 758
 759                         return 0;
 760                 }
 761         }
 762
 763         if (rxq->rx_tail >= rxq->nb_rx_desc)
 764                 rxq->rx_tail = 0;
 765
 766         if (rxq->rx_nb_avail)
 767                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 768
 769         return 0;
 770 }
 771
 772 static uint16_t
 773 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 774                           struct rte_mbuf **rx_pkts,
 775                           uint16_t nb_pkts)
 776 {
 777         uint16_t nb_rx = 0, n, count;
 778
 779         if (unlikely(nb_pkts == 0))
 780                 return 0;
 781
 782         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 783                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 784
 785         while (nb_pkts) {
 786                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 787                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 788                 nb_rx = (uint16_t)(nb_rx + count);
 789                 nb_pkts = (uint16_t)(nb_pkts - count);
 790                 if (count < n)
 791                         break;
 792         }
 793
 794         return nb_rx;
 795 }
 796 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 797
 798 uint16_t
 799 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 800 {
 801         struct i40e_rx_queue *rxq;
 802         volatile union i40e_rx_desc *rx_ring;
 803         volatile union i40e_rx_desc *rxdp;
 804         union i40e_rx_desc rxd;
 805         struct i40e_rx_entry *sw_ring;
 806         struct i40e_rx_entry *rxe;
 807         struct rte_mbuf *rxm;
 808         struct rte_mbuf *nmb;
 809         uint16_t nb_rx;
 810         uint32_t rx_status;
 811         uint64_t qword1;
 812         uint16_t rx_packet_len;
 813         uint16_t rx_id, nb_hold;
 814         uint64_t dma_addr;
 815         uint64_t pkt_flags;
 816
 817         nb_rx = 0;
 818         nb_hold = 0;
 819         rxq = rx_queue;
 820         rx_id = rxq->rx_tail;
 821         rx_ring = rxq->rx_ring;
 822         sw_ring = rxq->sw_ring;
 823
 824         while (nb_rx < nb_pkts) {
 825                 rxdp = &rx_ring[rx_id];
 826                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 827                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 828                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 829                 /* Check the DD bit first */
 830                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 831                         break;
 832
 833                 nmb = rte_rxmbuf_alloc(rxq->mp);
 834                 if (unlikely(!nmb))
 835                         break;
 836                 rxd = *rxdp;
 837
 838                 nb_hold++;
 839                 rxe = &sw_ring[rx_id];
 840                 rx_id++;
 841                 if (unlikely(rx_id == rxq->nb_rx_desc))
 842                         rx_id = 0;
 843
 844                 /* Prefetch next mbuf */
 845                 rte_prefetch0(sw_ring[rx_id].mbuf);
 846
 847                 /**
 848                  * When next RX descriptor is on a cache line boundary,
 849                  * prefetch the next 4 RX descriptors and next 8 pointers
 850                  * to mbufs.
 851                  */
 852                 if ((rx_id & 0x3) == 0) {
 853                         rte_prefetch0(&rx_ring[rx_id]);
 854                         rte_prefetch0(&sw_ring[rx_id]);
 855                 }
 856                 rxm = rxe->mbuf;
 857                 rxe->mbuf = nmb;
 858                 dma_addr =
 859                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
 860                 rxdp->read.hdr_addr = dma_addr;
 861                 rxdp->read.pkt_addr = dma_addr;
 862
 863                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 864                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 865
 866                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 867                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 868                 rxm->nb_segs = 1;
 869                 rxm->next = NULL;
 870                 rxm->pkt_len = rx_packet_len;
 871                 rxm->data_len = rx_packet_len;
 872                 rxm->port = rxq->port_id;
 873
 874                 rxm->vlan_tci = rx_status &
 875                         (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
 876                         rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
 877                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 878                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 879                 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
 880                 rxm->packet_type = (uint16_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >>
 881                                 I40E_RXD_QW1_PTYPE_SHIFT);
 882                 rxm->ol_flags = pkt_flags;
 883                 if (pkt_flags & PKT_RX_RSS_HASH)
 884                         rxm->hash.rss =
 885                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 886
 887                 rx_pkts[nb_rx++] = rxm;
 888         }
 889         rxq->rx_tail = rx_id;
 890
 891         /**
 892          * If the number of free RX descriptors is greater than the RX free
 893          * threshold of the queue, advance the receive tail register of queue.
 894          * Update that register with the value of the last processed RX
 895          * descriptor minus 1.
 896          */
 897         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 898         if (nb_hold > rxq->rx_free_thresh) {
 899                 rx_id = (uint16_t) ((rx_id == 0) ?
 900                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 901                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 902                 nb_hold = 0;
 903         }
 904         rxq->nb_rx_hold = nb_hold;
 905
 906         return nb_rx;
 907 }
 908
 909 uint16_t
 910 i40e_recv_scattered_pkts(void *rx_queue,
 911                          struct rte_mbuf **rx_pkts,
 912                          uint16_t nb_pkts)
 913 {
 914         struct i40e_rx_queue *rxq = rx_queue;
 915         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 916         volatile union i40e_rx_desc *rxdp;
 917         union i40e_rx_desc rxd;
 918         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 919         struct i40e_rx_entry *rxe;
 920         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 921         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 922         struct rte_mbuf *nmb, *rxm;
 923         uint16_t rx_id = rxq->rx_tail;
 924         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 925         uint32_t rx_status;
 926         uint64_t qword1;
 927         uint64_t dma_addr;
 928         uint64_t pkt_flags;
 929
 930         while (nb_rx < nb_pkts) {
 931                 rxdp = &rx_ring[rx_id];
 932                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 933                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 934                                         I40E_RXD_QW1_STATUS_SHIFT;
 935                 /* Check the DD bit */
 936                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 937                         break;
 938
 939                 nmb = rte_rxmbuf_alloc(rxq->mp);
 940                 if (unlikely(!nmb))
 941                         break;
 942                 rxd = *rxdp;
 943                 nb_hold++;
 944                 rxe = &sw_ring[rx_id];
 945                 rx_id++;
 946                 if (rx_id == rxq->nb_rx_desc)
 947                         rx_id = 0;
 948
 949                 /* Prefetch next mbuf */
 950                 rte_prefetch0(sw_ring[rx_id].mbuf);
 951
 952                 /**
 953                  * When next RX descriptor is on a cache line boundary,
 954                  * prefetch the next 4 RX descriptors and next 8 pointers
 955                  * to mbufs.
 956                  */
 957                 if ((rx_id & 0x3) == 0) {
 958                         rte_prefetch0(&rx_ring[rx_id]);
 959                         rte_prefetch0(&sw_ring[rx_id]);
 960                 }
 961
 962                 rxm = rxe->mbuf;
 963                 rxe->mbuf = nmb;
 964                 dma_addr =
 965                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
 966
 967                 /* Set data buffer address and data length of the mbuf */
 968                 rxdp->read.hdr_addr = dma_addr;
 969                 rxdp->read.pkt_addr = dma_addr;
 970                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 971                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 972                 rxm->data_len = rx_packet_len;
 973                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 974
 975                 /**
 976                  * If this is the first buffer of the received packet, set the
 977                  * pointer to the first mbuf of the packet and initialize its
 978                  * context. Otherwise, update the total length and the number
 979                  * of segments of the current scattered packet, and update the
 980                  * pointer to the last mbuf of the current packet.
 981                  */
 982                 if (!first_seg) {
 983                         first_seg = rxm;
 984                         first_seg->nb_segs = 1;
 985                         first_seg->pkt_len = rx_packet_len;
 986                 } else {
 987                         first_seg->pkt_len =
 988                                 (uint16_t)(first_seg->pkt_len +
 989                                                 rx_packet_len);
 990                         first_seg->nb_segs++;
 991                         last_seg->next = rxm;
 992                 }
 993
 994                 /**
 995                  * If this is not the last buffer of the received packet,
 996                  * update the pointer to the last mbuf of the current scattered
 997                  * packet and continue to parse the RX ring.
 998                  */
 999                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1000                         last_seg = rxm;
1001                         continue;
1002                 }
1003
1004                 /**
1005                  * This is the last buffer of the received packet. If the CRC
1006                  * is not stripped by the hardware:
1007                  *  - Subtract the CRC length from the total packet length.
1008                  *  - If the last buffer only contains the whole CRC or a part
1009                  *  of it, free the mbuf associated to the last buffer. If part
1010                  *  of the CRC is also contained in the previous mbuf, subtract
1011                  *  the length of that CRC part from the data length of the
1012                  *  previous mbuf.
1013                  */
1014                 rxm->next = NULL;
1015                 if (unlikely(rxq->crc_len > 0)) {
1016                         first_seg->pkt_len -= ETHER_CRC_LEN;
1017                         if (rx_packet_len <= ETHER_CRC_LEN) {
1018                                 rte_pktmbuf_free_seg(rxm);
1019                                 first_seg->nb_segs--;
1020                                 last_seg->data_len =
1021                                         (uint16_t)(last_seg->data_len -
1022                                         (ETHER_CRC_LEN - rx_packet_len));
1023                                 last_seg->next = NULL;
1024                         } else
1025                                 rxm->data_len = (uint16_t)(rx_packet_len -
1026                                                                 ETHER_CRC_LEN);
1027                 }
1028
1029                 first_seg->port = rxq->port_id;
1030                 first_seg->vlan_tci = (rx_status &
1031                         (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1032                         rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
1033                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1034                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1035                 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1036                 first_seg->packet_type = (uint16_t)((qword1 &
1037                                         I40E_RXD_QW1_PTYPE_MASK) >>
1038                                         I40E_RXD_QW1_PTYPE_SHIFT);
1039                 first_seg->ol_flags = pkt_flags;
1040                 if (pkt_flags & PKT_RX_RSS_HASH)
1041                         rxm->hash.rss =
1042                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1043
1044                 /* Prefetch data of first segment, if configured to do so. */
1045                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1046                         first_seg->data_off));
1047                 rx_pkts[nb_rx++] = first_seg;
1048                 first_seg = NULL;
1049         }
1050
1051         /* Record index of the next RX descriptor to probe. */
1052         rxq->rx_tail = rx_id;
1053         rxq->pkt_first_seg = first_seg;
1054         rxq->pkt_last_seg = last_seg;
1055
1056         /**
1057          * If the number of free RX descriptors is greater than the RX free
1058          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1059          * register. Update the RDT with the value of the last processed RX
1060          * descriptor minus 1, to guarantee that the RDT register is never
1061          * equal to the RDH register, which creates a "full" ring situtation
1062          * from the hardware point of view.
1063          */
1064         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1065         if (nb_hold > rxq->rx_free_thresh) {
1066                 rx_id = (uint16_t)(rx_id == 0 ?
1067                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1068                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1069                 nb_hold = 0;
1070         }
1071         rxq->nb_rx_hold = nb_hold;
1072
1073         return nb_rx;
1074 }
1075
1076 /* Check if the context descriptor is needed for TX offloading */
1077 static inline uint16_t
1078 i40e_calc_context_desc(uint64_t flags)
1079 {
1080         uint16_t mask = 0;
1081
1082 #ifdef RTE_LIBRTE_IEEE1588
1083         mask |= PKT_TX_IEEE1588_TMST;
1084 #endif
1085         if (flags & mask)
1086                 return 1;
1087
1088         return 0;
1089 }
1090
1091 uint16_t
1092 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1093 {
1094         struct i40e_tx_queue *txq;
1095         struct i40e_tx_entry *sw_ring;
1096         struct i40e_tx_entry *txe, *txn;
1097         volatile struct i40e_tx_desc *txd;
1098         volatile struct i40e_tx_desc *txr;
1099         struct rte_mbuf *tx_pkt;
1100         struct rte_mbuf *m_seg;
1101         uint16_t tx_id;
1102         uint16_t nb_tx;
1103         uint32_t td_cmd;
1104         uint32_t td_offset;
1105         uint32_t tx_flags;
1106         uint32_t td_tag;
1107         uint64_t ol_flags;
1108         uint8_t l2_len;
1109         uint8_t l3_len;
1110         uint16_t nb_used;
1111         uint16_t nb_ctx;
1112         uint16_t tx_last;
1113         uint16_t slen;
1114         uint64_t buf_dma_addr;
1115
1116         txq = tx_queue;
1117         sw_ring = txq->sw_ring;
1118         txr = txq->tx_ring;
1119         tx_id = txq->tx_tail;
1120         txe = &sw_ring[tx_id];
1121
1122         /* Check if the descriptor ring needs to be cleaned. */
1123         if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh)
1124                 i40e_xmit_cleanup(txq);
1125
1126         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1127                 td_cmd = 0;
1128                 td_tag = 0;
1129                 td_offset = 0;
1130                 tx_flags = 0;
1131
1132                 tx_pkt = *tx_pkts++;
1133                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1134
1135                 ol_flags = tx_pkt->ol_flags;
1136                 l2_len = tx_pkt->l2_len;
1137                 l3_len = tx_pkt->l3_len;
1138
1139                 /* Calculate the number of context descriptors needed. */
1140                 nb_ctx = i40e_calc_context_desc(ol_flags);
1141
1142                 /**
1143                  * The number of descriptors that must be allocated for
1144                  * a packet equals to the number of the segments of that
1145                  * packet plus 1 context descriptor if needed.
1146                  */
1147                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1148                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1149
1150                 /* Circular ring */
1151                 if (tx_last >= txq->nb_tx_desc)
1152                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1153
1154                 if (nb_used > txq->nb_tx_free) {
1155                         if (i40e_xmit_cleanup(txq) != 0) {
1156                                 if (nb_tx == 0)
1157                                         return 0;
1158                                 goto end_of_tx;
1159                         }
1160                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1161                                 while (nb_used > txq->nb_tx_free) {
1162                                         if (i40e_xmit_cleanup(txq) != 0) {
1163                                                 if (nb_tx == 0)
1164                                                         return 0;
1165                                                 goto end_of_tx;
1166                                         }
1167                                 }
1168                         }
1169                 }
1170
1171                 /* Descriptor based VLAN insertion */
1172                 if (ol_flags & PKT_TX_VLAN_PKT) {
1173                         tx_flags |= tx_pkt->vlan_tci <<
1174                                         I40E_TX_FLAG_L2TAG1_SHIFT;
1175                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1176                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1177                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1178                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1179                 }
1180
1181                 /* Always enable CRC offload insertion */
1182                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1183
1184                 /* Enable checksum offloading */
1185                 i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1186                                                         l2_len, l3_len);
1187
1188                 if (unlikely(nb_ctx)) {
1189                         /* Setup TX context descriptor if required */
1190                         volatile struct i40e_tx_context_desc *ctx_txd =
1191                                 (volatile struct i40e_tx_context_desc *)\
1192                                                         &txr[tx_id];
1193                         uint32_t cd_tunneling_params = 0;
1194                         uint16_t cd_l2tag2 = 0;
1195                         uint64_t cd_type_cmd_tso_mss =
1196                                 I40E_TX_DESC_DTYPE_CONTEXT;
1197
1198                         txn = &sw_ring[txe->next_id];
1199                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1200                         if (txe->mbuf != NULL) {
1201                                 rte_pktmbuf_free_seg(txe->mbuf);
1202                                 txe->mbuf = NULL;
1203                         }
1204 #ifdef RTE_LIBRTE_IEEE1588
1205                         if (ol_flags & PKT_TX_IEEE1588_TMST)
1206                                 cd_type_cmd_tso_mss |=
1207                                         ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1208                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1209 #endif
1210                         ctx_txd->tunneling_params =
1211                                 rte_cpu_to_le_32(cd_tunneling_params);
1212                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1213                         ctx_txd->type_cmd_tso_mss =
1214                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1215                         txe->last_id = tx_last;
1216                         tx_id = txe->next_id;
1217                         txe = txn;
1218                 }
1219
1220                 m_seg = tx_pkt;
1221                 do {
1222                         txd = &txr[tx_id];
1223                         txn = &sw_ring[txe->next_id];
1224
1225                         if (txe->mbuf)
1226                                 rte_pktmbuf_free_seg(txe->mbuf);
1227                         txe->mbuf = m_seg;
1228
1229                         /* Setup TX Descriptor */
1230                         slen = m_seg->data_len;
1231                         buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1232                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1233                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1234                                                 td_offset, slen, td_tag);
1235                         txe->last_id = tx_last;
1236                         tx_id = txe->next_id;
1237                         txe = txn;
1238                         m_seg = m_seg->next;
1239                 } while (m_seg != NULL);
1240
1241                 /* The last packet data descriptor needs End Of Packet (EOP) */
1242                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1243                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1244                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1245
1246                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1247                         PMD_TX_FREE_LOG(DEBUG,
1248                                         "Setting RS bit on TXD id="
1249                                         "%4u (port=%d queue=%d)",
1250                                         tx_last, txq->port_id, txq->queue_id);
1251
1252                         td_cmd |= I40E_TX_DESC_CMD_RS;
1253
1254                         /* Update txq RS bit counters */
1255                         txq->nb_tx_used = 0;
1256                 }
1257
1258                 txd->cmd_type_offset_bsz |=
1259                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1260                                         I40E_TXD_QW1_CMD_SHIFT);
1261         }
1262
1263 end_of_tx:
1264         rte_wmb();
1265
1266         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1267                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1268                    (unsigned) tx_id, (unsigned) nb_tx);
1269
1270         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1271         txq->tx_tail = tx_id;
1272
1273         return nb_tx;
1274 }
1275
1276 static inline int __attribute__((always_inline))
1277 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1278 {
1279         struct i40e_tx_entry *txep;
1280         uint16_t i;
1281
1282         if (!(txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1283                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)))
1284                 return 0;
1285
1286         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1287
1288         for (i = 0; i < txq->tx_rs_thresh; i++)
1289                 rte_prefetch0((txep + i)->mbuf);
1290
1291         if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1292                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1293                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1294                         txep->mbuf = NULL;
1295                 }
1296         } else {
1297                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1298                         rte_pktmbuf_free_seg(txep->mbuf);
1299                         txep->mbuf = NULL;
1300                 }
1301         }
1302
1303         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1304         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1305         if (txq->tx_next_dd >= txq->nb_tx_desc)
1306                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1307
1308         return txq->tx_rs_thresh;
1309 }
1310
1311 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1312                      I40E_TX_DESC_CMD_EOP)
1313
1314 /* Populate 4 descriptors with data from 4 mbufs */
1315 static inline void
1316 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1317 {
1318         uint64_t dma_addr;
1319         uint32_t i;
1320
1321         for (i = 0; i < 4; i++, txdp++, pkts++) {
1322                 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1323                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1324                 txdp->cmd_type_offset_bsz =
1325                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1326                                         (*pkts)->data_len, 0);
1327         }
1328 }
1329
1330 /* Populate 1 descriptor with data from 1 mbuf */
1331 static inline void
1332 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1333 {
1334         uint64_t dma_addr;
1335
1336         dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1337         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1338         txdp->cmd_type_offset_bsz =
1339                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1340                                 (*pkts)->data_len, 0);
1341 }
1342
1343 /* Fill hardware descriptor ring with mbuf data */
1344 static inline void
1345 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1346                      struct rte_mbuf **pkts,
1347                      uint16_t nb_pkts)
1348 {
1349         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1350         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1351         const int N_PER_LOOP = 4;
1352         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1353         int mainpart, leftover;
1354         int i, j;
1355
1356         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1357         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1358         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1359                 for (j = 0; j < N_PER_LOOP; ++j) {
1360                         (txep + i + j)->mbuf = *(pkts + i + j);
1361                 }
1362                 tx4(txdp + i, pkts + i);
1363         }
1364         if (unlikely(leftover > 0)) {
1365                 for (i = 0; i < leftover; ++i) {
1366                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1367                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1368                 }
1369         }
1370 }
1371
1372 static inline uint16_t
1373 tx_xmit_pkts(struct i40e_tx_queue *txq,
1374              struct rte_mbuf **tx_pkts,
1375              uint16_t nb_pkts)
1376 {
1377         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1378         uint16_t n = 0;
1379
1380         /**
1381          * Begin scanning the H/W ring for done descriptors when the number
1382          * of available descriptors drops below tx_free_thresh. For each done
1383          * descriptor, free the associated buffer.
1384          */
1385         if (txq->nb_tx_free < txq->tx_free_thresh)
1386                 i40e_tx_free_bufs(txq);
1387
1388         /* Use available descriptor only */
1389         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1390         if (unlikely(!nb_pkts))
1391                 return 0;
1392
1393         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1394         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1395                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1396                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1397                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1398                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1399                                                 I40E_TXD_QW1_CMD_SHIFT);
1400                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1401                 txq->tx_tail = 0;
1402         }
1403
1404         /* Fill hardware descriptor ring with mbuf data */
1405         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1406         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1407
1408         /* Determin if RS bit needs to be set */
1409         if (txq->tx_tail > txq->tx_next_rs) {
1410                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1411                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1412                                                 I40E_TXD_QW1_CMD_SHIFT);
1413                 txq->tx_next_rs =
1414                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1415                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1416                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1417         }
1418
1419         if (txq->tx_tail >= txq->nb_tx_desc)
1420                 txq->tx_tail = 0;
1421
1422         /* Update the tx tail register */
1423         rte_wmb();
1424         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1425
1426         return nb_pkts;
1427 }
1428
1429 static uint16_t
1430 i40e_xmit_pkts_simple(void *tx_queue,
1431                       struct rte_mbuf **tx_pkts,
1432                       uint16_t nb_pkts)
1433 {
1434         uint16_t nb_tx = 0;
1435
1436         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1437                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1438                                                 tx_pkts, nb_pkts);
1439
1440         while (nb_pkts) {
1441                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1442                                                 I40E_TX_MAX_BURST);
1443
1444                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1445                                                 &tx_pkts[nb_tx], num);
1446                 nb_tx = (uint16_t)(nb_tx + ret);
1447                 nb_pkts = (uint16_t)(nb_pkts - ret);
1448                 if (ret < num)
1449                         break;
1450         }
1451
1452         return nb_tx;
1453 }
1454
1455 int
1456 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1457 {
1458         struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1459         struct i40e_rx_queue *rxq;
1460         int err = -1;
1461         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1462         uint16_t q_base = vsi->base_queue;
1463
1464         PMD_INIT_FUNC_TRACE();
1465
1466         if (rx_queue_id < dev->data->nb_rx_queues) {
1467                 rxq = dev->data->rx_queues[rx_queue_id];
1468
1469                 err = i40e_alloc_rx_queue_mbufs(rxq);
1470                 if (err) {
1471                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1472                         return err;
1473                 }
1474
1475                 rte_wmb();
1476
1477                 /* Init the RX tail regieter. */
1478                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1479
1480                 err = i40e_switch_rx_queue(hw, rx_queue_id + q_base, TRUE);
1481
1482                 if (err) {
1483                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1484                                     rx_queue_id);
1485
1486                         i40e_rx_queue_release_mbufs(rxq);
1487                         i40e_reset_rx_queue(rxq);
1488                 }
1489         }
1490
1491         return err;
1492 }
1493
1494 int
1495 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1496 {
1497         struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1498         struct i40e_rx_queue *rxq;
1499         int err;
1500         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1501         uint16_t q_base = vsi->base_queue;
1502
1503         if (rx_queue_id < dev->data->nb_rx_queues) {
1504                 rxq = dev->data->rx_queues[rx_queue_id];
1505
1506                 err = i40e_switch_rx_queue(hw, rx_queue_id + q_base, FALSE);
1507
1508                 if (err) {
1509                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1510                                     rx_queue_id);
1511                         return err;
1512                 }
1513                 i40e_rx_queue_release_mbufs(rxq);
1514                 i40e_reset_rx_queue(rxq);
1515         }
1516
1517         return 0;
1518 }
1519
1520 int
1521 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1522 {
1523         struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1524         int err = -1;
1525         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1526         uint16_t q_base = vsi->base_queue;
1527
1528         PMD_INIT_FUNC_TRACE();
1529
1530         if (tx_queue_id < dev->data->nb_tx_queues) {
1531                 err = i40e_switch_tx_queue(hw, tx_queue_id + q_base, TRUE);
1532                 if (err)
1533                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1534                                     tx_queue_id);
1535         }
1536
1537         return err;
1538 }
1539
1540 int
1541 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1542 {
1543         struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1544         struct i40e_tx_queue *txq;
1545         int err;
1546         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1547         uint16_t q_base = vsi->base_queue;
1548
1549         if (tx_queue_id < dev->data->nb_tx_queues) {
1550                 txq = dev->data->tx_queues[tx_queue_id];
1551
1552                 err = i40e_switch_tx_queue(hw, tx_queue_id + q_base, FALSE);
1553
1554                 if (err) {
1555                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1556                                     tx_queue_id);
1557                         return err;
1558                 }
1559
1560                 i40e_tx_queue_release_mbufs(txq);
1561                 i40e_reset_tx_queue(txq);
1562         }
1563
1564         return 0;
1565 }
1566
1567 int
1568 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1569                         uint16_t queue_idx,
1570                         uint16_t nb_desc,
1571                         unsigned int socket_id,
1572                         const struct rte_eth_rxconf *rx_conf,
1573                         struct rte_mempool *mp)
1574 {
1575         struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1576         struct i40e_rx_queue *rxq;
1577         const struct rte_memzone *rz;
1578         uint32_t ring_size;
1579         uint16_t len;
1580         int use_def_burst_func = 1;
1581
1582         if (!vsi || queue_idx >= vsi->nb_qps) {
1583                 PMD_DRV_LOG(ERR, "VSI not available or queue "
1584                             "index exceeds the maximum");
1585                 return I40E_ERR_PARAM;
1586         }
1587         if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1588                                         (nb_desc > I40E_MAX_RING_DESC) ||
1589                                         (nb_desc < I40E_MIN_RING_DESC)) {
1590                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1591                             "invalid", nb_desc);
1592                 return I40E_ERR_PARAM;
1593         }
1594
1595         /* Free memory if needed */
1596         if (dev->data->rx_queues[queue_idx]) {
1597                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1598                 dev->data->rx_queues[queue_idx] = NULL;
1599         }
1600
1601         /* Allocate the rx queue data structure */
1602         rxq = rte_zmalloc_socket("i40e rx queue",
1603                                  sizeof(struct i40e_rx_queue),
1604                                  CACHE_LINE_SIZE,
1605                                  socket_id);
1606         if (!rxq) {
1607                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1608                             "rx queue data structure");
1609                 return (-ENOMEM);
1610         }
1611         rxq->mp = mp;
1612         rxq->nb_rx_desc = nb_desc;
1613         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1614         rxq->queue_id = queue_idx;
1615         rxq->reg_idx = vsi->base_queue + queue_idx;
1616         rxq->port_id = dev->data->port_id;
1617         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1618                                                         0 : ETHER_CRC_LEN);
1619         rxq->drop_en = rx_conf->rx_drop_en;
1620         rxq->vsi = vsi;
1621         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1622
1623         /* Allocate the maximun number of RX ring hardware descriptor. */
1624         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1625         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1626         rz = i40e_ring_dma_zone_reserve(dev,
1627                                         "rx_ring",
1628                                         queue_idx,
1629                                         ring_size,
1630                                         socket_id);
1631         if (!rz) {
1632                 i40e_dev_rx_queue_release(rxq);
1633                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1634                 return (-ENOMEM);
1635         }
1636
1637         /* Zero all the descriptors in the ring. */
1638         memset(rz->addr, 0, ring_size);
1639
1640 #ifdef RTE_LIBRTE_XEN_DOM0
1641         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1642 #else
1643         rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1644 #endif
1645
1646         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1647
1648 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1649         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1650 #else
1651         len = nb_desc;
1652 #endif
1653
1654         /* Allocate the software ring. */
1655         rxq->sw_ring =
1656                 rte_zmalloc_socket("i40e rx sw ring",
1657                                    sizeof(struct i40e_rx_entry) * len,
1658                                    CACHE_LINE_SIZE,
1659                                    socket_id);
1660         if (!rxq->sw_ring) {
1661                 i40e_dev_rx_queue_release(rxq);
1662                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1663                 return (-ENOMEM);
1664         }
1665
1666         i40e_reset_rx_queue(rxq);
1667         rxq->q_set = TRUE;
1668         dev->data->rx_queues[queue_idx] = rxq;
1669
1670         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1671
1672         if (!use_def_burst_func && !dev->data->scattered_rx) {
1673 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1674                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1675                              "satisfied. Rx Burst Bulk Alloc function will be "
1676                              "used on port=%d, queue=%d.",
1677                              rxq->port_id, rxq->queue_id);
1678                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1679 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1680         } else {
1681                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1682                              "not satisfied, Scattered Rx is requested, "
1683                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1684                              "not enabled on port=%d, queue=%d.",
1685                              rxq->port_id, rxq->queue_id);
1686         }
1687
1688         return 0;
1689 }
1690
1691 void
1692 i40e_dev_rx_queue_release(void *rxq)
1693 {
1694         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1695
1696         if (!q) {
1697                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1698                 return;
1699         }
1700
1701         i40e_rx_queue_release_mbufs(q);
1702         rte_free(q->sw_ring);
1703         rte_free(q);
1704 }
1705
1706 uint32_t
1707 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1708 {
1709 #define I40E_RXQ_SCAN_INTERVAL 4
1710         volatile union i40e_rx_desc *rxdp;
1711         struct i40e_rx_queue *rxq;
1712         uint16_t desc = 0;
1713
1714         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1715                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1716                 return 0;
1717         }
1718
1719         rxq = dev->data->rx_queues[rx_queue_id];
1720         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1721         while ((desc < rxq->nb_rx_desc) &&
1722                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1723                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1724                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1725                 /**
1726                  * Check the DD bit of a rx descriptor of each 4 in a group,
1727                  * to avoid checking too frequently and downgrading performance
1728                  * too much.
1729                  */
1730                 desc += I40E_RXQ_SCAN_INTERVAL;
1731                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1732                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1733                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1734                                         desc - rxq->nb_rx_desc]);
1735         }
1736
1737         return desc;
1738 }
1739
1740 int
1741 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1742 {
1743         volatile union i40e_rx_desc *rxdp;
1744         struct i40e_rx_queue *rxq = rx_queue;
1745         uint16_t desc;
1746         int ret;
1747
1748         if (unlikely(offset >= rxq->nb_rx_desc)) {
1749                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1750                 return 0;
1751         }
1752
1753         desc = rxq->rx_tail + offset;
1754         if (desc >= rxq->nb_rx_desc)
1755                 desc -= rxq->nb_rx_desc;
1756
1757         rxdp = &(rxq->rx_ring[desc]);
1758
1759         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1760                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1761                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1762
1763         return ret;
1764 }
1765
1766 int
1767 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1768                         uint16_t queue_idx,
1769                         uint16_t nb_desc,
1770                         unsigned int socket_id,
1771                         const struct rte_eth_txconf *tx_conf)
1772 {
1773         struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1774         struct i40e_tx_queue *txq;
1775         const struct rte_memzone *tz;
1776         uint32_t ring_size;
1777         uint16_t tx_rs_thresh, tx_free_thresh;
1778
1779         if (!vsi || queue_idx >= vsi->nb_qps) {
1780                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1781                             "exceeds the maximum", queue_idx);
1782                 return I40E_ERR_PARAM;
1783         }
1784
1785         if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
1786                                         (nb_desc > I40E_MAX_RING_DESC) ||
1787                                         (nb_desc < I40E_MIN_RING_DESC)) {
1788                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1789                             "invalid", nb_desc);
1790                 return I40E_ERR_PARAM;
1791         }
1792
1793         /**
1794          * The following two parameters control the setting of the RS bit on
1795          * transmit descriptors. TX descriptors will have their RS bit set
1796          * after txq->tx_rs_thresh descriptors have been used. The TX
1797          * descriptor ring will be cleaned after txq->tx_free_thresh
1798          * descriptors are used or if the number of descriptors required to
1799          * transmit a packet is greater than the number of free TX descriptors.
1800          *
1801          * The following constraints must be satisfied:
1802          *  - tx_rs_thresh must be greater than 0.
1803          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1804          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1805          *  - tx_rs_thresh must be a divisor of the ring size.
1806          *  - tx_free_thresh must be greater than 0.
1807          *  - tx_free_thresh must be less than the size of the ring minus 3.
1808          *
1809          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1810          * race condition, hence the maximum threshold constraints. When set
1811          * to zero use default values.
1812          */
1813         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1814                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1815         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1816                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1817         if (tx_rs_thresh >= (nb_desc - 2)) {
1818                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1819                              "number of TX descriptors minus 2. "
1820                              "(tx_rs_thresh=%u port=%d queue=%d)",
1821                              (unsigned int)tx_rs_thresh,
1822                              (int)dev->data->port_id,
1823                              (int)queue_idx);
1824                 return I40E_ERR_PARAM;
1825         }
1826         if (tx_free_thresh >= (nb_desc - 3)) {
1827                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1828                              "tx_free_thresh must be less than the "
1829                              "number of TX descriptors minus 3. "
1830                              "(tx_free_thresh=%u port=%d queue=%d)",
1831                              (unsigned int)tx_free_thresh,
1832                              (int)dev->data->port_id,
1833                              (int)queue_idx);
1834                 return I40E_ERR_PARAM;
1835         }
1836         if (tx_rs_thresh > tx_free_thresh) {
1837                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1838                              "equal to tx_free_thresh. (tx_free_thresh=%u"
1839                              " tx_rs_thresh=%u port=%d queue=%d)",
1840                              (unsigned int)tx_free_thresh,
1841                              (unsigned int)tx_rs_thresh,
1842                              (int)dev->data->port_id,
1843                              (int)queue_idx);
1844                 return I40E_ERR_PARAM;
1845         }
1846         if ((nb_desc % tx_rs_thresh) != 0) {
1847                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1848                              "number of TX descriptors. (tx_rs_thresh=%u"
1849                              " port=%d queue=%d)",
1850                              (unsigned int)tx_rs_thresh,
1851                              (int)dev->data->port_id,
1852                              (int)queue_idx);
1853                 return I40E_ERR_PARAM;
1854         }
1855         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1856                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1857                              "tx_rs_thresh is greater than 1. "
1858                              "(tx_rs_thresh=%u port=%d queue=%d)",
1859                              (unsigned int)tx_rs_thresh,
1860                              (int)dev->data->port_id,
1861                              (int)queue_idx);
1862                 return I40E_ERR_PARAM;
1863         }
1864
1865         /* Free memory if needed. */
1866         if (dev->data->tx_queues[queue_idx]) {
1867                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
1868                 dev->data->tx_queues[queue_idx] = NULL;
1869         }
1870
1871         /* Allocate the TX queue data structure. */
1872         txq = rte_zmalloc_socket("i40e tx queue",
1873                                   sizeof(struct i40e_tx_queue),
1874                                   CACHE_LINE_SIZE,
1875                                   socket_id);
1876         if (!txq) {
1877                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1878                             "tx queue structure");
1879                 return (-ENOMEM);
1880         }
1881
1882         /* Allocate TX hardware ring descriptors. */
1883         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
1884         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1885         tz = i40e_ring_dma_zone_reserve(dev,
1886                                         "tx_ring",
1887                                         queue_idx,
1888                                         ring_size,
1889                                         socket_id);
1890         if (!tz) {
1891                 i40e_dev_tx_queue_release(txq);
1892                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
1893                 return (-ENOMEM);
1894         }
1895
1896         txq->nb_tx_desc = nb_desc;
1897         txq->tx_rs_thresh = tx_rs_thresh;
1898         txq->tx_free_thresh = tx_free_thresh;
1899         txq->pthresh = tx_conf->tx_thresh.pthresh;
1900         txq->hthresh = tx_conf->tx_thresh.hthresh;
1901         txq->wthresh = tx_conf->tx_thresh.wthresh;
1902         txq->queue_id = queue_idx;
1903         txq->reg_idx = vsi->base_queue + queue_idx;
1904         txq->port_id = dev->data->port_id;
1905         txq->txq_flags = tx_conf->txq_flags;
1906         txq->vsi = vsi;
1907         txq->tx_deferred_start = tx_conf->tx_deferred_start;
1908
1909 #ifdef RTE_LIBRTE_XEN_DOM0
1910         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1911 #else
1912         txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
1913 #endif
1914         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
1915
1916         /* Allocate software ring */
1917         txq->sw_ring =
1918                 rte_zmalloc_socket("i40e tx sw ring",
1919                                    sizeof(struct i40e_tx_entry) * nb_desc,
1920                                    CACHE_LINE_SIZE,
1921                                    socket_id);
1922         if (!txq->sw_ring) {
1923                 i40e_dev_tx_queue_release(txq);
1924                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
1925                 return (-ENOMEM);
1926         }
1927
1928         i40e_reset_tx_queue(txq);
1929         txq->q_set = TRUE;
1930         dev->data->tx_queues[queue_idx] = txq;
1931
1932         /* Use a simple TX queue without offloads or multi segs if possible */
1933         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
1934                                 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
1935                 PMD_INIT_LOG(INFO, "Using simple tx path");
1936                 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
1937         } else {
1938                 PMD_INIT_LOG(INFO, "Using full-featured tx path");
1939                 dev->tx_pkt_burst = i40e_xmit_pkts;
1940         }
1941
1942         return 0;
1943 }
1944
1945 void
1946 i40e_dev_tx_queue_release(void *txq)
1947 {
1948         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
1949
1950         if (!q) {
1951                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1952                 return;
1953         }
1954
1955         i40e_tx_queue_release_mbufs(q);
1956         rte_free(q->sw_ring);
1957         rte_free(q);
1958 }
1959
1960 static const struct rte_memzone *
1961 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
1962                            const char *ring_name,
1963                            uint16_t queue_id,
1964                            uint32_t ring_size,
1965                            int socket_id)
1966 {
1967         char z_name[RTE_MEMZONE_NAMESIZE];
1968         const struct rte_memzone *mz;
1969
1970         snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1971                         dev->driver->pci_drv.name, ring_name,
1972                                 dev->data->port_id, queue_id);
1973         mz = rte_memzone_lookup(z_name);
1974         if (mz)
1975                 return mz;
1976
1977 #ifdef RTE_LIBRTE_XEN_DOM0
1978         return rte_memzone_reserve_bounded(z_name, ring_size,
1979                 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
1980 #else
1981         return rte_memzone_reserve_aligned(z_name, ring_size,
1982                                 socket_id, 0, I40E_ALIGN);
1983 #endif
1984 }
1985
1986 void
1987 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
1988 {
1989         uint16_t i;
1990
1991         if (!rxq || !rxq->sw_ring) {
1992                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
1993                 return;
1994         }
1995
1996         for (i = 0; i < rxq->nb_rx_desc; i++) {
1997                 if (rxq->sw_ring[i].mbuf) {
1998                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1999                         rxq->sw_ring[i].mbuf = NULL;
2000                 }
2001         }
2002 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2003         if (rxq->rx_nb_avail == 0)
2004                 return;
2005         for (i = 0; i < rxq->rx_nb_avail; i++) {
2006                 struct rte_mbuf *mbuf;
2007
2008                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2009                 rte_pktmbuf_free_seg(mbuf);
2010         }
2011         rxq->rx_nb_avail = 0;
2012 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2013 }
2014
2015 void
2016 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2017 {
2018         unsigned i;
2019         uint16_t len;
2020
2021 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2022         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2023                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2024         else
2025 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2026                 len = rxq->nb_rx_desc;
2027
2028         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2029                 ((volatile char *)rxq->rx_ring)[i] = 0;
2030
2031 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2032         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2033         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2034                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2035
2036         rxq->rx_nb_avail = 0;
2037         rxq->rx_next_avail = 0;
2038         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2039 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2040         rxq->rx_tail = 0;
2041         rxq->nb_rx_hold = 0;
2042         rxq->pkt_first_seg = NULL;
2043         rxq->pkt_last_seg = NULL;
2044 }
2045
2046 void
2047 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2048 {
2049         uint16_t i;
2050
2051         if (!txq || !txq->sw_ring) {
2052                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2053                 return;
2054         }
2055
2056         for (i = 0; i < txq->nb_tx_desc; i++) {
2057                 if (txq->sw_ring[i].mbuf) {
2058                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2059                         txq->sw_ring[i].mbuf = NULL;
2060                 }
2061         }
2062 }
2063
2064 void
2065 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2066 {
2067         struct i40e_tx_entry *txe;
2068         uint16_t i, prev, size;
2069
2070         if (!txq) {
2071                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2072                 return;
2073         }
2074
2075         txe = txq->sw_ring;
2076         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2077         for (i = 0; i < size; i++)
2078                 ((volatile char *)txq->tx_ring)[i] = 0;
2079
2080         prev = (uint16_t)(txq->nb_tx_desc - 1);
2081         for (i = 0; i < txq->nb_tx_desc; i++) {
2082                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2083
2084                 txd->cmd_type_offset_bsz =
2085                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2086                 txe[i].mbuf =  NULL;
2087                 txe[i].last_id = i;
2088                 txe[prev].next_id = i;
2089                 prev = i;
2090         }
2091
2092         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2093         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2094
2095         txq->tx_tail = 0;
2096         txq->nb_tx_used = 0;
2097
2098         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2099         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2100 }
2101
2102 /* Init the TX queue in hardware */
2103 int
2104 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2105 {
2106         enum i40e_status_code err = I40E_SUCCESS;
2107         struct i40e_vsi *vsi = txq->vsi;
2108         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2109         uint16_t pf_q = txq->reg_idx;
2110         struct i40e_hmc_obj_txq tx_ctx;
2111         uint32_t qtx_ctl;
2112
2113         /* clear the context structure first */
2114         memset(&tx_ctx, 0, sizeof(tx_ctx));
2115         tx_ctx.new_context = 1;
2116         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2117         tx_ctx.qlen = txq->nb_tx_desc;
2118         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2119
2120         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2121         if (err != I40E_SUCCESS) {
2122                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2123                 return err;
2124         }
2125
2126         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2127         if (err != I40E_SUCCESS) {
2128                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2129                 return err;
2130         }
2131
2132         /* Now associate this queue with this PCI function */
2133         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2134         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2135                                         I40E_QTX_CTL_PF_INDX_MASK);
2136         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2137         I40E_WRITE_FLUSH(hw);
2138
2139         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2140
2141         return err;
2142 }
2143
2144 int
2145 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2146 {
2147         struct i40e_rx_entry *rxe = rxq->sw_ring;
2148         uint64_t dma_addr;
2149         uint16_t i;
2150
2151         for (i = 0; i < rxq->nb_rx_desc; i++) {
2152                 volatile union i40e_rx_desc *rxd;
2153                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2154
2155                 if (unlikely(!mbuf)) {
2156                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2157                         return -ENOMEM;
2158                 }
2159
2160                 rte_mbuf_refcnt_set(mbuf, 1);
2161                 mbuf->next = NULL;
2162                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2163                 mbuf->nb_segs = 1;
2164                 mbuf->port = rxq->port_id;
2165
2166                 dma_addr =
2167                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2168
2169                 rxd = &rxq->rx_ring[i];
2170                 rxd->read.pkt_addr = dma_addr;
2171                 rxd->read.hdr_addr = dma_addr;
2172 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2173                 rxd->read.rsvd1 = 0;
2174                 rxd->read.rsvd2 = 0;
2175 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2176
2177                 rxe[i].mbuf = mbuf;
2178         }
2179
2180         return 0;
2181 }
2182
2183 /*
2184  * Calculate the buffer length, and check the jumbo frame
2185  * and maximum packet length.
2186  */
2187 static int
2188 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2189 {
2190         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2191         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2192         struct rte_eth_dev_data *data = pf->dev_data;
2193         struct rte_pktmbuf_pool_private *mbp_priv =
2194                         rte_mempool_get_priv(rxq->mp);
2195         uint16_t buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2196                                                 RTE_PKTMBUF_HEADROOM);
2197         uint16_t len;
2198
2199         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2200                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2201         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2202                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2203                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2204                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2205                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2206                 rxq->hs_mode = i40e_header_split_enabled;
2207                 break;
2208         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2209         default:
2210                 rxq->rx_hdr_len = 0;
2211                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2212                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2213                 rxq->hs_mode = i40e_header_split_none;
2214                 break;
2215         }
2216
2217         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2218         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2219         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2220                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2221                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2222                         PMD_DRV_LOG(ERR, "maximum packet length must "
2223                                     "be larger than %u and smaller than %u,"
2224                                     "as jumbo frame is enabled",
2225                                     (uint32_t)ETHER_MAX_LEN,
2226                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2227                         return I40E_ERR_CONFIG;
2228                 }
2229         } else {
2230                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2231                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2232                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2233                                     "larger than %u and smaller than %u, "
2234                                     "as jumbo frame is disabled",
2235                                     (uint32_t)ETHER_MIN_LEN,
2236                                     (uint32_t)ETHER_MAX_LEN);
2237                         return I40E_ERR_CONFIG;
2238                 }
2239         }
2240
2241         return 0;
2242 }
2243
2244 /* Init the RX queue in hardware */
2245 int
2246 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2247 {
2248         int err = I40E_SUCCESS;
2249         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2250         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2251         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2252         uint16_t pf_q = rxq->reg_idx;
2253         uint16_t buf_size;
2254         struct i40e_hmc_obj_rxq rx_ctx;
2255         struct rte_pktmbuf_pool_private *mbp_priv;
2256
2257         err = i40e_rx_queue_config(rxq);
2258         if (err < 0) {
2259                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2260                 return err;
2261         }
2262
2263         /* Clear the context structure first */
2264         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2265         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2266         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2267
2268         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2269         rx_ctx.qlen = rxq->nb_rx_desc;
2270 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2271         rx_ctx.dsize = 1;
2272 #endif
2273         rx_ctx.dtype = rxq->hs_mode;
2274         if (rxq->hs_mode)
2275                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2276         else
2277                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2278         rx_ctx.rxmax = rxq->max_pkt_len;
2279         rx_ctx.tphrdesc_ena = 1;
2280         rx_ctx.tphwdesc_ena = 1;
2281         rx_ctx.tphdata_ena = 1;
2282         rx_ctx.tphhead_ena = 1;
2283         rx_ctx.lrxqthresh = 2;
2284         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2285         rx_ctx.l2tsel = 1;
2286         rx_ctx.showiv = 1;
2287         rx_ctx.prefena = 1;
2288
2289         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2290         if (err != I40E_SUCCESS) {
2291                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2292                 return err;
2293         }
2294         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2295         if (err != I40E_SUCCESS) {
2296                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2297                 return err;
2298         }
2299
2300         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2301
2302         mbp_priv = rte_mempool_get_priv(rxq->mp);
2303         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2304                                         RTE_PKTMBUF_HEADROOM);
2305
2306         /* Check if scattered RX needs to be used. */
2307         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2308                 dev_data->scattered_rx = 1;
2309                 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2310         }
2311
2312         /* Init the RX tail regieter. */
2313         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2314
2315         return 0;
2316 }
2317
2318 void
2319 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2320 {
2321         uint16_t i;
2322
2323         PMD_INIT_FUNC_TRACE();
2324
2325         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2326                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2327                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2328         }
2329
2330         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2331                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2332                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2333         }
2334 }