4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
54 #include "i40e_logs.h"
55 #include "i40e/i40e_prototype.h"
56 #include "i40e/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
60 #define I40E_MIN_RING_DESC 64
61 #define I40E_MAX_RING_DESC 4096
62 #define I40E_ALIGN 128
63 #define DEFAULT_TX_RS_THRESH 32
64 #define DEFAULT_TX_FREE_THRESH 32
65 #define I40E_MAX_PKT_TYPE 256
67 #define I40E_VLAN_TAG_SIZE 4
68 #define I40E_TX_MAX_BURST 32
70 #define I40E_DMA_MEM_ALIGN 4096
72 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
73 ETH_TXQ_FLAGS_NOOFFLOADS)
75 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
77 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
78 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
80 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
81 ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
83 static const struct rte_memzone *
84 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
85 const char *ring_name,
89 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
90 struct rte_mbuf **tx_pkts,
93 /* Translate the rx descriptor status to pkt flags */
94 static inline uint64_t
95 i40e_rxd_status_to_pkt_flags(uint64_t qword)
99 /* Check if VLAN packet */
100 flags = qword & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
103 /* Check if RSS_HASH */
104 flags |= (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
105 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
106 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
108 /* Check if FDIR Match */
109 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
115 static inline uint64_t
116 i40e_rxd_error_to_pkt_flags(uint64_t qword)
119 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
121 #define I40E_RX_ERR_BITS 0x3f
122 if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
124 /* If RXE bit set, all other status bits are meaningless */
125 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
126 flags |= PKT_RX_MAC_ERR;
130 /* If RECIPE bit set, all other status indications should be ignored */
131 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
132 flags |= PKT_RX_RECIP_ERR;
135 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
136 flags |= PKT_RX_HBUF_OVERFLOW;
137 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
138 flags |= PKT_RX_IP_CKSUM_BAD;
139 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
140 flags |= PKT_RX_L4_CKSUM_BAD;
141 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
142 flags |= PKT_RX_EIP_CKSUM_BAD;
143 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
144 flags |= PKT_RX_OVERSIZE;
149 /* Translate pkt types to pkt flags */
150 static inline uint64_t
151 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
153 uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
154 I40E_RXD_QW1_PTYPE_SHIFT);
155 static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
178 PKT_RX_IPV4_HDR, /* PTYPE 22 */
179 PKT_RX_IPV4_HDR, /* PTYPE 23 */
180 PKT_RX_IPV4_HDR, /* PTYPE 24 */
182 PKT_RX_IPV4_HDR, /* PTYPE 26 */
183 PKT_RX_IPV4_HDR, /* PTYPE 27 */
184 PKT_RX_IPV4_HDR, /* PTYPE 28 */
185 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
186 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
187 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
189 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
190 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
191 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
192 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
193 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
194 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
196 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
197 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
198 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
199 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
200 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
201 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
202 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
204 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
205 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
206 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
207 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
208 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
209 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
211 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
212 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
213 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
214 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
215 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 59 */
216 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 60 */
217 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 61 */
219 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 63 */
220 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 64 */
221 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 65 */
222 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 66 */
223 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 67 */
224 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 68 */
226 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 70 */
227 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 71 */
228 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 72 */
229 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 73 */
230 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 74 */
231 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 75 */
232 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 76 */
234 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 78 */
235 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 79 */
236 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 80 */
237 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 81 */
238 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 82 */
239 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 83 */
241 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 85 */
242 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 86 */
243 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
244 PKT_RX_IPV6_HDR, /* PTYPE 88 */
245 PKT_RX_IPV6_HDR, /* PTYPE 89 */
246 PKT_RX_IPV6_HDR, /* PTYPE 90 */
248 PKT_RX_IPV6_HDR, /* PTYPE 92 */
249 PKT_RX_IPV6_HDR, /* PTYPE 93 */
250 PKT_RX_IPV6_HDR, /* PTYPE 94 */
251 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
252 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
253 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
255 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
256 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
257 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
258 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
259 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
260 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
262 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
263 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
264 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
265 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
266 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
267 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
268 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
270 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
271 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
272 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
273 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
274 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
275 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
277 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
278 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
279 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
280 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
281 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 125 */
282 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 126 */
283 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 127 */
285 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 129 */
286 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 130 */
287 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 131 */
288 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 132 */
289 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 133 */
290 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 134 */
292 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 136 */
293 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 137 */
294 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 138 */
295 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 139 */
296 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 140 */
297 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 141 */
298 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 142 */
300 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 144 */
301 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 145 */
302 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 146 */
303 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 147 */
304 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 148 */
305 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 149 */
307 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 151 */
308 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 152 */
309 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
414 return ip_ptype_map[ptype];
417 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
418 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
419 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
420 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
421 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
423 static inline uint64_t
424 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
427 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
428 uint16_t flexbh, flexbl;
430 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
431 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
432 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
433 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
434 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
435 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
438 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
440 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
441 flags |= PKT_RX_FDIR_ID;
442 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
444 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
445 flags |= PKT_RX_FDIR_FLX;
447 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
449 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
450 flags |= PKT_RX_FDIR_FLX;
454 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
455 flags |= PKT_RX_FDIR_ID;
460 i40e_txd_enable_checksum(uint64_t ol_flags,
465 uint8_t outer_l2_len,
466 uint16_t outer_l3_len,
467 uint32_t *cd_tunneling)
470 PMD_DRV_LOG(DEBUG, "L2 length set to 0");
475 PMD_DRV_LOG(DEBUG, "L3 length set to 0");
479 /* UDP tunneling packet TX checksum offload */
480 if (unlikely(ol_flags & PKT_TX_UDP_TUNNEL_PKT)) {
482 *td_offset |= (outer_l2_len >> 1)
483 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
485 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
486 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
487 else if (ol_flags & PKT_TX_OUTER_IPV4)
488 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
489 else if (ol_flags & PKT_TX_OUTER_IPV6)
490 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
492 /* Now set the ctx descriptor fields */
493 *cd_tunneling |= (outer_l3_len >> 2) <<
494 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
495 I40E_TXD_CTX_UDP_TUNNELING |
497 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
500 *td_offset |= (l2_len >> 1)
501 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
503 /* Enable L3 checksum offloads */
504 if (ol_flags & PKT_TX_IPV4_CSUM) {
505 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
506 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
507 } else if (ol_flags & PKT_TX_IPV4) {
508 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
509 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
510 } else if (ol_flags & PKT_TX_IPV6) {
511 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
512 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
515 /* Enable L4 checksum offloads */
516 switch (ol_flags & PKT_TX_L4_MASK) {
517 case PKT_TX_TCP_CKSUM:
518 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
519 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
520 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
522 case PKT_TX_SCTP_CKSUM:
523 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
524 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
525 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
527 case PKT_TX_UDP_CKSUM:
528 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
529 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
530 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
537 static inline struct rte_mbuf *
538 rte_rxmbuf_alloc(struct rte_mempool *mp)
542 m = __rte_mbuf_raw_alloc(mp);
543 __rte_mbuf_sanity_check_raw(m, 0);
548 /* Construct the tx flags */
549 static inline uint64_t
550 i40e_build_ctob(uint32_t td_cmd,
555 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
556 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
557 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
558 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
559 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
563 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
565 struct i40e_tx_entry *sw_ring = txq->sw_ring;
566 volatile struct i40e_tx_desc *txd = txq->tx_ring;
567 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
568 uint16_t nb_tx_desc = txq->nb_tx_desc;
569 uint16_t desc_to_clean_to;
570 uint16_t nb_tx_to_clean;
572 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
573 if (desc_to_clean_to >= nb_tx_desc)
574 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
576 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
577 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
578 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) {
579 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
580 "(port=%d queue=%d)", desc_to_clean_to,
581 txq->port_id, txq->queue_id);
585 if (last_desc_cleaned > desc_to_clean_to)
586 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
589 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
592 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
594 txq->last_desc_cleaned = desc_to_clean_to;
595 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
601 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
602 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
604 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
609 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
610 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
611 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
612 "rxq->rx_free_thresh=%d, "
613 "RTE_PMD_I40E_RX_MAX_BURST=%d",
614 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
616 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
617 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
618 "rxq->rx_free_thresh=%d, "
619 "rxq->nb_rx_desc=%d",
620 rxq->rx_free_thresh, rxq->nb_rx_desc);
622 } else if (!(rxq->nb_rx_desc % rxq->rx_free_thresh) == 0) {
623 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
624 "rxq->nb_rx_desc=%d, "
625 "rxq->rx_free_thresh=%d",
626 rxq->nb_rx_desc, rxq->rx_free_thresh);
628 } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
629 RTE_PMD_I40E_RX_MAX_BURST))) {
630 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
631 "rxq->nb_rx_desc=%d, "
632 "I40E_MAX_RING_DESC=%d, "
633 "RTE_PMD_I40E_RX_MAX_BURST=%d",
634 rxq->nb_rx_desc, I40E_MAX_RING_DESC,
635 RTE_PMD_I40E_RX_MAX_BURST);
645 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
646 #define I40E_LOOK_AHEAD 8
647 #if (I40E_LOOK_AHEAD != 8)
648 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
651 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
653 volatile union i40e_rx_desc *rxdp;
654 struct i40e_rx_entry *rxep;
659 int32_t s[I40E_LOOK_AHEAD], nb_dd;
660 int32_t i, j, nb_rx = 0;
663 rxdp = &rxq->rx_ring[rxq->rx_tail];
664 rxep = &rxq->sw_ring[rxq->rx_tail];
666 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
667 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
668 I40E_RXD_QW1_STATUS_SHIFT;
670 /* Make sure there is at least 1 packet to receive */
671 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
675 * Scan LOOK_AHEAD descriptors at a time to determine which
676 * descriptors reference packets that are ready to be received.
678 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
679 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
680 /* Read desc statuses backwards to avoid race condition */
681 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
682 qword1 = rte_le_to_cpu_64(\
683 rxdp[j].wb.qword1.status_error_len);
684 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
685 I40E_RXD_QW1_STATUS_SHIFT;
688 /* Compute how many status bits were set */
689 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
690 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
694 /* Translate descriptor info to mbuf parameters */
695 for (j = 0; j < nb_dd; j++) {
697 qword1 = rte_le_to_cpu_64(\
698 rxdp[j].wb.qword1.status_error_len);
699 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
700 I40E_RXD_QW1_STATUS_SHIFT;
701 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
702 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
703 mb->data_len = pkt_len;
704 mb->pkt_len = pkt_len;
705 mb->vlan_tci = rx_status &
706 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
708 rxdp[j].wb.qword0.lo_dword.l2tag1) : 0;
709 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
710 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
711 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
713 mb->packet_type = (uint16_t)((qword1 &
714 I40E_RXD_QW1_PTYPE_MASK) >>
715 I40E_RXD_QW1_PTYPE_SHIFT);
716 if (pkt_flags & PKT_RX_RSS_HASH)
717 mb->hash.rss = rte_le_to_cpu_32(\
718 rxdp[j].wb.qword0.hi_dword.rss);
719 if (pkt_flags & PKT_RX_FDIR)
720 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
722 mb->ol_flags = pkt_flags;
725 for (j = 0; j < I40E_LOOK_AHEAD; j++)
726 rxq->rx_stage[i + j] = rxep[j].mbuf;
728 if (nb_dd != I40E_LOOK_AHEAD)
732 /* Clear software ring entries */
733 for (i = 0; i < nb_rx; i++)
734 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
739 static inline uint16_t
740 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
741 struct rte_mbuf **rx_pkts,
745 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
747 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
749 for (i = 0; i < nb_pkts; i++)
750 rx_pkts[i] = stage[i];
752 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
753 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
759 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
761 volatile union i40e_rx_desc *rxdp;
762 struct i40e_rx_entry *rxep;
764 uint16_t alloc_idx, i;
768 /* Allocate buffers in bulk */
769 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
770 (rxq->rx_free_thresh - 1));
771 rxep = &(rxq->sw_ring[alloc_idx]);
772 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
773 rxq->rx_free_thresh);
774 if (unlikely(diag != 0)) {
775 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
779 rxdp = &rxq->rx_ring[alloc_idx];
780 for (i = 0; i < rxq->rx_free_thresh; i++) {
782 rte_mbuf_refcnt_set(mb, 1);
784 mb->data_off = RTE_PKTMBUF_HEADROOM;
786 mb->port = rxq->port_id;
787 dma_addr = rte_cpu_to_le_64(\
788 RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
789 rxdp[i].read.hdr_addr = dma_addr;
790 rxdp[i].read.pkt_addr = dma_addr;
793 /* Update rx tail regsiter */
795 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
797 rxq->rx_free_trigger =
798 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
799 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
800 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
805 static inline uint16_t
806 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
808 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
814 if (rxq->rx_nb_avail)
815 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
817 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
818 rxq->rx_next_avail = 0;
819 rxq->rx_nb_avail = nb_rx;
820 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
822 if (rxq->rx_tail > rxq->rx_free_trigger) {
823 if (i40e_rx_alloc_bufs(rxq) != 0) {
826 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
827 "port_id=%u, queue_id=%u",
828 rxq->port_id, rxq->queue_id);
829 rxq->rx_nb_avail = 0;
830 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
831 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
832 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
838 if (rxq->rx_tail >= rxq->nb_rx_desc)
841 if (rxq->rx_nb_avail)
842 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
848 i40e_recv_pkts_bulk_alloc(void *rx_queue,
849 struct rte_mbuf **rx_pkts,
852 uint16_t nb_rx = 0, n, count;
854 if (unlikely(nb_pkts == 0))
857 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
858 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
861 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
862 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
863 nb_rx = (uint16_t)(nb_rx + count);
864 nb_pkts = (uint16_t)(nb_pkts - count);
871 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
874 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
876 struct i40e_rx_queue *rxq;
877 volatile union i40e_rx_desc *rx_ring;
878 volatile union i40e_rx_desc *rxdp;
879 union i40e_rx_desc rxd;
880 struct i40e_rx_entry *sw_ring;
881 struct i40e_rx_entry *rxe;
882 struct rte_mbuf *rxm;
883 struct rte_mbuf *nmb;
887 uint16_t rx_packet_len;
888 uint16_t rx_id, nb_hold;
895 rx_id = rxq->rx_tail;
896 rx_ring = rxq->rx_ring;
897 sw_ring = rxq->sw_ring;
899 while (nb_rx < nb_pkts) {
900 rxdp = &rx_ring[rx_id];
901 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
902 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
903 >> I40E_RXD_QW1_STATUS_SHIFT;
904 /* Check the DD bit first */
905 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
908 nmb = rte_rxmbuf_alloc(rxq->mp);
914 rxe = &sw_ring[rx_id];
916 if (unlikely(rx_id == rxq->nb_rx_desc))
919 /* Prefetch next mbuf */
920 rte_prefetch0(sw_ring[rx_id].mbuf);
923 * When next RX descriptor is on a cache line boundary,
924 * prefetch the next 4 RX descriptors and next 8 pointers
927 if ((rx_id & 0x3) == 0) {
928 rte_prefetch0(&rx_ring[rx_id]);
929 rte_prefetch0(&sw_ring[rx_id]);
934 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
935 rxdp->read.hdr_addr = dma_addr;
936 rxdp->read.pkt_addr = dma_addr;
938 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
939 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
941 rxm->data_off = RTE_PKTMBUF_HEADROOM;
942 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
945 rxm->pkt_len = rx_packet_len;
946 rxm->data_len = rx_packet_len;
947 rxm->port = rxq->port_id;
949 rxm->vlan_tci = rx_status &
950 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
951 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
952 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
953 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
954 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
955 rxm->packet_type = (uint16_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >>
956 I40E_RXD_QW1_PTYPE_SHIFT);
957 if (pkt_flags & PKT_RX_RSS_HASH)
959 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
960 if (pkt_flags & PKT_RX_FDIR)
961 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
963 rxm->ol_flags = pkt_flags;
965 rx_pkts[nb_rx++] = rxm;
967 rxq->rx_tail = rx_id;
970 * If the number of free RX descriptors is greater than the RX free
971 * threshold of the queue, advance the receive tail register of queue.
972 * Update that register with the value of the last processed RX
973 * descriptor minus 1.
975 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
976 if (nb_hold > rxq->rx_free_thresh) {
977 rx_id = (uint16_t) ((rx_id == 0) ?
978 (rxq->nb_rx_desc - 1) : (rx_id - 1));
979 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
982 rxq->nb_rx_hold = nb_hold;
988 i40e_recv_scattered_pkts(void *rx_queue,
989 struct rte_mbuf **rx_pkts,
992 struct i40e_rx_queue *rxq = rx_queue;
993 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
994 volatile union i40e_rx_desc *rxdp;
995 union i40e_rx_desc rxd;
996 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
997 struct i40e_rx_entry *rxe;
998 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
999 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1000 struct rte_mbuf *nmb, *rxm;
1001 uint16_t rx_id = rxq->rx_tail;
1002 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1008 while (nb_rx < nb_pkts) {
1009 rxdp = &rx_ring[rx_id];
1010 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1011 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1012 I40E_RXD_QW1_STATUS_SHIFT;
1013 /* Check the DD bit */
1014 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1017 nmb = rte_rxmbuf_alloc(rxq->mp);
1022 rxe = &sw_ring[rx_id];
1024 if (rx_id == rxq->nb_rx_desc)
1027 /* Prefetch next mbuf */
1028 rte_prefetch0(sw_ring[rx_id].mbuf);
1031 * When next RX descriptor is on a cache line boundary,
1032 * prefetch the next 4 RX descriptors and next 8 pointers
1035 if ((rx_id & 0x3) == 0) {
1036 rte_prefetch0(&rx_ring[rx_id]);
1037 rte_prefetch0(&sw_ring[rx_id]);
1043 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1045 /* Set data buffer address and data length of the mbuf */
1046 rxdp->read.hdr_addr = dma_addr;
1047 rxdp->read.pkt_addr = dma_addr;
1048 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1049 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1050 rxm->data_len = rx_packet_len;
1051 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1054 * If this is the first buffer of the received packet, set the
1055 * pointer to the first mbuf of the packet and initialize its
1056 * context. Otherwise, update the total length and the number
1057 * of segments of the current scattered packet, and update the
1058 * pointer to the last mbuf of the current packet.
1062 first_seg->nb_segs = 1;
1063 first_seg->pkt_len = rx_packet_len;
1065 first_seg->pkt_len =
1066 (uint16_t)(first_seg->pkt_len +
1068 first_seg->nb_segs++;
1069 last_seg->next = rxm;
1073 * If this is not the last buffer of the received packet,
1074 * update the pointer to the last mbuf of the current scattered
1075 * packet and continue to parse the RX ring.
1077 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1083 * This is the last buffer of the received packet. If the CRC
1084 * is not stripped by the hardware:
1085 * - Subtract the CRC length from the total packet length.
1086 * - If the last buffer only contains the whole CRC or a part
1087 * of it, free the mbuf associated to the last buffer. If part
1088 * of the CRC is also contained in the previous mbuf, subtract
1089 * the length of that CRC part from the data length of the
1093 if (unlikely(rxq->crc_len > 0)) {
1094 first_seg->pkt_len -= ETHER_CRC_LEN;
1095 if (rx_packet_len <= ETHER_CRC_LEN) {
1096 rte_pktmbuf_free_seg(rxm);
1097 first_seg->nb_segs--;
1098 last_seg->data_len =
1099 (uint16_t)(last_seg->data_len -
1100 (ETHER_CRC_LEN - rx_packet_len));
1101 last_seg->next = NULL;
1103 rxm->data_len = (uint16_t)(rx_packet_len -
1107 first_seg->port = rxq->port_id;
1108 first_seg->vlan_tci = (rx_status &
1109 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1110 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
1111 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1112 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1113 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1114 first_seg->packet_type = (uint16_t)((qword1 &
1115 I40E_RXD_QW1_PTYPE_MASK) >>
1116 I40E_RXD_QW1_PTYPE_SHIFT);
1117 if (pkt_flags & PKT_RX_RSS_HASH)
1119 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1120 if (pkt_flags & PKT_RX_FDIR)
1121 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1123 first_seg->ol_flags = pkt_flags;
1125 /* Prefetch data of first segment, if configured to do so. */
1126 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1127 first_seg->data_off));
1128 rx_pkts[nb_rx++] = first_seg;
1132 /* Record index of the next RX descriptor to probe. */
1133 rxq->rx_tail = rx_id;
1134 rxq->pkt_first_seg = first_seg;
1135 rxq->pkt_last_seg = last_seg;
1138 * If the number of free RX descriptors is greater than the RX free
1139 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1140 * register. Update the RDT with the value of the last processed RX
1141 * descriptor minus 1, to guarantee that the RDT register is never
1142 * equal to the RDH register, which creates a "full" ring situtation
1143 * from the hardware point of view.
1145 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1146 if (nb_hold > rxq->rx_free_thresh) {
1147 rx_id = (uint16_t)(rx_id == 0 ?
1148 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1149 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1152 rxq->nb_rx_hold = nb_hold;
1157 /* Check if the context descriptor is needed for TX offloading */
1158 static inline uint16_t
1159 i40e_calc_context_desc(uint64_t flags)
1161 uint64_t mask = 0ULL;
1163 if (flags | PKT_TX_UDP_TUNNEL_PKT)
1164 mask |= PKT_TX_UDP_TUNNEL_PKT;
1166 #ifdef RTE_LIBRTE_IEEE1588
1167 mask |= PKT_TX_IEEE1588_TMST;
1176 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1178 struct i40e_tx_queue *txq;
1179 struct i40e_tx_entry *sw_ring;
1180 struct i40e_tx_entry *txe, *txn;
1181 volatile struct i40e_tx_desc *txd;
1182 volatile struct i40e_tx_desc *txr;
1183 struct rte_mbuf *tx_pkt;
1184 struct rte_mbuf *m_seg;
1185 uint32_t cd_tunneling_params;
1195 uint8_t outer_l2_len;
1196 uint16_t outer_l3_len;
1201 uint64_t buf_dma_addr;
1204 sw_ring = txq->sw_ring;
1206 tx_id = txq->tx_tail;
1207 txe = &sw_ring[tx_id];
1209 /* Check if the descriptor ring needs to be cleaned. */
1210 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh)
1211 i40e_xmit_cleanup(txq);
1213 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1219 tx_pkt = *tx_pkts++;
1220 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1222 ol_flags = tx_pkt->ol_flags;
1223 l2_len = tx_pkt->l2_len;
1224 l3_len = tx_pkt->l3_len;
1225 outer_l2_len = tx_pkt->outer_l2_len;
1226 outer_l3_len = tx_pkt->outer_l3_len;
1228 /* Calculate the number of context descriptors needed. */
1229 nb_ctx = i40e_calc_context_desc(ol_flags);
1232 * The number of descriptors that must be allocated for
1233 * a packet equals to the number of the segments of that
1234 * packet plus 1 context descriptor if needed.
1236 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1237 tx_last = (uint16_t)(tx_id + nb_used - 1);
1240 if (tx_last >= txq->nb_tx_desc)
1241 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1243 if (nb_used > txq->nb_tx_free) {
1244 if (i40e_xmit_cleanup(txq) != 0) {
1249 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1250 while (nb_used > txq->nb_tx_free) {
1251 if (i40e_xmit_cleanup(txq) != 0) {
1260 /* Descriptor based VLAN insertion */
1261 if (ol_flags & PKT_TX_VLAN_PKT) {
1262 tx_flags |= tx_pkt->vlan_tci <<
1263 I40E_TX_FLAG_L2TAG1_SHIFT;
1264 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1265 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1266 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1267 I40E_TX_FLAG_L2TAG1_SHIFT;
1270 /* Always enable CRC offload insertion */
1271 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1273 /* Enable checksum offloading */
1274 cd_tunneling_params = 0;
1275 i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1276 l2_len, l3_len, outer_l2_len,
1278 &cd_tunneling_params);
1280 if (unlikely(nb_ctx)) {
1281 /* Setup TX context descriptor if required */
1282 volatile struct i40e_tx_context_desc *ctx_txd =
1283 (volatile struct i40e_tx_context_desc *)\
1285 uint16_t cd_l2tag2 = 0;
1286 uint64_t cd_type_cmd_tso_mss =
1287 I40E_TX_DESC_DTYPE_CONTEXT;
1289 txn = &sw_ring[txe->next_id];
1290 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1291 if (txe->mbuf != NULL) {
1292 rte_pktmbuf_free_seg(txe->mbuf);
1295 #ifdef RTE_LIBRTE_IEEE1588
1296 if (ol_flags & PKT_TX_IEEE1588_TMST)
1297 cd_type_cmd_tso_mss |=
1298 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1299 I40E_TXD_CTX_QW1_CMD_SHIFT);
1301 ctx_txd->tunneling_params =
1302 rte_cpu_to_le_32(cd_tunneling_params);
1303 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1304 ctx_txd->type_cmd_tso_mss =
1305 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1306 txe->last_id = tx_last;
1307 tx_id = txe->next_id;
1314 txn = &sw_ring[txe->next_id];
1317 rte_pktmbuf_free_seg(txe->mbuf);
1320 /* Setup TX Descriptor */
1321 slen = m_seg->data_len;
1322 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1323 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1324 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1325 td_offset, slen, td_tag);
1326 txe->last_id = tx_last;
1327 tx_id = txe->next_id;
1329 m_seg = m_seg->next;
1330 } while (m_seg != NULL);
1332 /* The last packet data descriptor needs End Of Packet (EOP) */
1333 td_cmd |= I40E_TX_DESC_CMD_EOP;
1334 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1335 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1337 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1338 PMD_TX_FREE_LOG(DEBUG,
1339 "Setting RS bit on TXD id="
1340 "%4u (port=%d queue=%d)",
1341 tx_last, txq->port_id, txq->queue_id);
1343 td_cmd |= I40E_TX_DESC_CMD_RS;
1345 /* Update txq RS bit counters */
1346 txq->nb_tx_used = 0;
1349 txd->cmd_type_offset_bsz |=
1350 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1351 I40E_TXD_QW1_CMD_SHIFT);
1357 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1358 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1359 (unsigned) tx_id, (unsigned) nb_tx);
1361 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1362 txq->tx_tail = tx_id;
1367 static inline int __attribute__((always_inline))
1368 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1370 struct i40e_tx_entry *txep;
1373 if (!(txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1374 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)))
1377 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1379 for (i = 0; i < txq->tx_rs_thresh; i++)
1380 rte_prefetch0((txep + i)->mbuf);
1382 if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1383 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1384 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1388 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1389 rte_pktmbuf_free_seg(txep->mbuf);
1394 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1395 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1396 if (txq->tx_next_dd >= txq->nb_tx_desc)
1397 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1399 return txq->tx_rs_thresh;
1402 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1403 I40E_TX_DESC_CMD_EOP)
1405 /* Populate 4 descriptors with data from 4 mbufs */
1407 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1412 for (i = 0; i < 4; i++, txdp++, pkts++) {
1413 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1414 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1415 txdp->cmd_type_offset_bsz =
1416 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1417 (*pkts)->data_len, 0);
1421 /* Populate 1 descriptor with data from 1 mbuf */
1423 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1427 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1428 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1429 txdp->cmd_type_offset_bsz =
1430 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1431 (*pkts)->data_len, 0);
1434 /* Fill hardware descriptor ring with mbuf data */
1436 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1437 struct rte_mbuf **pkts,
1440 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1441 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1442 const int N_PER_LOOP = 4;
1443 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1444 int mainpart, leftover;
1447 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1448 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1449 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1450 for (j = 0; j < N_PER_LOOP; ++j) {
1451 (txep + i + j)->mbuf = *(pkts + i + j);
1453 tx4(txdp + i, pkts + i);
1455 if (unlikely(leftover > 0)) {
1456 for (i = 0; i < leftover; ++i) {
1457 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1458 tx1(txdp + mainpart + i, pkts + mainpart + i);
1463 static inline uint16_t
1464 tx_xmit_pkts(struct i40e_tx_queue *txq,
1465 struct rte_mbuf **tx_pkts,
1468 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1472 * Begin scanning the H/W ring for done descriptors when the number
1473 * of available descriptors drops below tx_free_thresh. For each done
1474 * descriptor, free the associated buffer.
1476 if (txq->nb_tx_free < txq->tx_free_thresh)
1477 i40e_tx_free_bufs(txq);
1479 /* Use available descriptor only */
1480 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1481 if (unlikely(!nb_pkts))
1484 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1485 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1486 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1487 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1488 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1489 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1490 I40E_TXD_QW1_CMD_SHIFT);
1491 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1495 /* Fill hardware descriptor ring with mbuf data */
1496 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1497 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1499 /* Determin if RS bit needs to be set */
1500 if (txq->tx_tail > txq->tx_next_rs) {
1501 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1502 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1503 I40E_TXD_QW1_CMD_SHIFT);
1505 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1506 if (txq->tx_next_rs >= txq->nb_tx_desc)
1507 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1510 if (txq->tx_tail >= txq->nb_tx_desc)
1513 /* Update the tx tail register */
1515 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1521 i40e_xmit_pkts_simple(void *tx_queue,
1522 struct rte_mbuf **tx_pkts,
1527 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1528 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1532 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1535 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1536 &tx_pkts[nb_tx], num);
1537 nb_tx = (uint16_t)(nb_tx + ret);
1538 nb_pkts = (uint16_t)(nb_pkts - ret);
1547 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1548 * application used, which assume having sequential ones. But from driver's
1549 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1550 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1551 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1552 * use queue_idx from 0 to 95 to access queues, while real queue would be
1553 * different. This function will do a queue mapping to find VSI the queue
1556 static struct i40e_vsi*
1557 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1559 /* the queue in MAIN VSI range */
1560 if (queue_idx < pf->main_vsi->nb_qps)
1561 return pf->main_vsi;
1563 queue_idx -= pf->main_vsi->nb_qps;
1565 /* queue_idx is greater than VMDQ VSIs range */
1566 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1567 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1571 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1575 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1577 /* the queue in MAIN VSI range */
1578 if (queue_idx < pf->main_vsi->nb_qps)
1581 /* It's VMDQ queues */
1582 queue_idx -= pf->main_vsi->nb_qps;
1584 if (pf->nb_cfg_vmdq_vsi)
1585 return queue_idx % pf->vmdq_nb_qps;
1587 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1588 return (uint16_t)(-1);
1593 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1595 struct i40e_rx_queue *rxq;
1597 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599 PMD_INIT_FUNC_TRACE();
1601 if (rx_queue_id < dev->data->nb_rx_queues) {
1602 rxq = dev->data->rx_queues[rx_queue_id];
1604 err = i40e_alloc_rx_queue_mbufs(rxq);
1606 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1612 /* Init the RX tail regieter. */
1613 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1615 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1618 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1621 i40e_rx_queue_release_mbufs(rxq);
1622 i40e_reset_rx_queue(rxq);
1630 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1632 struct i40e_rx_queue *rxq;
1634 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1636 if (rx_queue_id < dev->data->nb_rx_queues) {
1637 rxq = dev->data->rx_queues[rx_queue_id];
1640 * rx_queue_id is queue id aplication refers to, while
1641 * rxq->reg_idx is the real queue index.
1643 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1646 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1650 i40e_rx_queue_release_mbufs(rxq);
1651 i40e_reset_rx_queue(rxq);
1658 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1661 struct i40e_tx_queue *txq;
1662 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1664 PMD_INIT_FUNC_TRACE();
1666 if (tx_queue_id < dev->data->nb_tx_queues) {
1667 txq = dev->data->tx_queues[tx_queue_id];
1670 * tx_queue_id is queue id aplication refers to, while
1671 * rxq->reg_idx is the real queue index.
1673 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1675 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1683 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1685 struct i40e_tx_queue *txq;
1687 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1689 if (tx_queue_id < dev->data->nb_tx_queues) {
1690 txq = dev->data->tx_queues[tx_queue_id];
1693 * tx_queue_id is queue id aplication refers to, while
1694 * txq->reg_idx is the real queue index.
1696 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1699 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1704 i40e_tx_queue_release_mbufs(txq);
1705 i40e_reset_tx_queue(txq);
1712 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1715 unsigned int socket_id,
1716 const struct rte_eth_rxconf *rx_conf,
1717 struct rte_mempool *mp)
1719 struct i40e_vsi *vsi;
1720 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1721 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1722 struct i40e_rx_queue *rxq;
1723 const struct rte_memzone *rz;
1726 int use_def_burst_func = 1;
1728 if (hw->mac.type == I40E_MAC_VF) {
1729 struct i40e_vf *vf =
1730 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1733 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1736 PMD_DRV_LOG(ERR, "VSI not available or queue "
1737 "index exceeds the maximum");
1738 return I40E_ERR_PARAM;
1740 if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1741 (nb_desc > I40E_MAX_RING_DESC) ||
1742 (nb_desc < I40E_MIN_RING_DESC)) {
1743 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1744 "invalid", nb_desc);
1745 return I40E_ERR_PARAM;
1748 /* Free memory if needed */
1749 if (dev->data->rx_queues[queue_idx]) {
1750 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1751 dev->data->rx_queues[queue_idx] = NULL;
1754 /* Allocate the rx queue data structure */
1755 rxq = rte_zmalloc_socket("i40e rx queue",
1756 sizeof(struct i40e_rx_queue),
1757 RTE_CACHE_LINE_SIZE,
1760 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1761 "rx queue data structure");
1765 rxq->nb_rx_desc = nb_desc;
1766 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1767 rxq->queue_id = queue_idx;
1768 if (hw->mac.type == I40E_MAC_VF)
1769 rxq->reg_idx = queue_idx;
1770 else /* PF device */
1771 rxq->reg_idx = vsi->base_queue +
1772 i40e_get_queue_offset_by_qindex(pf, queue_idx);
1774 rxq->port_id = dev->data->port_id;
1775 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1777 rxq->drop_en = rx_conf->rx_drop_en;
1779 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1781 /* Allocate the maximun number of RX ring hardware descriptor. */
1782 ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1783 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1784 rz = i40e_ring_dma_zone_reserve(dev,
1790 i40e_dev_rx_queue_release(rxq);
1791 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1795 /* Zero all the descriptors in the ring. */
1796 memset(rz->addr, 0, ring_size);
1798 #ifdef RTE_LIBRTE_XEN_DOM0
1799 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1801 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1804 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1806 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1807 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1812 /* Allocate the software ring. */
1814 rte_zmalloc_socket("i40e rx sw ring",
1815 sizeof(struct i40e_rx_entry) * len,
1816 RTE_CACHE_LINE_SIZE,
1818 if (!rxq->sw_ring) {
1819 i40e_dev_rx_queue_release(rxq);
1820 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1824 i40e_reset_rx_queue(rxq);
1826 dev->data->rx_queues[queue_idx] = rxq;
1828 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1830 if (!use_def_burst_func && !dev->data->scattered_rx) {
1831 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1832 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1833 "satisfied. Rx Burst Bulk Alloc function will be "
1834 "used on port=%d, queue=%d.",
1835 rxq->port_id, rxq->queue_id);
1836 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1837 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1839 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1840 "not satisfied, Scattered Rx is requested, "
1841 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1842 "not enabled on port=%d, queue=%d.",
1843 rxq->port_id, rxq->queue_id);
1850 i40e_dev_rx_queue_release(void *rxq)
1852 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1855 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1859 i40e_rx_queue_release_mbufs(q);
1860 rte_free(q->sw_ring);
1865 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1867 #define I40E_RXQ_SCAN_INTERVAL 4
1868 volatile union i40e_rx_desc *rxdp;
1869 struct i40e_rx_queue *rxq;
1872 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1873 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1877 rxq = dev->data->rx_queues[rx_queue_id];
1878 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1879 while ((desc < rxq->nb_rx_desc) &&
1880 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1881 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1882 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1884 * Check the DD bit of a rx descriptor of each 4 in a group,
1885 * to avoid checking too frequently and downgrading performance
1888 desc += I40E_RXQ_SCAN_INTERVAL;
1889 rxdp += I40E_RXQ_SCAN_INTERVAL;
1890 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1891 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1892 desc - rxq->nb_rx_desc]);
1899 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1901 volatile union i40e_rx_desc *rxdp;
1902 struct i40e_rx_queue *rxq = rx_queue;
1906 if (unlikely(offset >= rxq->nb_rx_desc)) {
1907 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1911 desc = rxq->rx_tail + offset;
1912 if (desc >= rxq->nb_rx_desc)
1913 desc -= rxq->nb_rx_desc;
1915 rxdp = &(rxq->rx_ring[desc]);
1917 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1918 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1919 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1925 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1928 unsigned int socket_id,
1929 const struct rte_eth_txconf *tx_conf)
1931 struct i40e_vsi *vsi;
1932 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1933 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1934 struct i40e_tx_queue *txq;
1935 const struct rte_memzone *tz;
1937 uint16_t tx_rs_thresh, tx_free_thresh;
1939 if (hw->mac.type == I40E_MAC_VF) {
1940 struct i40e_vf *vf =
1941 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1944 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1947 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1948 "exceeds the maximum", queue_idx);
1949 return I40E_ERR_PARAM;
1952 if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
1953 (nb_desc > I40E_MAX_RING_DESC) ||
1954 (nb_desc < I40E_MIN_RING_DESC)) {
1955 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1956 "invalid", nb_desc);
1957 return I40E_ERR_PARAM;
1961 * The following two parameters control the setting of the RS bit on
1962 * transmit descriptors. TX descriptors will have their RS bit set
1963 * after txq->tx_rs_thresh descriptors have been used. The TX
1964 * descriptor ring will be cleaned after txq->tx_free_thresh
1965 * descriptors are used or if the number of descriptors required to
1966 * transmit a packet is greater than the number of free TX descriptors.
1968 * The following constraints must be satisfied:
1969 * - tx_rs_thresh must be greater than 0.
1970 * - tx_rs_thresh must be less than the size of the ring minus 2.
1971 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1972 * - tx_rs_thresh must be a divisor of the ring size.
1973 * - tx_free_thresh must be greater than 0.
1974 * - tx_free_thresh must be less than the size of the ring minus 3.
1976 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1977 * race condition, hence the maximum threshold constraints. When set
1978 * to zero use default values.
1980 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1981 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1982 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1983 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1984 if (tx_rs_thresh >= (nb_desc - 2)) {
1985 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1986 "number of TX descriptors minus 2. "
1987 "(tx_rs_thresh=%u port=%d queue=%d)",
1988 (unsigned int)tx_rs_thresh,
1989 (int)dev->data->port_id,
1991 return I40E_ERR_PARAM;
1993 if (tx_free_thresh >= (nb_desc - 3)) {
1994 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1995 "tx_free_thresh must be less than the "
1996 "number of TX descriptors minus 3. "
1997 "(tx_free_thresh=%u port=%d queue=%d)",
1998 (unsigned int)tx_free_thresh,
1999 (int)dev->data->port_id,
2001 return I40E_ERR_PARAM;
2003 if (tx_rs_thresh > tx_free_thresh) {
2004 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2005 "equal to tx_free_thresh. (tx_free_thresh=%u"
2006 " tx_rs_thresh=%u port=%d queue=%d)",
2007 (unsigned int)tx_free_thresh,
2008 (unsigned int)tx_rs_thresh,
2009 (int)dev->data->port_id,
2011 return I40E_ERR_PARAM;
2013 if ((nb_desc % tx_rs_thresh) != 0) {
2014 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2015 "number of TX descriptors. (tx_rs_thresh=%u"
2016 " port=%d queue=%d)",
2017 (unsigned int)tx_rs_thresh,
2018 (int)dev->data->port_id,
2020 return I40E_ERR_PARAM;
2022 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2023 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2024 "tx_rs_thresh is greater than 1. "
2025 "(tx_rs_thresh=%u port=%d queue=%d)",
2026 (unsigned int)tx_rs_thresh,
2027 (int)dev->data->port_id,
2029 return I40E_ERR_PARAM;
2032 /* Free memory if needed. */
2033 if (dev->data->tx_queues[queue_idx]) {
2034 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2035 dev->data->tx_queues[queue_idx] = NULL;
2038 /* Allocate the TX queue data structure. */
2039 txq = rte_zmalloc_socket("i40e tx queue",
2040 sizeof(struct i40e_tx_queue),
2041 RTE_CACHE_LINE_SIZE,
2044 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2045 "tx queue structure");
2049 /* Allocate TX hardware ring descriptors. */
2050 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2051 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2052 tz = i40e_ring_dma_zone_reserve(dev,
2058 i40e_dev_tx_queue_release(txq);
2059 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2063 txq->nb_tx_desc = nb_desc;
2064 txq->tx_rs_thresh = tx_rs_thresh;
2065 txq->tx_free_thresh = tx_free_thresh;
2066 txq->pthresh = tx_conf->tx_thresh.pthresh;
2067 txq->hthresh = tx_conf->tx_thresh.hthresh;
2068 txq->wthresh = tx_conf->tx_thresh.wthresh;
2069 txq->queue_id = queue_idx;
2070 if (hw->mac.type == I40E_MAC_VF)
2071 txq->reg_idx = queue_idx;
2072 else /* PF device */
2073 txq->reg_idx = vsi->base_queue +
2074 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2076 txq->port_id = dev->data->port_id;
2077 txq->txq_flags = tx_conf->txq_flags;
2079 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2081 #ifdef RTE_LIBRTE_XEN_DOM0
2082 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2084 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2086 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2088 /* Allocate software ring */
2090 rte_zmalloc_socket("i40e tx sw ring",
2091 sizeof(struct i40e_tx_entry) * nb_desc,
2092 RTE_CACHE_LINE_SIZE,
2094 if (!txq->sw_ring) {
2095 i40e_dev_tx_queue_release(txq);
2096 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2100 i40e_reset_tx_queue(txq);
2102 dev->data->tx_queues[queue_idx] = txq;
2104 /* Use a simple TX queue without offloads or multi segs if possible */
2105 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
2106 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
2107 PMD_INIT_LOG(INFO, "Using simple tx path");
2108 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2110 PMD_INIT_LOG(INFO, "Using full-featured tx path");
2111 dev->tx_pkt_burst = i40e_xmit_pkts;
2118 i40e_dev_tx_queue_release(void *txq)
2120 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2123 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2127 i40e_tx_queue_release_mbufs(q);
2128 rte_free(q->sw_ring);
2132 static const struct rte_memzone *
2133 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
2134 const char *ring_name,
2139 char z_name[RTE_MEMZONE_NAMESIZE];
2140 const struct rte_memzone *mz;
2142 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2143 dev->driver->pci_drv.name, ring_name,
2144 dev->data->port_id, queue_id);
2145 mz = rte_memzone_lookup(z_name);
2149 #ifdef RTE_LIBRTE_XEN_DOM0
2150 return rte_memzone_reserve_bounded(z_name, ring_size,
2151 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2153 return rte_memzone_reserve_aligned(z_name, ring_size,
2154 socket_id, 0, I40E_ALIGN);
2158 const struct rte_memzone *
2159 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2161 const struct rte_memzone *mz = NULL;
2163 mz = rte_memzone_lookup(name);
2166 #ifdef RTE_LIBRTE_XEN_DOM0
2167 mz = rte_memzone_reserve_bounded(name, len,
2168 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2170 mz = rte_memzone_reserve_aligned(name, len,
2171 socket_id, 0, I40E_ALIGN);
2177 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2181 if (!rxq || !rxq->sw_ring) {
2182 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2186 for (i = 0; i < rxq->nb_rx_desc; i++) {
2187 if (rxq->sw_ring[i].mbuf) {
2188 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2189 rxq->sw_ring[i].mbuf = NULL;
2192 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2193 if (rxq->rx_nb_avail == 0)
2195 for (i = 0; i < rxq->rx_nb_avail; i++) {
2196 struct rte_mbuf *mbuf;
2198 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2199 rte_pktmbuf_free_seg(mbuf);
2201 rxq->rx_nb_avail = 0;
2202 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2206 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2211 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2212 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2213 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2215 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2216 len = rxq->nb_rx_desc;
2218 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2219 ((volatile char *)rxq->rx_ring)[i] = 0;
2221 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2222 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2223 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2224 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2226 rxq->rx_nb_avail = 0;
2227 rxq->rx_next_avail = 0;
2228 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2229 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2231 rxq->nb_rx_hold = 0;
2232 rxq->pkt_first_seg = NULL;
2233 rxq->pkt_last_seg = NULL;
2237 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2241 if (!txq || !txq->sw_ring) {
2242 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2246 for (i = 0; i < txq->nb_tx_desc; i++) {
2247 if (txq->sw_ring[i].mbuf) {
2248 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2249 txq->sw_ring[i].mbuf = NULL;
2255 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2257 struct i40e_tx_entry *txe;
2258 uint16_t i, prev, size;
2261 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2266 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2267 for (i = 0; i < size; i++)
2268 ((volatile char *)txq->tx_ring)[i] = 0;
2270 prev = (uint16_t)(txq->nb_tx_desc - 1);
2271 for (i = 0; i < txq->nb_tx_desc; i++) {
2272 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2274 txd->cmd_type_offset_bsz =
2275 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2278 txe[prev].next_id = i;
2282 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2283 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2286 txq->nb_tx_used = 0;
2288 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2289 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2292 /* Init the TX queue in hardware */
2294 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2296 enum i40e_status_code err = I40E_SUCCESS;
2297 struct i40e_vsi *vsi = txq->vsi;
2298 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2299 uint16_t pf_q = txq->reg_idx;
2300 struct i40e_hmc_obj_txq tx_ctx;
2303 /* clear the context structure first */
2304 memset(&tx_ctx, 0, sizeof(tx_ctx));
2305 tx_ctx.new_context = 1;
2306 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2307 tx_ctx.qlen = txq->nb_tx_desc;
2308 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2309 if (vsi->type == I40E_VSI_FDIR)
2310 tx_ctx.fd_ena = TRUE;
2312 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2313 if (err != I40E_SUCCESS) {
2314 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2318 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2319 if (err != I40E_SUCCESS) {
2320 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2324 /* Now associate this queue with this PCI function */
2325 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2326 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2327 I40E_QTX_CTL_PF_INDX_MASK);
2328 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2329 I40E_WRITE_FLUSH(hw);
2331 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2337 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2339 struct i40e_rx_entry *rxe = rxq->sw_ring;
2343 for (i = 0; i < rxq->nb_rx_desc; i++) {
2344 volatile union i40e_rx_desc *rxd;
2345 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2347 if (unlikely(!mbuf)) {
2348 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2352 rte_mbuf_refcnt_set(mbuf, 1);
2354 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2356 mbuf->port = rxq->port_id;
2359 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2361 rxd = &rxq->rx_ring[i];
2362 rxd->read.pkt_addr = dma_addr;
2363 rxd->read.hdr_addr = dma_addr;
2364 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2365 rxd->read.rsvd1 = 0;
2366 rxd->read.rsvd2 = 0;
2367 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2376 * Calculate the buffer length, and check the jumbo frame
2377 * and maximum packet length.
2380 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2382 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2383 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2384 struct rte_eth_dev_data *data = pf->dev_data;
2385 struct rte_pktmbuf_pool_private *mbp_priv =
2386 rte_mempool_get_priv(rxq->mp);
2387 uint16_t buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2388 RTE_PKTMBUF_HEADROOM);
2391 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2392 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2393 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2394 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2395 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2396 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2397 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2398 rxq->hs_mode = i40e_header_split_enabled;
2400 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2402 rxq->rx_hdr_len = 0;
2403 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2404 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2405 rxq->hs_mode = i40e_header_split_none;
2409 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2410 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2411 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2412 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2413 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2414 PMD_DRV_LOG(ERR, "maximum packet length must "
2415 "be larger than %u and smaller than %u,"
2416 "as jumbo frame is enabled",
2417 (uint32_t)ETHER_MAX_LEN,
2418 (uint32_t)I40E_FRAME_SIZE_MAX);
2419 return I40E_ERR_CONFIG;
2422 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2423 rxq->max_pkt_len > ETHER_MAX_LEN) {
2424 PMD_DRV_LOG(ERR, "maximum packet length must be "
2425 "larger than %u and smaller than %u, "
2426 "as jumbo frame is disabled",
2427 (uint32_t)ETHER_MIN_LEN,
2428 (uint32_t)ETHER_MAX_LEN);
2429 return I40E_ERR_CONFIG;
2436 /* Init the RX queue in hardware */
2438 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2440 int err = I40E_SUCCESS;
2441 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2442 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2443 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2444 uint16_t pf_q = rxq->reg_idx;
2446 struct i40e_hmc_obj_rxq rx_ctx;
2447 struct rte_pktmbuf_pool_private *mbp_priv;
2449 err = i40e_rx_queue_config(rxq);
2451 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2455 /* Clear the context structure first */
2456 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2457 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2458 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2460 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2461 rx_ctx.qlen = rxq->nb_rx_desc;
2462 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2465 rx_ctx.dtype = rxq->hs_mode;
2467 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2469 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2470 rx_ctx.rxmax = rxq->max_pkt_len;
2471 rx_ctx.tphrdesc_ena = 1;
2472 rx_ctx.tphwdesc_ena = 1;
2473 rx_ctx.tphdata_ena = 1;
2474 rx_ctx.tphhead_ena = 1;
2475 rx_ctx.lrxqthresh = 2;
2476 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2481 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2482 if (err != I40E_SUCCESS) {
2483 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2486 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2487 if (err != I40E_SUCCESS) {
2488 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2492 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2494 mbp_priv = rte_mempool_get_priv(rxq->mp);
2495 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2496 RTE_PKTMBUF_HEADROOM);
2498 /* Check if scattered RX needs to be used. */
2499 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2500 dev_data->scattered_rx = 1;
2501 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2504 /* Init the RX tail regieter. */
2505 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2511 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2515 PMD_INIT_FUNC_TRACE();
2517 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2518 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2519 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2522 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2523 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2524 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2528 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2529 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2531 enum i40e_status_code
2532 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2534 struct i40e_tx_queue *txq;
2535 const struct rte_memzone *tz = NULL;
2537 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2540 PMD_DRV_LOG(ERR, "PF is not available");
2541 return I40E_ERR_BAD_PTR;
2544 /* Allocate the TX queue data structure. */
2545 txq = rte_zmalloc_socket("i40e fdir tx queue",
2546 sizeof(struct i40e_tx_queue),
2547 RTE_CACHE_LINE_SIZE,
2550 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2551 "tx queue structure.");
2552 return I40E_ERR_NO_MEMORY;
2555 /* Allocate TX hardware ring descriptors. */
2556 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2557 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2559 tz = i40e_ring_dma_zone_reserve(dev,
2565 i40e_dev_tx_queue_release(txq);
2566 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2567 return I40E_ERR_NO_MEMORY;
2570 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2571 txq->queue_id = I40E_FDIR_QUEUE_ID;
2572 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2573 txq->vsi = pf->fdir.fdir_vsi;
2575 #ifdef RTE_LIBRTE_XEN_DOM0
2576 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2578 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2580 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2582 * don't need to allocate software ring and reset for the fdir
2583 * program queue just set the queue has been configured.
2588 return I40E_SUCCESS;
2591 enum i40e_status_code
2592 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2594 struct i40e_rx_queue *rxq;
2595 const struct rte_memzone *rz = NULL;
2597 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2600 PMD_DRV_LOG(ERR, "PF is not available");
2601 return I40E_ERR_BAD_PTR;
2604 /* Allocate the RX queue data structure. */
2605 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2606 sizeof(struct i40e_rx_queue),
2607 RTE_CACHE_LINE_SIZE,
2610 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2611 "rx queue structure.");
2612 return I40E_ERR_NO_MEMORY;
2615 /* Allocate RX hardware ring descriptors. */
2616 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2617 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2619 rz = i40e_ring_dma_zone_reserve(dev,
2625 i40e_dev_rx_queue_release(rxq);
2626 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2627 return I40E_ERR_NO_MEMORY;
2630 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2631 rxq->queue_id = I40E_FDIR_QUEUE_ID;
2632 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2633 rxq->vsi = pf->fdir.fdir_vsi;
2635 #ifdef RTE_LIBRTE_XEN_DOM0
2636 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2638 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
2640 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2643 * Don't need to allocate software ring and reset for the fdir
2644 * rx queue, just set the queue has been configured.
2649 return I40E_SUCCESS;