4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
54 #include "i40e_logs.h"
55 #include "i40e/i40e_prototype.h"
56 #include "i40e/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
60 #define I40E_MIN_RING_DESC 64
61 #define I40E_MAX_RING_DESC 4096
62 #define I40E_ALIGN 128
63 #define DEFAULT_TX_RS_THRESH 32
64 #define DEFAULT_TX_FREE_THRESH 32
65 #define I40E_MAX_PKT_TYPE 256
67 #define I40E_VLAN_TAG_SIZE 4
68 #define I40E_TX_MAX_BURST 32
70 #define I40E_DMA_MEM_ALIGN 4096
72 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
73 ETH_TXQ_FLAGS_NOOFFLOADS)
75 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
77 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
78 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
80 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
81 ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
83 static const struct rte_memzone *
84 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
85 const char *ring_name,
89 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
90 struct rte_mbuf **tx_pkts,
93 /* Translate the rx descriptor status to pkt flags */
94 static inline uint64_t
95 i40e_rxd_status_to_pkt_flags(uint64_t qword)
99 /* Check if VLAN packet */
100 flags = qword & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
103 /* Check if RSS_HASH */
104 flags |= (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
105 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
106 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
111 static inline uint64_t
112 i40e_rxd_error_to_pkt_flags(uint64_t qword)
115 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
117 #define I40E_RX_ERR_BITS 0x3f
118 if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
120 /* If RXE bit set, all other status bits are meaningless */
121 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
122 flags |= PKT_RX_MAC_ERR;
126 /* If RECIPE bit set, all other status indications should be ignored */
127 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
128 flags |= PKT_RX_RECIP_ERR;
131 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
132 flags |= PKT_RX_HBUF_OVERFLOW;
133 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
134 flags |= PKT_RX_IP_CKSUM_BAD;
135 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
136 flags |= PKT_RX_L4_CKSUM_BAD;
137 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
138 flags |= PKT_RX_EIP_CKSUM_BAD;
139 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
140 flags |= PKT_RX_OVERSIZE;
145 /* Translate pkt types to pkt flags */
146 static inline uint64_t
147 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
149 uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
150 I40E_RXD_QW1_PTYPE_SHIFT);
151 static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
174 PKT_RX_IPV4_HDR, /* PTYPE 22 */
175 PKT_RX_IPV4_HDR, /* PTYPE 23 */
176 PKT_RX_IPV4_HDR, /* PTYPE 24 */
178 PKT_RX_IPV4_HDR, /* PTYPE 26 */
179 PKT_RX_IPV4_HDR, /* PTYPE 27 */
180 PKT_RX_IPV4_HDR, /* PTYPE 28 */
181 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
182 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
183 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
185 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
186 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
187 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
188 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
189 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
190 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
192 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
193 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
194 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
195 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
196 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
197 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
198 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
200 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
201 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
202 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
203 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
204 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
205 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
207 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
208 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
209 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
210 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
211 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 59 */
212 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 60 */
213 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 61 */
215 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 63 */
216 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 64 */
217 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 65 */
218 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 66 */
219 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 67 */
220 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 68 */
222 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 70 */
223 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 71 */
224 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 72 */
225 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 73 */
226 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 74 */
227 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 75 */
228 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 76 */
230 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 78 */
231 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 79 */
232 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 80 */
233 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 81 */
234 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 82 */
235 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 83 */
237 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 85 */
238 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 86 */
239 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
240 PKT_RX_IPV6_HDR, /* PTYPE 88 */
241 PKT_RX_IPV6_HDR, /* PTYPE 89 */
242 PKT_RX_IPV6_HDR, /* PTYPE 90 */
244 PKT_RX_IPV6_HDR, /* PTYPE 92 */
245 PKT_RX_IPV6_HDR, /* PTYPE 93 */
246 PKT_RX_IPV6_HDR, /* PTYPE 94 */
247 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
248 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
249 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
251 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
252 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
253 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
254 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
255 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
256 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
258 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
259 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
260 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
261 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
262 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
263 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
264 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
266 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
267 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
268 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
269 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
270 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
271 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
273 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
274 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
275 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
276 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
277 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 125 */
278 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 126 */
279 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 127 */
281 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 129 */
282 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 130 */
283 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 131 */
284 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 132 */
285 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 133 */
286 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 134 */
288 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 136 */
289 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 137 */
290 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 138 */
291 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 139 */
292 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 140 */
293 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 141 */
294 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 142 */
296 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 144 */
297 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 145 */
298 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 146 */
299 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 147 */
300 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 148 */
301 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 149 */
303 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 151 */
304 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 152 */
305 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
410 return ip_ptype_map[ptype];
414 i40e_txd_enable_checksum(uint64_t ol_flags,
419 uint8_t inner_l2_len,
420 uint16_t inner_l3_len,
421 uint32_t *cd_tunneling)
424 PMD_DRV_LOG(DEBUG, "L2 length set to 0");
427 *td_offset |= (l2_len >> 1) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
430 PMD_DRV_LOG(DEBUG, "L3 length set to 0");
434 /* VXLAN packet TX checksum offload */
435 if (unlikely(ol_flags & PKT_TX_VXLAN_CKSUM)) {
438 l4tun_len = ETHER_VXLAN_HLEN + inner_l2_len;
440 if (ol_flags & PKT_TX_IPV4_CSUM)
441 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
442 else if (ol_flags & PKT_TX_IPV6)
443 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
445 /* Now set the ctx descriptor fields */
446 *cd_tunneling |= (l3_len >> 2) <<
447 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
448 I40E_TXD_CTX_UDP_TUNNELING |
450 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
452 l3_len = inner_l3_len;
455 /* Enable L3 checksum offloads */
456 if (ol_flags & PKT_TX_IPV4_CSUM) {
457 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
458 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
459 } else if (ol_flags & PKT_TX_IPV4) {
460 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
461 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
462 } else if (ol_flags & PKT_TX_IPV6) {
463 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
464 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
467 /* Enable L4 checksum offloads */
468 switch (ol_flags & PKT_TX_L4_MASK) {
469 case PKT_TX_TCP_CKSUM:
470 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
471 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
472 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
474 case PKT_TX_SCTP_CKSUM:
475 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
476 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
477 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
479 case PKT_TX_UDP_CKSUM:
480 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
481 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
482 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
489 static inline struct rte_mbuf *
490 rte_rxmbuf_alloc(struct rte_mempool *mp)
494 m = __rte_mbuf_raw_alloc(mp);
495 __rte_mbuf_sanity_check_raw(m, 0);
500 /* Construct the tx flags */
501 static inline uint64_t
502 i40e_build_ctob(uint32_t td_cmd,
507 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
508 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
509 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
510 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
511 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
515 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
517 struct i40e_tx_entry *sw_ring = txq->sw_ring;
518 volatile struct i40e_tx_desc *txd = txq->tx_ring;
519 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
520 uint16_t nb_tx_desc = txq->nb_tx_desc;
521 uint16_t desc_to_clean_to;
522 uint16_t nb_tx_to_clean;
524 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
525 if (desc_to_clean_to >= nb_tx_desc)
526 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
528 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
529 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
530 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) {
531 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
532 "(port=%d queue=%d)", desc_to_clean_to,
533 txq->port_id, txq->queue_id);
537 if (last_desc_cleaned > desc_to_clean_to)
538 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
541 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
544 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
546 txq->last_desc_cleaned = desc_to_clean_to;
547 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
553 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
554 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
556 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
561 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
562 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
563 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
564 "rxq->rx_free_thresh=%d, "
565 "RTE_PMD_I40E_RX_MAX_BURST=%d",
566 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
568 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
569 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
570 "rxq->rx_free_thresh=%d, "
571 "rxq->nb_rx_desc=%d",
572 rxq->rx_free_thresh, rxq->nb_rx_desc);
574 } else if (!(rxq->nb_rx_desc % rxq->rx_free_thresh) == 0) {
575 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
576 "rxq->nb_rx_desc=%d, "
577 "rxq->rx_free_thresh=%d",
578 rxq->nb_rx_desc, rxq->rx_free_thresh);
580 } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
581 RTE_PMD_I40E_RX_MAX_BURST))) {
582 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
583 "rxq->nb_rx_desc=%d, "
584 "I40E_MAX_RING_DESC=%d, "
585 "RTE_PMD_I40E_RX_MAX_BURST=%d",
586 rxq->nb_rx_desc, I40E_MAX_RING_DESC,
587 RTE_PMD_I40E_RX_MAX_BURST);
597 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
598 #define I40E_LOOK_AHEAD 8
599 #if (I40E_LOOK_AHEAD != 8)
600 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
603 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
605 volatile union i40e_rx_desc *rxdp;
606 struct i40e_rx_entry *rxep;
611 int32_t s[I40E_LOOK_AHEAD], nb_dd;
612 int32_t i, j, nb_rx = 0;
615 rxdp = &rxq->rx_ring[rxq->rx_tail];
616 rxep = &rxq->sw_ring[rxq->rx_tail];
618 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
619 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
620 I40E_RXD_QW1_STATUS_SHIFT;
622 /* Make sure there is at least 1 packet to receive */
623 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
627 * Scan LOOK_AHEAD descriptors at a time to determine which
628 * descriptors reference packets that are ready to be received.
630 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
631 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
632 /* Read desc statuses backwards to avoid race condition */
633 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
634 qword1 = rte_le_to_cpu_64(\
635 rxdp[j].wb.qword1.status_error_len);
636 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
637 I40E_RXD_QW1_STATUS_SHIFT;
640 /* Compute how many status bits were set */
641 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
642 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
646 /* Translate descriptor info to mbuf parameters */
647 for (j = 0; j < nb_dd; j++) {
649 qword1 = rte_le_to_cpu_64(\
650 rxdp[j].wb.qword1.status_error_len);
651 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
652 I40E_RXD_QW1_STATUS_SHIFT;
653 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
654 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
655 mb->data_len = pkt_len;
656 mb->pkt_len = pkt_len;
657 mb->vlan_tci = rx_status &
658 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
660 rxdp[j].wb.qword0.lo_dword.l2tag1) : 0;
661 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
662 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
663 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
664 mb->ol_flags = pkt_flags;
666 mb->packet_type = (uint16_t)((qword1 &
667 I40E_RXD_QW1_PTYPE_MASK) >>
668 I40E_RXD_QW1_PTYPE_SHIFT);
669 if (pkt_flags & PKT_RX_RSS_HASH)
670 mb->hash.rss = rte_le_to_cpu_32(\
671 rxdp->wb.qword0.hi_dword.rss);
674 for (j = 0; j < I40E_LOOK_AHEAD; j++)
675 rxq->rx_stage[i + j] = rxep[j].mbuf;
677 if (nb_dd != I40E_LOOK_AHEAD)
681 /* Clear software ring entries */
682 for (i = 0; i < nb_rx; i++)
683 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
688 static inline uint16_t
689 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
690 struct rte_mbuf **rx_pkts,
694 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
696 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
698 for (i = 0; i < nb_pkts; i++)
699 rx_pkts[i] = stage[i];
701 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
702 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
708 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
710 volatile union i40e_rx_desc *rxdp;
711 struct i40e_rx_entry *rxep;
713 uint16_t alloc_idx, i;
717 /* Allocate buffers in bulk */
718 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
719 (rxq->rx_free_thresh - 1));
720 rxep = &(rxq->sw_ring[alloc_idx]);
721 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
722 rxq->rx_free_thresh);
723 if (unlikely(diag != 0)) {
724 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
728 rxdp = &rxq->rx_ring[alloc_idx];
729 for (i = 0; i < rxq->rx_free_thresh; i++) {
731 rte_mbuf_refcnt_set(mb, 1);
733 mb->data_off = RTE_PKTMBUF_HEADROOM;
735 mb->port = rxq->port_id;
736 dma_addr = rte_cpu_to_le_64(\
737 RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
738 rxdp[i].read.hdr_addr = dma_addr;
739 rxdp[i].read.pkt_addr = dma_addr;
742 /* Update rx tail regsiter */
744 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
746 rxq->rx_free_trigger =
747 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
748 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
749 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
754 static inline uint16_t
755 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
757 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
763 if (rxq->rx_nb_avail)
764 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
766 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
767 rxq->rx_next_avail = 0;
768 rxq->rx_nb_avail = nb_rx;
769 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
771 if (rxq->rx_tail > rxq->rx_free_trigger) {
772 if (i40e_rx_alloc_bufs(rxq) != 0) {
775 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
776 "port_id=%u, queue_id=%u",
777 rxq->port_id, rxq->queue_id);
778 rxq->rx_nb_avail = 0;
779 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
780 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
781 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
787 if (rxq->rx_tail >= rxq->nb_rx_desc)
790 if (rxq->rx_nb_avail)
791 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
797 i40e_recv_pkts_bulk_alloc(void *rx_queue,
798 struct rte_mbuf **rx_pkts,
801 uint16_t nb_rx = 0, n, count;
803 if (unlikely(nb_pkts == 0))
806 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
807 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
810 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
811 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
812 nb_rx = (uint16_t)(nb_rx + count);
813 nb_pkts = (uint16_t)(nb_pkts - count);
820 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
823 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
825 struct i40e_rx_queue *rxq;
826 volatile union i40e_rx_desc *rx_ring;
827 volatile union i40e_rx_desc *rxdp;
828 union i40e_rx_desc rxd;
829 struct i40e_rx_entry *sw_ring;
830 struct i40e_rx_entry *rxe;
831 struct rte_mbuf *rxm;
832 struct rte_mbuf *nmb;
836 uint16_t rx_packet_len;
837 uint16_t rx_id, nb_hold;
844 rx_id = rxq->rx_tail;
845 rx_ring = rxq->rx_ring;
846 sw_ring = rxq->sw_ring;
848 while (nb_rx < nb_pkts) {
849 rxdp = &rx_ring[rx_id];
850 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
851 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
852 >> I40E_RXD_QW1_STATUS_SHIFT;
853 /* Check the DD bit first */
854 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
857 nmb = rte_rxmbuf_alloc(rxq->mp);
863 rxe = &sw_ring[rx_id];
865 if (unlikely(rx_id == rxq->nb_rx_desc))
868 /* Prefetch next mbuf */
869 rte_prefetch0(sw_ring[rx_id].mbuf);
872 * When next RX descriptor is on a cache line boundary,
873 * prefetch the next 4 RX descriptors and next 8 pointers
876 if ((rx_id & 0x3) == 0) {
877 rte_prefetch0(&rx_ring[rx_id]);
878 rte_prefetch0(&sw_ring[rx_id]);
883 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
884 rxdp->read.hdr_addr = dma_addr;
885 rxdp->read.pkt_addr = dma_addr;
887 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
888 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
890 rxm->data_off = RTE_PKTMBUF_HEADROOM;
891 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
894 rxm->pkt_len = rx_packet_len;
895 rxm->data_len = rx_packet_len;
896 rxm->port = rxq->port_id;
898 rxm->vlan_tci = rx_status &
899 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
900 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
901 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
902 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
903 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
904 rxm->packet_type = (uint16_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >>
905 I40E_RXD_QW1_PTYPE_SHIFT);
906 rxm->ol_flags = pkt_flags;
907 if (pkt_flags & PKT_RX_RSS_HASH)
909 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
911 rx_pkts[nb_rx++] = rxm;
913 rxq->rx_tail = rx_id;
916 * If the number of free RX descriptors is greater than the RX free
917 * threshold of the queue, advance the receive tail register of queue.
918 * Update that register with the value of the last processed RX
919 * descriptor minus 1.
921 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
922 if (nb_hold > rxq->rx_free_thresh) {
923 rx_id = (uint16_t) ((rx_id == 0) ?
924 (rxq->nb_rx_desc - 1) : (rx_id - 1));
925 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
928 rxq->nb_rx_hold = nb_hold;
934 i40e_recv_scattered_pkts(void *rx_queue,
935 struct rte_mbuf **rx_pkts,
938 struct i40e_rx_queue *rxq = rx_queue;
939 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
940 volatile union i40e_rx_desc *rxdp;
941 union i40e_rx_desc rxd;
942 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
943 struct i40e_rx_entry *rxe;
944 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
945 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
946 struct rte_mbuf *nmb, *rxm;
947 uint16_t rx_id = rxq->rx_tail;
948 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
954 while (nb_rx < nb_pkts) {
955 rxdp = &rx_ring[rx_id];
956 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
957 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
958 I40E_RXD_QW1_STATUS_SHIFT;
959 /* Check the DD bit */
960 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
963 nmb = rte_rxmbuf_alloc(rxq->mp);
968 rxe = &sw_ring[rx_id];
970 if (rx_id == rxq->nb_rx_desc)
973 /* Prefetch next mbuf */
974 rte_prefetch0(sw_ring[rx_id].mbuf);
977 * When next RX descriptor is on a cache line boundary,
978 * prefetch the next 4 RX descriptors and next 8 pointers
981 if ((rx_id & 0x3) == 0) {
982 rte_prefetch0(&rx_ring[rx_id]);
983 rte_prefetch0(&sw_ring[rx_id]);
989 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
991 /* Set data buffer address and data length of the mbuf */
992 rxdp->read.hdr_addr = dma_addr;
993 rxdp->read.pkt_addr = dma_addr;
994 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
995 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
996 rxm->data_len = rx_packet_len;
997 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1000 * If this is the first buffer of the received packet, set the
1001 * pointer to the first mbuf of the packet and initialize its
1002 * context. Otherwise, update the total length and the number
1003 * of segments of the current scattered packet, and update the
1004 * pointer to the last mbuf of the current packet.
1008 first_seg->nb_segs = 1;
1009 first_seg->pkt_len = rx_packet_len;
1011 first_seg->pkt_len =
1012 (uint16_t)(first_seg->pkt_len +
1014 first_seg->nb_segs++;
1015 last_seg->next = rxm;
1019 * If this is not the last buffer of the received packet,
1020 * update the pointer to the last mbuf of the current scattered
1021 * packet and continue to parse the RX ring.
1023 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1029 * This is the last buffer of the received packet. If the CRC
1030 * is not stripped by the hardware:
1031 * - Subtract the CRC length from the total packet length.
1032 * - If the last buffer only contains the whole CRC or a part
1033 * of it, free the mbuf associated to the last buffer. If part
1034 * of the CRC is also contained in the previous mbuf, subtract
1035 * the length of that CRC part from the data length of the
1039 if (unlikely(rxq->crc_len > 0)) {
1040 first_seg->pkt_len -= ETHER_CRC_LEN;
1041 if (rx_packet_len <= ETHER_CRC_LEN) {
1042 rte_pktmbuf_free_seg(rxm);
1043 first_seg->nb_segs--;
1044 last_seg->data_len =
1045 (uint16_t)(last_seg->data_len -
1046 (ETHER_CRC_LEN - rx_packet_len));
1047 last_seg->next = NULL;
1049 rxm->data_len = (uint16_t)(rx_packet_len -
1053 first_seg->port = rxq->port_id;
1054 first_seg->vlan_tci = (rx_status &
1055 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1056 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
1057 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1058 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1059 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1060 first_seg->packet_type = (uint16_t)((qword1 &
1061 I40E_RXD_QW1_PTYPE_MASK) >>
1062 I40E_RXD_QW1_PTYPE_SHIFT);
1063 first_seg->ol_flags = pkt_flags;
1064 if (pkt_flags & PKT_RX_RSS_HASH)
1066 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1068 /* Prefetch data of first segment, if configured to do so. */
1069 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1070 first_seg->data_off));
1071 rx_pkts[nb_rx++] = first_seg;
1075 /* Record index of the next RX descriptor to probe. */
1076 rxq->rx_tail = rx_id;
1077 rxq->pkt_first_seg = first_seg;
1078 rxq->pkt_last_seg = last_seg;
1081 * If the number of free RX descriptors is greater than the RX free
1082 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1083 * register. Update the RDT with the value of the last processed RX
1084 * descriptor minus 1, to guarantee that the RDT register is never
1085 * equal to the RDH register, which creates a "full" ring situtation
1086 * from the hardware point of view.
1088 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1089 if (nb_hold > rxq->rx_free_thresh) {
1090 rx_id = (uint16_t)(rx_id == 0 ?
1091 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1092 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1095 rxq->nb_rx_hold = nb_hold;
1100 /* Check if the context descriptor is needed for TX offloading */
1101 static inline uint16_t
1102 i40e_calc_context_desc(uint64_t flags)
1104 uint64_t mask = 0ULL;
1106 if (flags | PKT_TX_VXLAN_CKSUM)
1107 mask |= PKT_TX_VXLAN_CKSUM;
1109 #ifdef RTE_LIBRTE_IEEE1588
1110 mask |= PKT_TX_IEEE1588_TMST;
1119 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1121 struct i40e_tx_queue *txq;
1122 struct i40e_tx_entry *sw_ring;
1123 struct i40e_tx_entry *txe, *txn;
1124 volatile struct i40e_tx_desc *txd;
1125 volatile struct i40e_tx_desc *txr;
1126 struct rte_mbuf *tx_pkt;
1127 struct rte_mbuf *m_seg;
1128 uint32_t cd_tunneling_params;
1138 uint8_t inner_l2_len;
1139 uint16_t inner_l3_len;
1144 uint64_t buf_dma_addr;
1147 sw_ring = txq->sw_ring;
1149 tx_id = txq->tx_tail;
1150 txe = &sw_ring[tx_id];
1152 /* Check if the descriptor ring needs to be cleaned. */
1153 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh)
1154 i40e_xmit_cleanup(txq);
1156 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1162 tx_pkt = *tx_pkts++;
1163 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1165 ol_flags = tx_pkt->ol_flags;
1166 l2_len = tx_pkt->l2_len;
1167 inner_l2_len = tx_pkt->inner_l2_len;
1168 l3_len = tx_pkt->l3_len;
1169 inner_l3_len = tx_pkt->inner_l3_len;
1171 /* Calculate the number of context descriptors needed. */
1172 nb_ctx = i40e_calc_context_desc(ol_flags);
1175 * The number of descriptors that must be allocated for
1176 * a packet equals to the number of the segments of that
1177 * packet plus 1 context descriptor if needed.
1179 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1180 tx_last = (uint16_t)(tx_id + nb_used - 1);
1183 if (tx_last >= txq->nb_tx_desc)
1184 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1186 if (nb_used > txq->nb_tx_free) {
1187 if (i40e_xmit_cleanup(txq) != 0) {
1192 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1193 while (nb_used > txq->nb_tx_free) {
1194 if (i40e_xmit_cleanup(txq) != 0) {
1203 /* Descriptor based VLAN insertion */
1204 if (ol_flags & PKT_TX_VLAN_PKT) {
1205 tx_flags |= tx_pkt->vlan_tci <<
1206 I40E_TX_FLAG_L2TAG1_SHIFT;
1207 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1208 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1209 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1210 I40E_TX_FLAG_L2TAG1_SHIFT;
1213 /* Always enable CRC offload insertion */
1214 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1216 /* Enable checksum offloading */
1217 cd_tunneling_params = 0;
1218 i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1219 l2_len, l3_len, inner_l2_len,
1221 &cd_tunneling_params);
1223 if (unlikely(nb_ctx)) {
1224 /* Setup TX context descriptor if required */
1225 volatile struct i40e_tx_context_desc *ctx_txd =
1226 (volatile struct i40e_tx_context_desc *)\
1228 uint16_t cd_l2tag2 = 0;
1229 uint64_t cd_type_cmd_tso_mss =
1230 I40E_TX_DESC_DTYPE_CONTEXT;
1232 txn = &sw_ring[txe->next_id];
1233 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1234 if (txe->mbuf != NULL) {
1235 rte_pktmbuf_free_seg(txe->mbuf);
1238 #ifdef RTE_LIBRTE_IEEE1588
1239 if (ol_flags & PKT_TX_IEEE1588_TMST)
1240 cd_type_cmd_tso_mss |=
1241 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1242 I40E_TXD_CTX_QW1_CMD_SHIFT);
1244 ctx_txd->tunneling_params =
1245 rte_cpu_to_le_32(cd_tunneling_params);
1246 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1247 ctx_txd->type_cmd_tso_mss =
1248 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1249 txe->last_id = tx_last;
1250 tx_id = txe->next_id;
1257 txn = &sw_ring[txe->next_id];
1260 rte_pktmbuf_free_seg(txe->mbuf);
1263 /* Setup TX Descriptor */
1264 slen = m_seg->data_len;
1265 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1266 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1267 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1268 td_offset, slen, td_tag);
1269 txe->last_id = tx_last;
1270 tx_id = txe->next_id;
1272 m_seg = m_seg->next;
1273 } while (m_seg != NULL);
1275 /* The last packet data descriptor needs End Of Packet (EOP) */
1276 td_cmd |= I40E_TX_DESC_CMD_EOP;
1277 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1278 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1280 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1281 PMD_TX_FREE_LOG(DEBUG,
1282 "Setting RS bit on TXD id="
1283 "%4u (port=%d queue=%d)",
1284 tx_last, txq->port_id, txq->queue_id);
1286 td_cmd |= I40E_TX_DESC_CMD_RS;
1288 /* Update txq RS bit counters */
1289 txq->nb_tx_used = 0;
1292 txd->cmd_type_offset_bsz |=
1293 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1294 I40E_TXD_QW1_CMD_SHIFT);
1300 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1301 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1302 (unsigned) tx_id, (unsigned) nb_tx);
1304 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1305 txq->tx_tail = tx_id;
1310 static inline int __attribute__((always_inline))
1311 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1313 struct i40e_tx_entry *txep;
1316 if (!(txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1317 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)))
1320 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1322 for (i = 0; i < txq->tx_rs_thresh; i++)
1323 rte_prefetch0((txep + i)->mbuf);
1325 if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1326 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1327 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1331 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1332 rte_pktmbuf_free_seg(txep->mbuf);
1337 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1338 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1339 if (txq->tx_next_dd >= txq->nb_tx_desc)
1340 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1342 return txq->tx_rs_thresh;
1345 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1346 I40E_TX_DESC_CMD_EOP)
1348 /* Populate 4 descriptors with data from 4 mbufs */
1350 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1355 for (i = 0; i < 4; i++, txdp++, pkts++) {
1356 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1357 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1358 txdp->cmd_type_offset_bsz =
1359 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1360 (*pkts)->data_len, 0);
1364 /* Populate 1 descriptor with data from 1 mbuf */
1366 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1370 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1371 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1372 txdp->cmd_type_offset_bsz =
1373 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1374 (*pkts)->data_len, 0);
1377 /* Fill hardware descriptor ring with mbuf data */
1379 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1380 struct rte_mbuf **pkts,
1383 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1384 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1385 const int N_PER_LOOP = 4;
1386 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1387 int mainpart, leftover;
1390 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1391 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1392 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1393 for (j = 0; j < N_PER_LOOP; ++j) {
1394 (txep + i + j)->mbuf = *(pkts + i + j);
1396 tx4(txdp + i, pkts + i);
1398 if (unlikely(leftover > 0)) {
1399 for (i = 0; i < leftover; ++i) {
1400 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1401 tx1(txdp + mainpart + i, pkts + mainpart + i);
1406 static inline uint16_t
1407 tx_xmit_pkts(struct i40e_tx_queue *txq,
1408 struct rte_mbuf **tx_pkts,
1411 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1415 * Begin scanning the H/W ring for done descriptors when the number
1416 * of available descriptors drops below tx_free_thresh. For each done
1417 * descriptor, free the associated buffer.
1419 if (txq->nb_tx_free < txq->tx_free_thresh)
1420 i40e_tx_free_bufs(txq);
1422 /* Use available descriptor only */
1423 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1424 if (unlikely(!nb_pkts))
1427 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1428 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1429 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1430 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1431 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1432 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1433 I40E_TXD_QW1_CMD_SHIFT);
1434 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1438 /* Fill hardware descriptor ring with mbuf data */
1439 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1440 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1442 /* Determin if RS bit needs to be set */
1443 if (txq->tx_tail > txq->tx_next_rs) {
1444 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1445 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1446 I40E_TXD_QW1_CMD_SHIFT);
1448 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1449 if (txq->tx_next_rs >= txq->nb_tx_desc)
1450 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1453 if (txq->tx_tail >= txq->nb_tx_desc)
1456 /* Update the tx tail register */
1458 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1464 i40e_xmit_pkts_simple(void *tx_queue,
1465 struct rte_mbuf **tx_pkts,
1470 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1471 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1475 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1478 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1479 &tx_pkts[nb_tx], num);
1480 nb_tx = (uint16_t)(nb_tx + ret);
1481 nb_pkts = (uint16_t)(nb_pkts - ret);
1490 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1491 * application used, which assume having sequential ones. But from driver's
1492 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1493 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1494 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1495 * use queue_idx from 0 to 95 to access queues, while real queue would be
1496 * different. This function will do a queue mapping to find VSI the queue
1499 static struct i40e_vsi*
1500 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1502 /* the queue in MAIN VSI range */
1503 if (queue_idx < pf->main_vsi->nb_qps)
1504 return pf->main_vsi;
1506 queue_idx -= pf->main_vsi->nb_qps;
1508 /* queue_idx is greater than VMDQ VSIs range */
1509 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1510 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1514 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1518 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1520 /* the queue in MAIN VSI range */
1521 if (queue_idx < pf->main_vsi->nb_qps)
1524 /* It's VMDQ queues */
1525 queue_idx -= pf->main_vsi->nb_qps;
1527 if (pf->nb_cfg_vmdq_vsi)
1528 return queue_idx % pf->vmdq_nb_qps;
1530 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1531 return (uint16_t)(-1);
1536 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1538 struct i40e_rx_queue *rxq;
1540 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1542 PMD_INIT_FUNC_TRACE();
1544 if (rx_queue_id < dev->data->nb_rx_queues) {
1545 rxq = dev->data->rx_queues[rx_queue_id];
1547 err = i40e_alloc_rx_queue_mbufs(rxq);
1549 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1555 /* Init the RX tail regieter. */
1556 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1558 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1561 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1564 i40e_rx_queue_release_mbufs(rxq);
1565 i40e_reset_rx_queue(rxq);
1573 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1575 struct i40e_rx_queue *rxq;
1577 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1579 if (rx_queue_id < dev->data->nb_rx_queues) {
1580 rxq = dev->data->rx_queues[rx_queue_id];
1583 * rx_queue_id is queue id aplication refers to, while
1584 * rxq->reg_idx is the real queue index.
1586 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1589 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1593 i40e_rx_queue_release_mbufs(rxq);
1594 i40e_reset_rx_queue(rxq);
1601 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1604 struct i40e_tx_queue *txq;
1605 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1607 PMD_INIT_FUNC_TRACE();
1609 if (tx_queue_id < dev->data->nb_tx_queues) {
1610 txq = dev->data->tx_queues[tx_queue_id];
1613 * tx_queue_id is queue id aplication refers to, while
1614 * rxq->reg_idx is the real queue index.
1616 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1618 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1626 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1628 struct i40e_tx_queue *txq;
1630 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1632 if (tx_queue_id < dev->data->nb_tx_queues) {
1633 txq = dev->data->tx_queues[tx_queue_id];
1636 * tx_queue_id is queue id aplication refers to, while
1637 * txq->reg_idx is the real queue index.
1639 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1642 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1647 i40e_tx_queue_release_mbufs(txq);
1648 i40e_reset_tx_queue(txq);
1655 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1658 unsigned int socket_id,
1659 const struct rte_eth_rxconf *rx_conf,
1660 struct rte_mempool *mp)
1662 struct i40e_vsi *vsi;
1663 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1664 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1665 struct i40e_rx_queue *rxq;
1666 const struct rte_memzone *rz;
1669 int use_def_burst_func = 1;
1671 if (hw->mac.type == I40E_MAC_VF) {
1672 struct i40e_vf *vf =
1673 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1676 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1679 PMD_DRV_LOG(ERR, "VSI not available or queue "
1680 "index exceeds the maximum");
1681 return I40E_ERR_PARAM;
1683 if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1684 (nb_desc > I40E_MAX_RING_DESC) ||
1685 (nb_desc < I40E_MIN_RING_DESC)) {
1686 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1687 "invalid", nb_desc);
1688 return I40E_ERR_PARAM;
1691 /* Free memory if needed */
1692 if (dev->data->rx_queues[queue_idx]) {
1693 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1694 dev->data->rx_queues[queue_idx] = NULL;
1697 /* Allocate the rx queue data structure */
1698 rxq = rte_zmalloc_socket("i40e rx queue",
1699 sizeof(struct i40e_rx_queue),
1703 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1704 "rx queue data structure");
1708 rxq->nb_rx_desc = nb_desc;
1709 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1710 rxq->queue_id = queue_idx;
1711 if (hw->mac.type == I40E_MAC_VF)
1712 rxq->reg_idx = queue_idx;
1713 else /* PF device */
1714 rxq->reg_idx = vsi->base_queue +
1715 i40e_get_queue_offset_by_qindex(pf, queue_idx);
1717 rxq->port_id = dev->data->port_id;
1718 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1720 rxq->drop_en = rx_conf->rx_drop_en;
1722 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1724 /* Allocate the maximun number of RX ring hardware descriptor. */
1725 ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1726 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1727 rz = i40e_ring_dma_zone_reserve(dev,
1733 i40e_dev_rx_queue_release(rxq);
1734 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1738 /* Zero all the descriptors in the ring. */
1739 memset(rz->addr, 0, ring_size);
1741 #ifdef RTE_LIBRTE_XEN_DOM0
1742 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1744 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1747 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1749 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1750 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1755 /* Allocate the software ring. */
1757 rte_zmalloc_socket("i40e rx sw ring",
1758 sizeof(struct i40e_rx_entry) * len,
1761 if (!rxq->sw_ring) {
1762 i40e_dev_rx_queue_release(rxq);
1763 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1767 i40e_reset_rx_queue(rxq);
1769 dev->data->rx_queues[queue_idx] = rxq;
1771 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1773 if (!use_def_burst_func && !dev->data->scattered_rx) {
1774 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1775 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1776 "satisfied. Rx Burst Bulk Alloc function will be "
1777 "used on port=%d, queue=%d.",
1778 rxq->port_id, rxq->queue_id);
1779 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1780 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1782 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1783 "not satisfied, Scattered Rx is requested, "
1784 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1785 "not enabled on port=%d, queue=%d.",
1786 rxq->port_id, rxq->queue_id);
1793 i40e_dev_rx_queue_release(void *rxq)
1795 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1798 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1802 i40e_rx_queue_release_mbufs(q);
1803 rte_free(q->sw_ring);
1808 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1810 #define I40E_RXQ_SCAN_INTERVAL 4
1811 volatile union i40e_rx_desc *rxdp;
1812 struct i40e_rx_queue *rxq;
1815 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1816 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1820 rxq = dev->data->rx_queues[rx_queue_id];
1821 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1822 while ((desc < rxq->nb_rx_desc) &&
1823 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1824 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1825 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1827 * Check the DD bit of a rx descriptor of each 4 in a group,
1828 * to avoid checking too frequently and downgrading performance
1831 desc += I40E_RXQ_SCAN_INTERVAL;
1832 rxdp += I40E_RXQ_SCAN_INTERVAL;
1833 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1834 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1835 desc - rxq->nb_rx_desc]);
1842 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1844 volatile union i40e_rx_desc *rxdp;
1845 struct i40e_rx_queue *rxq = rx_queue;
1849 if (unlikely(offset >= rxq->nb_rx_desc)) {
1850 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1854 desc = rxq->rx_tail + offset;
1855 if (desc >= rxq->nb_rx_desc)
1856 desc -= rxq->nb_rx_desc;
1858 rxdp = &(rxq->rx_ring[desc]);
1860 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1861 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1862 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1868 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1871 unsigned int socket_id,
1872 const struct rte_eth_txconf *tx_conf)
1874 struct i40e_vsi *vsi;
1875 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1876 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1877 struct i40e_tx_queue *txq;
1878 const struct rte_memzone *tz;
1880 uint16_t tx_rs_thresh, tx_free_thresh;
1882 if (hw->mac.type == I40E_MAC_VF) {
1883 struct i40e_vf *vf =
1884 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1887 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1890 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1891 "exceeds the maximum", queue_idx);
1892 return I40E_ERR_PARAM;
1895 if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
1896 (nb_desc > I40E_MAX_RING_DESC) ||
1897 (nb_desc < I40E_MIN_RING_DESC)) {
1898 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1899 "invalid", nb_desc);
1900 return I40E_ERR_PARAM;
1904 * The following two parameters control the setting of the RS bit on
1905 * transmit descriptors. TX descriptors will have their RS bit set
1906 * after txq->tx_rs_thresh descriptors have been used. The TX
1907 * descriptor ring will be cleaned after txq->tx_free_thresh
1908 * descriptors are used or if the number of descriptors required to
1909 * transmit a packet is greater than the number of free TX descriptors.
1911 * The following constraints must be satisfied:
1912 * - tx_rs_thresh must be greater than 0.
1913 * - tx_rs_thresh must be less than the size of the ring minus 2.
1914 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1915 * - tx_rs_thresh must be a divisor of the ring size.
1916 * - tx_free_thresh must be greater than 0.
1917 * - tx_free_thresh must be less than the size of the ring minus 3.
1919 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1920 * race condition, hence the maximum threshold constraints. When set
1921 * to zero use default values.
1923 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1924 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1925 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1926 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1927 if (tx_rs_thresh >= (nb_desc - 2)) {
1928 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1929 "number of TX descriptors minus 2. "
1930 "(tx_rs_thresh=%u port=%d queue=%d)",
1931 (unsigned int)tx_rs_thresh,
1932 (int)dev->data->port_id,
1934 return I40E_ERR_PARAM;
1936 if (tx_free_thresh >= (nb_desc - 3)) {
1937 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1938 "tx_free_thresh must be less than the "
1939 "number of TX descriptors minus 3. "
1940 "(tx_free_thresh=%u port=%d queue=%d)",
1941 (unsigned int)tx_free_thresh,
1942 (int)dev->data->port_id,
1944 return I40E_ERR_PARAM;
1946 if (tx_rs_thresh > tx_free_thresh) {
1947 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1948 "equal to tx_free_thresh. (tx_free_thresh=%u"
1949 " tx_rs_thresh=%u port=%d queue=%d)",
1950 (unsigned int)tx_free_thresh,
1951 (unsigned int)tx_rs_thresh,
1952 (int)dev->data->port_id,
1954 return I40E_ERR_PARAM;
1956 if ((nb_desc % tx_rs_thresh) != 0) {
1957 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1958 "number of TX descriptors. (tx_rs_thresh=%u"
1959 " port=%d queue=%d)",
1960 (unsigned int)tx_rs_thresh,
1961 (int)dev->data->port_id,
1963 return I40E_ERR_PARAM;
1965 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1966 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1967 "tx_rs_thresh is greater than 1. "
1968 "(tx_rs_thresh=%u port=%d queue=%d)",
1969 (unsigned int)tx_rs_thresh,
1970 (int)dev->data->port_id,
1972 return I40E_ERR_PARAM;
1975 /* Free memory if needed. */
1976 if (dev->data->tx_queues[queue_idx]) {
1977 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
1978 dev->data->tx_queues[queue_idx] = NULL;
1981 /* Allocate the TX queue data structure. */
1982 txq = rte_zmalloc_socket("i40e tx queue",
1983 sizeof(struct i40e_tx_queue),
1987 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1988 "tx queue structure");
1992 /* Allocate TX hardware ring descriptors. */
1993 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
1994 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1995 tz = i40e_ring_dma_zone_reserve(dev,
2001 i40e_dev_tx_queue_release(txq);
2002 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2006 txq->nb_tx_desc = nb_desc;
2007 txq->tx_rs_thresh = tx_rs_thresh;
2008 txq->tx_free_thresh = tx_free_thresh;
2009 txq->pthresh = tx_conf->tx_thresh.pthresh;
2010 txq->hthresh = tx_conf->tx_thresh.hthresh;
2011 txq->wthresh = tx_conf->tx_thresh.wthresh;
2012 txq->queue_id = queue_idx;
2013 if (hw->mac.type == I40E_MAC_VF)
2014 txq->reg_idx = queue_idx;
2015 else /* PF device */
2016 txq->reg_idx = vsi->base_queue +
2017 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2019 txq->port_id = dev->data->port_id;
2020 txq->txq_flags = tx_conf->txq_flags;
2022 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2024 #ifdef RTE_LIBRTE_XEN_DOM0
2025 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2027 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2029 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2031 /* Allocate software ring */
2033 rte_zmalloc_socket("i40e tx sw ring",
2034 sizeof(struct i40e_tx_entry) * nb_desc,
2037 if (!txq->sw_ring) {
2038 i40e_dev_tx_queue_release(txq);
2039 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2043 i40e_reset_tx_queue(txq);
2045 dev->data->tx_queues[queue_idx] = txq;
2047 /* Use a simple TX queue without offloads or multi segs if possible */
2048 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
2049 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
2050 PMD_INIT_LOG(INFO, "Using simple tx path");
2051 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2053 PMD_INIT_LOG(INFO, "Using full-featured tx path");
2054 dev->tx_pkt_burst = i40e_xmit_pkts;
2061 i40e_dev_tx_queue_release(void *txq)
2063 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2066 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2070 i40e_tx_queue_release_mbufs(q);
2071 rte_free(q->sw_ring);
2075 static const struct rte_memzone *
2076 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
2077 const char *ring_name,
2082 char z_name[RTE_MEMZONE_NAMESIZE];
2083 const struct rte_memzone *mz;
2085 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2086 dev->driver->pci_drv.name, ring_name,
2087 dev->data->port_id, queue_id);
2088 mz = rte_memzone_lookup(z_name);
2092 #ifdef RTE_LIBRTE_XEN_DOM0
2093 return rte_memzone_reserve_bounded(z_name, ring_size,
2094 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2096 return rte_memzone_reserve_aligned(z_name, ring_size,
2097 socket_id, 0, I40E_ALIGN);
2102 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2106 if (!rxq || !rxq->sw_ring) {
2107 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2111 for (i = 0; i < rxq->nb_rx_desc; i++) {
2112 if (rxq->sw_ring[i].mbuf) {
2113 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2114 rxq->sw_ring[i].mbuf = NULL;
2117 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2118 if (rxq->rx_nb_avail == 0)
2120 for (i = 0; i < rxq->rx_nb_avail; i++) {
2121 struct rte_mbuf *mbuf;
2123 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2124 rte_pktmbuf_free_seg(mbuf);
2126 rxq->rx_nb_avail = 0;
2127 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2131 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2136 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2137 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2138 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2140 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2141 len = rxq->nb_rx_desc;
2143 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2144 ((volatile char *)rxq->rx_ring)[i] = 0;
2146 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2147 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2148 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2149 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2151 rxq->rx_nb_avail = 0;
2152 rxq->rx_next_avail = 0;
2153 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2154 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2156 rxq->nb_rx_hold = 0;
2157 rxq->pkt_first_seg = NULL;
2158 rxq->pkt_last_seg = NULL;
2162 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2166 if (!txq || !txq->sw_ring) {
2167 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2171 for (i = 0; i < txq->nb_tx_desc; i++) {
2172 if (txq->sw_ring[i].mbuf) {
2173 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2174 txq->sw_ring[i].mbuf = NULL;
2180 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2182 struct i40e_tx_entry *txe;
2183 uint16_t i, prev, size;
2186 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2191 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2192 for (i = 0; i < size; i++)
2193 ((volatile char *)txq->tx_ring)[i] = 0;
2195 prev = (uint16_t)(txq->nb_tx_desc - 1);
2196 for (i = 0; i < txq->nb_tx_desc; i++) {
2197 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2199 txd->cmd_type_offset_bsz =
2200 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2203 txe[prev].next_id = i;
2207 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2208 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2211 txq->nb_tx_used = 0;
2213 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2214 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2217 /* Init the TX queue in hardware */
2219 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2221 enum i40e_status_code err = I40E_SUCCESS;
2222 struct i40e_vsi *vsi = txq->vsi;
2223 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2224 uint16_t pf_q = txq->reg_idx;
2225 struct i40e_hmc_obj_txq tx_ctx;
2228 /* clear the context structure first */
2229 memset(&tx_ctx, 0, sizeof(tx_ctx));
2230 tx_ctx.new_context = 1;
2231 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2232 tx_ctx.qlen = txq->nb_tx_desc;
2233 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2235 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2236 if (err != I40E_SUCCESS) {
2237 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2241 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2242 if (err != I40E_SUCCESS) {
2243 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2247 /* Now associate this queue with this PCI function */
2248 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2249 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2250 I40E_QTX_CTL_PF_INDX_MASK);
2251 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2252 I40E_WRITE_FLUSH(hw);
2254 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2260 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2262 struct i40e_rx_entry *rxe = rxq->sw_ring;
2266 for (i = 0; i < rxq->nb_rx_desc; i++) {
2267 volatile union i40e_rx_desc *rxd;
2268 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2270 if (unlikely(!mbuf)) {
2271 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2275 rte_mbuf_refcnt_set(mbuf, 1);
2277 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2279 mbuf->port = rxq->port_id;
2282 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2284 rxd = &rxq->rx_ring[i];
2285 rxd->read.pkt_addr = dma_addr;
2286 rxd->read.hdr_addr = dma_addr;
2287 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2288 rxd->read.rsvd1 = 0;
2289 rxd->read.rsvd2 = 0;
2290 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2299 * Calculate the buffer length, and check the jumbo frame
2300 * and maximum packet length.
2303 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2305 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2306 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2307 struct rte_eth_dev_data *data = pf->dev_data;
2308 struct rte_pktmbuf_pool_private *mbp_priv =
2309 rte_mempool_get_priv(rxq->mp);
2310 uint16_t buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2311 RTE_PKTMBUF_HEADROOM);
2314 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2315 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2316 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2317 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2318 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2319 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2320 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2321 rxq->hs_mode = i40e_header_split_enabled;
2323 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2325 rxq->rx_hdr_len = 0;
2326 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2327 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2328 rxq->hs_mode = i40e_header_split_none;
2332 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2333 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2334 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2335 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2336 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2337 PMD_DRV_LOG(ERR, "maximum packet length must "
2338 "be larger than %u and smaller than %u,"
2339 "as jumbo frame is enabled",
2340 (uint32_t)ETHER_MAX_LEN,
2341 (uint32_t)I40E_FRAME_SIZE_MAX);
2342 return I40E_ERR_CONFIG;
2345 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2346 rxq->max_pkt_len > ETHER_MAX_LEN) {
2347 PMD_DRV_LOG(ERR, "maximum packet length must be "
2348 "larger than %u and smaller than %u, "
2349 "as jumbo frame is disabled",
2350 (uint32_t)ETHER_MIN_LEN,
2351 (uint32_t)ETHER_MAX_LEN);
2352 return I40E_ERR_CONFIG;
2359 /* Init the RX queue in hardware */
2361 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2363 int err = I40E_SUCCESS;
2364 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2365 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2366 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2367 uint16_t pf_q = rxq->reg_idx;
2369 struct i40e_hmc_obj_rxq rx_ctx;
2370 struct rte_pktmbuf_pool_private *mbp_priv;
2372 err = i40e_rx_queue_config(rxq);
2374 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2378 /* Clear the context structure first */
2379 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2380 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2381 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2383 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2384 rx_ctx.qlen = rxq->nb_rx_desc;
2385 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2388 rx_ctx.dtype = rxq->hs_mode;
2390 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2392 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2393 rx_ctx.rxmax = rxq->max_pkt_len;
2394 rx_ctx.tphrdesc_ena = 1;
2395 rx_ctx.tphwdesc_ena = 1;
2396 rx_ctx.tphdata_ena = 1;
2397 rx_ctx.tphhead_ena = 1;
2398 rx_ctx.lrxqthresh = 2;
2399 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2404 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2405 if (err != I40E_SUCCESS) {
2406 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2409 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2410 if (err != I40E_SUCCESS) {
2411 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2415 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2417 mbp_priv = rte_mempool_get_priv(rxq->mp);
2418 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2419 RTE_PKTMBUF_HEADROOM);
2421 /* Check if scattered RX needs to be used. */
2422 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2423 dev_data->scattered_rx = 1;
2424 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2427 /* Init the RX tail regieter. */
2428 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2434 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2438 PMD_INIT_FUNC_TRACE();
2440 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2441 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2442 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2445 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2446 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2447 i40e_reset_rx_queue(dev->data->rx_queues[i]);