4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
54 #include "i40e_logs.h"
55 #include "i40e/i40e_prototype.h"
56 #include "i40e/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
60 #define I40E_MIN_RING_DESC 64
61 #define I40E_MAX_RING_DESC 4096
62 #define I40E_ALIGN 128
63 #define DEFAULT_TX_RS_THRESH 32
64 #define DEFAULT_TX_FREE_THRESH 32
65 #define I40E_MAX_PKT_TYPE 256
67 #define I40E_VLAN_TAG_SIZE 4
68 #define I40E_TX_MAX_BURST 32
70 #define I40E_DMA_MEM_ALIGN 4096
72 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
73 ETH_TXQ_FLAGS_NOOFFLOADS)
75 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
77 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
78 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
80 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
81 ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
83 static const struct rte_memzone *
84 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
85 const char *ring_name,
89 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
90 struct rte_mbuf **tx_pkts,
93 /* Translate the rx descriptor status to pkt flags */
94 static inline uint64_t
95 i40e_rxd_status_to_pkt_flags(uint64_t qword)
99 /* Check if VLAN packet */
100 flags = qword & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
103 /* Check if RSS_HASH */
104 flags |= (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
105 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
106 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
111 static inline uint64_t
112 i40e_rxd_error_to_pkt_flags(uint64_t qword)
115 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
117 #define I40E_RX_ERR_BITS 0x3f
118 if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
120 /* If RXE bit set, all other status bits are meaningless */
121 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
122 flags |= PKT_RX_MAC_ERR;
126 /* If RECIPE bit set, all other status indications should be ignored */
127 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
128 flags |= PKT_RX_RECIP_ERR;
131 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
132 flags |= PKT_RX_HBUF_OVERFLOW;
133 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
134 flags |= PKT_RX_IP_CKSUM_BAD;
135 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
136 flags |= PKT_RX_L4_CKSUM_BAD;
137 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
138 flags |= PKT_RX_EIP_CKSUM_BAD;
139 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
140 flags |= PKT_RX_OVERSIZE;
145 /* Translate pkt types to pkt flags */
146 static inline uint64_t
147 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
149 uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
150 I40E_RXD_QW1_PTYPE_SHIFT);
151 static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
174 PKT_RX_IPV4_HDR, /* PTYPE 22 */
175 PKT_RX_IPV4_HDR, /* PTYPE 23 */
176 PKT_RX_IPV4_HDR, /* PTYPE 24 */
178 PKT_RX_IPV4_HDR, /* PTYPE 26 */
179 PKT_RX_IPV4_HDR, /* PTYPE 27 */
180 PKT_RX_IPV4_HDR, /* PTYPE 28 */
181 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
182 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
183 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
185 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
186 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
187 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
188 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
189 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
190 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
192 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
193 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
194 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
195 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
196 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
197 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
198 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
200 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
201 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
202 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
203 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
204 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
205 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
207 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
208 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
209 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
210 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
211 PKT_RX_IPV4_HDR_EXT, /* PTYPE 59 */
212 PKT_RX_IPV4_HDR_EXT, /* PTYPE 60 */
213 PKT_RX_IPV4_HDR_EXT, /* PTYPE 61 */
215 PKT_RX_IPV4_HDR_EXT, /* PTYPE 63 */
216 PKT_RX_IPV4_HDR_EXT, /* PTYPE 64 */
217 PKT_RX_IPV4_HDR_EXT, /* PTYPE 65 */
218 PKT_RX_IPV4_HDR_EXT, /* PTYPE 66 */
219 PKT_RX_IPV4_HDR_EXT, /* PTYPE 67 */
220 PKT_RX_IPV4_HDR_EXT, /* PTYPE 68 */
222 PKT_RX_IPV4_HDR_EXT, /* PTYPE 70 */
223 PKT_RX_IPV4_HDR_EXT, /* PTYPE 71 */
224 PKT_RX_IPV4_HDR_EXT, /* PTYPE 72 */
225 PKT_RX_IPV4_HDR_EXT, /* PTYPE 73 */
226 PKT_RX_IPV4_HDR_EXT, /* PTYPE 74 */
227 PKT_RX_IPV4_HDR_EXT, /* PTYPE 75 */
228 PKT_RX_IPV4_HDR_EXT, /* PTYPE 76 */
230 PKT_RX_IPV4_HDR_EXT, /* PTYPE 78 */
231 PKT_RX_IPV4_HDR_EXT, /* PTYPE 79 */
232 PKT_RX_IPV4_HDR_EXT, /* PTYPE 80 */
233 PKT_RX_IPV4_HDR_EXT, /* PTYPE 81 */
234 PKT_RX_IPV4_HDR_EXT, /* PTYPE 82 */
235 PKT_RX_IPV4_HDR_EXT, /* PTYPE 83 */
237 PKT_RX_IPV4_HDR_EXT, /* PTYPE 85 */
238 PKT_RX_IPV4_HDR_EXT, /* PTYPE 86 */
239 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
240 PKT_RX_IPV6_HDR, /* PTYPE 88 */
241 PKT_RX_IPV6_HDR, /* PTYPE 89 */
242 PKT_RX_IPV6_HDR, /* PTYPE 90 */
244 PKT_RX_IPV6_HDR, /* PTYPE 92 */
245 PKT_RX_IPV6_HDR, /* PTYPE 93 */
246 PKT_RX_IPV6_HDR, /* PTYPE 94 */
247 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
248 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
249 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
251 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
252 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
253 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
254 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
255 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
256 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
258 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
259 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
260 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
261 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
262 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
263 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
264 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
266 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
267 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
268 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
269 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
270 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
271 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
273 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
274 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
275 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
276 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
277 PKT_RX_IPV6_HDR_EXT, /* PTYPE 125 */
278 PKT_RX_IPV6_HDR_EXT, /* PTYPE 126 */
279 PKT_RX_IPV6_HDR_EXT, /* PTYPE 127 */
281 PKT_RX_IPV6_HDR_EXT, /* PTYPE 129 */
282 PKT_RX_IPV6_HDR_EXT, /* PTYPE 130 */
283 PKT_RX_IPV6_HDR_EXT, /* PTYPE 131 */
284 PKT_RX_IPV6_HDR_EXT, /* PTYPE 132 */
285 PKT_RX_IPV6_HDR_EXT, /* PTYPE 133 */
286 PKT_RX_IPV6_HDR_EXT, /* PTYPE 134 */
288 PKT_RX_IPV6_HDR_EXT, /* PTYPE 136 */
289 PKT_RX_IPV6_HDR_EXT, /* PTYPE 137 */
290 PKT_RX_IPV6_HDR_EXT, /* PTYPE 138 */
291 PKT_RX_IPV6_HDR_EXT, /* PTYPE 139 */
292 PKT_RX_IPV6_HDR_EXT, /* PTYPE 140 */
293 PKT_RX_IPV6_HDR_EXT, /* PTYPE 141 */
294 PKT_RX_IPV6_HDR_EXT, /* PTYPE 142 */
296 PKT_RX_IPV6_HDR_EXT, /* PTYPE 144 */
297 PKT_RX_IPV6_HDR_EXT, /* PTYPE 145 */
298 PKT_RX_IPV6_HDR_EXT, /* PTYPE 146 */
299 PKT_RX_IPV6_HDR_EXT, /* PTYPE 147 */
300 PKT_RX_IPV6_HDR_EXT, /* PTYPE 148 */
301 PKT_RX_IPV6_HDR_EXT, /* PTYPE 149 */
303 PKT_RX_IPV6_HDR_EXT, /* PTYPE 151 */
304 PKT_RX_IPV6_HDR_EXT, /* PTYPE 152 */
305 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
410 return ip_ptype_map[ptype];
414 i40e_txd_enable_checksum(uint32_t ol_flags,
421 PMD_DRV_LOG(DEBUG, "L2 length set to 0");
424 *td_offset |= (l2_len >> 1) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
427 PMD_DRV_LOG(DEBUG, "L3 length set to 0");
431 /* Enable L3 checksum offloads */
432 if (ol_flags & PKT_TX_IPV4_CSUM) {
433 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
434 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
435 } else if (ol_flags & PKT_TX_IPV4) {
436 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
437 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
438 } else if (ol_flags & PKT_TX_IPV6) {
439 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
440 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
443 /* Enable L4 checksum offloads */
444 switch (ol_flags & PKT_TX_L4_MASK) {
445 case PKT_TX_TCP_CKSUM:
446 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
447 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
448 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
450 case PKT_TX_SCTP_CKSUM:
451 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
452 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
453 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
455 case PKT_TX_UDP_CKSUM:
456 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
457 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
458 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
465 static inline struct rte_mbuf *
466 rte_rxmbuf_alloc(struct rte_mempool *mp)
470 m = __rte_mbuf_raw_alloc(mp);
471 __rte_mbuf_sanity_check_raw(m, 0);
476 /* Construct the tx flags */
477 static inline uint64_t
478 i40e_build_ctob(uint32_t td_cmd,
483 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
484 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
485 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
486 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
487 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
491 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
493 struct i40e_tx_entry *sw_ring = txq->sw_ring;
494 volatile struct i40e_tx_desc *txd = txq->tx_ring;
495 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
496 uint16_t nb_tx_desc = txq->nb_tx_desc;
497 uint16_t desc_to_clean_to;
498 uint16_t nb_tx_to_clean;
500 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
501 if (desc_to_clean_to >= nb_tx_desc)
502 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
504 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
505 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
506 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) {
507 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
508 "(port=%d queue=%d)", desc_to_clean_to,
509 txq->port_id, txq->queue_id);
513 if (last_desc_cleaned > desc_to_clean_to)
514 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
517 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
520 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
522 txq->last_desc_cleaned = desc_to_clean_to;
523 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
529 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
530 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
532 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
537 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
538 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
539 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
540 "rxq->rx_free_thresh=%d, "
541 "RTE_PMD_I40E_RX_MAX_BURST=%d",
542 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
544 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
545 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
546 "rxq->rx_free_thresh=%d, "
547 "rxq->nb_rx_desc=%d",
548 rxq->rx_free_thresh, rxq->nb_rx_desc);
550 } else if (!(rxq->nb_rx_desc % rxq->rx_free_thresh) == 0) {
551 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
552 "rxq->nb_rx_desc=%d, "
553 "rxq->rx_free_thresh=%d",
554 rxq->nb_rx_desc, rxq->rx_free_thresh);
556 } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
557 RTE_PMD_I40E_RX_MAX_BURST))) {
558 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
559 "rxq->nb_rx_desc=%d, "
560 "I40E_MAX_RING_DESC=%d, "
561 "RTE_PMD_I40E_RX_MAX_BURST=%d",
562 rxq->nb_rx_desc, I40E_MAX_RING_DESC,
563 RTE_PMD_I40E_RX_MAX_BURST);
573 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
574 #define I40E_LOOK_AHEAD 8
575 #if (I40E_LOOK_AHEAD != 8)
576 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
579 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
581 volatile union i40e_rx_desc *rxdp;
582 struct i40e_rx_entry *rxep;
587 int32_t s[I40E_LOOK_AHEAD], nb_dd;
588 int32_t i, j, nb_rx = 0;
591 rxdp = &rxq->rx_ring[rxq->rx_tail];
592 rxep = &rxq->sw_ring[rxq->rx_tail];
594 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
595 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
596 I40E_RXD_QW1_STATUS_SHIFT;
598 /* Make sure there is at least 1 packet to receive */
599 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
603 * Scan LOOK_AHEAD descriptors at a time to determine which
604 * descriptors reference packets that are ready to be received.
606 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
607 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
608 /* Read desc statuses backwards to avoid race condition */
609 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
610 qword1 = rte_le_to_cpu_64(\
611 rxdp[j].wb.qword1.status_error_len);
612 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
613 I40E_RXD_QW1_STATUS_SHIFT;
616 /* Compute how many status bits were set */
617 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
618 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
622 /* Translate descriptor info to mbuf parameters */
623 for (j = 0; j < nb_dd; j++) {
625 qword1 = rte_le_to_cpu_64(\
626 rxdp[j].wb.qword1.status_error_len);
627 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
628 I40E_RXD_QW1_STATUS_SHIFT;
629 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
630 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
631 mb->data_len = pkt_len;
632 mb->pkt_len = pkt_len;
633 mb->vlan_tci = rx_status &
634 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
636 rxdp[j].wb.qword0.lo_dword.l2tag1) : 0;
637 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
638 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
639 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
640 mb->ol_flags = pkt_flags;
641 if (pkt_flags & PKT_RX_RSS_HASH)
642 mb->hash.rss = rte_le_to_cpu_32(\
643 rxdp->wb.qword0.hi_dword.rss);
646 for (j = 0; j < I40E_LOOK_AHEAD; j++)
647 rxq->rx_stage[i + j] = rxep[j].mbuf;
649 if (nb_dd != I40E_LOOK_AHEAD)
653 /* Clear software ring entries */
654 for (i = 0; i < nb_rx; i++)
655 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
660 static inline uint16_t
661 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
662 struct rte_mbuf **rx_pkts,
666 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
668 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
670 for (i = 0; i < nb_pkts; i++)
671 rx_pkts[i] = stage[i];
673 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
674 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
680 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
682 volatile union i40e_rx_desc *rxdp;
683 struct i40e_rx_entry *rxep;
685 uint16_t alloc_idx, i;
689 /* Allocate buffers in bulk */
690 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
691 (rxq->rx_free_thresh - 1));
692 rxep = &(rxq->sw_ring[alloc_idx]);
693 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
694 rxq->rx_free_thresh);
695 if (unlikely(diag != 0)) {
696 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
700 rxdp = &rxq->rx_ring[alloc_idx];
701 for (i = 0; i < rxq->rx_free_thresh; i++) {
703 rte_mbuf_refcnt_set(mb, 1);
705 mb->data_off = RTE_PKTMBUF_HEADROOM;
707 mb->port = rxq->port_id;
708 dma_addr = rte_cpu_to_le_64(\
709 RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
710 rxdp[i].read.hdr_addr = dma_addr;
711 rxdp[i].read.pkt_addr = dma_addr;
714 /* Update rx tail regsiter */
716 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
718 rxq->rx_free_trigger =
719 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
720 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
721 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
726 static inline uint16_t
727 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
729 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
735 if (rxq->rx_nb_avail)
736 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
738 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
739 rxq->rx_next_avail = 0;
740 rxq->rx_nb_avail = nb_rx;
741 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
743 if (rxq->rx_tail > rxq->rx_free_trigger) {
744 if (i40e_rx_alloc_bufs(rxq) != 0) {
747 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
748 "port_id=%u, queue_id=%u",
749 rxq->port_id, rxq->queue_id);
750 rxq->rx_nb_avail = 0;
751 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
752 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
753 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
759 if (rxq->rx_tail >= rxq->nb_rx_desc)
762 if (rxq->rx_nb_avail)
763 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
769 i40e_recv_pkts_bulk_alloc(void *rx_queue,
770 struct rte_mbuf **rx_pkts,
773 uint16_t nb_rx = 0, n, count;
775 if (unlikely(nb_pkts == 0))
778 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
779 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
782 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
783 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
784 nb_rx = (uint16_t)(nb_rx + count);
785 nb_pkts = (uint16_t)(nb_pkts - count);
792 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
795 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
797 struct i40e_rx_queue *rxq;
798 volatile union i40e_rx_desc *rx_ring;
799 volatile union i40e_rx_desc *rxdp;
800 union i40e_rx_desc rxd;
801 struct i40e_rx_entry *sw_ring;
802 struct i40e_rx_entry *rxe;
803 struct rte_mbuf *rxm;
804 struct rte_mbuf *nmb;
808 uint16_t rx_packet_len;
809 uint16_t rx_id, nb_hold;
816 rx_id = rxq->rx_tail;
817 rx_ring = rxq->rx_ring;
818 sw_ring = rxq->sw_ring;
820 while (nb_rx < nb_pkts) {
821 rxdp = &rx_ring[rx_id];
822 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
823 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
824 >> I40E_RXD_QW1_STATUS_SHIFT;
825 /* Check the DD bit first */
826 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
829 nmb = rte_rxmbuf_alloc(rxq->mp);
835 rxe = &sw_ring[rx_id];
837 if (unlikely(rx_id == rxq->nb_rx_desc))
840 /* Prefetch next mbuf */
841 rte_prefetch0(sw_ring[rx_id].mbuf);
844 * When next RX descriptor is on a cache line boundary,
845 * prefetch the next 4 RX descriptors and next 8 pointers
848 if ((rx_id & 0x3) == 0) {
849 rte_prefetch0(&rx_ring[rx_id]);
850 rte_prefetch0(&sw_ring[rx_id]);
855 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
856 rxdp->read.hdr_addr = dma_addr;
857 rxdp->read.pkt_addr = dma_addr;
859 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
860 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
862 rxm->data_off = RTE_PKTMBUF_HEADROOM;
863 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
866 rxm->pkt_len = rx_packet_len;
867 rxm->data_len = rx_packet_len;
868 rxm->port = rxq->port_id;
870 rxm->vlan_tci = rx_status &
871 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
872 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
873 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
874 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
875 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
876 rxm->ol_flags = pkt_flags;
877 if (pkt_flags & PKT_RX_RSS_HASH)
879 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
881 rx_pkts[nb_rx++] = rxm;
883 rxq->rx_tail = rx_id;
886 * If the number of free RX descriptors is greater than the RX free
887 * threshold of the queue, advance the receive tail register of queue.
888 * Update that register with the value of the last processed RX
889 * descriptor minus 1.
891 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
892 if (nb_hold > rxq->rx_free_thresh) {
893 rx_id = (uint16_t) ((rx_id == 0) ?
894 (rxq->nb_rx_desc - 1) : (rx_id - 1));
895 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
898 rxq->nb_rx_hold = nb_hold;
904 i40e_recv_scattered_pkts(void *rx_queue,
905 struct rte_mbuf **rx_pkts,
908 struct i40e_rx_queue *rxq = rx_queue;
909 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
910 volatile union i40e_rx_desc *rxdp;
911 union i40e_rx_desc rxd;
912 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
913 struct i40e_rx_entry *rxe;
914 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
915 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
916 struct rte_mbuf *nmb, *rxm;
917 uint16_t rx_id = rxq->rx_tail;
918 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
924 while (nb_rx < nb_pkts) {
925 rxdp = &rx_ring[rx_id];
926 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
927 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
928 I40E_RXD_QW1_STATUS_SHIFT;
929 /* Check the DD bit */
930 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
933 nmb = rte_rxmbuf_alloc(rxq->mp);
938 rxe = &sw_ring[rx_id];
940 if (rx_id == rxq->nb_rx_desc)
943 /* Prefetch next mbuf */
944 rte_prefetch0(sw_ring[rx_id].mbuf);
947 * When next RX descriptor is on a cache line boundary,
948 * prefetch the next 4 RX descriptors and next 8 pointers
951 if ((rx_id & 0x3) == 0) {
952 rte_prefetch0(&rx_ring[rx_id]);
953 rte_prefetch0(&sw_ring[rx_id]);
959 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
961 /* Set data buffer address and data length of the mbuf */
962 rxdp->read.hdr_addr = dma_addr;
963 rxdp->read.pkt_addr = dma_addr;
964 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
965 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
966 rxm->data_len = rx_packet_len;
967 rxm->data_off = RTE_PKTMBUF_HEADROOM;
970 * If this is the first buffer of the received packet, set the
971 * pointer to the first mbuf of the packet and initialize its
972 * context. Otherwise, update the total length and the number
973 * of segments of the current scattered packet, and update the
974 * pointer to the last mbuf of the current packet.
978 first_seg->nb_segs = 1;
979 first_seg->pkt_len = rx_packet_len;
982 (uint16_t)(first_seg->pkt_len +
984 first_seg->nb_segs++;
985 last_seg->next = rxm;
989 * If this is not the last buffer of the received packet,
990 * update the pointer to the last mbuf of the current scattered
991 * packet and continue to parse the RX ring.
993 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
999 * This is the last buffer of the received packet. If the CRC
1000 * is not stripped by the hardware:
1001 * - Subtract the CRC length from the total packet length.
1002 * - If the last buffer only contains the whole CRC or a part
1003 * of it, free the mbuf associated to the last buffer. If part
1004 * of the CRC is also contained in the previous mbuf, subtract
1005 * the length of that CRC part from the data length of the
1009 if (unlikely(rxq->crc_len > 0)) {
1010 first_seg->pkt_len -= ETHER_CRC_LEN;
1011 if (rx_packet_len <= ETHER_CRC_LEN) {
1012 rte_pktmbuf_free_seg(rxm);
1013 first_seg->nb_segs--;
1014 last_seg->data_len =
1015 (uint16_t)(last_seg->data_len -
1016 (ETHER_CRC_LEN - rx_packet_len));
1017 last_seg->next = NULL;
1019 rxm->data_len = (uint16_t)(rx_packet_len -
1023 first_seg->port = rxq->port_id;
1024 first_seg->vlan_tci = (rx_status &
1025 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1026 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
1027 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1028 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1029 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1030 first_seg->ol_flags = pkt_flags;
1031 if (pkt_flags & PKT_RX_RSS_HASH)
1033 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1035 /* Prefetch data of first segment, if configured to do so. */
1036 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1037 first_seg->data_off));
1038 rx_pkts[nb_rx++] = first_seg;
1042 /* Record index of the next RX descriptor to probe. */
1043 rxq->rx_tail = rx_id;
1044 rxq->pkt_first_seg = first_seg;
1045 rxq->pkt_last_seg = last_seg;
1048 * If the number of free RX descriptors is greater than the RX free
1049 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1050 * register. Update the RDT with the value of the last processed RX
1051 * descriptor minus 1, to guarantee that the RDT register is never
1052 * equal to the RDH register, which creates a "full" ring situtation
1053 * from the hardware point of view.
1055 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1056 if (nb_hold > rxq->rx_free_thresh) {
1057 rx_id = (uint16_t)(rx_id == 0 ?
1058 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1059 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1062 rxq->nb_rx_hold = nb_hold;
1067 /* Check if the context descriptor is needed for TX offloading */
1068 static inline uint16_t
1069 i40e_calc_context_desc(uint64_t flags)
1073 #ifdef RTE_LIBRTE_IEEE1588
1074 mask |= PKT_TX_IEEE1588_TMST;
1083 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1085 struct i40e_tx_queue *txq;
1086 struct i40e_tx_entry *sw_ring;
1087 struct i40e_tx_entry *txe, *txn;
1088 volatile struct i40e_tx_desc *txd;
1089 volatile struct i40e_tx_desc *txr;
1090 struct rte_mbuf *tx_pkt;
1091 struct rte_mbuf *m_seg;
1105 uint64_t buf_dma_addr;
1108 sw_ring = txq->sw_ring;
1110 tx_id = txq->tx_tail;
1111 txe = &sw_ring[tx_id];
1113 /* Check if the descriptor ring needs to be cleaned. */
1114 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh)
1115 i40e_xmit_cleanup(txq);
1117 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1123 tx_pkt = *tx_pkts++;
1124 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1126 ol_flags = tx_pkt->ol_flags;
1127 l2_len = tx_pkt->l2_len;
1128 l3_len = tx_pkt->l3_len;
1130 /* Calculate the number of context descriptors needed. */
1131 nb_ctx = i40e_calc_context_desc(ol_flags);
1134 * The number of descriptors that must be allocated for
1135 * a packet equals to the number of the segments of that
1136 * packet plus 1 context descriptor if needed.
1138 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1139 tx_last = (uint16_t)(tx_id + nb_used - 1);
1142 if (tx_last >= txq->nb_tx_desc)
1143 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1145 if (nb_used > txq->nb_tx_free) {
1146 if (i40e_xmit_cleanup(txq) != 0) {
1151 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1152 while (nb_used > txq->nb_tx_free) {
1153 if (i40e_xmit_cleanup(txq) != 0) {
1162 /* Descriptor based VLAN insertion */
1163 if (ol_flags & PKT_TX_VLAN_PKT) {
1164 tx_flags |= tx_pkt->vlan_tci <<
1165 I40E_TX_FLAG_L2TAG1_SHIFT;
1166 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1167 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1168 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1169 I40E_TX_FLAG_L2TAG1_SHIFT;
1172 /* Always enable CRC offload insertion */
1173 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1175 /* Enable checksum offloading */
1176 i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1179 if (unlikely(nb_ctx)) {
1180 /* Setup TX context descriptor if required */
1181 volatile struct i40e_tx_context_desc *ctx_txd =
1182 (volatile struct i40e_tx_context_desc *)\
1184 uint32_t cd_tunneling_params = 0;
1185 uint16_t cd_l2tag2 = 0;
1186 uint64_t cd_type_cmd_tso_mss =
1187 I40E_TX_DESC_DTYPE_CONTEXT;
1189 txn = &sw_ring[txe->next_id];
1190 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1191 if (txe->mbuf != NULL) {
1192 rte_pktmbuf_free_seg(txe->mbuf);
1195 #ifdef RTE_LIBRTE_IEEE1588
1196 if (ol_flags & PKT_TX_IEEE1588_TMST)
1197 cd_type_cmd_tso_mss |=
1198 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1199 I40E_TXD_CTX_QW1_CMD_SHIFT);
1201 ctx_txd->tunneling_params =
1202 rte_cpu_to_le_32(cd_tunneling_params);
1203 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1204 ctx_txd->type_cmd_tso_mss =
1205 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1206 txe->last_id = tx_last;
1207 tx_id = txe->next_id;
1214 txn = &sw_ring[txe->next_id];
1217 rte_pktmbuf_free_seg(txe->mbuf);
1220 /* Setup TX Descriptor */
1221 slen = m_seg->data_len;
1222 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1223 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1224 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1225 td_offset, slen, td_tag);
1226 txe->last_id = tx_last;
1227 tx_id = txe->next_id;
1229 m_seg = m_seg->next;
1230 } while (m_seg != NULL);
1232 /* The last packet data descriptor needs End Of Packet (EOP) */
1233 td_cmd |= I40E_TX_DESC_CMD_EOP;
1234 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1235 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1237 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1238 PMD_TX_FREE_LOG(DEBUG,
1239 "Setting RS bit on TXD id="
1240 "%4u (port=%d queue=%d)",
1241 tx_last, txq->port_id, txq->queue_id);
1243 td_cmd |= I40E_TX_DESC_CMD_RS;
1245 /* Update txq RS bit counters */
1246 txq->nb_tx_used = 0;
1249 txd->cmd_type_offset_bsz |=
1250 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1251 I40E_TXD_QW1_CMD_SHIFT);
1257 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1258 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1259 (unsigned) tx_id, (unsigned) nb_tx);
1261 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1262 txq->tx_tail = tx_id;
1267 static inline int __attribute__((always_inline))
1268 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1270 struct i40e_tx_entry *txep;
1273 if (!(txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1274 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)))
1277 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1279 for (i = 0; i < txq->tx_rs_thresh; i++)
1280 rte_prefetch0((txep + i)->mbuf);
1282 if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1283 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1284 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1288 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1289 rte_pktmbuf_free_seg(txep->mbuf);
1294 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1295 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1296 if (txq->tx_next_dd >= txq->nb_tx_desc)
1297 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1299 return txq->tx_rs_thresh;
1302 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1303 I40E_TX_DESC_CMD_EOP)
1305 /* Populate 4 descriptors with data from 4 mbufs */
1307 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1312 for (i = 0; i < 4; i++, txdp++, pkts++) {
1313 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1314 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1315 txdp->cmd_type_offset_bsz =
1316 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1317 (*pkts)->data_len, 0);
1321 /* Populate 1 descriptor with data from 1 mbuf */
1323 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1327 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1328 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1329 txdp->cmd_type_offset_bsz =
1330 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1331 (*pkts)->data_len, 0);
1334 /* Fill hardware descriptor ring with mbuf data */
1336 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1337 struct rte_mbuf **pkts,
1340 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1341 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1342 const int N_PER_LOOP = 4;
1343 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1344 int mainpart, leftover;
1347 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1348 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1349 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1350 for (j = 0; j < N_PER_LOOP; ++j) {
1351 (txep + i + j)->mbuf = *(pkts + i + j);
1353 tx4(txdp + i, pkts + i);
1355 if (unlikely(leftover > 0)) {
1356 for (i = 0; i < leftover; ++i) {
1357 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1358 tx1(txdp + mainpart + i, pkts + mainpart + i);
1363 static inline uint16_t
1364 tx_xmit_pkts(struct i40e_tx_queue *txq,
1365 struct rte_mbuf **tx_pkts,
1368 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1372 * Begin scanning the H/W ring for done descriptors when the number
1373 * of available descriptors drops below tx_free_thresh. For each done
1374 * descriptor, free the associated buffer.
1376 if (txq->nb_tx_free < txq->tx_free_thresh)
1377 i40e_tx_free_bufs(txq);
1379 /* Use available descriptor only */
1380 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1381 if (unlikely(!nb_pkts))
1384 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1385 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1386 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1387 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1388 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1389 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1390 I40E_TXD_QW1_CMD_SHIFT);
1391 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1395 /* Fill hardware descriptor ring with mbuf data */
1396 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1397 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1399 /* Determin if RS bit needs to be set */
1400 if (txq->tx_tail > txq->tx_next_rs) {
1401 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1402 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1403 I40E_TXD_QW1_CMD_SHIFT);
1405 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1406 if (txq->tx_next_rs >= txq->nb_tx_desc)
1407 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1410 if (txq->tx_tail >= txq->nb_tx_desc)
1413 /* Update the tx tail register */
1415 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1421 i40e_xmit_pkts_simple(void *tx_queue,
1422 struct rte_mbuf **tx_pkts,
1427 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1428 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1432 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1435 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1436 &tx_pkts[nb_tx], num);
1437 nb_tx = (uint16_t)(nb_tx + ret);
1438 nb_pkts = (uint16_t)(nb_pkts - ret);
1447 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1449 struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1450 struct i40e_rx_queue *rxq;
1452 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1453 uint16_t q_base = vsi->base_queue;
1455 PMD_INIT_FUNC_TRACE();
1457 if (rx_queue_id < dev->data->nb_rx_queues) {
1458 rxq = dev->data->rx_queues[rx_queue_id];
1460 err = i40e_alloc_rx_queue_mbufs(rxq);
1462 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1468 /* Init the RX tail regieter. */
1469 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1471 err = i40e_switch_rx_queue(hw, rx_queue_id + q_base, TRUE);
1474 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1477 i40e_rx_queue_release_mbufs(rxq);
1478 i40e_reset_rx_queue(rxq);
1486 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1488 struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1489 struct i40e_rx_queue *rxq;
1491 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1492 uint16_t q_base = vsi->base_queue;
1494 if (rx_queue_id < dev->data->nb_rx_queues) {
1495 rxq = dev->data->rx_queues[rx_queue_id];
1497 err = i40e_switch_rx_queue(hw, rx_queue_id + q_base, FALSE);
1500 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1504 i40e_rx_queue_release_mbufs(rxq);
1505 i40e_reset_rx_queue(rxq);
1512 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1514 struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1516 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1517 uint16_t q_base = vsi->base_queue;
1519 PMD_INIT_FUNC_TRACE();
1521 if (tx_queue_id < dev->data->nb_tx_queues) {
1522 err = i40e_switch_tx_queue(hw, tx_queue_id + q_base, TRUE);
1524 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1532 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1534 struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1535 struct i40e_tx_queue *txq;
1537 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1538 uint16_t q_base = vsi->base_queue;
1540 if (tx_queue_id < dev->data->nb_tx_queues) {
1541 txq = dev->data->tx_queues[tx_queue_id];
1543 err = i40e_switch_tx_queue(hw, tx_queue_id + q_base, FALSE);
1546 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1551 i40e_tx_queue_release_mbufs(txq);
1552 i40e_reset_tx_queue(txq);
1559 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1562 unsigned int socket_id,
1563 const struct rte_eth_rxconf *rx_conf,
1564 struct rte_mempool *mp)
1566 struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1567 struct i40e_rx_queue *rxq;
1568 const struct rte_memzone *rz;
1571 int use_def_burst_func = 1;
1573 if (!vsi || queue_idx >= vsi->nb_qps) {
1574 PMD_DRV_LOG(ERR, "VSI not available or queue "
1575 "index exceeds the maximum");
1576 return I40E_ERR_PARAM;
1578 if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1579 (nb_desc > I40E_MAX_RING_DESC) ||
1580 (nb_desc < I40E_MIN_RING_DESC)) {
1581 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1582 "invalid", nb_desc);
1583 return I40E_ERR_PARAM;
1586 /* Free memory if needed */
1587 if (dev->data->rx_queues[queue_idx]) {
1588 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1589 dev->data->rx_queues[queue_idx] = NULL;
1592 /* Allocate the rx queue data structure */
1593 rxq = rte_zmalloc_socket("i40e rx queue",
1594 sizeof(struct i40e_rx_queue),
1598 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1599 "rx queue data structure");
1603 rxq->nb_rx_desc = nb_desc;
1604 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1605 rxq->queue_id = queue_idx;
1606 rxq->reg_idx = vsi->base_queue + queue_idx;
1607 rxq->port_id = dev->data->port_id;
1608 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1610 rxq->drop_en = rx_conf->rx_drop_en;
1612 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1614 /* Allocate the maximun number of RX ring hardware descriptor. */
1615 ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1616 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1617 rz = i40e_ring_dma_zone_reserve(dev,
1623 i40e_dev_rx_queue_release(rxq);
1624 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1628 /* Zero all the descriptors in the ring. */
1629 memset(rz->addr, 0, ring_size);
1631 #ifdef RTE_LIBRTE_XEN_DOM0
1632 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1634 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1637 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1639 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1640 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1645 /* Allocate the software ring. */
1647 rte_zmalloc_socket("i40e rx sw ring",
1648 sizeof(struct i40e_rx_entry) * len,
1651 if (!rxq->sw_ring) {
1652 i40e_dev_rx_queue_release(rxq);
1653 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1657 i40e_reset_rx_queue(rxq);
1659 dev->data->rx_queues[queue_idx] = rxq;
1661 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1663 if (!use_def_burst_func && !dev->data->scattered_rx) {
1664 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1665 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1666 "satisfied. Rx Burst Bulk Alloc function will be "
1667 "used on port=%d, queue=%d.",
1668 rxq->port_id, rxq->queue_id);
1669 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1670 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1672 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1673 "not satisfied, Scattered Rx is requested, "
1674 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1675 "not enabled on port=%d, queue=%d.",
1676 rxq->port_id, rxq->queue_id);
1683 i40e_dev_rx_queue_release(void *rxq)
1685 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1688 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1692 i40e_rx_queue_release_mbufs(q);
1693 rte_free(q->sw_ring);
1698 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1700 #define I40E_RXQ_SCAN_INTERVAL 4
1701 volatile union i40e_rx_desc *rxdp;
1702 struct i40e_rx_queue *rxq;
1705 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1706 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1710 rxq = dev->data->rx_queues[rx_queue_id];
1711 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1712 while ((desc < rxq->nb_rx_desc) &&
1713 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1714 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1715 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1717 * Check the DD bit of a rx descriptor of each 4 in a group,
1718 * to avoid checking too frequently and downgrading performance
1721 desc += I40E_RXQ_SCAN_INTERVAL;
1722 rxdp += I40E_RXQ_SCAN_INTERVAL;
1723 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1724 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1725 desc - rxq->nb_rx_desc]);
1732 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1734 volatile union i40e_rx_desc *rxdp;
1735 struct i40e_rx_queue *rxq = rx_queue;
1739 if (unlikely(offset >= rxq->nb_rx_desc)) {
1740 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1744 desc = rxq->rx_tail + offset;
1745 if (desc >= rxq->nb_rx_desc)
1746 desc -= rxq->nb_rx_desc;
1748 rxdp = &(rxq->rx_ring[desc]);
1750 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1751 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1752 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1758 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1761 unsigned int socket_id,
1762 const struct rte_eth_txconf *tx_conf)
1764 struct i40e_vsi *vsi = I40E_DEV_PRIVATE_TO_VSI(dev->data->dev_private);
1765 struct i40e_tx_queue *txq;
1766 const struct rte_memzone *tz;
1768 uint16_t tx_rs_thresh, tx_free_thresh;
1770 if (!vsi || queue_idx >= vsi->nb_qps) {
1771 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1772 "exceeds the maximum", queue_idx);
1773 return I40E_ERR_PARAM;
1776 if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
1777 (nb_desc > I40E_MAX_RING_DESC) ||
1778 (nb_desc < I40E_MIN_RING_DESC)) {
1779 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1780 "invalid", nb_desc);
1781 return I40E_ERR_PARAM;
1785 * The following two parameters control the setting of the RS bit on
1786 * transmit descriptors. TX descriptors will have their RS bit set
1787 * after txq->tx_rs_thresh descriptors have been used. The TX
1788 * descriptor ring will be cleaned after txq->tx_free_thresh
1789 * descriptors are used or if the number of descriptors required to
1790 * transmit a packet is greater than the number of free TX descriptors.
1792 * The following constraints must be satisfied:
1793 * - tx_rs_thresh must be greater than 0.
1794 * - tx_rs_thresh must be less than the size of the ring minus 2.
1795 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1796 * - tx_rs_thresh must be a divisor of the ring size.
1797 * - tx_free_thresh must be greater than 0.
1798 * - tx_free_thresh must be less than the size of the ring minus 3.
1800 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1801 * race condition, hence the maximum threshold constraints. When set
1802 * to zero use default values.
1804 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1805 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1806 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1807 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1808 if (tx_rs_thresh >= (nb_desc - 2)) {
1809 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1810 "number of TX descriptors minus 2. "
1811 "(tx_rs_thresh=%u port=%d queue=%d)",
1812 (unsigned int)tx_rs_thresh,
1813 (int)dev->data->port_id,
1815 return I40E_ERR_PARAM;
1817 if (tx_free_thresh >= (nb_desc - 3)) {
1818 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1819 "tx_free_thresh must be less than the "
1820 "number of TX descriptors minus 3. "
1821 "(tx_free_thresh=%u port=%d queue=%d)",
1822 (unsigned int)tx_free_thresh,
1823 (int)dev->data->port_id,
1825 return I40E_ERR_PARAM;
1827 if (tx_rs_thresh > tx_free_thresh) {
1828 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
1829 "equal to tx_free_thresh. (tx_free_thresh=%u"
1830 " tx_rs_thresh=%u port=%d queue=%d)",
1831 (unsigned int)tx_free_thresh,
1832 (unsigned int)tx_rs_thresh,
1833 (int)dev->data->port_id,
1835 return I40E_ERR_PARAM;
1837 if ((nb_desc % tx_rs_thresh) != 0) {
1838 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
1839 "number of TX descriptors. (tx_rs_thresh=%u"
1840 " port=%d queue=%d)",
1841 (unsigned int)tx_rs_thresh,
1842 (int)dev->data->port_id,
1844 return I40E_ERR_PARAM;
1846 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
1847 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
1848 "tx_rs_thresh is greater than 1. "
1849 "(tx_rs_thresh=%u port=%d queue=%d)",
1850 (unsigned int)tx_rs_thresh,
1851 (int)dev->data->port_id,
1853 return I40E_ERR_PARAM;
1856 /* Free memory if needed. */
1857 if (dev->data->tx_queues[queue_idx]) {
1858 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
1859 dev->data->tx_queues[queue_idx] = NULL;
1862 /* Allocate the TX queue data structure. */
1863 txq = rte_zmalloc_socket("i40e tx queue",
1864 sizeof(struct i40e_tx_queue),
1868 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1869 "tx queue structure");
1873 /* Allocate TX hardware ring descriptors. */
1874 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
1875 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1876 tz = i40e_ring_dma_zone_reserve(dev,
1882 i40e_dev_tx_queue_release(txq);
1883 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
1887 txq->nb_tx_desc = nb_desc;
1888 txq->tx_rs_thresh = tx_rs_thresh;
1889 txq->tx_free_thresh = tx_free_thresh;
1890 txq->pthresh = tx_conf->tx_thresh.pthresh;
1891 txq->hthresh = tx_conf->tx_thresh.hthresh;
1892 txq->wthresh = tx_conf->tx_thresh.wthresh;
1893 txq->queue_id = queue_idx;
1894 txq->reg_idx = vsi->base_queue + queue_idx;
1895 txq->port_id = dev->data->port_id;
1896 txq->txq_flags = tx_conf->txq_flags;
1898 txq->tx_deferred_start = tx_conf->tx_deferred_start;
1900 #ifdef RTE_LIBRTE_XEN_DOM0
1901 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
1903 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
1905 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
1907 /* Allocate software ring */
1909 rte_zmalloc_socket("i40e tx sw ring",
1910 sizeof(struct i40e_tx_entry) * nb_desc,
1913 if (!txq->sw_ring) {
1914 i40e_dev_tx_queue_release(txq);
1915 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
1919 i40e_reset_tx_queue(txq);
1921 dev->data->tx_queues[queue_idx] = txq;
1923 /* Use a simple TX queue without offloads or multi segs if possible */
1924 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
1925 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
1926 PMD_INIT_LOG(INFO, "Using simple tx path");
1927 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
1929 PMD_INIT_LOG(INFO, "Using full-featured tx path");
1930 dev->tx_pkt_burst = i40e_xmit_pkts;
1937 i40e_dev_tx_queue_release(void *txq)
1939 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
1942 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
1946 i40e_tx_queue_release_mbufs(q);
1947 rte_free(q->sw_ring);
1951 static const struct rte_memzone *
1952 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
1953 const char *ring_name,
1958 char z_name[RTE_MEMZONE_NAMESIZE];
1959 const struct rte_memzone *mz;
1961 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
1962 dev->driver->pci_drv.name, ring_name,
1963 dev->data->port_id, queue_id);
1964 mz = rte_memzone_lookup(z_name);
1968 #ifdef RTE_LIBRTE_XEN_DOM0
1969 return rte_memzone_reserve_bounded(z_name, ring_size,
1970 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
1972 return rte_memzone_reserve_aligned(z_name, ring_size,
1973 socket_id, 0, I40E_ALIGN);
1978 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
1982 if (!rxq || !rxq->sw_ring) {
1983 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
1987 for (i = 0; i < rxq->nb_rx_desc; i++) {
1988 if (rxq->sw_ring[i].mbuf) {
1989 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
1990 rxq->sw_ring[i].mbuf = NULL;
1993 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1994 if (rxq->rx_nb_avail == 0)
1996 for (i = 0; i < rxq->rx_nb_avail; i++) {
1997 struct rte_mbuf *mbuf;
1999 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2000 rte_pktmbuf_free_seg(mbuf);
2002 rxq->rx_nb_avail = 0;
2003 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2007 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2012 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2013 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2014 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2016 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2017 len = rxq->nb_rx_desc;
2019 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2020 ((volatile char *)rxq->rx_ring)[i] = 0;
2022 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2023 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2024 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2025 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2027 rxq->rx_nb_avail = 0;
2028 rxq->rx_next_avail = 0;
2029 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2030 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2032 rxq->nb_rx_hold = 0;
2033 rxq->pkt_first_seg = NULL;
2034 rxq->pkt_last_seg = NULL;
2038 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2042 if (!txq || !txq->sw_ring) {
2043 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2047 for (i = 0; i < txq->nb_tx_desc; i++) {
2048 if (txq->sw_ring[i].mbuf) {
2049 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2050 txq->sw_ring[i].mbuf = NULL;
2056 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2058 struct i40e_tx_entry *txe;
2059 uint16_t i, prev, size;
2062 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2067 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2068 for (i = 0; i < size; i++)
2069 ((volatile char *)txq->tx_ring)[i] = 0;
2071 prev = (uint16_t)(txq->nb_tx_desc - 1);
2072 for (i = 0; i < txq->nb_tx_desc; i++) {
2073 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2075 txd[i].cmd_type_offset_bsz =
2076 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2079 txe[prev].next_id = i;
2083 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2084 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2087 txq->nb_tx_used = 0;
2089 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2090 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2093 /* Init the TX queue in hardware */
2095 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2097 enum i40e_status_code err = I40E_SUCCESS;
2098 struct i40e_vsi *vsi = txq->vsi;
2099 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2100 uint16_t pf_q = txq->reg_idx;
2101 struct i40e_hmc_obj_txq tx_ctx;
2104 /* clear the context structure first */
2105 memset(&tx_ctx, 0, sizeof(tx_ctx));
2106 tx_ctx.new_context = 1;
2107 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2108 tx_ctx.qlen = txq->nb_tx_desc;
2109 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2111 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2112 if (err != I40E_SUCCESS) {
2113 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2117 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2118 if (err != I40E_SUCCESS) {
2119 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2123 /* Now associate this queue with this PCI function */
2124 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2125 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2126 I40E_QTX_CTL_PF_INDX_MASK);
2127 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2128 I40E_WRITE_FLUSH(hw);
2130 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2136 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2138 struct i40e_rx_entry *rxe = rxq->sw_ring;
2142 for (i = 0; i < rxq->nb_rx_desc; i++) {
2143 volatile union i40e_rx_desc *rxd;
2144 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2146 if (unlikely(!mbuf)) {
2147 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2151 rte_mbuf_refcnt_set(mbuf, 1);
2153 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2155 mbuf->port = rxq->port_id;
2158 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2160 rxd = &rxq->rx_ring[i];
2161 rxd->read.pkt_addr = dma_addr;
2162 rxd->read.hdr_addr = dma_addr;
2163 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2164 rxd->read.rsvd1 = 0;
2165 rxd->read.rsvd2 = 0;
2166 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2175 * Calculate the buffer length, and check the jumbo frame
2176 * and maximum packet length.
2179 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2181 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2182 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2183 struct rte_eth_dev_data *data = pf->dev_data;
2184 struct rte_pktmbuf_pool_private *mbp_priv =
2185 rte_mempool_get_priv(rxq->mp);
2186 uint16_t buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2187 RTE_PKTMBUF_HEADROOM);
2190 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2191 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2192 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2193 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2194 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2195 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2196 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2197 rxq->hs_mode = i40e_header_split_enabled;
2199 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2201 rxq->rx_hdr_len = 0;
2202 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2203 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2204 rxq->hs_mode = i40e_header_split_none;
2208 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2209 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2210 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2211 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2212 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2213 PMD_DRV_LOG(ERR, "maximum packet length must "
2214 "be larger than %u and smaller than %u,"
2215 "as jumbo frame is enabled",
2216 (uint32_t)ETHER_MAX_LEN,
2217 (uint32_t)I40E_FRAME_SIZE_MAX);
2218 return I40E_ERR_CONFIG;
2221 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2222 rxq->max_pkt_len > ETHER_MAX_LEN) {
2223 PMD_DRV_LOG(ERR, "maximum packet length must be "
2224 "larger than %u and smaller than %u, "
2225 "as jumbo frame is disabled",
2226 (uint32_t)ETHER_MIN_LEN,
2227 (uint32_t)ETHER_MAX_LEN);
2228 return I40E_ERR_CONFIG;
2235 /* Init the RX queue in hardware */
2237 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2239 int err = I40E_SUCCESS;
2240 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2241 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2242 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2243 uint16_t pf_q = rxq->reg_idx;
2245 struct i40e_hmc_obj_rxq rx_ctx;
2246 struct rte_pktmbuf_pool_private *mbp_priv;
2248 err = i40e_rx_queue_config(rxq);
2250 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2254 /* Clear the context structure first */
2255 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2256 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2257 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2259 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2260 rx_ctx.qlen = rxq->nb_rx_desc;
2261 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2264 rx_ctx.dtype = rxq->hs_mode;
2266 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2268 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2269 rx_ctx.rxmax = rxq->max_pkt_len;
2270 rx_ctx.tphrdesc_ena = 1;
2271 rx_ctx.tphwdesc_ena = 1;
2272 rx_ctx.tphdata_ena = 1;
2273 rx_ctx.tphhead_ena = 1;
2274 rx_ctx.lrxqthresh = 2;
2275 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2280 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2281 if (err != I40E_SUCCESS) {
2282 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2285 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2286 if (err != I40E_SUCCESS) {
2287 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2291 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2293 mbp_priv = rte_mempool_get_priv(rxq->mp);
2294 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2295 RTE_PKTMBUF_HEADROOM);
2297 /* Check if scattered RX needs to be used. */
2298 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2299 dev_data->scattered_rx = 1;
2300 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2303 /* Init the RX tail regieter. */
2304 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2310 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2314 PMD_INIT_FUNC_TRACE();
2316 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2317 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2318 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2321 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2322 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2323 i40e_reset_rx_queue(dev->data->rx_queues[i]);