4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
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19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
54 #include "i40e_logs.h"
55 #include "i40e/i40e_prototype.h"
56 #include "i40e/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
60 #define I40E_MIN_RING_DESC 64
61 #define I40E_MAX_RING_DESC 4096
62 #define I40E_ALIGN 128
63 #define DEFAULT_TX_RS_THRESH 32
64 #define DEFAULT_TX_FREE_THRESH 32
65 #define I40E_MAX_PKT_TYPE 256
67 #define I40E_VLAN_TAG_SIZE 4
68 #define I40E_TX_MAX_BURST 32
70 #define I40E_DMA_MEM_ALIGN 4096
72 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
73 ETH_TXQ_FLAGS_NOOFFLOADS)
75 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
77 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
80 PKT_TX_OUTER_IP_CKSUM)
82 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
83 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
85 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
86 ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
88 static const struct rte_memzone *
89 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
90 const char *ring_name,
94 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
95 struct rte_mbuf **tx_pkts,
98 /* Translate the rx descriptor status to pkt flags */
99 static inline uint64_t
100 i40e_rxd_status_to_pkt_flags(uint64_t qword)
104 /* Check if VLAN packet */
105 flags = qword & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
108 /* Check if RSS_HASH */
109 flags |= (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
110 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
111 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
113 /* Check if FDIR Match */
114 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
120 static inline uint64_t
121 i40e_rxd_error_to_pkt_flags(uint64_t qword)
124 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
126 #define I40E_RX_ERR_BITS 0x3f
127 if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
129 /* If RXE bit set, all other status bits are meaningless */
130 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
131 flags |= PKT_RX_MAC_ERR;
135 /* If RECIPE bit set, all other status indications should be ignored */
136 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
137 flags |= PKT_RX_RECIP_ERR;
140 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
141 flags |= PKT_RX_HBUF_OVERFLOW;
142 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
143 flags |= PKT_RX_IP_CKSUM_BAD;
144 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
145 flags |= PKT_RX_L4_CKSUM_BAD;
146 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
147 flags |= PKT_RX_EIP_CKSUM_BAD;
148 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
149 flags |= PKT_RX_OVERSIZE;
154 /* Translate pkt types to pkt flags */
155 static inline uint64_t
156 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
158 uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
159 I40E_RXD_QW1_PTYPE_SHIFT);
160 static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
183 PKT_RX_IPV4_HDR, /* PTYPE 22 */
184 PKT_RX_IPV4_HDR, /* PTYPE 23 */
185 PKT_RX_IPV4_HDR, /* PTYPE 24 */
187 PKT_RX_IPV4_HDR, /* PTYPE 26 */
188 PKT_RX_IPV4_HDR, /* PTYPE 27 */
189 PKT_RX_IPV4_HDR, /* PTYPE 28 */
190 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
191 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
192 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
194 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
195 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
196 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
197 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
198 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
199 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
201 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
202 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
203 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
204 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
205 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
206 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
207 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
209 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
210 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
211 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
212 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
213 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
214 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
216 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
217 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
218 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
219 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
220 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 59 */
221 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 60 */
222 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 61 */
224 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 63 */
225 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 64 */
226 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 65 */
227 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 66 */
228 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 67 */
229 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 68 */
231 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 70 */
232 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 71 */
233 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 72 */
234 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 73 */
235 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 74 */
236 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 75 */
237 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 76 */
239 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 78 */
240 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 79 */
241 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 80 */
242 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 81 */
243 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 82 */
244 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 83 */
246 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 85 */
247 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 86 */
248 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
249 PKT_RX_IPV6_HDR, /* PTYPE 88 */
250 PKT_RX_IPV6_HDR, /* PTYPE 89 */
251 PKT_RX_IPV6_HDR, /* PTYPE 90 */
253 PKT_RX_IPV6_HDR, /* PTYPE 92 */
254 PKT_RX_IPV6_HDR, /* PTYPE 93 */
255 PKT_RX_IPV6_HDR, /* PTYPE 94 */
256 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
257 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
258 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
260 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
261 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
262 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
263 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
264 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
265 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
267 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
268 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
269 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
270 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
271 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
272 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
273 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
275 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
276 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
277 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
278 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
279 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
280 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
282 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
283 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
284 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
285 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
286 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 125 */
287 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 126 */
288 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 127 */
290 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 129 */
291 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 130 */
292 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 131 */
293 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 132 */
294 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 133 */
295 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 134 */
297 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 136 */
298 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 137 */
299 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 138 */
300 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 139 */
301 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 140 */
302 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 141 */
303 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 142 */
305 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 144 */
306 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 145 */
307 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 146 */
308 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 147 */
309 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 148 */
310 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 149 */
312 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 151 */
313 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 152 */
314 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
419 return ip_ptype_map[ptype];
422 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
423 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
424 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
425 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
426 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
428 static inline uint64_t
429 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
432 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
433 uint16_t flexbh, flexbl;
435 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
436 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
437 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
438 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
439 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
440 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
443 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
445 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
446 flags |= PKT_RX_FDIR_ID;
447 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
449 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
450 flags |= PKT_RX_FDIR_FLX;
452 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
454 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
455 flags |= PKT_RX_FDIR_FLX;
459 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
460 flags |= PKT_RX_FDIR_ID;
465 i40e_txd_enable_checksum(uint64_t ol_flags,
468 union i40e_tx_offload tx_offload,
469 uint32_t *cd_tunneling)
471 /* UDP tunneling packet TX checksum offload */
472 if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
474 *td_offset |= (tx_offload.outer_l2_len >> 1)
475 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
477 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
478 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
479 else if (ol_flags & PKT_TX_OUTER_IPV4)
480 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
481 else if (ol_flags & PKT_TX_OUTER_IPV6)
482 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
484 /* Now set the ctx descriptor fields */
485 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
486 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
487 (tx_offload.l2_len >> 1) <<
488 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
491 *td_offset |= (tx_offload.l2_len >> 1)
492 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
494 /* Enable L3 checksum offloads */
495 if (ol_flags & PKT_TX_IP_CKSUM) {
496 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
497 *td_offset |= (tx_offload.l3_len >> 2)
498 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
499 } else if (ol_flags & PKT_TX_IPV4) {
500 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
501 *td_offset |= (tx_offload.l3_len >> 2)
502 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
503 } else if (ol_flags & PKT_TX_IPV6) {
504 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
505 *td_offset |= (tx_offload.l3_len >> 2)
506 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
509 if (ol_flags & PKT_TX_TCP_SEG) {
510 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
511 *td_offset |= (tx_offload.l4_len >> 2)
512 << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
516 /* Enable L4 checksum offloads */
517 switch (ol_flags & PKT_TX_L4_MASK) {
518 case PKT_TX_TCP_CKSUM:
519 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
520 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
521 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
523 case PKT_TX_SCTP_CKSUM:
524 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
525 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
526 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
528 case PKT_TX_UDP_CKSUM:
529 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
530 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
531 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
538 static inline struct rte_mbuf *
539 rte_rxmbuf_alloc(struct rte_mempool *mp)
543 m = __rte_mbuf_raw_alloc(mp);
544 __rte_mbuf_sanity_check_raw(m, 0);
549 /* Construct the tx flags */
550 static inline uint64_t
551 i40e_build_ctob(uint32_t td_cmd,
556 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
557 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
558 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
559 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
560 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
564 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
566 struct i40e_tx_entry *sw_ring = txq->sw_ring;
567 volatile struct i40e_tx_desc *txd = txq->tx_ring;
568 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
569 uint16_t nb_tx_desc = txq->nb_tx_desc;
570 uint16_t desc_to_clean_to;
571 uint16_t nb_tx_to_clean;
573 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
574 if (desc_to_clean_to >= nb_tx_desc)
575 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
577 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
578 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
579 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) {
580 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
581 "(port=%d queue=%d)", desc_to_clean_to,
582 txq->port_id, txq->queue_id);
586 if (last_desc_cleaned > desc_to_clean_to)
587 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
590 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
593 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
595 txq->last_desc_cleaned = desc_to_clean_to;
596 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
602 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
603 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
605 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
610 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
611 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
612 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
613 "rxq->rx_free_thresh=%d, "
614 "RTE_PMD_I40E_RX_MAX_BURST=%d",
615 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
617 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
618 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
619 "rxq->rx_free_thresh=%d, "
620 "rxq->nb_rx_desc=%d",
621 rxq->rx_free_thresh, rxq->nb_rx_desc);
623 } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
624 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
625 "rxq->nb_rx_desc=%d, "
626 "rxq->rx_free_thresh=%d",
627 rxq->nb_rx_desc, rxq->rx_free_thresh);
629 } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
630 RTE_PMD_I40E_RX_MAX_BURST))) {
631 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
632 "rxq->nb_rx_desc=%d, "
633 "I40E_MAX_RING_DESC=%d, "
634 "RTE_PMD_I40E_RX_MAX_BURST=%d",
635 rxq->nb_rx_desc, I40E_MAX_RING_DESC,
636 RTE_PMD_I40E_RX_MAX_BURST);
646 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
647 #define I40E_LOOK_AHEAD 8
648 #if (I40E_LOOK_AHEAD != 8)
649 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
652 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
654 volatile union i40e_rx_desc *rxdp;
655 struct i40e_rx_entry *rxep;
660 int32_t s[I40E_LOOK_AHEAD], nb_dd;
661 int32_t i, j, nb_rx = 0;
664 rxdp = &rxq->rx_ring[rxq->rx_tail];
665 rxep = &rxq->sw_ring[rxq->rx_tail];
667 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
668 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
669 I40E_RXD_QW1_STATUS_SHIFT;
671 /* Make sure there is at least 1 packet to receive */
672 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
676 * Scan LOOK_AHEAD descriptors at a time to determine which
677 * descriptors reference packets that are ready to be received.
679 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
680 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
681 /* Read desc statuses backwards to avoid race condition */
682 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
683 qword1 = rte_le_to_cpu_64(\
684 rxdp[j].wb.qword1.status_error_len);
685 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
686 I40E_RXD_QW1_STATUS_SHIFT;
689 /* Compute how many status bits were set */
690 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
691 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
695 /* Translate descriptor info to mbuf parameters */
696 for (j = 0; j < nb_dd; j++) {
698 qword1 = rte_le_to_cpu_64(\
699 rxdp[j].wb.qword1.status_error_len);
700 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
701 I40E_RXD_QW1_STATUS_SHIFT;
702 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
703 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
704 mb->data_len = pkt_len;
705 mb->pkt_len = pkt_len;
706 mb->vlan_tci = rx_status &
707 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
709 rxdp[j].wb.qword0.lo_dword.l2tag1) : 0;
710 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
711 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
712 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
714 mb->packet_type = (uint16_t)((qword1 &
715 I40E_RXD_QW1_PTYPE_MASK) >>
716 I40E_RXD_QW1_PTYPE_SHIFT);
717 if (pkt_flags & PKT_RX_RSS_HASH)
718 mb->hash.rss = rte_le_to_cpu_32(\
719 rxdp[j].wb.qword0.hi_dword.rss);
720 if (pkt_flags & PKT_RX_FDIR)
721 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
723 mb->ol_flags = pkt_flags;
726 for (j = 0; j < I40E_LOOK_AHEAD; j++)
727 rxq->rx_stage[i + j] = rxep[j].mbuf;
729 if (nb_dd != I40E_LOOK_AHEAD)
733 /* Clear software ring entries */
734 for (i = 0; i < nb_rx; i++)
735 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
740 static inline uint16_t
741 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
742 struct rte_mbuf **rx_pkts,
746 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
748 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
750 for (i = 0; i < nb_pkts; i++)
751 rx_pkts[i] = stage[i];
753 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
754 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
760 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
762 volatile union i40e_rx_desc *rxdp;
763 struct i40e_rx_entry *rxep;
765 uint16_t alloc_idx, i;
769 /* Allocate buffers in bulk */
770 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
771 (rxq->rx_free_thresh - 1));
772 rxep = &(rxq->sw_ring[alloc_idx]);
773 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
774 rxq->rx_free_thresh);
775 if (unlikely(diag != 0)) {
776 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
780 rxdp = &rxq->rx_ring[alloc_idx];
781 for (i = 0; i < rxq->rx_free_thresh; i++) {
783 rte_mbuf_refcnt_set(mb, 1);
785 mb->data_off = RTE_PKTMBUF_HEADROOM;
787 mb->port = rxq->port_id;
788 dma_addr = rte_cpu_to_le_64(\
789 RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
790 rxdp[i].read.hdr_addr = dma_addr;
791 rxdp[i].read.pkt_addr = dma_addr;
794 /* Update rx tail regsiter */
796 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
798 rxq->rx_free_trigger =
799 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
800 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
801 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
806 static inline uint16_t
807 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
809 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
815 if (rxq->rx_nb_avail)
816 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
818 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
819 rxq->rx_next_avail = 0;
820 rxq->rx_nb_avail = nb_rx;
821 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
823 if (rxq->rx_tail > rxq->rx_free_trigger) {
824 if (i40e_rx_alloc_bufs(rxq) != 0) {
827 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
828 "port_id=%u, queue_id=%u",
829 rxq->port_id, rxq->queue_id);
830 rxq->rx_nb_avail = 0;
831 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
832 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
833 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
839 if (rxq->rx_tail >= rxq->nb_rx_desc)
842 if (rxq->rx_nb_avail)
843 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
849 i40e_recv_pkts_bulk_alloc(void *rx_queue,
850 struct rte_mbuf **rx_pkts,
853 uint16_t nb_rx = 0, n, count;
855 if (unlikely(nb_pkts == 0))
858 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
859 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
862 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
863 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
864 nb_rx = (uint16_t)(nb_rx + count);
865 nb_pkts = (uint16_t)(nb_pkts - count);
872 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
875 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
877 struct i40e_rx_queue *rxq;
878 volatile union i40e_rx_desc *rx_ring;
879 volatile union i40e_rx_desc *rxdp;
880 union i40e_rx_desc rxd;
881 struct i40e_rx_entry *sw_ring;
882 struct i40e_rx_entry *rxe;
883 struct rte_mbuf *rxm;
884 struct rte_mbuf *nmb;
888 uint16_t rx_packet_len;
889 uint16_t rx_id, nb_hold;
896 rx_id = rxq->rx_tail;
897 rx_ring = rxq->rx_ring;
898 sw_ring = rxq->sw_ring;
900 while (nb_rx < nb_pkts) {
901 rxdp = &rx_ring[rx_id];
902 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
903 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
904 >> I40E_RXD_QW1_STATUS_SHIFT;
905 /* Check the DD bit first */
906 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
909 nmb = rte_rxmbuf_alloc(rxq->mp);
915 rxe = &sw_ring[rx_id];
917 if (unlikely(rx_id == rxq->nb_rx_desc))
920 /* Prefetch next mbuf */
921 rte_prefetch0(sw_ring[rx_id].mbuf);
924 * When next RX descriptor is on a cache line boundary,
925 * prefetch the next 4 RX descriptors and next 8 pointers
928 if ((rx_id & 0x3) == 0) {
929 rte_prefetch0(&rx_ring[rx_id]);
930 rte_prefetch0(&sw_ring[rx_id]);
935 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
936 rxdp->read.hdr_addr = dma_addr;
937 rxdp->read.pkt_addr = dma_addr;
939 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
940 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
942 rxm->data_off = RTE_PKTMBUF_HEADROOM;
943 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
946 rxm->pkt_len = rx_packet_len;
947 rxm->data_len = rx_packet_len;
948 rxm->port = rxq->port_id;
950 rxm->vlan_tci = rx_status &
951 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
952 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
953 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
954 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
955 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
956 rxm->packet_type = (uint16_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >>
957 I40E_RXD_QW1_PTYPE_SHIFT);
958 if (pkt_flags & PKT_RX_RSS_HASH)
960 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
961 if (pkt_flags & PKT_RX_FDIR)
962 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
964 rxm->ol_flags = pkt_flags;
966 rx_pkts[nb_rx++] = rxm;
968 rxq->rx_tail = rx_id;
971 * If the number of free RX descriptors is greater than the RX free
972 * threshold of the queue, advance the receive tail register of queue.
973 * Update that register with the value of the last processed RX
974 * descriptor minus 1.
976 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
977 if (nb_hold > rxq->rx_free_thresh) {
978 rx_id = (uint16_t) ((rx_id == 0) ?
979 (rxq->nb_rx_desc - 1) : (rx_id - 1));
980 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
983 rxq->nb_rx_hold = nb_hold;
989 i40e_recv_scattered_pkts(void *rx_queue,
990 struct rte_mbuf **rx_pkts,
993 struct i40e_rx_queue *rxq = rx_queue;
994 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
995 volatile union i40e_rx_desc *rxdp;
996 union i40e_rx_desc rxd;
997 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
998 struct i40e_rx_entry *rxe;
999 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1000 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1001 struct rte_mbuf *nmb, *rxm;
1002 uint16_t rx_id = rxq->rx_tail;
1003 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1009 while (nb_rx < nb_pkts) {
1010 rxdp = &rx_ring[rx_id];
1011 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1012 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1013 I40E_RXD_QW1_STATUS_SHIFT;
1014 /* Check the DD bit */
1015 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1018 nmb = rte_rxmbuf_alloc(rxq->mp);
1023 rxe = &sw_ring[rx_id];
1025 if (rx_id == rxq->nb_rx_desc)
1028 /* Prefetch next mbuf */
1029 rte_prefetch0(sw_ring[rx_id].mbuf);
1032 * When next RX descriptor is on a cache line boundary,
1033 * prefetch the next 4 RX descriptors and next 8 pointers
1036 if ((rx_id & 0x3) == 0) {
1037 rte_prefetch0(&rx_ring[rx_id]);
1038 rte_prefetch0(&sw_ring[rx_id]);
1044 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1046 /* Set data buffer address and data length of the mbuf */
1047 rxdp->read.hdr_addr = dma_addr;
1048 rxdp->read.pkt_addr = dma_addr;
1049 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1050 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1051 rxm->data_len = rx_packet_len;
1052 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1055 * If this is the first buffer of the received packet, set the
1056 * pointer to the first mbuf of the packet and initialize its
1057 * context. Otherwise, update the total length and the number
1058 * of segments of the current scattered packet, and update the
1059 * pointer to the last mbuf of the current packet.
1063 first_seg->nb_segs = 1;
1064 first_seg->pkt_len = rx_packet_len;
1066 first_seg->pkt_len =
1067 (uint16_t)(first_seg->pkt_len +
1069 first_seg->nb_segs++;
1070 last_seg->next = rxm;
1074 * If this is not the last buffer of the received packet,
1075 * update the pointer to the last mbuf of the current scattered
1076 * packet and continue to parse the RX ring.
1078 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1084 * This is the last buffer of the received packet. If the CRC
1085 * is not stripped by the hardware:
1086 * - Subtract the CRC length from the total packet length.
1087 * - If the last buffer only contains the whole CRC or a part
1088 * of it, free the mbuf associated to the last buffer. If part
1089 * of the CRC is also contained in the previous mbuf, subtract
1090 * the length of that CRC part from the data length of the
1094 if (unlikely(rxq->crc_len > 0)) {
1095 first_seg->pkt_len -= ETHER_CRC_LEN;
1096 if (rx_packet_len <= ETHER_CRC_LEN) {
1097 rte_pktmbuf_free_seg(rxm);
1098 first_seg->nb_segs--;
1099 last_seg->data_len =
1100 (uint16_t)(last_seg->data_len -
1101 (ETHER_CRC_LEN - rx_packet_len));
1102 last_seg->next = NULL;
1104 rxm->data_len = (uint16_t)(rx_packet_len -
1108 first_seg->port = rxq->port_id;
1109 first_seg->vlan_tci = (rx_status &
1110 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1111 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
1112 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1113 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1114 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1115 first_seg->packet_type = (uint16_t)((qword1 &
1116 I40E_RXD_QW1_PTYPE_MASK) >>
1117 I40E_RXD_QW1_PTYPE_SHIFT);
1118 if (pkt_flags & PKT_RX_RSS_HASH)
1120 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1121 if (pkt_flags & PKT_RX_FDIR)
1122 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1124 first_seg->ol_flags = pkt_flags;
1126 /* Prefetch data of first segment, if configured to do so. */
1127 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1128 first_seg->data_off));
1129 rx_pkts[nb_rx++] = first_seg;
1133 /* Record index of the next RX descriptor to probe. */
1134 rxq->rx_tail = rx_id;
1135 rxq->pkt_first_seg = first_seg;
1136 rxq->pkt_last_seg = last_seg;
1139 * If the number of free RX descriptors is greater than the RX free
1140 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1141 * register. Update the RDT with the value of the last processed RX
1142 * descriptor minus 1, to guarantee that the RDT register is never
1143 * equal to the RDH register, which creates a "full" ring situtation
1144 * from the hardware point of view.
1146 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1147 if (nb_hold > rxq->rx_free_thresh) {
1148 rx_id = (uint16_t)(rx_id == 0 ?
1149 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1150 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1153 rxq->nb_rx_hold = nb_hold;
1158 /* Check if the context descriptor is needed for TX offloading */
1159 static inline uint16_t
1160 i40e_calc_context_desc(uint64_t flags)
1162 uint64_t mask = 0ULL;
1164 mask |= (PKT_TX_OUTER_IP_CKSUM | PKT_TX_TCP_SEG);
1166 #ifdef RTE_LIBRTE_IEEE1588
1167 mask |= PKT_TX_IEEE1588_TMST;
1175 /* set i40e TSO context descriptor */
1176 static inline uint64_t
1177 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1179 uint64_t ctx_desc = 0;
1180 uint32_t cd_cmd, hdr_len, cd_tso_len;
1182 if (!tx_offload.l4_len) {
1183 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1188 * in case of tunneling packet, the outer_l2_len and
1189 * outer_l3_len must be 0.
1191 hdr_len = tx_offload.outer_l2_len +
1192 tx_offload.outer_l3_len +
1197 cd_cmd = I40E_TX_CTX_DESC_TSO;
1198 cd_tso_len = mbuf->pkt_len - hdr_len;
1199 ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1200 ((uint64_t)cd_tso_len <<
1201 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1202 ((uint64_t)mbuf->tso_segsz <<
1203 I40E_TXD_CTX_QW1_MSS_SHIFT);
1209 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1211 struct i40e_tx_queue *txq;
1212 struct i40e_tx_entry *sw_ring;
1213 struct i40e_tx_entry *txe, *txn;
1214 volatile struct i40e_tx_desc *txd;
1215 volatile struct i40e_tx_desc *txr;
1216 struct rte_mbuf *tx_pkt;
1217 struct rte_mbuf *m_seg;
1218 uint32_t cd_tunneling_params;
1230 uint64_t buf_dma_addr;
1231 union i40e_tx_offload tx_offload = { .data = 0 };
1234 sw_ring = txq->sw_ring;
1236 tx_id = txq->tx_tail;
1237 txe = &sw_ring[tx_id];
1239 /* Check if the descriptor ring needs to be cleaned. */
1240 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh)
1241 i40e_xmit_cleanup(txq);
1243 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1249 tx_pkt = *tx_pkts++;
1250 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1252 ol_flags = tx_pkt->ol_flags;
1253 tx_offload.l2_len = tx_pkt->l2_len;
1254 tx_offload.l3_len = tx_pkt->l3_len;
1255 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1256 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1257 tx_offload.l4_len = tx_pkt->l4_len;
1258 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1260 /* Calculate the number of context descriptors needed. */
1261 nb_ctx = i40e_calc_context_desc(ol_flags);
1264 * The number of descriptors that must be allocated for
1265 * a packet equals to the number of the segments of that
1266 * packet plus 1 context descriptor if needed.
1268 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1269 tx_last = (uint16_t)(tx_id + nb_used - 1);
1272 if (tx_last >= txq->nb_tx_desc)
1273 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1275 if (nb_used > txq->nb_tx_free) {
1276 if (i40e_xmit_cleanup(txq) != 0) {
1281 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1282 while (nb_used > txq->nb_tx_free) {
1283 if (i40e_xmit_cleanup(txq) != 0) {
1292 /* Descriptor based VLAN insertion */
1293 if (ol_flags & PKT_TX_VLAN_PKT) {
1294 tx_flags |= tx_pkt->vlan_tci <<
1295 I40E_TX_FLAG_L2TAG1_SHIFT;
1296 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1297 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1298 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1299 I40E_TX_FLAG_L2TAG1_SHIFT;
1302 /* Always enable CRC offload insertion */
1303 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1305 /* Enable checksum offloading */
1306 cd_tunneling_params = 0;
1307 if (unlikely(ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)) {
1308 i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1309 tx_offload, &cd_tunneling_params);
1312 if (unlikely(nb_ctx)) {
1313 /* Setup TX context descriptor if required */
1314 volatile struct i40e_tx_context_desc *ctx_txd =
1315 (volatile struct i40e_tx_context_desc *)\
1317 uint16_t cd_l2tag2 = 0;
1318 uint64_t cd_type_cmd_tso_mss =
1319 I40E_TX_DESC_DTYPE_CONTEXT;
1321 txn = &sw_ring[txe->next_id];
1322 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1323 if (txe->mbuf != NULL) {
1324 rte_pktmbuf_free_seg(txe->mbuf);
1328 /* TSO enabled means no timestamp */
1329 if (ol_flags & PKT_TX_TCP_SEG)
1330 cd_type_cmd_tso_mss |=
1331 i40e_set_tso_ctx(tx_pkt, tx_offload);
1333 #ifdef RTE_LIBRTE_IEEE1588
1334 if (ol_flags & PKT_TX_IEEE1588_TMST)
1335 cd_type_cmd_tso_mss |=
1336 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1337 I40E_TXD_CTX_QW1_CMD_SHIFT);
1341 ctx_txd->tunneling_params =
1342 rte_cpu_to_le_32(cd_tunneling_params);
1343 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1344 ctx_txd->type_cmd_tso_mss =
1345 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1347 PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1348 "tunneling_params: %#x;\n"
1351 "type_cmd_tso_mss: %#lx;\n",
1353 ctx_txd->tunneling_params,
1356 ctx_txd->type_cmd_tso_mss);
1358 txe->last_id = tx_last;
1359 tx_id = txe->next_id;
1366 txn = &sw_ring[txe->next_id];
1369 rte_pktmbuf_free_seg(txe->mbuf);
1372 /* Setup TX Descriptor */
1373 slen = m_seg->data_len;
1374 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1376 PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1377 "buf_dma_addr: %#"PRIx64";\n"
1382 tx_pkt, tx_id, buf_dma_addr,
1383 td_cmd, td_offset, slen, td_tag);
1385 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1386 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1387 td_offset, slen, td_tag);
1388 txe->last_id = tx_last;
1389 tx_id = txe->next_id;
1391 m_seg = m_seg->next;
1392 } while (m_seg != NULL);
1394 /* The last packet data descriptor needs End Of Packet (EOP) */
1395 td_cmd |= I40E_TX_DESC_CMD_EOP;
1396 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1397 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1399 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1400 PMD_TX_FREE_LOG(DEBUG,
1401 "Setting RS bit on TXD id="
1402 "%4u (port=%d queue=%d)",
1403 tx_last, txq->port_id, txq->queue_id);
1405 td_cmd |= I40E_TX_DESC_CMD_RS;
1407 /* Update txq RS bit counters */
1408 txq->nb_tx_used = 0;
1411 txd->cmd_type_offset_bsz |=
1412 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1413 I40E_TXD_QW1_CMD_SHIFT);
1419 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1420 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1421 (unsigned) tx_id, (unsigned) nb_tx);
1423 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1424 txq->tx_tail = tx_id;
1429 static inline int __attribute__((always_inline))
1430 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1432 struct i40e_tx_entry *txep;
1435 if (!(txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1436 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)))
1439 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1441 for (i = 0; i < txq->tx_rs_thresh; i++)
1442 rte_prefetch0((txep + i)->mbuf);
1444 if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1445 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1446 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1450 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1451 rte_pktmbuf_free_seg(txep->mbuf);
1456 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1457 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1458 if (txq->tx_next_dd >= txq->nb_tx_desc)
1459 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1461 return txq->tx_rs_thresh;
1464 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1465 I40E_TX_DESC_CMD_EOP)
1467 /* Populate 4 descriptors with data from 4 mbufs */
1469 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1474 for (i = 0; i < 4; i++, txdp++, pkts++) {
1475 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1476 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1477 txdp->cmd_type_offset_bsz =
1478 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1479 (*pkts)->data_len, 0);
1483 /* Populate 1 descriptor with data from 1 mbuf */
1485 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1489 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1490 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1491 txdp->cmd_type_offset_bsz =
1492 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1493 (*pkts)->data_len, 0);
1496 /* Fill hardware descriptor ring with mbuf data */
1498 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1499 struct rte_mbuf **pkts,
1502 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1503 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1504 const int N_PER_LOOP = 4;
1505 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1506 int mainpart, leftover;
1509 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1510 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1511 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1512 for (j = 0; j < N_PER_LOOP; ++j) {
1513 (txep + i + j)->mbuf = *(pkts + i + j);
1515 tx4(txdp + i, pkts + i);
1517 if (unlikely(leftover > 0)) {
1518 for (i = 0; i < leftover; ++i) {
1519 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1520 tx1(txdp + mainpart + i, pkts + mainpart + i);
1525 static inline uint16_t
1526 tx_xmit_pkts(struct i40e_tx_queue *txq,
1527 struct rte_mbuf **tx_pkts,
1530 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1534 * Begin scanning the H/W ring for done descriptors when the number
1535 * of available descriptors drops below tx_free_thresh. For each done
1536 * descriptor, free the associated buffer.
1538 if (txq->nb_tx_free < txq->tx_free_thresh)
1539 i40e_tx_free_bufs(txq);
1541 /* Use available descriptor only */
1542 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1543 if (unlikely(!nb_pkts))
1546 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1547 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1548 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1549 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1550 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1551 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1552 I40E_TXD_QW1_CMD_SHIFT);
1553 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1557 /* Fill hardware descriptor ring with mbuf data */
1558 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1559 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1561 /* Determin if RS bit needs to be set */
1562 if (txq->tx_tail > txq->tx_next_rs) {
1563 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1564 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1565 I40E_TXD_QW1_CMD_SHIFT);
1567 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1568 if (txq->tx_next_rs >= txq->nb_tx_desc)
1569 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1572 if (txq->tx_tail >= txq->nb_tx_desc)
1575 /* Update the tx tail register */
1577 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1583 i40e_xmit_pkts_simple(void *tx_queue,
1584 struct rte_mbuf **tx_pkts,
1589 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1590 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1594 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1597 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1598 &tx_pkts[nb_tx], num);
1599 nb_tx = (uint16_t)(nb_tx + ret);
1600 nb_pkts = (uint16_t)(nb_pkts - ret);
1609 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1610 * application used, which assume having sequential ones. But from driver's
1611 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1612 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1613 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1614 * use queue_idx from 0 to 95 to access queues, while real queue would be
1615 * different. This function will do a queue mapping to find VSI the queue
1618 static struct i40e_vsi*
1619 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1621 /* the queue in MAIN VSI range */
1622 if (queue_idx < pf->main_vsi->nb_qps)
1623 return pf->main_vsi;
1625 queue_idx -= pf->main_vsi->nb_qps;
1627 /* queue_idx is greater than VMDQ VSIs range */
1628 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1629 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1633 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1637 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1639 /* the queue in MAIN VSI range */
1640 if (queue_idx < pf->main_vsi->nb_qps)
1643 /* It's VMDQ queues */
1644 queue_idx -= pf->main_vsi->nb_qps;
1646 if (pf->nb_cfg_vmdq_vsi)
1647 return queue_idx % pf->vmdq_nb_qps;
1649 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1650 return (uint16_t)(-1);
1655 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1657 struct i40e_rx_queue *rxq;
1659 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1661 PMD_INIT_FUNC_TRACE();
1663 if (rx_queue_id < dev->data->nb_rx_queues) {
1664 rxq = dev->data->rx_queues[rx_queue_id];
1666 err = i40e_alloc_rx_queue_mbufs(rxq);
1668 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1674 /* Init the RX tail regieter. */
1675 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1677 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1680 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1683 i40e_rx_queue_release_mbufs(rxq);
1684 i40e_reset_rx_queue(rxq);
1692 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1694 struct i40e_rx_queue *rxq;
1696 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1698 if (rx_queue_id < dev->data->nb_rx_queues) {
1699 rxq = dev->data->rx_queues[rx_queue_id];
1702 * rx_queue_id is queue id aplication refers to, while
1703 * rxq->reg_idx is the real queue index.
1705 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1708 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1712 i40e_rx_queue_release_mbufs(rxq);
1713 i40e_reset_rx_queue(rxq);
1720 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1723 struct i40e_tx_queue *txq;
1724 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1726 PMD_INIT_FUNC_TRACE();
1728 if (tx_queue_id < dev->data->nb_tx_queues) {
1729 txq = dev->data->tx_queues[tx_queue_id];
1732 * tx_queue_id is queue id aplication refers to, while
1733 * rxq->reg_idx is the real queue index.
1735 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1737 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1745 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1747 struct i40e_tx_queue *txq;
1749 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1751 if (tx_queue_id < dev->data->nb_tx_queues) {
1752 txq = dev->data->tx_queues[tx_queue_id];
1755 * tx_queue_id is queue id aplication refers to, while
1756 * txq->reg_idx is the real queue index.
1758 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1761 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1766 i40e_tx_queue_release_mbufs(txq);
1767 i40e_reset_tx_queue(txq);
1774 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1777 unsigned int socket_id,
1778 const struct rte_eth_rxconf *rx_conf,
1779 struct rte_mempool *mp)
1781 struct i40e_vsi *vsi;
1782 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1783 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1784 struct i40e_rx_queue *rxq;
1785 const struct rte_memzone *rz;
1788 int use_def_burst_func = 1;
1790 if (hw->mac.type == I40E_MAC_VF) {
1791 struct i40e_vf *vf =
1792 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1795 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1798 PMD_DRV_LOG(ERR, "VSI not available or queue "
1799 "index exceeds the maximum");
1800 return I40E_ERR_PARAM;
1802 if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1803 (nb_desc > I40E_MAX_RING_DESC) ||
1804 (nb_desc < I40E_MIN_RING_DESC)) {
1805 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1806 "invalid", nb_desc);
1807 return I40E_ERR_PARAM;
1810 /* Free memory if needed */
1811 if (dev->data->rx_queues[queue_idx]) {
1812 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1813 dev->data->rx_queues[queue_idx] = NULL;
1816 /* Allocate the rx queue data structure */
1817 rxq = rte_zmalloc_socket("i40e rx queue",
1818 sizeof(struct i40e_rx_queue),
1819 RTE_CACHE_LINE_SIZE,
1822 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1823 "rx queue data structure");
1827 rxq->nb_rx_desc = nb_desc;
1828 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1829 rxq->queue_id = queue_idx;
1830 if (hw->mac.type == I40E_MAC_VF)
1831 rxq->reg_idx = queue_idx;
1832 else /* PF device */
1833 rxq->reg_idx = vsi->base_queue +
1834 i40e_get_queue_offset_by_qindex(pf, queue_idx);
1836 rxq->port_id = dev->data->port_id;
1837 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1839 rxq->drop_en = rx_conf->rx_drop_en;
1841 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1843 /* Allocate the maximun number of RX ring hardware descriptor. */
1844 ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1845 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1846 rz = i40e_ring_dma_zone_reserve(dev,
1852 i40e_dev_rx_queue_release(rxq);
1853 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1857 /* Zero all the descriptors in the ring. */
1858 memset(rz->addr, 0, ring_size);
1860 #ifdef RTE_LIBRTE_XEN_DOM0
1861 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1863 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1866 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1868 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1869 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1874 /* Allocate the software ring. */
1876 rte_zmalloc_socket("i40e rx sw ring",
1877 sizeof(struct i40e_rx_entry) * len,
1878 RTE_CACHE_LINE_SIZE,
1880 if (!rxq->sw_ring) {
1881 i40e_dev_rx_queue_release(rxq);
1882 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1886 i40e_reset_rx_queue(rxq);
1888 dev->data->rx_queues[queue_idx] = rxq;
1890 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1892 if (!use_def_burst_func && !dev->data->scattered_rx) {
1893 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1894 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1895 "satisfied. Rx Burst Bulk Alloc function will be "
1896 "used on port=%d, queue=%d.",
1897 rxq->port_id, rxq->queue_id);
1898 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1899 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1901 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1902 "not satisfied, Scattered Rx is requested, "
1903 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1904 "not enabled on port=%d, queue=%d.",
1905 rxq->port_id, rxq->queue_id);
1912 i40e_dev_rx_queue_release(void *rxq)
1914 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1917 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1921 i40e_rx_queue_release_mbufs(q);
1922 rte_free(q->sw_ring);
1927 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1929 #define I40E_RXQ_SCAN_INTERVAL 4
1930 volatile union i40e_rx_desc *rxdp;
1931 struct i40e_rx_queue *rxq;
1934 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1935 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1939 rxq = dev->data->rx_queues[rx_queue_id];
1940 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1941 while ((desc < rxq->nb_rx_desc) &&
1942 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1943 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1944 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1946 * Check the DD bit of a rx descriptor of each 4 in a group,
1947 * to avoid checking too frequently and downgrading performance
1950 desc += I40E_RXQ_SCAN_INTERVAL;
1951 rxdp += I40E_RXQ_SCAN_INTERVAL;
1952 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1953 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1954 desc - rxq->nb_rx_desc]);
1961 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1963 volatile union i40e_rx_desc *rxdp;
1964 struct i40e_rx_queue *rxq = rx_queue;
1968 if (unlikely(offset >= rxq->nb_rx_desc)) {
1969 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1973 desc = rxq->rx_tail + offset;
1974 if (desc >= rxq->nb_rx_desc)
1975 desc -= rxq->nb_rx_desc;
1977 rxdp = &(rxq->rx_ring[desc]);
1979 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1980 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1981 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1987 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1990 unsigned int socket_id,
1991 const struct rte_eth_txconf *tx_conf)
1993 struct i40e_vsi *vsi;
1994 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1995 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1996 struct i40e_tx_queue *txq;
1997 const struct rte_memzone *tz;
1999 uint16_t tx_rs_thresh, tx_free_thresh;
2001 if (hw->mac.type == I40E_MAC_VF) {
2002 struct i40e_vf *vf =
2003 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2006 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2009 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2010 "exceeds the maximum", queue_idx);
2011 return I40E_ERR_PARAM;
2014 if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
2015 (nb_desc > I40E_MAX_RING_DESC) ||
2016 (nb_desc < I40E_MIN_RING_DESC)) {
2017 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2018 "invalid", nb_desc);
2019 return I40E_ERR_PARAM;
2023 * The following two parameters control the setting of the RS bit on
2024 * transmit descriptors. TX descriptors will have their RS bit set
2025 * after txq->tx_rs_thresh descriptors have been used. The TX
2026 * descriptor ring will be cleaned after txq->tx_free_thresh
2027 * descriptors are used or if the number of descriptors required to
2028 * transmit a packet is greater than the number of free TX descriptors.
2030 * The following constraints must be satisfied:
2031 * - tx_rs_thresh must be greater than 0.
2032 * - tx_rs_thresh must be less than the size of the ring minus 2.
2033 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
2034 * - tx_rs_thresh must be a divisor of the ring size.
2035 * - tx_free_thresh must be greater than 0.
2036 * - tx_free_thresh must be less than the size of the ring minus 3.
2038 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2039 * race condition, hence the maximum threshold constraints. When set
2040 * to zero use default values.
2042 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2043 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2044 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2045 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2046 if (tx_rs_thresh >= (nb_desc - 2)) {
2047 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2048 "number of TX descriptors minus 2. "
2049 "(tx_rs_thresh=%u port=%d queue=%d)",
2050 (unsigned int)tx_rs_thresh,
2051 (int)dev->data->port_id,
2053 return I40E_ERR_PARAM;
2055 if (tx_free_thresh >= (nb_desc - 3)) {
2056 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2057 "tx_free_thresh must be less than the "
2058 "number of TX descriptors minus 3. "
2059 "(tx_free_thresh=%u port=%d queue=%d)",
2060 (unsigned int)tx_free_thresh,
2061 (int)dev->data->port_id,
2063 return I40E_ERR_PARAM;
2065 if (tx_rs_thresh > tx_free_thresh) {
2066 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2067 "equal to tx_free_thresh. (tx_free_thresh=%u"
2068 " tx_rs_thresh=%u port=%d queue=%d)",
2069 (unsigned int)tx_free_thresh,
2070 (unsigned int)tx_rs_thresh,
2071 (int)dev->data->port_id,
2073 return I40E_ERR_PARAM;
2075 if ((nb_desc % tx_rs_thresh) != 0) {
2076 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2077 "number of TX descriptors. (tx_rs_thresh=%u"
2078 " port=%d queue=%d)",
2079 (unsigned int)tx_rs_thresh,
2080 (int)dev->data->port_id,
2082 return I40E_ERR_PARAM;
2084 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2085 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2086 "tx_rs_thresh is greater than 1. "
2087 "(tx_rs_thresh=%u port=%d queue=%d)",
2088 (unsigned int)tx_rs_thresh,
2089 (int)dev->data->port_id,
2091 return I40E_ERR_PARAM;
2094 /* Free memory if needed. */
2095 if (dev->data->tx_queues[queue_idx]) {
2096 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2097 dev->data->tx_queues[queue_idx] = NULL;
2100 /* Allocate the TX queue data structure. */
2101 txq = rte_zmalloc_socket("i40e tx queue",
2102 sizeof(struct i40e_tx_queue),
2103 RTE_CACHE_LINE_SIZE,
2106 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2107 "tx queue structure");
2111 /* Allocate TX hardware ring descriptors. */
2112 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2113 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2114 tz = i40e_ring_dma_zone_reserve(dev,
2120 i40e_dev_tx_queue_release(txq);
2121 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2125 txq->nb_tx_desc = nb_desc;
2126 txq->tx_rs_thresh = tx_rs_thresh;
2127 txq->tx_free_thresh = tx_free_thresh;
2128 txq->pthresh = tx_conf->tx_thresh.pthresh;
2129 txq->hthresh = tx_conf->tx_thresh.hthresh;
2130 txq->wthresh = tx_conf->tx_thresh.wthresh;
2131 txq->queue_id = queue_idx;
2132 if (hw->mac.type == I40E_MAC_VF)
2133 txq->reg_idx = queue_idx;
2134 else /* PF device */
2135 txq->reg_idx = vsi->base_queue +
2136 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2138 txq->port_id = dev->data->port_id;
2139 txq->txq_flags = tx_conf->txq_flags;
2141 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2143 #ifdef RTE_LIBRTE_XEN_DOM0
2144 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2146 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2148 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2150 /* Allocate software ring */
2152 rte_zmalloc_socket("i40e tx sw ring",
2153 sizeof(struct i40e_tx_entry) * nb_desc,
2154 RTE_CACHE_LINE_SIZE,
2156 if (!txq->sw_ring) {
2157 i40e_dev_tx_queue_release(txq);
2158 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2162 i40e_reset_tx_queue(txq);
2164 dev->data->tx_queues[queue_idx] = txq;
2166 /* Use a simple TX queue without offloads or multi segs if possible */
2167 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
2168 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
2169 PMD_INIT_LOG(INFO, "Using simple tx path");
2170 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2172 PMD_INIT_LOG(INFO, "Using full-featured tx path");
2173 dev->tx_pkt_burst = i40e_xmit_pkts;
2180 i40e_dev_tx_queue_release(void *txq)
2182 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2185 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2189 i40e_tx_queue_release_mbufs(q);
2190 rte_free(q->sw_ring);
2194 static const struct rte_memzone *
2195 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
2196 const char *ring_name,
2201 char z_name[RTE_MEMZONE_NAMESIZE];
2202 const struct rte_memzone *mz;
2204 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2205 dev->driver->pci_drv.name, ring_name,
2206 dev->data->port_id, queue_id);
2207 mz = rte_memzone_lookup(z_name);
2211 #ifdef RTE_LIBRTE_XEN_DOM0
2212 return rte_memzone_reserve_bounded(z_name, ring_size,
2213 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2215 return rte_memzone_reserve_aligned(z_name, ring_size,
2216 socket_id, 0, I40E_ALIGN);
2220 const struct rte_memzone *
2221 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2223 const struct rte_memzone *mz = NULL;
2225 mz = rte_memzone_lookup(name);
2228 #ifdef RTE_LIBRTE_XEN_DOM0
2229 mz = rte_memzone_reserve_bounded(name, len,
2230 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2232 mz = rte_memzone_reserve_aligned(name, len,
2233 socket_id, 0, I40E_ALIGN);
2239 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2243 if (!rxq || !rxq->sw_ring) {
2244 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2248 for (i = 0; i < rxq->nb_rx_desc; i++) {
2249 if (rxq->sw_ring[i].mbuf) {
2250 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2251 rxq->sw_ring[i].mbuf = NULL;
2254 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2255 if (rxq->rx_nb_avail == 0)
2257 for (i = 0; i < rxq->rx_nb_avail; i++) {
2258 struct rte_mbuf *mbuf;
2260 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2261 rte_pktmbuf_free_seg(mbuf);
2263 rxq->rx_nb_avail = 0;
2264 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2268 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2273 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2274 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2275 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2277 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2278 len = rxq->nb_rx_desc;
2280 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2281 ((volatile char *)rxq->rx_ring)[i] = 0;
2283 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2284 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2285 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2286 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2288 rxq->rx_nb_avail = 0;
2289 rxq->rx_next_avail = 0;
2290 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2291 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2293 rxq->nb_rx_hold = 0;
2294 rxq->pkt_first_seg = NULL;
2295 rxq->pkt_last_seg = NULL;
2299 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2303 if (!txq || !txq->sw_ring) {
2304 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2308 for (i = 0; i < txq->nb_tx_desc; i++) {
2309 if (txq->sw_ring[i].mbuf) {
2310 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2311 txq->sw_ring[i].mbuf = NULL;
2317 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2319 struct i40e_tx_entry *txe;
2320 uint16_t i, prev, size;
2323 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2328 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2329 for (i = 0; i < size; i++)
2330 ((volatile char *)txq->tx_ring)[i] = 0;
2332 prev = (uint16_t)(txq->nb_tx_desc - 1);
2333 for (i = 0; i < txq->nb_tx_desc; i++) {
2334 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2336 txd->cmd_type_offset_bsz =
2337 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2340 txe[prev].next_id = i;
2344 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2345 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2348 txq->nb_tx_used = 0;
2350 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2351 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2354 /* Init the TX queue in hardware */
2356 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2358 enum i40e_status_code err = I40E_SUCCESS;
2359 struct i40e_vsi *vsi = txq->vsi;
2360 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2361 uint16_t pf_q = txq->reg_idx;
2362 struct i40e_hmc_obj_txq tx_ctx;
2365 /* clear the context structure first */
2366 memset(&tx_ctx, 0, sizeof(tx_ctx));
2367 tx_ctx.new_context = 1;
2368 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2369 tx_ctx.qlen = txq->nb_tx_desc;
2370 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2371 if (vsi->type == I40E_VSI_FDIR)
2372 tx_ctx.fd_ena = TRUE;
2374 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2375 if (err != I40E_SUCCESS) {
2376 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2380 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2381 if (err != I40E_SUCCESS) {
2382 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2386 /* Now associate this queue with this PCI function */
2387 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2388 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2389 I40E_QTX_CTL_PF_INDX_MASK);
2390 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2391 I40E_WRITE_FLUSH(hw);
2393 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2399 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2401 struct i40e_rx_entry *rxe = rxq->sw_ring;
2405 for (i = 0; i < rxq->nb_rx_desc; i++) {
2406 volatile union i40e_rx_desc *rxd;
2407 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2409 if (unlikely(!mbuf)) {
2410 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2414 rte_mbuf_refcnt_set(mbuf, 1);
2416 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2418 mbuf->port = rxq->port_id;
2421 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2423 rxd = &rxq->rx_ring[i];
2424 rxd->read.pkt_addr = dma_addr;
2425 rxd->read.hdr_addr = dma_addr;
2426 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2427 rxd->read.rsvd1 = 0;
2428 rxd->read.rsvd2 = 0;
2429 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2438 * Calculate the buffer length, and check the jumbo frame
2439 * and maximum packet length.
2442 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2444 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2445 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2446 struct rte_eth_dev_data *data = pf->dev_data;
2447 struct rte_pktmbuf_pool_private *mbp_priv =
2448 rte_mempool_get_priv(rxq->mp);
2449 uint16_t buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2450 RTE_PKTMBUF_HEADROOM);
2453 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2454 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2455 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2456 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2457 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2458 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2459 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2460 rxq->hs_mode = i40e_header_split_enabled;
2462 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2464 rxq->rx_hdr_len = 0;
2465 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2466 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2467 rxq->hs_mode = i40e_header_split_none;
2471 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2472 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2473 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2474 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2475 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2476 PMD_DRV_LOG(ERR, "maximum packet length must "
2477 "be larger than %u and smaller than %u,"
2478 "as jumbo frame is enabled",
2479 (uint32_t)ETHER_MAX_LEN,
2480 (uint32_t)I40E_FRAME_SIZE_MAX);
2481 return I40E_ERR_CONFIG;
2484 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2485 rxq->max_pkt_len > ETHER_MAX_LEN) {
2486 PMD_DRV_LOG(ERR, "maximum packet length must be "
2487 "larger than %u and smaller than %u, "
2488 "as jumbo frame is disabled",
2489 (uint32_t)ETHER_MIN_LEN,
2490 (uint32_t)ETHER_MAX_LEN);
2491 return I40E_ERR_CONFIG;
2498 /* Init the RX queue in hardware */
2500 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2502 int err = I40E_SUCCESS;
2503 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2504 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2505 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2506 uint16_t pf_q = rxq->reg_idx;
2508 struct i40e_hmc_obj_rxq rx_ctx;
2509 struct rte_pktmbuf_pool_private *mbp_priv;
2511 err = i40e_rx_queue_config(rxq);
2513 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2517 /* Clear the context structure first */
2518 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2519 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2520 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2522 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2523 rx_ctx.qlen = rxq->nb_rx_desc;
2524 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2527 rx_ctx.dtype = rxq->hs_mode;
2529 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2531 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2532 rx_ctx.rxmax = rxq->max_pkt_len;
2533 rx_ctx.tphrdesc_ena = 1;
2534 rx_ctx.tphwdesc_ena = 1;
2535 rx_ctx.tphdata_ena = 1;
2536 rx_ctx.tphhead_ena = 1;
2537 rx_ctx.lrxqthresh = 2;
2538 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2543 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2544 if (err != I40E_SUCCESS) {
2545 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2548 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2549 if (err != I40E_SUCCESS) {
2550 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2554 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2556 mbp_priv = rte_mempool_get_priv(rxq->mp);
2557 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2558 RTE_PKTMBUF_HEADROOM);
2560 /* Check if scattered RX needs to be used. */
2561 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2562 dev_data->scattered_rx = 1;
2563 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2566 /* Init the RX tail regieter. */
2567 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2573 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2577 PMD_INIT_FUNC_TRACE();
2579 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2580 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2581 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2584 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2585 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2586 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2590 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2591 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2593 enum i40e_status_code
2594 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2596 struct i40e_tx_queue *txq;
2597 const struct rte_memzone *tz = NULL;
2599 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2602 PMD_DRV_LOG(ERR, "PF is not available");
2603 return I40E_ERR_BAD_PTR;
2606 /* Allocate the TX queue data structure. */
2607 txq = rte_zmalloc_socket("i40e fdir tx queue",
2608 sizeof(struct i40e_tx_queue),
2609 RTE_CACHE_LINE_SIZE,
2612 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2613 "tx queue structure.");
2614 return I40E_ERR_NO_MEMORY;
2617 /* Allocate TX hardware ring descriptors. */
2618 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2619 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2621 tz = i40e_ring_dma_zone_reserve(dev,
2627 i40e_dev_tx_queue_release(txq);
2628 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2629 return I40E_ERR_NO_MEMORY;
2632 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2633 txq->queue_id = I40E_FDIR_QUEUE_ID;
2634 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2635 txq->vsi = pf->fdir.fdir_vsi;
2637 #ifdef RTE_LIBRTE_XEN_DOM0
2638 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2640 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2642 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2644 * don't need to allocate software ring and reset for the fdir
2645 * program queue just set the queue has been configured.
2650 return I40E_SUCCESS;
2653 enum i40e_status_code
2654 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2656 struct i40e_rx_queue *rxq;
2657 const struct rte_memzone *rz = NULL;
2659 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2662 PMD_DRV_LOG(ERR, "PF is not available");
2663 return I40E_ERR_BAD_PTR;
2666 /* Allocate the RX queue data structure. */
2667 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2668 sizeof(struct i40e_rx_queue),
2669 RTE_CACHE_LINE_SIZE,
2672 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2673 "rx queue structure.");
2674 return I40E_ERR_NO_MEMORY;
2677 /* Allocate RX hardware ring descriptors. */
2678 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2679 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2681 rz = i40e_ring_dma_zone_reserve(dev,
2687 i40e_dev_rx_queue_release(rxq);
2688 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2689 return I40E_ERR_NO_MEMORY;
2692 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2693 rxq->queue_id = I40E_FDIR_QUEUE_ID;
2694 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2695 rxq->vsi = pf->fdir.fdir_vsi;
2697 #ifdef RTE_LIBRTE_XEN_DOM0
2698 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2700 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
2702 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2705 * Don't need to allocate software ring and reset for the fdir
2706 * rx queue, just set the queue has been configured.
2711 return I40E_SUCCESS;