4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
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8 * modification, are permitted provided that the following conditions
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31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
54 #include "i40e_logs.h"
55 #include "i40e/i40e_prototype.h"
56 #include "i40e/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
60 #define I40E_MIN_RING_DESC 64
61 #define I40E_MAX_RING_DESC 4096
62 #define I40E_ALIGN 128
63 #define DEFAULT_TX_RS_THRESH 32
64 #define DEFAULT_TX_FREE_THRESH 32
65 #define I40E_MAX_PKT_TYPE 256
67 #define I40E_VLAN_TAG_SIZE 4
68 #define I40E_TX_MAX_BURST 32
70 #define I40E_DMA_MEM_ALIGN 4096
72 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
73 ETH_TXQ_FLAGS_NOOFFLOADS)
75 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
77 #define I40E_TX_CKSUM_OFFLOAD_MASK ( \
80 PKT_TX_OUTER_IP_CKSUM)
82 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
83 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
85 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
86 ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
88 static const struct rte_memzone *
89 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
90 const char *ring_name,
94 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
95 struct rte_mbuf **tx_pkts,
98 /* Translate the rx descriptor status to pkt flags */
99 static inline uint64_t
100 i40e_rxd_status_to_pkt_flags(uint64_t qword)
104 /* Check if VLAN packet */
105 flags = qword & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
108 /* Check if RSS_HASH */
109 flags |= (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
110 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
111 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
113 /* Check if FDIR Match */
114 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
120 static inline uint64_t
121 i40e_rxd_error_to_pkt_flags(uint64_t qword)
124 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
126 #define I40E_RX_ERR_BITS 0x3f
127 if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
129 /* If RXE bit set, all other status bits are meaningless */
130 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
131 flags |= PKT_RX_MAC_ERR;
135 /* If RECIPE bit set, all other status indications should be ignored */
136 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
137 flags |= PKT_RX_RECIP_ERR;
140 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
141 flags |= PKT_RX_HBUF_OVERFLOW;
142 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
143 flags |= PKT_RX_IP_CKSUM_BAD;
144 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
145 flags |= PKT_RX_L4_CKSUM_BAD;
146 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
147 flags |= PKT_RX_EIP_CKSUM_BAD;
148 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
149 flags |= PKT_RX_OVERSIZE;
154 /* Translate pkt types to pkt flags */
155 static inline uint64_t
156 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
158 uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
159 I40E_RXD_QW1_PTYPE_SHIFT);
160 static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
183 PKT_RX_IPV4_HDR, /* PTYPE 22 */
184 PKT_RX_IPV4_HDR, /* PTYPE 23 */
185 PKT_RX_IPV4_HDR, /* PTYPE 24 */
187 PKT_RX_IPV4_HDR, /* PTYPE 26 */
188 PKT_RX_IPV4_HDR, /* PTYPE 27 */
189 PKT_RX_IPV4_HDR, /* PTYPE 28 */
190 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
191 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
192 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
194 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
195 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
196 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
197 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
198 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
199 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
201 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
202 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
203 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
204 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
205 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
206 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
207 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
209 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
210 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
211 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
212 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
213 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
214 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
216 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
217 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
218 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
219 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
220 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 59 */
221 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 60 */
222 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 61 */
224 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 63 */
225 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 64 */
226 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 65 */
227 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 66 */
228 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 67 */
229 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 68 */
231 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 70 */
232 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 71 */
233 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 72 */
234 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 73 */
235 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 74 */
236 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 75 */
237 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 76 */
239 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 78 */
240 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 79 */
241 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 80 */
242 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 81 */
243 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 82 */
244 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 83 */
246 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 85 */
247 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 86 */
248 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
249 PKT_RX_IPV6_HDR, /* PTYPE 88 */
250 PKT_RX_IPV6_HDR, /* PTYPE 89 */
251 PKT_RX_IPV6_HDR, /* PTYPE 90 */
253 PKT_RX_IPV6_HDR, /* PTYPE 92 */
254 PKT_RX_IPV6_HDR, /* PTYPE 93 */
255 PKT_RX_IPV6_HDR, /* PTYPE 94 */
256 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
257 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
258 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
260 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
261 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
262 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
263 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
264 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
265 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
267 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
268 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
269 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
270 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
271 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
272 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
273 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
275 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
276 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
277 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
278 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
279 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
280 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
282 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
283 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
284 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
285 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
286 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 125 */
287 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 126 */
288 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 127 */
290 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 129 */
291 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 130 */
292 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 131 */
293 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 132 */
294 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 133 */
295 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 134 */
297 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 136 */
298 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 137 */
299 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 138 */
300 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 139 */
301 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 140 */
302 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 141 */
303 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 142 */
305 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 144 */
306 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 145 */
307 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 146 */
308 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 147 */
309 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 148 */
310 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 149 */
312 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 151 */
313 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 152 */
314 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
419 return ip_ptype_map[ptype];
422 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
423 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
424 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
425 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
426 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
428 static inline uint64_t
429 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
432 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
433 uint16_t flexbh, flexbl;
435 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
436 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
437 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
438 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
439 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
440 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
443 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
445 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
446 flags |= PKT_RX_FDIR_ID;
447 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
449 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
450 flags |= PKT_RX_FDIR_FLX;
452 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
454 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
455 flags |= PKT_RX_FDIR_FLX;
459 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
460 flags |= PKT_RX_FDIR_ID;
465 i40e_txd_enable_checksum(uint64_t ol_flags,
470 uint8_t outer_l2_len,
471 uint16_t outer_l3_len,
472 uint32_t *cd_tunneling)
475 PMD_DRV_LOG(DEBUG, "L2 length set to 0");
480 PMD_DRV_LOG(DEBUG, "L3 length set to 0");
484 /* UDP tunneling packet TX checksum offload */
485 if (unlikely(ol_flags & PKT_TX_UDP_TUNNEL_PKT)) {
487 *td_offset |= (outer_l2_len >> 1)
488 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
490 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
491 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
492 else if (ol_flags & PKT_TX_OUTER_IPV4)
493 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
494 else if (ol_flags & PKT_TX_OUTER_IPV6)
495 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
497 /* Now set the ctx descriptor fields */
498 *cd_tunneling |= (outer_l3_len >> 2) <<
499 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
500 I40E_TXD_CTX_UDP_TUNNELING |
502 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
505 *td_offset |= (l2_len >> 1)
506 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
508 /* Enable L3 checksum offloads */
509 if (ol_flags & PKT_TX_IP_CKSUM) {
510 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
511 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
512 } else if (ol_flags & PKT_TX_IPV4) {
513 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
514 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
515 } else if (ol_flags & PKT_TX_IPV6) {
516 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
517 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
520 /* Enable L4 checksum offloads */
521 switch (ol_flags & PKT_TX_L4_MASK) {
522 case PKT_TX_TCP_CKSUM:
523 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
524 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
525 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
527 case PKT_TX_SCTP_CKSUM:
528 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
529 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
530 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
532 case PKT_TX_UDP_CKSUM:
533 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
534 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
535 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
542 static inline struct rte_mbuf *
543 rte_rxmbuf_alloc(struct rte_mempool *mp)
547 m = __rte_mbuf_raw_alloc(mp);
548 __rte_mbuf_sanity_check_raw(m, 0);
553 /* Construct the tx flags */
554 static inline uint64_t
555 i40e_build_ctob(uint32_t td_cmd,
560 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
561 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
562 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
563 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
564 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
568 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
570 struct i40e_tx_entry *sw_ring = txq->sw_ring;
571 volatile struct i40e_tx_desc *txd = txq->tx_ring;
572 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
573 uint16_t nb_tx_desc = txq->nb_tx_desc;
574 uint16_t desc_to_clean_to;
575 uint16_t nb_tx_to_clean;
577 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
578 if (desc_to_clean_to >= nb_tx_desc)
579 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
581 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
582 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
583 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) {
584 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
585 "(port=%d queue=%d)", desc_to_clean_to,
586 txq->port_id, txq->queue_id);
590 if (last_desc_cleaned > desc_to_clean_to)
591 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
594 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
597 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
599 txq->last_desc_cleaned = desc_to_clean_to;
600 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
606 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
607 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
609 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
614 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
615 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
616 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
617 "rxq->rx_free_thresh=%d, "
618 "RTE_PMD_I40E_RX_MAX_BURST=%d",
619 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
621 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
622 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
623 "rxq->rx_free_thresh=%d, "
624 "rxq->nb_rx_desc=%d",
625 rxq->rx_free_thresh, rxq->nb_rx_desc);
627 } else if (!(rxq->nb_rx_desc % rxq->rx_free_thresh) == 0) {
628 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
629 "rxq->nb_rx_desc=%d, "
630 "rxq->rx_free_thresh=%d",
631 rxq->nb_rx_desc, rxq->rx_free_thresh);
633 } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
634 RTE_PMD_I40E_RX_MAX_BURST))) {
635 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
636 "rxq->nb_rx_desc=%d, "
637 "I40E_MAX_RING_DESC=%d, "
638 "RTE_PMD_I40E_RX_MAX_BURST=%d",
639 rxq->nb_rx_desc, I40E_MAX_RING_DESC,
640 RTE_PMD_I40E_RX_MAX_BURST);
650 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
651 #define I40E_LOOK_AHEAD 8
652 #if (I40E_LOOK_AHEAD != 8)
653 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
656 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
658 volatile union i40e_rx_desc *rxdp;
659 struct i40e_rx_entry *rxep;
664 int32_t s[I40E_LOOK_AHEAD], nb_dd;
665 int32_t i, j, nb_rx = 0;
668 rxdp = &rxq->rx_ring[rxq->rx_tail];
669 rxep = &rxq->sw_ring[rxq->rx_tail];
671 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
672 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
673 I40E_RXD_QW1_STATUS_SHIFT;
675 /* Make sure there is at least 1 packet to receive */
676 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
680 * Scan LOOK_AHEAD descriptors at a time to determine which
681 * descriptors reference packets that are ready to be received.
683 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
684 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
685 /* Read desc statuses backwards to avoid race condition */
686 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
687 qword1 = rte_le_to_cpu_64(\
688 rxdp[j].wb.qword1.status_error_len);
689 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
690 I40E_RXD_QW1_STATUS_SHIFT;
693 /* Compute how many status bits were set */
694 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
695 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
699 /* Translate descriptor info to mbuf parameters */
700 for (j = 0; j < nb_dd; j++) {
702 qword1 = rte_le_to_cpu_64(\
703 rxdp[j].wb.qword1.status_error_len);
704 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
705 I40E_RXD_QW1_STATUS_SHIFT;
706 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
707 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
708 mb->data_len = pkt_len;
709 mb->pkt_len = pkt_len;
710 mb->vlan_tci = rx_status &
711 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
713 rxdp[j].wb.qword0.lo_dword.l2tag1) : 0;
714 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
715 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
716 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
718 mb->packet_type = (uint16_t)((qword1 &
719 I40E_RXD_QW1_PTYPE_MASK) >>
720 I40E_RXD_QW1_PTYPE_SHIFT);
721 if (pkt_flags & PKT_RX_RSS_HASH)
722 mb->hash.rss = rte_le_to_cpu_32(\
723 rxdp[j].wb.qword0.hi_dword.rss);
724 if (pkt_flags & PKT_RX_FDIR)
725 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
727 mb->ol_flags = pkt_flags;
730 for (j = 0; j < I40E_LOOK_AHEAD; j++)
731 rxq->rx_stage[i + j] = rxep[j].mbuf;
733 if (nb_dd != I40E_LOOK_AHEAD)
737 /* Clear software ring entries */
738 for (i = 0; i < nb_rx; i++)
739 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
744 static inline uint16_t
745 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
746 struct rte_mbuf **rx_pkts,
750 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
752 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
754 for (i = 0; i < nb_pkts; i++)
755 rx_pkts[i] = stage[i];
757 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
758 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
764 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
766 volatile union i40e_rx_desc *rxdp;
767 struct i40e_rx_entry *rxep;
769 uint16_t alloc_idx, i;
773 /* Allocate buffers in bulk */
774 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
775 (rxq->rx_free_thresh - 1));
776 rxep = &(rxq->sw_ring[alloc_idx]);
777 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
778 rxq->rx_free_thresh);
779 if (unlikely(diag != 0)) {
780 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
784 rxdp = &rxq->rx_ring[alloc_idx];
785 for (i = 0; i < rxq->rx_free_thresh; i++) {
787 rte_mbuf_refcnt_set(mb, 1);
789 mb->data_off = RTE_PKTMBUF_HEADROOM;
791 mb->port = rxq->port_id;
792 dma_addr = rte_cpu_to_le_64(\
793 RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
794 rxdp[i].read.hdr_addr = dma_addr;
795 rxdp[i].read.pkt_addr = dma_addr;
798 /* Update rx tail regsiter */
800 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
802 rxq->rx_free_trigger =
803 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
804 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
805 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
810 static inline uint16_t
811 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
813 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
819 if (rxq->rx_nb_avail)
820 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
822 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
823 rxq->rx_next_avail = 0;
824 rxq->rx_nb_avail = nb_rx;
825 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
827 if (rxq->rx_tail > rxq->rx_free_trigger) {
828 if (i40e_rx_alloc_bufs(rxq) != 0) {
831 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
832 "port_id=%u, queue_id=%u",
833 rxq->port_id, rxq->queue_id);
834 rxq->rx_nb_avail = 0;
835 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
836 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
837 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
843 if (rxq->rx_tail >= rxq->nb_rx_desc)
846 if (rxq->rx_nb_avail)
847 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
853 i40e_recv_pkts_bulk_alloc(void *rx_queue,
854 struct rte_mbuf **rx_pkts,
857 uint16_t nb_rx = 0, n, count;
859 if (unlikely(nb_pkts == 0))
862 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
863 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
866 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
867 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
868 nb_rx = (uint16_t)(nb_rx + count);
869 nb_pkts = (uint16_t)(nb_pkts - count);
876 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
879 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
881 struct i40e_rx_queue *rxq;
882 volatile union i40e_rx_desc *rx_ring;
883 volatile union i40e_rx_desc *rxdp;
884 union i40e_rx_desc rxd;
885 struct i40e_rx_entry *sw_ring;
886 struct i40e_rx_entry *rxe;
887 struct rte_mbuf *rxm;
888 struct rte_mbuf *nmb;
892 uint16_t rx_packet_len;
893 uint16_t rx_id, nb_hold;
900 rx_id = rxq->rx_tail;
901 rx_ring = rxq->rx_ring;
902 sw_ring = rxq->sw_ring;
904 while (nb_rx < nb_pkts) {
905 rxdp = &rx_ring[rx_id];
906 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
907 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
908 >> I40E_RXD_QW1_STATUS_SHIFT;
909 /* Check the DD bit first */
910 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
913 nmb = rte_rxmbuf_alloc(rxq->mp);
919 rxe = &sw_ring[rx_id];
921 if (unlikely(rx_id == rxq->nb_rx_desc))
924 /* Prefetch next mbuf */
925 rte_prefetch0(sw_ring[rx_id].mbuf);
928 * When next RX descriptor is on a cache line boundary,
929 * prefetch the next 4 RX descriptors and next 8 pointers
932 if ((rx_id & 0x3) == 0) {
933 rte_prefetch0(&rx_ring[rx_id]);
934 rte_prefetch0(&sw_ring[rx_id]);
939 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
940 rxdp->read.hdr_addr = dma_addr;
941 rxdp->read.pkt_addr = dma_addr;
943 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
944 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
946 rxm->data_off = RTE_PKTMBUF_HEADROOM;
947 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
950 rxm->pkt_len = rx_packet_len;
951 rxm->data_len = rx_packet_len;
952 rxm->port = rxq->port_id;
954 rxm->vlan_tci = rx_status &
955 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
956 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
957 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
958 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
959 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
960 rxm->packet_type = (uint16_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >>
961 I40E_RXD_QW1_PTYPE_SHIFT);
962 if (pkt_flags & PKT_RX_RSS_HASH)
964 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
965 if (pkt_flags & PKT_RX_FDIR)
966 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
968 rxm->ol_flags = pkt_flags;
970 rx_pkts[nb_rx++] = rxm;
972 rxq->rx_tail = rx_id;
975 * If the number of free RX descriptors is greater than the RX free
976 * threshold of the queue, advance the receive tail register of queue.
977 * Update that register with the value of the last processed RX
978 * descriptor minus 1.
980 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
981 if (nb_hold > rxq->rx_free_thresh) {
982 rx_id = (uint16_t) ((rx_id == 0) ?
983 (rxq->nb_rx_desc - 1) : (rx_id - 1));
984 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
987 rxq->nb_rx_hold = nb_hold;
993 i40e_recv_scattered_pkts(void *rx_queue,
994 struct rte_mbuf **rx_pkts,
997 struct i40e_rx_queue *rxq = rx_queue;
998 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
999 volatile union i40e_rx_desc *rxdp;
1000 union i40e_rx_desc rxd;
1001 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1002 struct i40e_rx_entry *rxe;
1003 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1004 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1005 struct rte_mbuf *nmb, *rxm;
1006 uint16_t rx_id = rxq->rx_tail;
1007 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1013 while (nb_rx < nb_pkts) {
1014 rxdp = &rx_ring[rx_id];
1015 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1016 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1017 I40E_RXD_QW1_STATUS_SHIFT;
1018 /* Check the DD bit */
1019 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1022 nmb = rte_rxmbuf_alloc(rxq->mp);
1027 rxe = &sw_ring[rx_id];
1029 if (rx_id == rxq->nb_rx_desc)
1032 /* Prefetch next mbuf */
1033 rte_prefetch0(sw_ring[rx_id].mbuf);
1036 * When next RX descriptor is on a cache line boundary,
1037 * prefetch the next 4 RX descriptors and next 8 pointers
1040 if ((rx_id & 0x3) == 0) {
1041 rte_prefetch0(&rx_ring[rx_id]);
1042 rte_prefetch0(&sw_ring[rx_id]);
1048 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1050 /* Set data buffer address and data length of the mbuf */
1051 rxdp->read.hdr_addr = dma_addr;
1052 rxdp->read.pkt_addr = dma_addr;
1053 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1054 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1055 rxm->data_len = rx_packet_len;
1056 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1059 * If this is the first buffer of the received packet, set the
1060 * pointer to the first mbuf of the packet and initialize its
1061 * context. Otherwise, update the total length and the number
1062 * of segments of the current scattered packet, and update the
1063 * pointer to the last mbuf of the current packet.
1067 first_seg->nb_segs = 1;
1068 first_seg->pkt_len = rx_packet_len;
1070 first_seg->pkt_len =
1071 (uint16_t)(first_seg->pkt_len +
1073 first_seg->nb_segs++;
1074 last_seg->next = rxm;
1078 * If this is not the last buffer of the received packet,
1079 * update the pointer to the last mbuf of the current scattered
1080 * packet and continue to parse the RX ring.
1082 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1088 * This is the last buffer of the received packet. If the CRC
1089 * is not stripped by the hardware:
1090 * - Subtract the CRC length from the total packet length.
1091 * - If the last buffer only contains the whole CRC or a part
1092 * of it, free the mbuf associated to the last buffer. If part
1093 * of the CRC is also contained in the previous mbuf, subtract
1094 * the length of that CRC part from the data length of the
1098 if (unlikely(rxq->crc_len > 0)) {
1099 first_seg->pkt_len -= ETHER_CRC_LEN;
1100 if (rx_packet_len <= ETHER_CRC_LEN) {
1101 rte_pktmbuf_free_seg(rxm);
1102 first_seg->nb_segs--;
1103 last_seg->data_len =
1104 (uint16_t)(last_seg->data_len -
1105 (ETHER_CRC_LEN - rx_packet_len));
1106 last_seg->next = NULL;
1108 rxm->data_len = (uint16_t)(rx_packet_len -
1112 first_seg->port = rxq->port_id;
1113 first_seg->vlan_tci = (rx_status &
1114 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1115 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
1116 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1117 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1118 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1119 first_seg->packet_type = (uint16_t)((qword1 &
1120 I40E_RXD_QW1_PTYPE_MASK) >>
1121 I40E_RXD_QW1_PTYPE_SHIFT);
1122 if (pkt_flags & PKT_RX_RSS_HASH)
1124 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1125 if (pkt_flags & PKT_RX_FDIR)
1126 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1128 first_seg->ol_flags = pkt_flags;
1130 /* Prefetch data of first segment, if configured to do so. */
1131 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1132 first_seg->data_off));
1133 rx_pkts[nb_rx++] = first_seg;
1137 /* Record index of the next RX descriptor to probe. */
1138 rxq->rx_tail = rx_id;
1139 rxq->pkt_first_seg = first_seg;
1140 rxq->pkt_last_seg = last_seg;
1143 * If the number of free RX descriptors is greater than the RX free
1144 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1145 * register. Update the RDT with the value of the last processed RX
1146 * descriptor minus 1, to guarantee that the RDT register is never
1147 * equal to the RDH register, which creates a "full" ring situtation
1148 * from the hardware point of view.
1150 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1151 if (nb_hold > rxq->rx_free_thresh) {
1152 rx_id = (uint16_t)(rx_id == 0 ?
1153 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1154 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1157 rxq->nb_rx_hold = nb_hold;
1162 /* Check if the context descriptor is needed for TX offloading */
1163 static inline uint16_t
1164 i40e_calc_context_desc(uint64_t flags)
1166 uint64_t mask = 0ULL;
1168 if (flags | PKT_TX_UDP_TUNNEL_PKT)
1169 mask |= PKT_TX_UDP_TUNNEL_PKT;
1171 #ifdef RTE_LIBRTE_IEEE1588
1172 mask |= PKT_TX_IEEE1588_TMST;
1181 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1183 struct i40e_tx_queue *txq;
1184 struct i40e_tx_entry *sw_ring;
1185 struct i40e_tx_entry *txe, *txn;
1186 volatile struct i40e_tx_desc *txd;
1187 volatile struct i40e_tx_desc *txr;
1188 struct rte_mbuf *tx_pkt;
1189 struct rte_mbuf *m_seg;
1190 uint32_t cd_tunneling_params;
1200 uint8_t outer_l2_len;
1201 uint16_t outer_l3_len;
1206 uint64_t buf_dma_addr;
1209 sw_ring = txq->sw_ring;
1211 tx_id = txq->tx_tail;
1212 txe = &sw_ring[tx_id];
1214 /* Check if the descriptor ring needs to be cleaned. */
1215 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh)
1216 i40e_xmit_cleanup(txq);
1218 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1224 tx_pkt = *tx_pkts++;
1225 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1227 ol_flags = tx_pkt->ol_flags;
1228 l2_len = tx_pkt->l2_len;
1229 l3_len = tx_pkt->l3_len;
1230 outer_l2_len = tx_pkt->outer_l2_len;
1231 outer_l3_len = tx_pkt->outer_l3_len;
1233 /* Calculate the number of context descriptors needed. */
1234 nb_ctx = i40e_calc_context_desc(ol_flags);
1237 * The number of descriptors that must be allocated for
1238 * a packet equals to the number of the segments of that
1239 * packet plus 1 context descriptor if needed.
1241 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1242 tx_last = (uint16_t)(tx_id + nb_used - 1);
1245 if (tx_last >= txq->nb_tx_desc)
1246 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1248 if (nb_used > txq->nb_tx_free) {
1249 if (i40e_xmit_cleanup(txq) != 0) {
1254 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1255 while (nb_used > txq->nb_tx_free) {
1256 if (i40e_xmit_cleanup(txq) != 0) {
1265 /* Descriptor based VLAN insertion */
1266 if (ol_flags & PKT_TX_VLAN_PKT) {
1267 tx_flags |= tx_pkt->vlan_tci <<
1268 I40E_TX_FLAG_L2TAG1_SHIFT;
1269 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1270 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1271 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1272 I40E_TX_FLAG_L2TAG1_SHIFT;
1275 /* Always enable CRC offload insertion */
1276 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1278 /* Enable checksum offloading */
1279 cd_tunneling_params = 0;
1280 if (unlikely(ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)) {
1281 i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1282 l2_len, l3_len, outer_l2_len,
1284 &cd_tunneling_params);
1287 if (unlikely(nb_ctx)) {
1288 /* Setup TX context descriptor if required */
1289 volatile struct i40e_tx_context_desc *ctx_txd =
1290 (volatile struct i40e_tx_context_desc *)\
1292 uint16_t cd_l2tag2 = 0;
1293 uint64_t cd_type_cmd_tso_mss =
1294 I40E_TX_DESC_DTYPE_CONTEXT;
1296 txn = &sw_ring[txe->next_id];
1297 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1298 if (txe->mbuf != NULL) {
1299 rte_pktmbuf_free_seg(txe->mbuf);
1302 #ifdef RTE_LIBRTE_IEEE1588
1303 if (ol_flags & PKT_TX_IEEE1588_TMST)
1304 cd_type_cmd_tso_mss |=
1305 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1306 I40E_TXD_CTX_QW1_CMD_SHIFT);
1308 ctx_txd->tunneling_params =
1309 rte_cpu_to_le_32(cd_tunneling_params);
1310 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1311 ctx_txd->type_cmd_tso_mss =
1312 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1313 txe->last_id = tx_last;
1314 tx_id = txe->next_id;
1321 txn = &sw_ring[txe->next_id];
1324 rte_pktmbuf_free_seg(txe->mbuf);
1327 /* Setup TX Descriptor */
1328 slen = m_seg->data_len;
1329 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1330 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1331 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1332 td_offset, slen, td_tag);
1333 txe->last_id = tx_last;
1334 tx_id = txe->next_id;
1336 m_seg = m_seg->next;
1337 } while (m_seg != NULL);
1339 /* The last packet data descriptor needs End Of Packet (EOP) */
1340 td_cmd |= I40E_TX_DESC_CMD_EOP;
1341 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1342 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1344 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1345 PMD_TX_FREE_LOG(DEBUG,
1346 "Setting RS bit on TXD id="
1347 "%4u (port=%d queue=%d)",
1348 tx_last, txq->port_id, txq->queue_id);
1350 td_cmd |= I40E_TX_DESC_CMD_RS;
1352 /* Update txq RS bit counters */
1353 txq->nb_tx_used = 0;
1356 txd->cmd_type_offset_bsz |=
1357 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1358 I40E_TXD_QW1_CMD_SHIFT);
1364 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1365 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1366 (unsigned) tx_id, (unsigned) nb_tx);
1368 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1369 txq->tx_tail = tx_id;
1374 static inline int __attribute__((always_inline))
1375 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1377 struct i40e_tx_entry *txep;
1380 if (!(txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1381 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)))
1384 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1386 for (i = 0; i < txq->tx_rs_thresh; i++)
1387 rte_prefetch0((txep + i)->mbuf);
1389 if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1390 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1391 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1395 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1396 rte_pktmbuf_free_seg(txep->mbuf);
1401 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1402 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1403 if (txq->tx_next_dd >= txq->nb_tx_desc)
1404 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1406 return txq->tx_rs_thresh;
1409 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1410 I40E_TX_DESC_CMD_EOP)
1412 /* Populate 4 descriptors with data from 4 mbufs */
1414 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1419 for (i = 0; i < 4; i++, txdp++, pkts++) {
1420 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1421 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1422 txdp->cmd_type_offset_bsz =
1423 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1424 (*pkts)->data_len, 0);
1428 /* Populate 1 descriptor with data from 1 mbuf */
1430 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1434 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1435 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1436 txdp->cmd_type_offset_bsz =
1437 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1438 (*pkts)->data_len, 0);
1441 /* Fill hardware descriptor ring with mbuf data */
1443 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1444 struct rte_mbuf **pkts,
1447 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1448 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1449 const int N_PER_LOOP = 4;
1450 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1451 int mainpart, leftover;
1454 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1455 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1456 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1457 for (j = 0; j < N_PER_LOOP; ++j) {
1458 (txep + i + j)->mbuf = *(pkts + i + j);
1460 tx4(txdp + i, pkts + i);
1462 if (unlikely(leftover > 0)) {
1463 for (i = 0; i < leftover; ++i) {
1464 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1465 tx1(txdp + mainpart + i, pkts + mainpart + i);
1470 static inline uint16_t
1471 tx_xmit_pkts(struct i40e_tx_queue *txq,
1472 struct rte_mbuf **tx_pkts,
1475 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1479 * Begin scanning the H/W ring for done descriptors when the number
1480 * of available descriptors drops below tx_free_thresh. For each done
1481 * descriptor, free the associated buffer.
1483 if (txq->nb_tx_free < txq->tx_free_thresh)
1484 i40e_tx_free_bufs(txq);
1486 /* Use available descriptor only */
1487 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1488 if (unlikely(!nb_pkts))
1491 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1492 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1493 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1494 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1495 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1496 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1497 I40E_TXD_QW1_CMD_SHIFT);
1498 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1502 /* Fill hardware descriptor ring with mbuf data */
1503 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1504 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1506 /* Determin if RS bit needs to be set */
1507 if (txq->tx_tail > txq->tx_next_rs) {
1508 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1509 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1510 I40E_TXD_QW1_CMD_SHIFT);
1512 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1513 if (txq->tx_next_rs >= txq->nb_tx_desc)
1514 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1517 if (txq->tx_tail >= txq->nb_tx_desc)
1520 /* Update the tx tail register */
1522 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1528 i40e_xmit_pkts_simple(void *tx_queue,
1529 struct rte_mbuf **tx_pkts,
1534 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1535 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1539 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1542 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1543 &tx_pkts[nb_tx], num);
1544 nb_tx = (uint16_t)(nb_tx + ret);
1545 nb_pkts = (uint16_t)(nb_pkts - ret);
1554 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1555 * application used, which assume having sequential ones. But from driver's
1556 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1557 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1558 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1559 * use queue_idx from 0 to 95 to access queues, while real queue would be
1560 * different. This function will do a queue mapping to find VSI the queue
1563 static struct i40e_vsi*
1564 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1566 /* the queue in MAIN VSI range */
1567 if (queue_idx < pf->main_vsi->nb_qps)
1568 return pf->main_vsi;
1570 queue_idx -= pf->main_vsi->nb_qps;
1572 /* queue_idx is greater than VMDQ VSIs range */
1573 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1574 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1578 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1582 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1584 /* the queue in MAIN VSI range */
1585 if (queue_idx < pf->main_vsi->nb_qps)
1588 /* It's VMDQ queues */
1589 queue_idx -= pf->main_vsi->nb_qps;
1591 if (pf->nb_cfg_vmdq_vsi)
1592 return queue_idx % pf->vmdq_nb_qps;
1594 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1595 return (uint16_t)(-1);
1600 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1602 struct i40e_rx_queue *rxq;
1604 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606 PMD_INIT_FUNC_TRACE();
1608 if (rx_queue_id < dev->data->nb_rx_queues) {
1609 rxq = dev->data->rx_queues[rx_queue_id];
1611 err = i40e_alloc_rx_queue_mbufs(rxq);
1613 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1619 /* Init the RX tail regieter. */
1620 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1622 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1625 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1628 i40e_rx_queue_release_mbufs(rxq);
1629 i40e_reset_rx_queue(rxq);
1637 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1639 struct i40e_rx_queue *rxq;
1641 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1643 if (rx_queue_id < dev->data->nb_rx_queues) {
1644 rxq = dev->data->rx_queues[rx_queue_id];
1647 * rx_queue_id is queue id aplication refers to, while
1648 * rxq->reg_idx is the real queue index.
1650 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1653 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1657 i40e_rx_queue_release_mbufs(rxq);
1658 i40e_reset_rx_queue(rxq);
1665 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1668 struct i40e_tx_queue *txq;
1669 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1671 PMD_INIT_FUNC_TRACE();
1673 if (tx_queue_id < dev->data->nb_tx_queues) {
1674 txq = dev->data->tx_queues[tx_queue_id];
1677 * tx_queue_id is queue id aplication refers to, while
1678 * rxq->reg_idx is the real queue index.
1680 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1682 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1690 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1692 struct i40e_tx_queue *txq;
1694 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1696 if (tx_queue_id < dev->data->nb_tx_queues) {
1697 txq = dev->data->tx_queues[tx_queue_id];
1700 * tx_queue_id is queue id aplication refers to, while
1701 * txq->reg_idx is the real queue index.
1703 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1706 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1711 i40e_tx_queue_release_mbufs(txq);
1712 i40e_reset_tx_queue(txq);
1719 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1722 unsigned int socket_id,
1723 const struct rte_eth_rxconf *rx_conf,
1724 struct rte_mempool *mp)
1726 struct i40e_vsi *vsi;
1727 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1728 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1729 struct i40e_rx_queue *rxq;
1730 const struct rte_memzone *rz;
1733 int use_def_burst_func = 1;
1735 if (hw->mac.type == I40E_MAC_VF) {
1736 struct i40e_vf *vf =
1737 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1740 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1743 PMD_DRV_LOG(ERR, "VSI not available or queue "
1744 "index exceeds the maximum");
1745 return I40E_ERR_PARAM;
1747 if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1748 (nb_desc > I40E_MAX_RING_DESC) ||
1749 (nb_desc < I40E_MIN_RING_DESC)) {
1750 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1751 "invalid", nb_desc);
1752 return I40E_ERR_PARAM;
1755 /* Free memory if needed */
1756 if (dev->data->rx_queues[queue_idx]) {
1757 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1758 dev->data->rx_queues[queue_idx] = NULL;
1761 /* Allocate the rx queue data structure */
1762 rxq = rte_zmalloc_socket("i40e rx queue",
1763 sizeof(struct i40e_rx_queue),
1764 RTE_CACHE_LINE_SIZE,
1767 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1768 "rx queue data structure");
1772 rxq->nb_rx_desc = nb_desc;
1773 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1774 rxq->queue_id = queue_idx;
1775 if (hw->mac.type == I40E_MAC_VF)
1776 rxq->reg_idx = queue_idx;
1777 else /* PF device */
1778 rxq->reg_idx = vsi->base_queue +
1779 i40e_get_queue_offset_by_qindex(pf, queue_idx);
1781 rxq->port_id = dev->data->port_id;
1782 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1784 rxq->drop_en = rx_conf->rx_drop_en;
1786 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1788 /* Allocate the maximun number of RX ring hardware descriptor. */
1789 ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1790 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1791 rz = i40e_ring_dma_zone_reserve(dev,
1797 i40e_dev_rx_queue_release(rxq);
1798 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1802 /* Zero all the descriptors in the ring. */
1803 memset(rz->addr, 0, ring_size);
1805 #ifdef RTE_LIBRTE_XEN_DOM0
1806 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1808 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1811 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1813 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1814 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1819 /* Allocate the software ring. */
1821 rte_zmalloc_socket("i40e rx sw ring",
1822 sizeof(struct i40e_rx_entry) * len,
1823 RTE_CACHE_LINE_SIZE,
1825 if (!rxq->sw_ring) {
1826 i40e_dev_rx_queue_release(rxq);
1827 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1831 i40e_reset_rx_queue(rxq);
1833 dev->data->rx_queues[queue_idx] = rxq;
1835 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1837 if (!use_def_burst_func && !dev->data->scattered_rx) {
1838 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1839 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1840 "satisfied. Rx Burst Bulk Alloc function will be "
1841 "used on port=%d, queue=%d.",
1842 rxq->port_id, rxq->queue_id);
1843 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1844 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1846 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1847 "not satisfied, Scattered Rx is requested, "
1848 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1849 "not enabled on port=%d, queue=%d.",
1850 rxq->port_id, rxq->queue_id);
1857 i40e_dev_rx_queue_release(void *rxq)
1859 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1862 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1866 i40e_rx_queue_release_mbufs(q);
1867 rte_free(q->sw_ring);
1872 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1874 #define I40E_RXQ_SCAN_INTERVAL 4
1875 volatile union i40e_rx_desc *rxdp;
1876 struct i40e_rx_queue *rxq;
1879 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1880 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1884 rxq = dev->data->rx_queues[rx_queue_id];
1885 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1886 while ((desc < rxq->nb_rx_desc) &&
1887 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1888 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1889 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1891 * Check the DD bit of a rx descriptor of each 4 in a group,
1892 * to avoid checking too frequently and downgrading performance
1895 desc += I40E_RXQ_SCAN_INTERVAL;
1896 rxdp += I40E_RXQ_SCAN_INTERVAL;
1897 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1898 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1899 desc - rxq->nb_rx_desc]);
1906 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1908 volatile union i40e_rx_desc *rxdp;
1909 struct i40e_rx_queue *rxq = rx_queue;
1913 if (unlikely(offset >= rxq->nb_rx_desc)) {
1914 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1918 desc = rxq->rx_tail + offset;
1919 if (desc >= rxq->nb_rx_desc)
1920 desc -= rxq->nb_rx_desc;
1922 rxdp = &(rxq->rx_ring[desc]);
1924 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1925 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1926 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1932 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1935 unsigned int socket_id,
1936 const struct rte_eth_txconf *tx_conf)
1938 struct i40e_vsi *vsi;
1939 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1940 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1941 struct i40e_tx_queue *txq;
1942 const struct rte_memzone *tz;
1944 uint16_t tx_rs_thresh, tx_free_thresh;
1946 if (hw->mac.type == I40E_MAC_VF) {
1947 struct i40e_vf *vf =
1948 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1951 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1954 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1955 "exceeds the maximum", queue_idx);
1956 return I40E_ERR_PARAM;
1959 if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
1960 (nb_desc > I40E_MAX_RING_DESC) ||
1961 (nb_desc < I40E_MIN_RING_DESC)) {
1962 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1963 "invalid", nb_desc);
1964 return I40E_ERR_PARAM;
1968 * The following two parameters control the setting of the RS bit on
1969 * transmit descriptors. TX descriptors will have their RS bit set
1970 * after txq->tx_rs_thresh descriptors have been used. The TX
1971 * descriptor ring will be cleaned after txq->tx_free_thresh
1972 * descriptors are used or if the number of descriptors required to
1973 * transmit a packet is greater than the number of free TX descriptors.
1975 * The following constraints must be satisfied:
1976 * - tx_rs_thresh must be greater than 0.
1977 * - tx_rs_thresh must be less than the size of the ring minus 2.
1978 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1979 * - tx_rs_thresh must be a divisor of the ring size.
1980 * - tx_free_thresh must be greater than 0.
1981 * - tx_free_thresh must be less than the size of the ring minus 3.
1983 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1984 * race condition, hence the maximum threshold constraints. When set
1985 * to zero use default values.
1987 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1988 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1989 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1990 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1991 if (tx_rs_thresh >= (nb_desc - 2)) {
1992 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1993 "number of TX descriptors minus 2. "
1994 "(tx_rs_thresh=%u port=%d queue=%d)",
1995 (unsigned int)tx_rs_thresh,
1996 (int)dev->data->port_id,
1998 return I40E_ERR_PARAM;
2000 if (tx_free_thresh >= (nb_desc - 3)) {
2001 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2002 "tx_free_thresh must be less than the "
2003 "number of TX descriptors minus 3. "
2004 "(tx_free_thresh=%u port=%d queue=%d)",
2005 (unsigned int)tx_free_thresh,
2006 (int)dev->data->port_id,
2008 return I40E_ERR_PARAM;
2010 if (tx_rs_thresh > tx_free_thresh) {
2011 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2012 "equal to tx_free_thresh. (tx_free_thresh=%u"
2013 " tx_rs_thresh=%u port=%d queue=%d)",
2014 (unsigned int)tx_free_thresh,
2015 (unsigned int)tx_rs_thresh,
2016 (int)dev->data->port_id,
2018 return I40E_ERR_PARAM;
2020 if ((nb_desc % tx_rs_thresh) != 0) {
2021 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2022 "number of TX descriptors. (tx_rs_thresh=%u"
2023 " port=%d queue=%d)",
2024 (unsigned int)tx_rs_thresh,
2025 (int)dev->data->port_id,
2027 return I40E_ERR_PARAM;
2029 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2030 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2031 "tx_rs_thresh is greater than 1. "
2032 "(tx_rs_thresh=%u port=%d queue=%d)",
2033 (unsigned int)tx_rs_thresh,
2034 (int)dev->data->port_id,
2036 return I40E_ERR_PARAM;
2039 /* Free memory if needed. */
2040 if (dev->data->tx_queues[queue_idx]) {
2041 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2042 dev->data->tx_queues[queue_idx] = NULL;
2045 /* Allocate the TX queue data structure. */
2046 txq = rte_zmalloc_socket("i40e tx queue",
2047 sizeof(struct i40e_tx_queue),
2048 RTE_CACHE_LINE_SIZE,
2051 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2052 "tx queue structure");
2056 /* Allocate TX hardware ring descriptors. */
2057 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2058 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2059 tz = i40e_ring_dma_zone_reserve(dev,
2065 i40e_dev_tx_queue_release(txq);
2066 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2070 txq->nb_tx_desc = nb_desc;
2071 txq->tx_rs_thresh = tx_rs_thresh;
2072 txq->tx_free_thresh = tx_free_thresh;
2073 txq->pthresh = tx_conf->tx_thresh.pthresh;
2074 txq->hthresh = tx_conf->tx_thresh.hthresh;
2075 txq->wthresh = tx_conf->tx_thresh.wthresh;
2076 txq->queue_id = queue_idx;
2077 if (hw->mac.type == I40E_MAC_VF)
2078 txq->reg_idx = queue_idx;
2079 else /* PF device */
2080 txq->reg_idx = vsi->base_queue +
2081 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2083 txq->port_id = dev->data->port_id;
2084 txq->txq_flags = tx_conf->txq_flags;
2086 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2088 #ifdef RTE_LIBRTE_XEN_DOM0
2089 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2091 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2093 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2095 /* Allocate software ring */
2097 rte_zmalloc_socket("i40e tx sw ring",
2098 sizeof(struct i40e_tx_entry) * nb_desc,
2099 RTE_CACHE_LINE_SIZE,
2101 if (!txq->sw_ring) {
2102 i40e_dev_tx_queue_release(txq);
2103 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2107 i40e_reset_tx_queue(txq);
2109 dev->data->tx_queues[queue_idx] = txq;
2111 /* Use a simple TX queue without offloads or multi segs if possible */
2112 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
2113 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
2114 PMD_INIT_LOG(INFO, "Using simple tx path");
2115 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2117 PMD_INIT_LOG(INFO, "Using full-featured tx path");
2118 dev->tx_pkt_burst = i40e_xmit_pkts;
2125 i40e_dev_tx_queue_release(void *txq)
2127 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2130 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2134 i40e_tx_queue_release_mbufs(q);
2135 rte_free(q->sw_ring);
2139 static const struct rte_memzone *
2140 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
2141 const char *ring_name,
2146 char z_name[RTE_MEMZONE_NAMESIZE];
2147 const struct rte_memzone *mz;
2149 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2150 dev->driver->pci_drv.name, ring_name,
2151 dev->data->port_id, queue_id);
2152 mz = rte_memzone_lookup(z_name);
2156 #ifdef RTE_LIBRTE_XEN_DOM0
2157 return rte_memzone_reserve_bounded(z_name, ring_size,
2158 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2160 return rte_memzone_reserve_aligned(z_name, ring_size,
2161 socket_id, 0, I40E_ALIGN);
2165 const struct rte_memzone *
2166 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2168 const struct rte_memzone *mz = NULL;
2170 mz = rte_memzone_lookup(name);
2173 #ifdef RTE_LIBRTE_XEN_DOM0
2174 mz = rte_memzone_reserve_bounded(name, len,
2175 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2177 mz = rte_memzone_reserve_aligned(name, len,
2178 socket_id, 0, I40E_ALIGN);
2184 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2188 if (!rxq || !rxq->sw_ring) {
2189 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2193 for (i = 0; i < rxq->nb_rx_desc; i++) {
2194 if (rxq->sw_ring[i].mbuf) {
2195 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2196 rxq->sw_ring[i].mbuf = NULL;
2199 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2200 if (rxq->rx_nb_avail == 0)
2202 for (i = 0; i < rxq->rx_nb_avail; i++) {
2203 struct rte_mbuf *mbuf;
2205 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2206 rte_pktmbuf_free_seg(mbuf);
2208 rxq->rx_nb_avail = 0;
2209 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2213 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2218 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2219 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2220 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2222 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2223 len = rxq->nb_rx_desc;
2225 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2226 ((volatile char *)rxq->rx_ring)[i] = 0;
2228 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2229 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2230 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2231 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2233 rxq->rx_nb_avail = 0;
2234 rxq->rx_next_avail = 0;
2235 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2236 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2238 rxq->nb_rx_hold = 0;
2239 rxq->pkt_first_seg = NULL;
2240 rxq->pkt_last_seg = NULL;
2244 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2248 if (!txq || !txq->sw_ring) {
2249 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2253 for (i = 0; i < txq->nb_tx_desc; i++) {
2254 if (txq->sw_ring[i].mbuf) {
2255 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2256 txq->sw_ring[i].mbuf = NULL;
2262 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2264 struct i40e_tx_entry *txe;
2265 uint16_t i, prev, size;
2268 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2273 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2274 for (i = 0; i < size; i++)
2275 ((volatile char *)txq->tx_ring)[i] = 0;
2277 prev = (uint16_t)(txq->nb_tx_desc - 1);
2278 for (i = 0; i < txq->nb_tx_desc; i++) {
2279 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2281 txd->cmd_type_offset_bsz =
2282 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2285 txe[prev].next_id = i;
2289 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2290 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2293 txq->nb_tx_used = 0;
2295 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2296 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2299 /* Init the TX queue in hardware */
2301 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2303 enum i40e_status_code err = I40E_SUCCESS;
2304 struct i40e_vsi *vsi = txq->vsi;
2305 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2306 uint16_t pf_q = txq->reg_idx;
2307 struct i40e_hmc_obj_txq tx_ctx;
2310 /* clear the context structure first */
2311 memset(&tx_ctx, 0, sizeof(tx_ctx));
2312 tx_ctx.new_context = 1;
2313 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2314 tx_ctx.qlen = txq->nb_tx_desc;
2315 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2316 if (vsi->type == I40E_VSI_FDIR)
2317 tx_ctx.fd_ena = TRUE;
2319 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2320 if (err != I40E_SUCCESS) {
2321 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2325 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2326 if (err != I40E_SUCCESS) {
2327 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2331 /* Now associate this queue with this PCI function */
2332 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2333 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2334 I40E_QTX_CTL_PF_INDX_MASK);
2335 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2336 I40E_WRITE_FLUSH(hw);
2338 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2344 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2346 struct i40e_rx_entry *rxe = rxq->sw_ring;
2350 for (i = 0; i < rxq->nb_rx_desc; i++) {
2351 volatile union i40e_rx_desc *rxd;
2352 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2354 if (unlikely(!mbuf)) {
2355 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2359 rte_mbuf_refcnt_set(mbuf, 1);
2361 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2363 mbuf->port = rxq->port_id;
2366 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2368 rxd = &rxq->rx_ring[i];
2369 rxd->read.pkt_addr = dma_addr;
2370 rxd->read.hdr_addr = dma_addr;
2371 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2372 rxd->read.rsvd1 = 0;
2373 rxd->read.rsvd2 = 0;
2374 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2383 * Calculate the buffer length, and check the jumbo frame
2384 * and maximum packet length.
2387 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2389 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2390 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2391 struct rte_eth_dev_data *data = pf->dev_data;
2392 struct rte_pktmbuf_pool_private *mbp_priv =
2393 rte_mempool_get_priv(rxq->mp);
2394 uint16_t buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2395 RTE_PKTMBUF_HEADROOM);
2398 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2399 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2400 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2401 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2402 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2403 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2404 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2405 rxq->hs_mode = i40e_header_split_enabled;
2407 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2409 rxq->rx_hdr_len = 0;
2410 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2411 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2412 rxq->hs_mode = i40e_header_split_none;
2416 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2417 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2418 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2419 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2420 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2421 PMD_DRV_LOG(ERR, "maximum packet length must "
2422 "be larger than %u and smaller than %u,"
2423 "as jumbo frame is enabled",
2424 (uint32_t)ETHER_MAX_LEN,
2425 (uint32_t)I40E_FRAME_SIZE_MAX);
2426 return I40E_ERR_CONFIG;
2429 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2430 rxq->max_pkt_len > ETHER_MAX_LEN) {
2431 PMD_DRV_LOG(ERR, "maximum packet length must be "
2432 "larger than %u and smaller than %u, "
2433 "as jumbo frame is disabled",
2434 (uint32_t)ETHER_MIN_LEN,
2435 (uint32_t)ETHER_MAX_LEN);
2436 return I40E_ERR_CONFIG;
2443 /* Init the RX queue in hardware */
2445 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2447 int err = I40E_SUCCESS;
2448 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2449 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2450 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2451 uint16_t pf_q = rxq->reg_idx;
2453 struct i40e_hmc_obj_rxq rx_ctx;
2454 struct rte_pktmbuf_pool_private *mbp_priv;
2456 err = i40e_rx_queue_config(rxq);
2458 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2462 /* Clear the context structure first */
2463 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2464 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2465 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2467 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2468 rx_ctx.qlen = rxq->nb_rx_desc;
2469 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2472 rx_ctx.dtype = rxq->hs_mode;
2474 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2476 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2477 rx_ctx.rxmax = rxq->max_pkt_len;
2478 rx_ctx.tphrdesc_ena = 1;
2479 rx_ctx.tphwdesc_ena = 1;
2480 rx_ctx.tphdata_ena = 1;
2481 rx_ctx.tphhead_ena = 1;
2482 rx_ctx.lrxqthresh = 2;
2483 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2488 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2489 if (err != I40E_SUCCESS) {
2490 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2493 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2494 if (err != I40E_SUCCESS) {
2495 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2499 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2501 mbp_priv = rte_mempool_get_priv(rxq->mp);
2502 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2503 RTE_PKTMBUF_HEADROOM);
2505 /* Check if scattered RX needs to be used. */
2506 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2507 dev_data->scattered_rx = 1;
2508 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2511 /* Init the RX tail regieter. */
2512 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2518 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2522 PMD_INIT_FUNC_TRACE();
2524 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2525 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2526 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2529 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2530 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2531 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2535 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2536 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2538 enum i40e_status_code
2539 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2541 struct i40e_tx_queue *txq;
2542 const struct rte_memzone *tz = NULL;
2544 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2547 PMD_DRV_LOG(ERR, "PF is not available");
2548 return I40E_ERR_BAD_PTR;
2551 /* Allocate the TX queue data structure. */
2552 txq = rte_zmalloc_socket("i40e fdir tx queue",
2553 sizeof(struct i40e_tx_queue),
2554 RTE_CACHE_LINE_SIZE,
2557 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2558 "tx queue structure.");
2559 return I40E_ERR_NO_MEMORY;
2562 /* Allocate TX hardware ring descriptors. */
2563 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2564 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2566 tz = i40e_ring_dma_zone_reserve(dev,
2572 i40e_dev_tx_queue_release(txq);
2573 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2574 return I40E_ERR_NO_MEMORY;
2577 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2578 txq->queue_id = I40E_FDIR_QUEUE_ID;
2579 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2580 txq->vsi = pf->fdir.fdir_vsi;
2582 #ifdef RTE_LIBRTE_XEN_DOM0
2583 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2585 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2587 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2589 * don't need to allocate software ring and reset for the fdir
2590 * program queue just set the queue has been configured.
2595 return I40E_SUCCESS;
2598 enum i40e_status_code
2599 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2601 struct i40e_rx_queue *rxq;
2602 const struct rte_memzone *rz = NULL;
2604 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2607 PMD_DRV_LOG(ERR, "PF is not available");
2608 return I40E_ERR_BAD_PTR;
2611 /* Allocate the RX queue data structure. */
2612 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2613 sizeof(struct i40e_rx_queue),
2614 RTE_CACHE_LINE_SIZE,
2617 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2618 "rx queue structure.");
2619 return I40E_ERR_NO_MEMORY;
2622 /* Allocate RX hardware ring descriptors. */
2623 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2624 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2626 rz = i40e_ring_dma_zone_reserve(dev,
2632 i40e_dev_rx_queue_release(rxq);
2633 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2634 return I40E_ERR_NO_MEMORY;
2637 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2638 rxq->queue_id = I40E_FDIR_QUEUE_ID;
2639 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2640 rxq->vsi = pf->fdir.fdir_vsi;
2642 #ifdef RTE_LIBRTE_XEN_DOM0
2643 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2645 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
2647 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2650 * Don't need to allocate software ring and reset for the fdir
2651 * rx queue, just set the queue has been configured.
2656 return I40E_SUCCESS;