4 * Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/queue.h>
44 #include <rte_string_fns.h>
45 #include <rte_memzone.h>
47 #include <rte_malloc.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
54 #include "i40e_logs.h"
55 #include "i40e/i40e_prototype.h"
56 #include "i40e/i40e_type.h"
57 #include "i40e_ethdev.h"
58 #include "i40e_rxtx.h"
60 #define I40E_MIN_RING_DESC 64
61 #define I40E_MAX_RING_DESC 4096
62 #define I40E_ALIGN 128
63 #define DEFAULT_TX_RS_THRESH 32
64 #define DEFAULT_TX_FREE_THRESH 32
65 #define I40E_MAX_PKT_TYPE 256
67 #define I40E_VLAN_TAG_SIZE 4
68 #define I40E_TX_MAX_BURST 32
70 #define I40E_DMA_MEM_ALIGN 4096
72 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
73 ETH_TXQ_FLAGS_NOOFFLOADS)
75 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
77 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
78 (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
80 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
81 ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
83 static const struct rte_memzone *
84 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
85 const char *ring_name,
89 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
90 struct rte_mbuf **tx_pkts,
93 /* Translate the rx descriptor status to pkt flags */
94 static inline uint64_t
95 i40e_rxd_status_to_pkt_flags(uint64_t qword)
99 /* Check if VLAN packet */
100 flags = qword & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
103 /* Check if RSS_HASH */
104 flags |= (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
105 I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
106 I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
108 /* Check if FDIR Match */
109 flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
115 static inline uint64_t
116 i40e_rxd_error_to_pkt_flags(uint64_t qword)
119 uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
121 #define I40E_RX_ERR_BITS 0x3f
122 if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
124 /* If RXE bit set, all other status bits are meaningless */
125 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
126 flags |= PKT_RX_MAC_ERR;
130 /* If RECIPE bit set, all other status indications should be ignored */
131 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
132 flags |= PKT_RX_RECIP_ERR;
135 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
136 flags |= PKT_RX_HBUF_OVERFLOW;
137 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
138 flags |= PKT_RX_IP_CKSUM_BAD;
139 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
140 flags |= PKT_RX_L4_CKSUM_BAD;
141 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
142 flags |= PKT_RX_EIP_CKSUM_BAD;
143 if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
144 flags |= PKT_RX_OVERSIZE;
149 /* Translate pkt types to pkt flags */
150 static inline uint64_t
151 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
153 uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
154 I40E_RXD_QW1_PTYPE_SHIFT);
155 static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
178 PKT_RX_IPV4_HDR, /* PTYPE 22 */
179 PKT_RX_IPV4_HDR, /* PTYPE 23 */
180 PKT_RX_IPV4_HDR, /* PTYPE 24 */
182 PKT_RX_IPV4_HDR, /* PTYPE 26 */
183 PKT_RX_IPV4_HDR, /* PTYPE 27 */
184 PKT_RX_IPV4_HDR, /* PTYPE 28 */
185 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
186 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
187 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
189 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
190 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
191 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
192 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
193 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
194 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
196 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
197 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
198 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
199 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
200 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
201 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
202 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
204 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
205 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
206 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
207 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
208 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
209 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
211 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
212 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
213 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
214 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
215 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 59 */
216 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 60 */
217 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 61 */
219 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 63 */
220 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 64 */
221 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 65 */
222 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 66 */
223 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 67 */
224 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 68 */
226 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 70 */
227 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 71 */
228 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 72 */
229 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 73 */
230 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 74 */
231 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 75 */
232 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 76 */
234 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 78 */
235 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 79 */
236 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 80 */
237 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 81 */
238 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 82 */
239 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 83 */
241 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 85 */
242 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 86 */
243 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
244 PKT_RX_IPV6_HDR, /* PTYPE 88 */
245 PKT_RX_IPV6_HDR, /* PTYPE 89 */
246 PKT_RX_IPV6_HDR, /* PTYPE 90 */
248 PKT_RX_IPV6_HDR, /* PTYPE 92 */
249 PKT_RX_IPV6_HDR, /* PTYPE 93 */
250 PKT_RX_IPV6_HDR, /* PTYPE 94 */
251 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
252 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
253 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
255 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
256 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
257 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
258 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
259 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
260 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
262 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
263 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
264 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
265 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
266 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
267 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
268 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
270 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
271 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
272 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
273 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
274 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
275 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
277 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
278 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
279 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
280 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
281 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 125 */
282 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 126 */
283 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 127 */
285 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 129 */
286 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 130 */
287 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 131 */
288 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 132 */
289 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 133 */
290 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 134 */
292 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 136 */
293 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 137 */
294 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 138 */
295 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 139 */
296 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 140 */
297 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 141 */
298 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 142 */
300 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 144 */
301 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 145 */
302 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 146 */
303 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 147 */
304 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 148 */
305 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 149 */
307 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 151 */
308 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 152 */
309 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
414 return ip_ptype_map[ptype];
417 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK 0x03
418 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID 0x01
419 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX 0x02
420 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK 0x03
421 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX 0x01
423 static inline uint64_t
424 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
427 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
428 uint16_t flexbh, flexbl;
430 flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
431 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
432 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
433 flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
434 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
435 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
438 if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
440 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
441 flags |= PKT_RX_FDIR_ID;
442 } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
444 rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
445 flags |= PKT_RX_FDIR_FLX;
447 if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
449 rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
450 flags |= PKT_RX_FDIR_FLX;
454 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
455 flags |= PKT_RX_FDIR_ID;
460 i40e_txd_enable_checksum(uint64_t ol_flags,
465 uint8_t inner_l2_len,
466 uint16_t inner_l3_len,
467 uint32_t *cd_tunneling)
470 PMD_DRV_LOG(DEBUG, "L2 length set to 0");
473 *td_offset |= (l2_len >> 1) << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
476 PMD_DRV_LOG(DEBUG, "L3 length set to 0");
480 /* VXLAN packet TX checksum offload */
481 if (unlikely(ol_flags & PKT_TX_UDP_TUNNEL_PKT)) {
484 l4tun_len = ETHER_VXLAN_HLEN + inner_l2_len;
486 if (ol_flags & PKT_TX_IPV4_CSUM)
487 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
488 else if (ol_flags & PKT_TX_IPV6)
489 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
491 /* Now set the ctx descriptor fields */
492 *cd_tunneling |= (l3_len >> 2) <<
493 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
494 I40E_TXD_CTX_UDP_TUNNELING |
496 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
498 l3_len = inner_l3_len;
501 /* Enable L3 checksum offloads */
502 if (ol_flags & PKT_TX_IPV4_CSUM) {
503 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
504 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
505 } else if (ol_flags & PKT_TX_IPV4) {
506 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
507 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
508 } else if (ol_flags & PKT_TX_IPV6) {
509 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
510 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
513 /* Enable L4 checksum offloads */
514 switch (ol_flags & PKT_TX_L4_MASK) {
515 case PKT_TX_TCP_CKSUM:
516 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
517 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
518 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
520 case PKT_TX_SCTP_CKSUM:
521 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
522 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
523 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
525 case PKT_TX_UDP_CKSUM:
526 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
527 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
528 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
535 static inline struct rte_mbuf *
536 rte_rxmbuf_alloc(struct rte_mempool *mp)
540 m = __rte_mbuf_raw_alloc(mp);
541 __rte_mbuf_sanity_check_raw(m, 0);
546 /* Construct the tx flags */
547 static inline uint64_t
548 i40e_build_ctob(uint32_t td_cmd,
553 return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
554 ((uint64_t)td_cmd << I40E_TXD_QW1_CMD_SHIFT) |
555 ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
556 ((uint64_t)size << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
557 ((uint64_t)td_tag << I40E_TXD_QW1_L2TAG1_SHIFT));
561 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
563 struct i40e_tx_entry *sw_ring = txq->sw_ring;
564 volatile struct i40e_tx_desc *txd = txq->tx_ring;
565 uint16_t last_desc_cleaned = txq->last_desc_cleaned;
566 uint16_t nb_tx_desc = txq->nb_tx_desc;
567 uint16_t desc_to_clean_to;
568 uint16_t nb_tx_to_clean;
570 desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
571 if (desc_to_clean_to >= nb_tx_desc)
572 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
574 desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
575 if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
576 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) {
577 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
578 "(port=%d queue=%d)", desc_to_clean_to,
579 txq->port_id, txq->queue_id);
583 if (last_desc_cleaned > desc_to_clean_to)
584 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
587 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
590 txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
592 txq->last_desc_cleaned = desc_to_clean_to;
593 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
599 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
600 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
602 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
607 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
608 if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
609 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
610 "rxq->rx_free_thresh=%d, "
611 "RTE_PMD_I40E_RX_MAX_BURST=%d",
612 rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
614 } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
615 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
616 "rxq->rx_free_thresh=%d, "
617 "rxq->nb_rx_desc=%d",
618 rxq->rx_free_thresh, rxq->nb_rx_desc);
620 } else if (!(rxq->nb_rx_desc % rxq->rx_free_thresh) == 0) {
621 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
622 "rxq->nb_rx_desc=%d, "
623 "rxq->rx_free_thresh=%d",
624 rxq->nb_rx_desc, rxq->rx_free_thresh);
626 } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
627 RTE_PMD_I40E_RX_MAX_BURST))) {
628 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
629 "rxq->nb_rx_desc=%d, "
630 "I40E_MAX_RING_DESC=%d, "
631 "RTE_PMD_I40E_RX_MAX_BURST=%d",
632 rxq->nb_rx_desc, I40E_MAX_RING_DESC,
633 RTE_PMD_I40E_RX_MAX_BURST);
643 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
644 #define I40E_LOOK_AHEAD 8
645 #if (I40E_LOOK_AHEAD != 8)
646 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
649 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
651 volatile union i40e_rx_desc *rxdp;
652 struct i40e_rx_entry *rxep;
657 int32_t s[I40E_LOOK_AHEAD], nb_dd;
658 int32_t i, j, nb_rx = 0;
661 rxdp = &rxq->rx_ring[rxq->rx_tail];
662 rxep = &rxq->sw_ring[rxq->rx_tail];
664 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
665 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
666 I40E_RXD_QW1_STATUS_SHIFT;
668 /* Make sure there is at least 1 packet to receive */
669 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
673 * Scan LOOK_AHEAD descriptors at a time to determine which
674 * descriptors reference packets that are ready to be received.
676 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
677 rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
678 /* Read desc statuses backwards to avoid race condition */
679 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
680 qword1 = rte_le_to_cpu_64(\
681 rxdp[j].wb.qword1.status_error_len);
682 s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
683 I40E_RXD_QW1_STATUS_SHIFT;
686 /* Compute how many status bits were set */
687 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
688 nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
692 /* Translate descriptor info to mbuf parameters */
693 for (j = 0; j < nb_dd; j++) {
695 qword1 = rte_le_to_cpu_64(\
696 rxdp[j].wb.qword1.status_error_len);
697 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
698 I40E_RXD_QW1_STATUS_SHIFT;
699 pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
700 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
701 mb->data_len = pkt_len;
702 mb->pkt_len = pkt_len;
703 mb->vlan_tci = rx_status &
704 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
706 rxdp[j].wb.qword0.lo_dword.l2tag1) : 0;
707 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
708 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
709 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
711 mb->packet_type = (uint16_t)((qword1 &
712 I40E_RXD_QW1_PTYPE_MASK) >>
713 I40E_RXD_QW1_PTYPE_SHIFT);
714 if (pkt_flags & PKT_RX_RSS_HASH)
715 mb->hash.rss = rte_le_to_cpu_32(\
716 rxdp[j].wb.qword0.hi_dword.rss);
717 if (pkt_flags & PKT_RX_FDIR)
718 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
720 mb->ol_flags = pkt_flags;
723 for (j = 0; j < I40E_LOOK_AHEAD; j++)
724 rxq->rx_stage[i + j] = rxep[j].mbuf;
726 if (nb_dd != I40E_LOOK_AHEAD)
730 /* Clear software ring entries */
731 for (i = 0; i < nb_rx; i++)
732 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
737 static inline uint16_t
738 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
739 struct rte_mbuf **rx_pkts,
743 struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
745 nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
747 for (i = 0; i < nb_pkts; i++)
748 rx_pkts[i] = stage[i];
750 rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
751 rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
757 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
759 volatile union i40e_rx_desc *rxdp;
760 struct i40e_rx_entry *rxep;
762 uint16_t alloc_idx, i;
766 /* Allocate buffers in bulk */
767 alloc_idx = (uint16_t)(rxq->rx_free_trigger -
768 (rxq->rx_free_thresh - 1));
769 rxep = &(rxq->sw_ring[alloc_idx]);
770 diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
771 rxq->rx_free_thresh);
772 if (unlikely(diag != 0)) {
773 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
777 rxdp = &rxq->rx_ring[alloc_idx];
778 for (i = 0; i < rxq->rx_free_thresh; i++) {
780 rte_mbuf_refcnt_set(mb, 1);
782 mb->data_off = RTE_PKTMBUF_HEADROOM;
784 mb->port = rxq->port_id;
785 dma_addr = rte_cpu_to_le_64(\
786 RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
787 rxdp[i].read.hdr_addr = dma_addr;
788 rxdp[i].read.pkt_addr = dma_addr;
791 /* Update rx tail regsiter */
793 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
795 rxq->rx_free_trigger =
796 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
797 if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
798 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
803 static inline uint16_t
804 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
806 struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
812 if (rxq->rx_nb_avail)
813 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
815 nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
816 rxq->rx_next_avail = 0;
817 rxq->rx_nb_avail = nb_rx;
818 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
820 if (rxq->rx_tail > rxq->rx_free_trigger) {
821 if (i40e_rx_alloc_bufs(rxq) != 0) {
824 PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
825 "port_id=%u, queue_id=%u",
826 rxq->port_id, rxq->queue_id);
827 rxq->rx_nb_avail = 0;
828 rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
829 for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
830 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
836 if (rxq->rx_tail >= rxq->nb_rx_desc)
839 if (rxq->rx_nb_avail)
840 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
846 i40e_recv_pkts_bulk_alloc(void *rx_queue,
847 struct rte_mbuf **rx_pkts,
850 uint16_t nb_rx = 0, n, count;
852 if (unlikely(nb_pkts == 0))
855 if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
856 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
859 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
860 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
861 nb_rx = (uint16_t)(nb_rx + count);
862 nb_pkts = (uint16_t)(nb_pkts - count);
869 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
872 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
874 struct i40e_rx_queue *rxq;
875 volatile union i40e_rx_desc *rx_ring;
876 volatile union i40e_rx_desc *rxdp;
877 union i40e_rx_desc rxd;
878 struct i40e_rx_entry *sw_ring;
879 struct i40e_rx_entry *rxe;
880 struct rte_mbuf *rxm;
881 struct rte_mbuf *nmb;
885 uint16_t rx_packet_len;
886 uint16_t rx_id, nb_hold;
893 rx_id = rxq->rx_tail;
894 rx_ring = rxq->rx_ring;
895 sw_ring = rxq->sw_ring;
897 while (nb_rx < nb_pkts) {
898 rxdp = &rx_ring[rx_id];
899 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
900 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
901 >> I40E_RXD_QW1_STATUS_SHIFT;
902 /* Check the DD bit first */
903 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
906 nmb = rte_rxmbuf_alloc(rxq->mp);
912 rxe = &sw_ring[rx_id];
914 if (unlikely(rx_id == rxq->nb_rx_desc))
917 /* Prefetch next mbuf */
918 rte_prefetch0(sw_ring[rx_id].mbuf);
921 * When next RX descriptor is on a cache line boundary,
922 * prefetch the next 4 RX descriptors and next 8 pointers
925 if ((rx_id & 0x3) == 0) {
926 rte_prefetch0(&rx_ring[rx_id]);
927 rte_prefetch0(&sw_ring[rx_id]);
932 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
933 rxdp->read.hdr_addr = dma_addr;
934 rxdp->read.pkt_addr = dma_addr;
936 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
937 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
939 rxm->data_off = RTE_PKTMBUF_HEADROOM;
940 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
943 rxm->pkt_len = rx_packet_len;
944 rxm->data_len = rx_packet_len;
945 rxm->port = rxq->port_id;
947 rxm->vlan_tci = rx_status &
948 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
949 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
950 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
951 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
952 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
953 rxm->packet_type = (uint16_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >>
954 I40E_RXD_QW1_PTYPE_SHIFT);
955 if (pkt_flags & PKT_RX_RSS_HASH)
957 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
958 if (pkt_flags & PKT_RX_FDIR)
959 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
961 rxm->ol_flags = pkt_flags;
963 rx_pkts[nb_rx++] = rxm;
965 rxq->rx_tail = rx_id;
968 * If the number of free RX descriptors is greater than the RX free
969 * threshold of the queue, advance the receive tail register of queue.
970 * Update that register with the value of the last processed RX
971 * descriptor minus 1.
973 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
974 if (nb_hold > rxq->rx_free_thresh) {
975 rx_id = (uint16_t) ((rx_id == 0) ?
976 (rxq->nb_rx_desc - 1) : (rx_id - 1));
977 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
980 rxq->nb_rx_hold = nb_hold;
986 i40e_recv_scattered_pkts(void *rx_queue,
987 struct rte_mbuf **rx_pkts,
990 struct i40e_rx_queue *rxq = rx_queue;
991 volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
992 volatile union i40e_rx_desc *rxdp;
993 union i40e_rx_desc rxd;
994 struct i40e_rx_entry *sw_ring = rxq->sw_ring;
995 struct i40e_rx_entry *rxe;
996 struct rte_mbuf *first_seg = rxq->pkt_first_seg;
997 struct rte_mbuf *last_seg = rxq->pkt_last_seg;
998 struct rte_mbuf *nmb, *rxm;
999 uint16_t rx_id = rxq->rx_tail;
1000 uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1006 while (nb_rx < nb_pkts) {
1007 rxdp = &rx_ring[rx_id];
1008 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1009 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1010 I40E_RXD_QW1_STATUS_SHIFT;
1011 /* Check the DD bit */
1012 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1015 nmb = rte_rxmbuf_alloc(rxq->mp);
1020 rxe = &sw_ring[rx_id];
1022 if (rx_id == rxq->nb_rx_desc)
1025 /* Prefetch next mbuf */
1026 rte_prefetch0(sw_ring[rx_id].mbuf);
1029 * When next RX descriptor is on a cache line boundary,
1030 * prefetch the next 4 RX descriptors and next 8 pointers
1033 if ((rx_id & 0x3) == 0) {
1034 rte_prefetch0(&rx_ring[rx_id]);
1035 rte_prefetch0(&sw_ring[rx_id]);
1041 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1043 /* Set data buffer address and data length of the mbuf */
1044 rxdp->read.hdr_addr = dma_addr;
1045 rxdp->read.pkt_addr = dma_addr;
1046 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1047 I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1048 rxm->data_len = rx_packet_len;
1049 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1052 * If this is the first buffer of the received packet, set the
1053 * pointer to the first mbuf of the packet and initialize its
1054 * context. Otherwise, update the total length and the number
1055 * of segments of the current scattered packet, and update the
1056 * pointer to the last mbuf of the current packet.
1060 first_seg->nb_segs = 1;
1061 first_seg->pkt_len = rx_packet_len;
1063 first_seg->pkt_len =
1064 (uint16_t)(first_seg->pkt_len +
1066 first_seg->nb_segs++;
1067 last_seg->next = rxm;
1071 * If this is not the last buffer of the received packet,
1072 * update the pointer to the last mbuf of the current scattered
1073 * packet and continue to parse the RX ring.
1075 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1081 * This is the last buffer of the received packet. If the CRC
1082 * is not stripped by the hardware:
1083 * - Subtract the CRC length from the total packet length.
1084 * - If the last buffer only contains the whole CRC or a part
1085 * of it, free the mbuf associated to the last buffer. If part
1086 * of the CRC is also contained in the previous mbuf, subtract
1087 * the length of that CRC part from the data length of the
1091 if (unlikely(rxq->crc_len > 0)) {
1092 first_seg->pkt_len -= ETHER_CRC_LEN;
1093 if (rx_packet_len <= ETHER_CRC_LEN) {
1094 rte_pktmbuf_free_seg(rxm);
1095 first_seg->nb_segs--;
1096 last_seg->data_len =
1097 (uint16_t)(last_seg->data_len -
1098 (ETHER_CRC_LEN - rx_packet_len));
1099 last_seg->next = NULL;
1101 rxm->data_len = (uint16_t)(rx_packet_len -
1105 first_seg->port = rxq->port_id;
1106 first_seg->vlan_tci = (rx_status &
1107 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1108 rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
1109 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1110 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1111 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1112 first_seg->packet_type = (uint16_t)((qword1 &
1113 I40E_RXD_QW1_PTYPE_MASK) >>
1114 I40E_RXD_QW1_PTYPE_SHIFT);
1115 if (pkt_flags & PKT_RX_RSS_HASH)
1117 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1118 if (pkt_flags & PKT_RX_FDIR)
1119 pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1121 first_seg->ol_flags = pkt_flags;
1123 /* Prefetch data of first segment, if configured to do so. */
1124 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1125 first_seg->data_off));
1126 rx_pkts[nb_rx++] = first_seg;
1130 /* Record index of the next RX descriptor to probe. */
1131 rxq->rx_tail = rx_id;
1132 rxq->pkt_first_seg = first_seg;
1133 rxq->pkt_last_seg = last_seg;
1136 * If the number of free RX descriptors is greater than the RX free
1137 * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1138 * register. Update the RDT with the value of the last processed RX
1139 * descriptor minus 1, to guarantee that the RDT register is never
1140 * equal to the RDH register, which creates a "full" ring situtation
1141 * from the hardware point of view.
1143 nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1144 if (nb_hold > rxq->rx_free_thresh) {
1145 rx_id = (uint16_t)(rx_id == 0 ?
1146 (rxq->nb_rx_desc - 1) : (rx_id - 1));
1147 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1150 rxq->nb_rx_hold = nb_hold;
1155 /* Check if the context descriptor is needed for TX offloading */
1156 static inline uint16_t
1157 i40e_calc_context_desc(uint64_t flags)
1159 uint64_t mask = 0ULL;
1161 if (flags | PKT_TX_UDP_TUNNEL_PKT)
1162 mask |= PKT_TX_UDP_TUNNEL_PKT;
1164 #ifdef RTE_LIBRTE_IEEE1588
1165 mask |= PKT_TX_IEEE1588_TMST;
1174 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1176 struct i40e_tx_queue *txq;
1177 struct i40e_tx_entry *sw_ring;
1178 struct i40e_tx_entry *txe, *txn;
1179 volatile struct i40e_tx_desc *txd;
1180 volatile struct i40e_tx_desc *txr;
1181 struct rte_mbuf *tx_pkt;
1182 struct rte_mbuf *m_seg;
1183 uint32_t cd_tunneling_params;
1193 uint8_t inner_l2_len;
1194 uint16_t inner_l3_len;
1199 uint64_t buf_dma_addr;
1202 sw_ring = txq->sw_ring;
1204 tx_id = txq->tx_tail;
1205 txe = &sw_ring[tx_id];
1207 /* Check if the descriptor ring needs to be cleaned. */
1208 if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh)
1209 i40e_xmit_cleanup(txq);
1211 for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1217 tx_pkt = *tx_pkts++;
1218 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1220 ol_flags = tx_pkt->ol_flags;
1221 l2_len = tx_pkt->l2_len;
1222 inner_l2_len = tx_pkt->inner_l2_len;
1223 l3_len = tx_pkt->l3_len;
1224 inner_l3_len = tx_pkt->inner_l3_len;
1226 /* Calculate the number of context descriptors needed. */
1227 nb_ctx = i40e_calc_context_desc(ol_flags);
1230 * The number of descriptors that must be allocated for
1231 * a packet equals to the number of the segments of that
1232 * packet plus 1 context descriptor if needed.
1234 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1235 tx_last = (uint16_t)(tx_id + nb_used - 1);
1238 if (tx_last >= txq->nb_tx_desc)
1239 tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1241 if (nb_used > txq->nb_tx_free) {
1242 if (i40e_xmit_cleanup(txq) != 0) {
1247 if (unlikely(nb_used > txq->tx_rs_thresh)) {
1248 while (nb_used > txq->nb_tx_free) {
1249 if (i40e_xmit_cleanup(txq) != 0) {
1258 /* Descriptor based VLAN insertion */
1259 if (ol_flags & PKT_TX_VLAN_PKT) {
1260 tx_flags |= tx_pkt->vlan_tci <<
1261 I40E_TX_FLAG_L2TAG1_SHIFT;
1262 tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1263 td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1264 td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1265 I40E_TX_FLAG_L2TAG1_SHIFT;
1268 /* Always enable CRC offload insertion */
1269 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1271 /* Enable checksum offloading */
1272 cd_tunneling_params = 0;
1273 i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1274 l2_len, l3_len, inner_l2_len,
1276 &cd_tunneling_params);
1278 if (unlikely(nb_ctx)) {
1279 /* Setup TX context descriptor if required */
1280 volatile struct i40e_tx_context_desc *ctx_txd =
1281 (volatile struct i40e_tx_context_desc *)\
1283 uint16_t cd_l2tag2 = 0;
1284 uint64_t cd_type_cmd_tso_mss =
1285 I40E_TX_DESC_DTYPE_CONTEXT;
1287 txn = &sw_ring[txe->next_id];
1288 RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1289 if (txe->mbuf != NULL) {
1290 rte_pktmbuf_free_seg(txe->mbuf);
1293 #ifdef RTE_LIBRTE_IEEE1588
1294 if (ol_flags & PKT_TX_IEEE1588_TMST)
1295 cd_type_cmd_tso_mss |=
1296 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1297 I40E_TXD_CTX_QW1_CMD_SHIFT);
1299 ctx_txd->tunneling_params =
1300 rte_cpu_to_le_32(cd_tunneling_params);
1301 ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1302 ctx_txd->type_cmd_tso_mss =
1303 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1304 txe->last_id = tx_last;
1305 tx_id = txe->next_id;
1312 txn = &sw_ring[txe->next_id];
1315 rte_pktmbuf_free_seg(txe->mbuf);
1318 /* Setup TX Descriptor */
1319 slen = m_seg->data_len;
1320 buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1321 txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1322 txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1323 td_offset, slen, td_tag);
1324 txe->last_id = tx_last;
1325 tx_id = txe->next_id;
1327 m_seg = m_seg->next;
1328 } while (m_seg != NULL);
1330 /* The last packet data descriptor needs End Of Packet (EOP) */
1331 td_cmd |= I40E_TX_DESC_CMD_EOP;
1332 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1333 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1335 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1336 PMD_TX_FREE_LOG(DEBUG,
1337 "Setting RS bit on TXD id="
1338 "%4u (port=%d queue=%d)",
1339 tx_last, txq->port_id, txq->queue_id);
1341 td_cmd |= I40E_TX_DESC_CMD_RS;
1343 /* Update txq RS bit counters */
1344 txq->nb_tx_used = 0;
1347 txd->cmd_type_offset_bsz |=
1348 rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1349 I40E_TXD_QW1_CMD_SHIFT);
1355 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1356 (unsigned) txq->port_id, (unsigned) txq->queue_id,
1357 (unsigned) tx_id, (unsigned) nb_tx);
1359 I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1360 txq->tx_tail = tx_id;
1365 static inline int __attribute__((always_inline))
1366 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1368 struct i40e_tx_entry *txep;
1371 if (!(txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1372 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)))
1375 txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1377 for (i = 0; i < txq->tx_rs_thresh; i++)
1378 rte_prefetch0((txep + i)->mbuf);
1380 if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1381 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1382 rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1386 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1387 rte_pktmbuf_free_seg(txep->mbuf);
1392 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1393 txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1394 if (txq->tx_next_dd >= txq->nb_tx_desc)
1395 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1397 return txq->tx_rs_thresh;
1400 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1401 I40E_TX_DESC_CMD_EOP)
1403 /* Populate 4 descriptors with data from 4 mbufs */
1405 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1410 for (i = 0; i < 4; i++, txdp++, pkts++) {
1411 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1412 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1413 txdp->cmd_type_offset_bsz =
1414 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1415 (*pkts)->data_len, 0);
1419 /* Populate 1 descriptor with data from 1 mbuf */
1421 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1425 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1426 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1427 txdp->cmd_type_offset_bsz =
1428 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1429 (*pkts)->data_len, 0);
1432 /* Fill hardware descriptor ring with mbuf data */
1434 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1435 struct rte_mbuf **pkts,
1438 volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1439 struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1440 const int N_PER_LOOP = 4;
1441 const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1442 int mainpart, leftover;
1445 mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1446 leftover = (nb_pkts & ((uint32_t) N_PER_LOOP_MASK));
1447 for (i = 0; i < mainpart; i += N_PER_LOOP) {
1448 for (j = 0; j < N_PER_LOOP; ++j) {
1449 (txep + i + j)->mbuf = *(pkts + i + j);
1451 tx4(txdp + i, pkts + i);
1453 if (unlikely(leftover > 0)) {
1454 for (i = 0; i < leftover; ++i) {
1455 (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1456 tx1(txdp + mainpart + i, pkts + mainpart + i);
1461 static inline uint16_t
1462 tx_xmit_pkts(struct i40e_tx_queue *txq,
1463 struct rte_mbuf **tx_pkts,
1466 volatile struct i40e_tx_desc *txr = txq->tx_ring;
1470 * Begin scanning the H/W ring for done descriptors when the number
1471 * of available descriptors drops below tx_free_thresh. For each done
1472 * descriptor, free the associated buffer.
1474 if (txq->nb_tx_free < txq->tx_free_thresh)
1475 i40e_tx_free_bufs(txq);
1477 /* Use available descriptor only */
1478 nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1479 if (unlikely(!nb_pkts))
1482 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1483 if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1484 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1485 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1486 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1487 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1488 I40E_TXD_QW1_CMD_SHIFT);
1489 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1493 /* Fill hardware descriptor ring with mbuf data */
1494 i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1495 txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1497 /* Determin if RS bit needs to be set */
1498 if (txq->tx_tail > txq->tx_next_rs) {
1499 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1500 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1501 I40E_TXD_QW1_CMD_SHIFT);
1503 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1504 if (txq->tx_next_rs >= txq->nb_tx_desc)
1505 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1508 if (txq->tx_tail >= txq->nb_tx_desc)
1511 /* Update the tx tail register */
1513 I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1519 i40e_xmit_pkts_simple(void *tx_queue,
1520 struct rte_mbuf **tx_pkts,
1525 if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1526 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1530 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1533 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1534 &tx_pkts[nb_tx], num);
1535 nb_tx = (uint16_t)(nb_tx + ret);
1536 nb_pkts = (uint16_t)(nb_pkts - ret);
1545 * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1546 * application used, which assume having sequential ones. But from driver's
1547 * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1548 * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1549 * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1550 * use queue_idx from 0 to 95 to access queues, while real queue would be
1551 * different. This function will do a queue mapping to find VSI the queue
1554 static struct i40e_vsi*
1555 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1557 /* the queue in MAIN VSI range */
1558 if (queue_idx < pf->main_vsi->nb_qps)
1559 return pf->main_vsi;
1561 queue_idx -= pf->main_vsi->nb_qps;
1563 /* queue_idx is greater than VMDQ VSIs range */
1564 if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1565 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1569 return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1573 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1575 /* the queue in MAIN VSI range */
1576 if (queue_idx < pf->main_vsi->nb_qps)
1579 /* It's VMDQ queues */
1580 queue_idx -= pf->main_vsi->nb_qps;
1582 if (pf->nb_cfg_vmdq_vsi)
1583 return queue_idx % pf->vmdq_nb_qps;
1585 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1586 return (uint16_t)(-1);
1591 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1593 struct i40e_rx_queue *rxq;
1595 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1597 PMD_INIT_FUNC_TRACE();
1599 if (rx_queue_id < dev->data->nb_rx_queues) {
1600 rxq = dev->data->rx_queues[rx_queue_id];
1602 err = i40e_alloc_rx_queue_mbufs(rxq);
1604 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1610 /* Init the RX tail regieter. */
1611 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1613 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1616 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1619 i40e_rx_queue_release_mbufs(rxq);
1620 i40e_reset_rx_queue(rxq);
1628 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1630 struct i40e_rx_queue *rxq;
1632 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1634 if (rx_queue_id < dev->data->nb_rx_queues) {
1635 rxq = dev->data->rx_queues[rx_queue_id];
1638 * rx_queue_id is queue id aplication refers to, while
1639 * rxq->reg_idx is the real queue index.
1641 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1644 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1648 i40e_rx_queue_release_mbufs(rxq);
1649 i40e_reset_rx_queue(rxq);
1656 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1659 struct i40e_tx_queue *txq;
1660 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1662 PMD_INIT_FUNC_TRACE();
1664 if (tx_queue_id < dev->data->nb_tx_queues) {
1665 txq = dev->data->tx_queues[tx_queue_id];
1668 * tx_queue_id is queue id aplication refers to, while
1669 * rxq->reg_idx is the real queue index.
1671 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1673 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1681 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1683 struct i40e_tx_queue *txq;
1685 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1687 if (tx_queue_id < dev->data->nb_tx_queues) {
1688 txq = dev->data->tx_queues[tx_queue_id];
1691 * tx_queue_id is queue id aplication refers to, while
1692 * txq->reg_idx is the real queue index.
1694 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1697 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1702 i40e_tx_queue_release_mbufs(txq);
1703 i40e_reset_tx_queue(txq);
1710 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1713 unsigned int socket_id,
1714 const struct rte_eth_rxconf *rx_conf,
1715 struct rte_mempool *mp)
1717 struct i40e_vsi *vsi;
1718 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1719 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1720 struct i40e_rx_queue *rxq;
1721 const struct rte_memzone *rz;
1724 int use_def_burst_func = 1;
1726 if (hw->mac.type == I40E_MAC_VF) {
1727 struct i40e_vf *vf =
1728 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1731 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1734 PMD_DRV_LOG(ERR, "VSI not available or queue "
1735 "index exceeds the maximum");
1736 return I40E_ERR_PARAM;
1738 if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1739 (nb_desc > I40E_MAX_RING_DESC) ||
1740 (nb_desc < I40E_MIN_RING_DESC)) {
1741 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1742 "invalid", nb_desc);
1743 return I40E_ERR_PARAM;
1746 /* Free memory if needed */
1747 if (dev->data->rx_queues[queue_idx]) {
1748 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1749 dev->data->rx_queues[queue_idx] = NULL;
1752 /* Allocate the rx queue data structure */
1753 rxq = rte_zmalloc_socket("i40e rx queue",
1754 sizeof(struct i40e_rx_queue),
1755 RTE_CACHE_LINE_SIZE,
1758 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1759 "rx queue data structure");
1763 rxq->nb_rx_desc = nb_desc;
1764 rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1765 rxq->queue_id = queue_idx;
1766 if (hw->mac.type == I40E_MAC_VF)
1767 rxq->reg_idx = queue_idx;
1768 else /* PF device */
1769 rxq->reg_idx = vsi->base_queue +
1770 i40e_get_queue_offset_by_qindex(pf, queue_idx);
1772 rxq->port_id = dev->data->port_id;
1773 rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1775 rxq->drop_en = rx_conf->rx_drop_en;
1777 rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1779 /* Allocate the maximun number of RX ring hardware descriptor. */
1780 ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1781 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1782 rz = i40e_ring_dma_zone_reserve(dev,
1788 i40e_dev_rx_queue_release(rxq);
1789 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1793 /* Zero all the descriptors in the ring. */
1794 memset(rz->addr, 0, ring_size);
1796 #ifdef RTE_LIBRTE_XEN_DOM0
1797 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1799 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1802 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1804 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1805 len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1810 /* Allocate the software ring. */
1812 rte_zmalloc_socket("i40e rx sw ring",
1813 sizeof(struct i40e_rx_entry) * len,
1814 RTE_CACHE_LINE_SIZE,
1816 if (!rxq->sw_ring) {
1817 i40e_dev_rx_queue_release(rxq);
1818 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1822 i40e_reset_rx_queue(rxq);
1824 dev->data->rx_queues[queue_idx] = rxq;
1826 use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1828 if (!use_def_burst_func && !dev->data->scattered_rx) {
1829 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1830 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1831 "satisfied. Rx Burst Bulk Alloc function will be "
1832 "used on port=%d, queue=%d.",
1833 rxq->port_id, rxq->queue_id);
1834 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1835 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1837 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1838 "not satisfied, Scattered Rx is requested, "
1839 "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1840 "not enabled on port=%d, queue=%d.",
1841 rxq->port_id, rxq->queue_id);
1848 i40e_dev_rx_queue_release(void *rxq)
1850 struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1853 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1857 i40e_rx_queue_release_mbufs(q);
1858 rte_free(q->sw_ring);
1863 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1865 #define I40E_RXQ_SCAN_INTERVAL 4
1866 volatile union i40e_rx_desc *rxdp;
1867 struct i40e_rx_queue *rxq;
1870 if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1871 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1875 rxq = dev->data->rx_queues[rx_queue_id];
1876 rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1877 while ((desc < rxq->nb_rx_desc) &&
1878 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1879 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1880 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1882 * Check the DD bit of a rx descriptor of each 4 in a group,
1883 * to avoid checking too frequently and downgrading performance
1886 desc += I40E_RXQ_SCAN_INTERVAL;
1887 rxdp += I40E_RXQ_SCAN_INTERVAL;
1888 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1889 rxdp = &(rxq->rx_ring[rxq->rx_tail +
1890 desc - rxq->nb_rx_desc]);
1897 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1899 volatile union i40e_rx_desc *rxdp;
1900 struct i40e_rx_queue *rxq = rx_queue;
1904 if (unlikely(offset >= rxq->nb_rx_desc)) {
1905 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1909 desc = rxq->rx_tail + offset;
1910 if (desc >= rxq->nb_rx_desc)
1911 desc -= rxq->nb_rx_desc;
1913 rxdp = &(rxq->rx_ring[desc]);
1915 ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1916 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1917 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1923 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1926 unsigned int socket_id,
1927 const struct rte_eth_txconf *tx_conf)
1929 struct i40e_vsi *vsi;
1930 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1931 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1932 struct i40e_tx_queue *txq;
1933 const struct rte_memzone *tz;
1935 uint16_t tx_rs_thresh, tx_free_thresh;
1937 if (hw->mac.type == I40E_MAC_VF) {
1938 struct i40e_vf *vf =
1939 I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1942 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1945 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1946 "exceeds the maximum", queue_idx);
1947 return I40E_ERR_PARAM;
1950 if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
1951 (nb_desc > I40E_MAX_RING_DESC) ||
1952 (nb_desc < I40E_MIN_RING_DESC)) {
1953 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1954 "invalid", nb_desc);
1955 return I40E_ERR_PARAM;
1959 * The following two parameters control the setting of the RS bit on
1960 * transmit descriptors. TX descriptors will have their RS bit set
1961 * after txq->tx_rs_thresh descriptors have been used. The TX
1962 * descriptor ring will be cleaned after txq->tx_free_thresh
1963 * descriptors are used or if the number of descriptors required to
1964 * transmit a packet is greater than the number of free TX descriptors.
1966 * The following constraints must be satisfied:
1967 * - tx_rs_thresh must be greater than 0.
1968 * - tx_rs_thresh must be less than the size of the ring minus 2.
1969 * - tx_rs_thresh must be less than or equal to tx_free_thresh.
1970 * - tx_rs_thresh must be a divisor of the ring size.
1971 * - tx_free_thresh must be greater than 0.
1972 * - tx_free_thresh must be less than the size of the ring minus 3.
1974 * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1975 * race condition, hence the maximum threshold constraints. When set
1976 * to zero use default values.
1978 tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1979 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1980 tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1981 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1982 if (tx_rs_thresh >= (nb_desc - 2)) {
1983 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1984 "number of TX descriptors minus 2. "
1985 "(tx_rs_thresh=%u port=%d queue=%d)",
1986 (unsigned int)tx_rs_thresh,
1987 (int)dev->data->port_id,
1989 return I40E_ERR_PARAM;
1991 if (tx_free_thresh >= (nb_desc - 3)) {
1992 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1993 "tx_free_thresh must be less than the "
1994 "number of TX descriptors minus 3. "
1995 "(tx_free_thresh=%u port=%d queue=%d)",
1996 (unsigned int)tx_free_thresh,
1997 (int)dev->data->port_id,
1999 return I40E_ERR_PARAM;
2001 if (tx_rs_thresh > tx_free_thresh) {
2002 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2003 "equal to tx_free_thresh. (tx_free_thresh=%u"
2004 " tx_rs_thresh=%u port=%d queue=%d)",
2005 (unsigned int)tx_free_thresh,
2006 (unsigned int)tx_rs_thresh,
2007 (int)dev->data->port_id,
2009 return I40E_ERR_PARAM;
2011 if ((nb_desc % tx_rs_thresh) != 0) {
2012 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2013 "number of TX descriptors. (tx_rs_thresh=%u"
2014 " port=%d queue=%d)",
2015 (unsigned int)tx_rs_thresh,
2016 (int)dev->data->port_id,
2018 return I40E_ERR_PARAM;
2020 if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2021 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2022 "tx_rs_thresh is greater than 1. "
2023 "(tx_rs_thresh=%u port=%d queue=%d)",
2024 (unsigned int)tx_rs_thresh,
2025 (int)dev->data->port_id,
2027 return I40E_ERR_PARAM;
2030 /* Free memory if needed. */
2031 if (dev->data->tx_queues[queue_idx]) {
2032 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2033 dev->data->tx_queues[queue_idx] = NULL;
2036 /* Allocate the TX queue data structure. */
2037 txq = rte_zmalloc_socket("i40e tx queue",
2038 sizeof(struct i40e_tx_queue),
2039 RTE_CACHE_LINE_SIZE,
2042 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2043 "tx queue structure");
2047 /* Allocate TX hardware ring descriptors. */
2048 ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2049 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2050 tz = i40e_ring_dma_zone_reserve(dev,
2056 i40e_dev_tx_queue_release(txq);
2057 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2061 txq->nb_tx_desc = nb_desc;
2062 txq->tx_rs_thresh = tx_rs_thresh;
2063 txq->tx_free_thresh = tx_free_thresh;
2064 txq->pthresh = tx_conf->tx_thresh.pthresh;
2065 txq->hthresh = tx_conf->tx_thresh.hthresh;
2066 txq->wthresh = tx_conf->tx_thresh.wthresh;
2067 txq->queue_id = queue_idx;
2068 if (hw->mac.type == I40E_MAC_VF)
2069 txq->reg_idx = queue_idx;
2070 else /* PF device */
2071 txq->reg_idx = vsi->base_queue +
2072 i40e_get_queue_offset_by_qindex(pf, queue_idx);
2074 txq->port_id = dev->data->port_id;
2075 txq->txq_flags = tx_conf->txq_flags;
2077 txq->tx_deferred_start = tx_conf->tx_deferred_start;
2079 #ifdef RTE_LIBRTE_XEN_DOM0
2080 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2082 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2084 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2086 /* Allocate software ring */
2088 rte_zmalloc_socket("i40e tx sw ring",
2089 sizeof(struct i40e_tx_entry) * nb_desc,
2090 RTE_CACHE_LINE_SIZE,
2092 if (!txq->sw_ring) {
2093 i40e_dev_tx_queue_release(txq);
2094 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2098 i40e_reset_tx_queue(txq);
2100 dev->data->tx_queues[queue_idx] = txq;
2102 /* Use a simple TX queue without offloads or multi segs if possible */
2103 if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
2104 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
2105 PMD_INIT_LOG(INFO, "Using simple tx path");
2106 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2108 PMD_INIT_LOG(INFO, "Using full-featured tx path");
2109 dev->tx_pkt_burst = i40e_xmit_pkts;
2116 i40e_dev_tx_queue_release(void *txq)
2118 struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2121 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2125 i40e_tx_queue_release_mbufs(q);
2126 rte_free(q->sw_ring);
2130 static const struct rte_memzone *
2131 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
2132 const char *ring_name,
2137 char z_name[RTE_MEMZONE_NAMESIZE];
2138 const struct rte_memzone *mz;
2140 snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2141 dev->driver->pci_drv.name, ring_name,
2142 dev->data->port_id, queue_id);
2143 mz = rte_memzone_lookup(z_name);
2147 #ifdef RTE_LIBRTE_XEN_DOM0
2148 return rte_memzone_reserve_bounded(z_name, ring_size,
2149 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2151 return rte_memzone_reserve_aligned(z_name, ring_size,
2152 socket_id, 0, I40E_ALIGN);
2156 const struct rte_memzone *
2157 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2159 const struct rte_memzone *mz = NULL;
2161 mz = rte_memzone_lookup(name);
2164 #ifdef RTE_LIBRTE_XEN_DOM0
2165 mz = rte_memzone_reserve_bounded(name, len,
2166 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2168 mz = rte_memzone_reserve_aligned(name, len,
2169 socket_id, 0, I40E_ALIGN);
2175 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2179 if (!rxq || !rxq->sw_ring) {
2180 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2184 for (i = 0; i < rxq->nb_rx_desc; i++) {
2185 if (rxq->sw_ring[i].mbuf) {
2186 rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2187 rxq->sw_ring[i].mbuf = NULL;
2190 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2191 if (rxq->rx_nb_avail == 0)
2193 for (i = 0; i < rxq->rx_nb_avail; i++) {
2194 struct rte_mbuf *mbuf;
2196 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2197 rte_pktmbuf_free_seg(mbuf);
2199 rxq->rx_nb_avail = 0;
2200 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2204 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2209 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2210 if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2211 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2213 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2214 len = rxq->nb_rx_desc;
2216 for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2217 ((volatile char *)rxq->rx_ring)[i] = 0;
2219 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2220 memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2221 for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2222 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2224 rxq->rx_nb_avail = 0;
2225 rxq->rx_next_avail = 0;
2226 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2227 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2229 rxq->nb_rx_hold = 0;
2230 rxq->pkt_first_seg = NULL;
2231 rxq->pkt_last_seg = NULL;
2235 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2239 if (!txq || !txq->sw_ring) {
2240 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2244 for (i = 0; i < txq->nb_tx_desc; i++) {
2245 if (txq->sw_ring[i].mbuf) {
2246 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2247 txq->sw_ring[i].mbuf = NULL;
2253 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2255 struct i40e_tx_entry *txe;
2256 uint16_t i, prev, size;
2259 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2264 size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2265 for (i = 0; i < size; i++)
2266 ((volatile char *)txq->tx_ring)[i] = 0;
2268 prev = (uint16_t)(txq->nb_tx_desc - 1);
2269 for (i = 0; i < txq->nb_tx_desc; i++) {
2270 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2272 txd->cmd_type_offset_bsz =
2273 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2276 txe[prev].next_id = i;
2280 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2281 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2284 txq->nb_tx_used = 0;
2286 txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2287 txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2290 /* Init the TX queue in hardware */
2292 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2294 enum i40e_status_code err = I40E_SUCCESS;
2295 struct i40e_vsi *vsi = txq->vsi;
2296 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2297 uint16_t pf_q = txq->reg_idx;
2298 struct i40e_hmc_obj_txq tx_ctx;
2301 /* clear the context structure first */
2302 memset(&tx_ctx, 0, sizeof(tx_ctx));
2303 tx_ctx.new_context = 1;
2304 tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2305 tx_ctx.qlen = txq->nb_tx_desc;
2306 tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2307 if (vsi->type == I40E_VSI_FDIR)
2308 tx_ctx.fd_ena = TRUE;
2310 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2311 if (err != I40E_SUCCESS) {
2312 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2316 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2317 if (err != I40E_SUCCESS) {
2318 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2322 /* Now associate this queue with this PCI function */
2323 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2324 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2325 I40E_QTX_CTL_PF_INDX_MASK);
2326 I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2327 I40E_WRITE_FLUSH(hw);
2329 txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2335 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2337 struct i40e_rx_entry *rxe = rxq->sw_ring;
2341 for (i = 0; i < rxq->nb_rx_desc; i++) {
2342 volatile union i40e_rx_desc *rxd;
2343 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2345 if (unlikely(!mbuf)) {
2346 PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2350 rte_mbuf_refcnt_set(mbuf, 1);
2352 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2354 mbuf->port = rxq->port_id;
2357 rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2359 rxd = &rxq->rx_ring[i];
2360 rxd->read.pkt_addr = dma_addr;
2361 rxd->read.hdr_addr = dma_addr;
2362 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2363 rxd->read.rsvd1 = 0;
2364 rxd->read.rsvd2 = 0;
2365 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2374 * Calculate the buffer length, and check the jumbo frame
2375 * and maximum packet length.
2378 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2380 struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2381 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2382 struct rte_eth_dev_data *data = pf->dev_data;
2383 struct rte_pktmbuf_pool_private *mbp_priv =
2384 rte_mempool_get_priv(rxq->mp);
2385 uint16_t buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2386 RTE_PKTMBUF_HEADROOM);
2389 switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2390 I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2391 case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2392 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2393 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2394 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2395 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2396 rxq->hs_mode = i40e_header_split_enabled;
2398 case I40E_FLAG_HEADER_SPLIT_DISABLED:
2400 rxq->rx_hdr_len = 0;
2401 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2402 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2403 rxq->hs_mode = i40e_header_split_none;
2407 len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2408 rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2409 if (data->dev_conf.rxmode.jumbo_frame == 1) {
2410 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2411 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2412 PMD_DRV_LOG(ERR, "maximum packet length must "
2413 "be larger than %u and smaller than %u,"
2414 "as jumbo frame is enabled",
2415 (uint32_t)ETHER_MAX_LEN,
2416 (uint32_t)I40E_FRAME_SIZE_MAX);
2417 return I40E_ERR_CONFIG;
2420 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2421 rxq->max_pkt_len > ETHER_MAX_LEN) {
2422 PMD_DRV_LOG(ERR, "maximum packet length must be "
2423 "larger than %u and smaller than %u, "
2424 "as jumbo frame is disabled",
2425 (uint32_t)ETHER_MIN_LEN,
2426 (uint32_t)ETHER_MAX_LEN);
2427 return I40E_ERR_CONFIG;
2434 /* Init the RX queue in hardware */
2436 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2438 int err = I40E_SUCCESS;
2439 struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2440 struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2441 struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2442 uint16_t pf_q = rxq->reg_idx;
2444 struct i40e_hmc_obj_rxq rx_ctx;
2445 struct rte_pktmbuf_pool_private *mbp_priv;
2447 err = i40e_rx_queue_config(rxq);
2449 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2453 /* Clear the context structure first */
2454 memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2455 rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2456 rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2458 rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2459 rx_ctx.qlen = rxq->nb_rx_desc;
2460 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2463 rx_ctx.dtype = rxq->hs_mode;
2465 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2467 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2468 rx_ctx.rxmax = rxq->max_pkt_len;
2469 rx_ctx.tphrdesc_ena = 1;
2470 rx_ctx.tphwdesc_ena = 1;
2471 rx_ctx.tphdata_ena = 1;
2472 rx_ctx.tphhead_ena = 1;
2473 rx_ctx.lrxqthresh = 2;
2474 rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2479 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2480 if (err != I40E_SUCCESS) {
2481 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2484 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2485 if (err != I40E_SUCCESS) {
2486 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2490 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2492 mbp_priv = rte_mempool_get_priv(rxq->mp);
2493 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2494 RTE_PKTMBUF_HEADROOM);
2496 /* Check if scattered RX needs to be used. */
2497 if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2498 dev_data->scattered_rx = 1;
2499 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2502 /* Init the RX tail regieter. */
2503 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2509 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2513 PMD_INIT_FUNC_TRACE();
2515 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2516 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2517 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2520 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2521 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2522 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2526 #define I40E_FDIR_NUM_TX_DESC I40E_MIN_RING_DESC
2527 #define I40E_FDIR_NUM_RX_DESC I40E_MIN_RING_DESC
2529 enum i40e_status_code
2530 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2532 struct i40e_tx_queue *txq;
2533 const struct rte_memzone *tz = NULL;
2535 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2538 PMD_DRV_LOG(ERR, "PF is not available");
2539 return I40E_ERR_BAD_PTR;
2542 /* Allocate the TX queue data structure. */
2543 txq = rte_zmalloc_socket("i40e fdir tx queue",
2544 sizeof(struct i40e_tx_queue),
2545 RTE_CACHE_LINE_SIZE,
2548 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2549 "tx queue structure.");
2550 return I40E_ERR_NO_MEMORY;
2553 /* Allocate TX hardware ring descriptors. */
2554 ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2555 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2557 tz = i40e_ring_dma_zone_reserve(dev,
2563 i40e_dev_tx_queue_release(txq);
2564 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2565 return I40E_ERR_NO_MEMORY;
2568 txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2569 txq->queue_id = I40E_FDIR_QUEUE_ID;
2570 txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2571 txq->vsi = pf->fdir.fdir_vsi;
2573 #ifdef RTE_LIBRTE_XEN_DOM0
2574 txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2576 txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2578 txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2580 * don't need to allocate software ring and reset for the fdir
2581 * program queue just set the queue has been configured.
2586 return I40E_SUCCESS;
2589 enum i40e_status_code
2590 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2592 struct i40e_rx_queue *rxq;
2593 const struct rte_memzone *rz = NULL;
2595 struct rte_eth_dev *dev = pf->adapter->eth_dev;
2598 PMD_DRV_LOG(ERR, "PF is not available");
2599 return I40E_ERR_BAD_PTR;
2602 /* Allocate the RX queue data structure. */
2603 rxq = rte_zmalloc_socket("i40e fdir rx queue",
2604 sizeof(struct i40e_rx_queue),
2605 RTE_CACHE_LINE_SIZE,
2608 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2609 "rx queue structure.");
2610 return I40E_ERR_NO_MEMORY;
2613 /* Allocate RX hardware ring descriptors. */
2614 ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2615 ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2617 rz = i40e_ring_dma_zone_reserve(dev,
2623 i40e_dev_rx_queue_release(rxq);
2624 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2625 return I40E_ERR_NO_MEMORY;
2628 rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2629 rxq->queue_id = I40E_FDIR_QUEUE_ID;
2630 rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2631 rxq->vsi = pf->fdir.fdir_vsi;
2633 #ifdef RTE_LIBRTE_XEN_DOM0
2634 rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2636 rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
2638 rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2641 * Don't need to allocate software ring and reset for the fdir
2642 * rx queue, just set the queue has been configured.
2647 return I40E_SUCCESS;