lib/librte_pmd_i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2014 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "i40e/i40e_prototype.h"
  56 #include "i40e/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define I40E_MIN_RING_DESC     64
  61 #define I40E_MAX_RING_DESC     4096
  62 #define I40E_ALIGN             128
  63 #define DEFAULT_TX_RS_THRESH   32
  64 #define DEFAULT_TX_FREE_THRESH 32
  65 #define I40E_MAX_PKT_TYPE      256
  66
  67 #define I40E_VLAN_TAG_SIZE 4
  68 #define I40E_TX_MAX_BURST  32
  69
  70 #define I40E_DMA_MEM_ALIGN 4096
  71
  72 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  73                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  74
  75 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  76
  77 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  78                 PKT_TX_IP_CKSUM |                \
  79                 PKT_TX_L4_MASK |                 \
  80                 PKT_TX_OUTER_IP_CKSUM)
  81
  82 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
  83         (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
  84
  85 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
  86         ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
  87
  88 static const struct rte_memzone *
  89 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
  90                            const char *ring_name,
  91                            uint16_t queue_id,
  92                            uint32_t ring_size,
  93                            int socket_id);
  94 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  95                                       struct rte_mbuf **tx_pkts,
  96                                       uint16_t nb_pkts);
  97
  98 /* Translate the rx descriptor status to pkt flags */
  99 static inline uint64_t
 100 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 101 {
 102         uint64_t flags;
 103
 104         /* Check if VLAN packet */
 105         flags = qword & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
 106                                                         PKT_RX_VLAN_PKT : 0;
 107
 108         /* Check if RSS_HASH */
 109         flags |= (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 110                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 111                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 112
 113         /* Check if FDIR Match */
 114         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 115                                                         PKT_RX_FDIR : 0);
 116
 117         return flags;
 118 }
 119
 120 static inline uint64_t
 121 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 122 {
 123         uint64_t flags = 0;
 124         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 125
 126 #define I40E_RX_ERR_BITS 0x3f
 127         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 128                 return flags;
 129         /* If RXE bit set, all other status bits are meaningless */
 130         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 131                 flags |= PKT_RX_MAC_ERR;
 132                 return flags;
 133         }
 134
 135         /* If RECIPE bit set, all other status indications should be ignored */
 136         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
 137                 flags |= PKT_RX_RECIP_ERR;
 138                 return flags;
 139         }
 140         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
 141                 flags |= PKT_RX_HBUF_OVERFLOW;
 142         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 143                 flags |= PKT_RX_IP_CKSUM_BAD;
 144         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 145                 flags |= PKT_RX_L4_CKSUM_BAD;
 146         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 147                 flags |= PKT_RX_EIP_CKSUM_BAD;
 148         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
 149                 flags |= PKT_RX_OVERSIZE;
 150
 151         return flags;
 152 }
 153
 154 /* Translate pkt types to pkt flags */
 155 static inline uint64_t
 156 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
 157 {
 158         uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
 159                                         I40E_RXD_QW1_PTYPE_SHIFT);
 160         static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
 161                 0, /* PTYPE 0 */
 162                 0, /* PTYPE 1 */
 163                 0, /* PTYPE 2 */
 164                 0, /* PTYPE 3 */
 165                 0, /* PTYPE 4 */
 166                 0, /* PTYPE 5 */
 167                 0, /* PTYPE 6 */
 168                 0, /* PTYPE 7 */
 169                 0, /* PTYPE 8 */
 170                 0, /* PTYPE 9 */
 171                 0, /* PTYPE 10 */
 172                 0, /* PTYPE 11 */
 173                 0, /* PTYPE 12 */
 174                 0, /* PTYPE 13 */
 175                 0, /* PTYPE 14 */
 176                 0, /* PTYPE 15 */
 177                 0, /* PTYPE 16 */
 178                 0, /* PTYPE 17 */
 179                 0, /* PTYPE 18 */
 180                 0, /* PTYPE 19 */
 181                 0, /* PTYPE 20 */
 182                 0, /* PTYPE 21 */
 183                 PKT_RX_IPV4_HDR, /* PTYPE 22 */
 184                 PKT_RX_IPV4_HDR, /* PTYPE 23 */
 185                 PKT_RX_IPV4_HDR, /* PTYPE 24 */
 186                 0, /* PTYPE 25 */
 187                 PKT_RX_IPV4_HDR, /* PTYPE 26 */
 188                 PKT_RX_IPV4_HDR, /* PTYPE 27 */
 189                 PKT_RX_IPV4_HDR, /* PTYPE 28 */
 190                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
 191                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
 192                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
 193                 0, /* PTYPE 32 */
 194                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
 195                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
 196                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
 197                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
 198                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
 199                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
 200                 0, /* PTYPE 39 */
 201                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
 202                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
 203                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
 204                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
 205                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
 206                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
 207                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
 208                 0, /* PTYPE 47 */
 209                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
 210                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
 211                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
 212                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
 213                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
 214                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
 215                 0, /* PTYPE 54 */
 216                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
 217                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
 218                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
 219                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
 220                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 59 */
 221                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 60 */
 222                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 61 */
 223                 0, /* PTYPE 62 */
 224                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 63 */
 225                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 64 */
 226                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 65 */
 227                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 66 */
 228                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 67 */
 229                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 68 */
 230                 0, /* PTYPE 69 */
 231                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 70 */
 232                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 71 */
 233                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 72 */
 234                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 73 */
 235                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 74 */
 236                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 75 */
 237                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 76 */
 238                 0, /* PTYPE 77 */
 239                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 78 */
 240                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 79 */
 241                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 80 */
 242                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 81 */
 243                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 82 */
 244                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 83 */
 245                 0, /* PTYPE 84 */
 246                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 85 */
 247                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 86 */
 248                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
 249                 PKT_RX_IPV6_HDR, /* PTYPE 88 */
 250                 PKT_RX_IPV6_HDR, /* PTYPE 89 */
 251                 PKT_RX_IPV6_HDR, /* PTYPE 90 */
 252                 0, /* PTYPE 91 */
 253                 PKT_RX_IPV6_HDR, /* PTYPE 92 */
 254                 PKT_RX_IPV6_HDR, /* PTYPE 93 */
 255                 PKT_RX_IPV6_HDR, /* PTYPE 94 */
 256                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
 257                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
 258                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
 259                 0, /* PTYPE 98 */
 260                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
 261                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
 262                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
 263                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
 264                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
 265                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
 266                 0, /* PTYPE 105 */
 267                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
 268                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
 269                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
 270                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
 271                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
 272                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
 273                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
 274                 0, /* PTYPE 113 */
 275                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
 276                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
 277                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
 278                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
 279                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
 280                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
 281                 0, /* PTYPE 120 */
 282                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
 283                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
 284                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
 285                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
 286                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 125 */
 287                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 126 */
 288                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 127 */
 289                 0, /* PTYPE 128 */
 290                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 129 */
 291                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 130 */
 292                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 131 */
 293                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 132 */
 294                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 133 */
 295                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 134 */
 296                 0, /* PTYPE 135 */
 297                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 136 */
 298                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 137 */
 299                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 138 */
 300                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 139 */
 301                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 140 */
 302                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 141 */
 303                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 142 */
 304                 0, /* PTYPE 143 */
 305                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 144 */
 306                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 145 */
 307                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 146 */
 308                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 147 */
 309                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 148 */
 310                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 149 */
 311                 0, /* PTYPE 150 */
 312                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 151 */
 313                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 152 */
 314                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
 315                 0, /* PTYPE 154 */
 316                 0, /* PTYPE 155 */
 317                 0, /* PTYPE 156 */
 318                 0, /* PTYPE 157 */
 319                 0, /* PTYPE 158 */
 320                 0, /* PTYPE 159 */
 321                 0, /* PTYPE 160 */
 322                 0, /* PTYPE 161 */
 323                 0, /* PTYPE 162 */
 324                 0, /* PTYPE 163 */
 325                 0, /* PTYPE 164 */
 326                 0, /* PTYPE 165 */
 327                 0, /* PTYPE 166 */
 328                 0, /* PTYPE 167 */
 329                 0, /* PTYPE 168 */
 330                 0, /* PTYPE 169 */
 331                 0, /* PTYPE 170 */
 332                 0, /* PTYPE 171 */
 333                 0, /* PTYPE 172 */
 334                 0, /* PTYPE 173 */
 335                 0, /* PTYPE 174 */
 336                 0, /* PTYPE 175 */
 337                 0, /* PTYPE 176 */
 338                 0, /* PTYPE 177 */
 339                 0, /* PTYPE 178 */
 340                 0, /* PTYPE 179 */
 341                 0, /* PTYPE 180 */
 342                 0, /* PTYPE 181 */
 343                 0, /* PTYPE 182 */
 344                 0, /* PTYPE 183 */
 345                 0, /* PTYPE 184 */
 346                 0, /* PTYPE 185 */
 347                 0, /* PTYPE 186 */
 348                 0, /* PTYPE 187 */
 349                 0, /* PTYPE 188 */
 350                 0, /* PTYPE 189 */
 351                 0, /* PTYPE 190 */
 352                 0, /* PTYPE 191 */
 353                 0, /* PTYPE 192 */
 354                 0, /* PTYPE 193 */
 355                 0, /* PTYPE 194 */
 356                 0, /* PTYPE 195 */
 357                 0, /* PTYPE 196 */
 358                 0, /* PTYPE 197 */
 359                 0, /* PTYPE 198 */
 360                 0, /* PTYPE 199 */
 361                 0, /* PTYPE 200 */
 362                 0, /* PTYPE 201 */
 363                 0, /* PTYPE 202 */
 364                 0, /* PTYPE 203 */
 365                 0, /* PTYPE 204 */
 366                 0, /* PTYPE 205 */
 367                 0, /* PTYPE 206 */
 368                 0, /* PTYPE 207 */
 369                 0, /* PTYPE 208 */
 370                 0, /* PTYPE 209 */
 371                 0, /* PTYPE 210 */
 372                 0, /* PTYPE 211 */
 373                 0, /* PTYPE 212 */
 374                 0, /* PTYPE 213 */
 375                 0, /* PTYPE 214 */
 376                 0, /* PTYPE 215 */
 377                 0, /* PTYPE 216 */
 378                 0, /* PTYPE 217 */
 379                 0, /* PTYPE 218 */
 380                 0, /* PTYPE 219 */
 381                 0, /* PTYPE 220 */
 382                 0, /* PTYPE 221 */
 383                 0, /* PTYPE 222 */
 384                 0, /* PTYPE 223 */
 385                 0, /* PTYPE 224 */
 386                 0, /* PTYPE 225 */
 387                 0, /* PTYPE 226 */
 388                 0, /* PTYPE 227 */
 389                 0, /* PTYPE 228 */
 390                 0, /* PTYPE 229 */
 391                 0, /* PTYPE 230 */
 392                 0, /* PTYPE 231 */
 393                 0, /* PTYPE 232 */
 394                 0, /* PTYPE 233 */
 395                 0, /* PTYPE 234 */
 396                 0, /* PTYPE 235 */
 397                 0, /* PTYPE 236 */
 398                 0, /* PTYPE 237 */
 399                 0, /* PTYPE 238 */
 400                 0, /* PTYPE 239 */
 401                 0, /* PTYPE 240 */
 402                 0, /* PTYPE 241 */
 403                 0, /* PTYPE 242 */
 404                 0, /* PTYPE 243 */
 405                 0, /* PTYPE 244 */
 406                 0, /* PTYPE 245 */
 407                 0, /* PTYPE 246 */
 408                 0, /* PTYPE 247 */
 409                 0, /* PTYPE 248 */
 410                 0, /* PTYPE 249 */
 411                 0, /* PTYPE 250 */
 412                 0, /* PTYPE 251 */
 413                 0, /* PTYPE 252 */
 414                 0, /* PTYPE 253 */
 415                 0, /* PTYPE 254 */
 416                 0, /* PTYPE 255 */
 417         };
 418
 419         return ip_ptype_map[ptype];
 420 }
 421
 422 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 423 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 424 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 425 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 426 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 427
 428 static inline uint64_t
 429 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 430 {
 431         uint64_t flags = 0;
 432 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 433         uint16_t flexbh, flexbl;
 434
 435         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 436                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 437                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 438         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 439                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 440                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 441
 442
 443         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 444                 mb->hash.fdir.hi =
 445                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 446                 flags |= PKT_RX_FDIR_ID;
 447         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 448                 mb->hash.fdir.hi =
 449                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 450                 flags |= PKT_RX_FDIR_FLX;
 451         }
 452         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 453                 mb->hash.fdir.lo =
 454                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 455                 flags |= PKT_RX_FDIR_FLX;
 456         }
 457 #else
 458         mb->hash.fdir.hi =
 459                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 460         flags |= PKT_RX_FDIR_ID;
 461 #endif
 462         return flags;
 463 }
 464 static inline void
 465 i40e_txd_enable_checksum(uint64_t ol_flags,
 466                         uint32_t *td_cmd,
 467                         uint32_t *td_offset,
 468                         uint8_t l2_len,
 469                         uint16_t l3_len,
 470                         uint8_t outer_l2_len,
 471                         uint16_t outer_l3_len,
 472                         uint32_t *cd_tunneling)
 473 {
 474         /* UDP tunneling packet TX checksum offload */
 475         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 476
 477                 *td_offset |= (outer_l2_len >> 1)
 478                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 479
 480                 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 481                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 482                 else if (ol_flags & PKT_TX_OUTER_IPV4)
 483                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 484                 else if (ol_flags & PKT_TX_OUTER_IPV6)
 485                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 486
 487                 /* Now set the ctx descriptor fields */
 488                 *cd_tunneling |= (outer_l3_len >> 2) <<
 489                                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
 490                                 (l2_len >> 1) <<
 491                                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 492
 493         } else
 494                 *td_offset |= (l2_len >> 1)
 495                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 496
 497         /* Enable L3 checksum offloads */
 498         if (ol_flags & PKT_TX_IP_CKSUM) {
 499                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 500                 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 501         } else if (ol_flags & PKT_TX_IPV4) {
 502                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 503                 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 504         } else if (ol_flags & PKT_TX_IPV6) {
 505                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 506                 *td_offset |= (l3_len >> 2) << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 507         }
 508
 509         /* Enable L4 checksum offloads */
 510         switch (ol_flags & PKT_TX_L4_MASK) {
 511         case PKT_TX_TCP_CKSUM:
 512                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 513                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 514                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 515                 break;
 516         case PKT_TX_SCTP_CKSUM:
 517                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 518                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 519                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 520                 break;
 521         case PKT_TX_UDP_CKSUM:
 522                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 523                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 524                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 525                 break;
 526         default:
 527                 break;
 528         }
 529 }
 530
 531 static inline struct rte_mbuf *
 532 rte_rxmbuf_alloc(struct rte_mempool *mp)
 533 {
 534         struct rte_mbuf *m;
 535
 536         m = __rte_mbuf_raw_alloc(mp);
 537         __rte_mbuf_sanity_check_raw(m, 0);
 538
 539         return m;
 540 }
 541
 542 /* Construct the tx flags */
 543 static inline uint64_t
 544 i40e_build_ctob(uint32_t td_cmd,
 545                 uint32_t td_offset,
 546                 unsigned int size,
 547                 uint32_t td_tag)
 548 {
 549         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 550                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 551                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 552                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 553                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 554 }
 555
 556 static inline int
 557 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 558 {
 559         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 560         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 561         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 562         uint16_t nb_tx_desc = txq->nb_tx_desc;
 563         uint16_t desc_to_clean_to;
 564         uint16_t nb_tx_to_clean;
 565
 566         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 567         if (desc_to_clean_to >= nb_tx_desc)
 568                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 569
 570         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 571         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
 572                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) {
 573                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 574                         "(port=%d queue=%d)", desc_to_clean_to,
 575                                 txq->port_id, txq->queue_id);
 576                 return -1;
 577         }
 578
 579         if (last_desc_cleaned > desc_to_clean_to)
 580                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 581                                                         desc_to_clean_to);
 582         else
 583                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 584                                         last_desc_cleaned);
 585
 586         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 587
 588         txq->last_desc_cleaned = desc_to_clean_to;
 589         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 590
 591         return 0;
 592 }
 593
 594 static inline int
 595 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 596 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 597 #else
 598 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 599 #endif
 600 {
 601         int ret = 0;
 602
 603 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 604         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 605                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 606                              "rxq->rx_free_thresh=%d, "
 607                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 608                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 609                 ret = -EINVAL;
 610         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 611                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 612                              "rxq->rx_free_thresh=%d, "
 613                              "rxq->nb_rx_desc=%d",
 614                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 615                 ret = -EINVAL;
 616         } else if (!(rxq->nb_rx_desc % rxq->rx_free_thresh) == 0) {
 617                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 618                              "rxq->nb_rx_desc=%d, "
 619                              "rxq->rx_free_thresh=%d",
 620                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 621                 ret = -EINVAL;
 622         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 623                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 624                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 625                              "rxq->nb_rx_desc=%d, "
 626                              "I40E_MAX_RING_DESC=%d, "
 627                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 628                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 629                              RTE_PMD_I40E_RX_MAX_BURST);
 630                 ret = -EINVAL;
 631         }
 632 #else
 633         ret = -EINVAL;
 634 #endif
 635
 636         return ret;
 637 }
 638
 639 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 640 #define I40E_LOOK_AHEAD 8
 641 #if (I40E_LOOK_AHEAD != 8)
 642 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 643 #endif
 644 static inline int
 645 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 646 {
 647         volatile union i40e_rx_desc *rxdp;
 648         struct i40e_rx_entry *rxep;
 649         struct rte_mbuf *mb;
 650         uint16_t pkt_len;
 651         uint64_t qword1;
 652         uint32_t rx_status;
 653         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 654         int32_t i, j, nb_rx = 0;
 655         uint64_t pkt_flags;
 656
 657         rxdp = &rxq->rx_ring[rxq->rx_tail];
 658         rxep = &rxq->sw_ring[rxq->rx_tail];
 659
 660         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 661         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 662                                 I40E_RXD_QW1_STATUS_SHIFT;
 663
 664         /* Make sure there is at least 1 packet to receive */
 665         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 666                 return 0;
 667
 668         /**
 669          * Scan LOOK_AHEAD descriptors at a time to determine which
 670          * descriptors reference packets that are ready to be received.
 671          */
 672         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 673                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 674                 /* Read desc statuses backwards to avoid race condition */
 675                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 676                         qword1 = rte_le_to_cpu_64(\
 677                                 rxdp[j].wb.qword1.status_error_len);
 678                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 679                                         I40E_RXD_QW1_STATUS_SHIFT;
 680                 }
 681
 682                 /* Compute how many status bits were set */
 683                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 684                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 685
 686                 nb_rx += nb_dd;
 687
 688                 /* Translate descriptor info to mbuf parameters */
 689                 for (j = 0; j < nb_dd; j++) {
 690                         mb = rxep[j].mbuf;
 691                         qword1 = rte_le_to_cpu_64(\
 692                                 rxdp[j].wb.qword1.status_error_len);
 693                         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 694                                                 I40E_RXD_QW1_STATUS_SHIFT;
 695                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 696                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 697                         mb->data_len = pkt_len;
 698                         mb->pkt_len = pkt_len;
 699                         mb->vlan_tci = rx_status &
 700                                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
 701                         rte_le_to_cpu_16(\
 702                                 rxdp[j].wb.qword0.lo_dword.l2tag1) : 0;
 703                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 704                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 705                         pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
 706
 707                         mb->packet_type = (uint16_t)((qword1 &
 708                                         I40E_RXD_QW1_PTYPE_MASK) >>
 709                                         I40E_RXD_QW1_PTYPE_SHIFT);
 710                         if (pkt_flags & PKT_RX_RSS_HASH)
 711                                 mb->hash.rss = rte_le_to_cpu_32(\
 712                                         rxdp[j].wb.qword0.hi_dword.rss);
 713                         if (pkt_flags & PKT_RX_FDIR)
 714                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 715
 716                         mb->ol_flags = pkt_flags;
 717                 }
 718
 719                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 720                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 721
 722                 if (nb_dd != I40E_LOOK_AHEAD)
 723                         break;
 724         }
 725
 726         /* Clear software ring entries */
 727         for (i = 0; i < nb_rx; i++)
 728                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 729
 730         return nb_rx;
 731 }
 732
 733 static inline uint16_t
 734 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 735                         struct rte_mbuf **rx_pkts,
 736                         uint16_t nb_pkts)
 737 {
 738         uint16_t i;
 739         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 740
 741         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 742
 743         for (i = 0; i < nb_pkts; i++)
 744                 rx_pkts[i] = stage[i];
 745
 746         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 747         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 748
 749         return nb_pkts;
 750 }
 751
 752 static inline int
 753 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 754 {
 755         volatile union i40e_rx_desc *rxdp;
 756         struct i40e_rx_entry *rxep;
 757         struct rte_mbuf *mb;
 758         uint16_t alloc_idx, i;
 759         uint64_t dma_addr;
 760         int diag;
 761
 762         /* Allocate buffers in bulk */
 763         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 764                                 (rxq->rx_free_thresh - 1));
 765         rxep = &(rxq->sw_ring[alloc_idx]);
 766         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 767                                         rxq->rx_free_thresh);
 768         if (unlikely(diag != 0)) {
 769                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 770                 return -ENOMEM;
 771         }
 772
 773         rxdp = &rxq->rx_ring[alloc_idx];
 774         for (i = 0; i < rxq->rx_free_thresh; i++) {
 775                 mb = rxep[i].mbuf;
 776                 rte_mbuf_refcnt_set(mb, 1);
 777                 mb->next = NULL;
 778                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 779                 mb->nb_segs = 1;
 780                 mb->port = rxq->port_id;
 781                 dma_addr = rte_cpu_to_le_64(\
 782                         RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
 783                 rxdp[i].read.hdr_addr = dma_addr;
 784                 rxdp[i].read.pkt_addr = dma_addr;
 785         }
 786
 787         /* Update rx tail regsiter */
 788         rte_wmb();
 789         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 790
 791         rxq->rx_free_trigger =
 792                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 793         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 794                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 795
 796         return 0;
 797 }
 798
 799 static inline uint16_t
 800 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 801 {
 802         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 803         uint16_t nb_rx = 0;
 804
 805         if (!nb_pkts)
 806                 return 0;
 807
 808         if (rxq->rx_nb_avail)
 809                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 810
 811         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 812         rxq->rx_next_avail = 0;
 813         rxq->rx_nb_avail = nb_rx;
 814         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 815
 816         if (rxq->rx_tail > rxq->rx_free_trigger) {
 817                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 818                         uint16_t i, j;
 819
 820                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
 821                                    "port_id=%u, queue_id=%u",
 822                                    rxq->port_id, rxq->queue_id);
 823                         rxq->rx_nb_avail = 0;
 824                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 825                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 826                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 827
 828                         return 0;
 829                 }
 830         }
 831
 832         if (rxq->rx_tail >= rxq->nb_rx_desc)
 833                 rxq->rx_tail = 0;
 834
 835         if (rxq->rx_nb_avail)
 836                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 837
 838         return 0;
 839 }
 840
 841 static uint16_t
 842 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 843                           struct rte_mbuf **rx_pkts,
 844                           uint16_t nb_pkts)
 845 {
 846         uint16_t nb_rx = 0, n, count;
 847
 848         if (unlikely(nb_pkts == 0))
 849                 return 0;
 850
 851         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 852                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 853
 854         while (nb_pkts) {
 855                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 856                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 857                 nb_rx = (uint16_t)(nb_rx + count);
 858                 nb_pkts = (uint16_t)(nb_pkts - count);
 859                 if (count < n)
 860                         break;
 861         }
 862
 863         return nb_rx;
 864 }
 865 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 866
 867 uint16_t
 868 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 869 {
 870         struct i40e_rx_queue *rxq;
 871         volatile union i40e_rx_desc *rx_ring;
 872         volatile union i40e_rx_desc *rxdp;
 873         union i40e_rx_desc rxd;
 874         struct i40e_rx_entry *sw_ring;
 875         struct i40e_rx_entry *rxe;
 876         struct rte_mbuf *rxm;
 877         struct rte_mbuf *nmb;
 878         uint16_t nb_rx;
 879         uint32_t rx_status;
 880         uint64_t qword1;
 881         uint16_t rx_packet_len;
 882         uint16_t rx_id, nb_hold;
 883         uint64_t dma_addr;
 884         uint64_t pkt_flags;
 885
 886         nb_rx = 0;
 887         nb_hold = 0;
 888         rxq = rx_queue;
 889         rx_id = rxq->rx_tail;
 890         rx_ring = rxq->rx_ring;
 891         sw_ring = rxq->sw_ring;
 892
 893         while (nb_rx < nb_pkts) {
 894                 rxdp = &rx_ring[rx_id];
 895                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 896                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 897                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 898                 /* Check the DD bit first */
 899                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 900                         break;
 901
 902                 nmb = rte_rxmbuf_alloc(rxq->mp);
 903                 if (unlikely(!nmb))
 904                         break;
 905                 rxd = *rxdp;
 906
 907                 nb_hold++;
 908                 rxe = &sw_ring[rx_id];
 909                 rx_id++;
 910                 if (unlikely(rx_id == rxq->nb_rx_desc))
 911                         rx_id = 0;
 912
 913                 /* Prefetch next mbuf */
 914                 rte_prefetch0(sw_ring[rx_id].mbuf);
 915
 916                 /**
 917                  * When next RX descriptor is on a cache line boundary,
 918                  * prefetch the next 4 RX descriptors and next 8 pointers
 919                  * to mbufs.
 920                  */
 921                 if ((rx_id & 0x3) == 0) {
 922                         rte_prefetch0(&rx_ring[rx_id]);
 923                         rte_prefetch0(&sw_ring[rx_id]);
 924                 }
 925                 rxm = rxe->mbuf;
 926                 rxe->mbuf = nmb;
 927                 dma_addr =
 928                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
 929                 rxdp->read.hdr_addr = dma_addr;
 930                 rxdp->read.pkt_addr = dma_addr;
 931
 932                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 933                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 934
 935                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 936                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 937                 rxm->nb_segs = 1;
 938                 rxm->next = NULL;
 939                 rxm->pkt_len = rx_packet_len;
 940                 rxm->data_len = rx_packet_len;
 941                 rxm->port = rxq->port_id;
 942
 943                 rxm->vlan_tci = rx_status &
 944                         (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
 945                         rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
 946                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 947                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 948                 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
 949                 rxm->packet_type = (uint16_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >>
 950                                 I40E_RXD_QW1_PTYPE_SHIFT);
 951                 if (pkt_flags & PKT_RX_RSS_HASH)
 952                         rxm->hash.rss =
 953                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 954                 if (pkt_flags & PKT_RX_FDIR)
 955                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 956
 957                 rxm->ol_flags = pkt_flags;
 958
 959                 rx_pkts[nb_rx++] = rxm;
 960         }
 961         rxq->rx_tail = rx_id;
 962
 963         /**
 964          * If the number of free RX descriptors is greater than the RX free
 965          * threshold of the queue, advance the receive tail register of queue.
 966          * Update that register with the value of the last processed RX
 967          * descriptor minus 1.
 968          */
 969         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 970         if (nb_hold > rxq->rx_free_thresh) {
 971                 rx_id = (uint16_t) ((rx_id == 0) ?
 972                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 973                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 974                 nb_hold = 0;
 975         }
 976         rxq->nb_rx_hold = nb_hold;
 977
 978         return nb_rx;
 979 }
 980
 981 uint16_t
 982 i40e_recv_scattered_pkts(void *rx_queue,
 983                          struct rte_mbuf **rx_pkts,
 984                          uint16_t nb_pkts)
 985 {
 986         struct i40e_rx_queue *rxq = rx_queue;
 987         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 988         volatile union i40e_rx_desc *rxdp;
 989         union i40e_rx_desc rxd;
 990         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 991         struct i40e_rx_entry *rxe;
 992         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 993         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 994         struct rte_mbuf *nmb, *rxm;
 995         uint16_t rx_id = rxq->rx_tail;
 996         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 997         uint32_t rx_status;
 998         uint64_t qword1;
 999         uint64_t dma_addr;
1000         uint64_t pkt_flags;
1001
1002         while (nb_rx < nb_pkts) {
1003                 rxdp = &rx_ring[rx_id];
1004                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1005                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1006                                         I40E_RXD_QW1_STATUS_SHIFT;
1007                 /* Check the DD bit */
1008                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1009                         break;
1010
1011                 nmb = rte_rxmbuf_alloc(rxq->mp);
1012                 if (unlikely(!nmb))
1013                         break;
1014                 rxd = *rxdp;
1015                 nb_hold++;
1016                 rxe = &sw_ring[rx_id];
1017                 rx_id++;
1018                 if (rx_id == rxq->nb_rx_desc)
1019                         rx_id = 0;
1020
1021                 /* Prefetch next mbuf */
1022                 rte_prefetch0(sw_ring[rx_id].mbuf);
1023
1024                 /**
1025                  * When next RX descriptor is on a cache line boundary,
1026                  * prefetch the next 4 RX descriptors and next 8 pointers
1027                  * to mbufs.
1028                  */
1029                 if ((rx_id & 0x3) == 0) {
1030                         rte_prefetch0(&rx_ring[rx_id]);
1031                         rte_prefetch0(&sw_ring[rx_id]);
1032                 }
1033
1034                 rxm = rxe->mbuf;
1035                 rxe->mbuf = nmb;
1036                 dma_addr =
1037                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1038
1039                 /* Set data buffer address and data length of the mbuf */
1040                 rxdp->read.hdr_addr = dma_addr;
1041                 rxdp->read.pkt_addr = dma_addr;
1042                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1043                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1044                 rxm->data_len = rx_packet_len;
1045                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1046
1047                 /**
1048                  * If this is the first buffer of the received packet, set the
1049                  * pointer to the first mbuf of the packet and initialize its
1050                  * context. Otherwise, update the total length and the number
1051                  * of segments of the current scattered packet, and update the
1052                  * pointer to the last mbuf of the current packet.
1053                  */
1054                 if (!first_seg) {
1055                         first_seg = rxm;
1056                         first_seg->nb_segs = 1;
1057                         first_seg->pkt_len = rx_packet_len;
1058                 } else {
1059                         first_seg->pkt_len =
1060                                 (uint16_t)(first_seg->pkt_len +
1061                                                 rx_packet_len);
1062                         first_seg->nb_segs++;
1063                         last_seg->next = rxm;
1064                 }
1065
1066                 /**
1067                  * If this is not the last buffer of the received packet,
1068                  * update the pointer to the last mbuf of the current scattered
1069                  * packet and continue to parse the RX ring.
1070                  */
1071                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1072                         last_seg = rxm;
1073                         continue;
1074                 }
1075
1076                 /**
1077                  * This is the last buffer of the received packet. If the CRC
1078                  * is not stripped by the hardware:
1079                  *  - Subtract the CRC length from the total packet length.
1080                  *  - If the last buffer only contains the whole CRC or a part
1081                  *  of it, free the mbuf associated to the last buffer. If part
1082                  *  of the CRC is also contained in the previous mbuf, subtract
1083                  *  the length of that CRC part from the data length of the
1084                  *  previous mbuf.
1085                  */
1086                 rxm->next = NULL;
1087                 if (unlikely(rxq->crc_len > 0)) {
1088                         first_seg->pkt_len -= ETHER_CRC_LEN;
1089                         if (rx_packet_len <= ETHER_CRC_LEN) {
1090                                 rte_pktmbuf_free_seg(rxm);
1091                                 first_seg->nb_segs--;
1092                                 last_seg->data_len =
1093                                         (uint16_t)(last_seg->data_len -
1094                                         (ETHER_CRC_LEN - rx_packet_len));
1095                                 last_seg->next = NULL;
1096                         } else
1097                                 rxm->data_len = (uint16_t)(rx_packet_len -
1098                                                                 ETHER_CRC_LEN);
1099                 }
1100
1101                 first_seg->port = rxq->port_id;
1102                 first_seg->vlan_tci = (rx_status &
1103                         (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1104                         rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
1105                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1106                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1107                 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1108                 first_seg->packet_type = (uint16_t)((qword1 &
1109                                         I40E_RXD_QW1_PTYPE_MASK) >>
1110                                         I40E_RXD_QW1_PTYPE_SHIFT);
1111                 if (pkt_flags & PKT_RX_RSS_HASH)
1112                         rxm->hash.rss =
1113                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1114                 if (pkt_flags & PKT_RX_FDIR)
1115                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1116
1117                 first_seg->ol_flags = pkt_flags;
1118
1119                 /* Prefetch data of first segment, if configured to do so. */
1120                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1121                         first_seg->data_off));
1122                 rx_pkts[nb_rx++] = first_seg;
1123                 first_seg = NULL;
1124         }
1125
1126         /* Record index of the next RX descriptor to probe. */
1127         rxq->rx_tail = rx_id;
1128         rxq->pkt_first_seg = first_seg;
1129         rxq->pkt_last_seg = last_seg;
1130
1131         /**
1132          * If the number of free RX descriptors is greater than the RX free
1133          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1134          * register. Update the RDT with the value of the last processed RX
1135          * descriptor minus 1, to guarantee that the RDT register is never
1136          * equal to the RDH register, which creates a "full" ring situtation
1137          * from the hardware point of view.
1138          */
1139         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1140         if (nb_hold > rxq->rx_free_thresh) {
1141                 rx_id = (uint16_t)(rx_id == 0 ?
1142                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1143                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1144                 nb_hold = 0;
1145         }
1146         rxq->nb_rx_hold = nb_hold;
1147
1148         return nb_rx;
1149 }
1150
1151 /* Check if the context descriptor is needed for TX offloading */
1152 static inline uint16_t
1153 i40e_calc_context_desc(uint64_t flags)
1154 {
1155         uint64_t mask = 0ULL;
1156
1157         mask |= PKT_TX_OUTER_IP_CKSUM;
1158
1159 #ifdef RTE_LIBRTE_IEEE1588
1160         mask |= PKT_TX_IEEE1588_TMST;
1161 #endif
1162         if (flags & mask)
1163                 return 1;
1164
1165         return 0;
1166 }
1167
1168 uint16_t
1169 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1170 {
1171         struct i40e_tx_queue *txq;
1172         struct i40e_tx_entry *sw_ring;
1173         struct i40e_tx_entry *txe, *txn;
1174         volatile struct i40e_tx_desc *txd;
1175         volatile struct i40e_tx_desc *txr;
1176         struct rte_mbuf *tx_pkt;
1177         struct rte_mbuf *m_seg;
1178         uint32_t cd_tunneling_params;
1179         uint16_t tx_id;
1180         uint16_t nb_tx;
1181         uint32_t td_cmd;
1182         uint32_t td_offset;
1183         uint32_t tx_flags;
1184         uint32_t td_tag;
1185         uint64_t ol_flags;
1186         uint8_t l2_len;
1187         uint16_t l3_len;
1188         uint8_t outer_l2_len;
1189         uint16_t outer_l3_len;
1190         uint16_t nb_used;
1191         uint16_t nb_ctx;
1192         uint16_t tx_last;
1193         uint16_t slen;
1194         uint64_t buf_dma_addr;
1195
1196         txq = tx_queue;
1197         sw_ring = txq->sw_ring;
1198         txr = txq->tx_ring;
1199         tx_id = txq->tx_tail;
1200         txe = &sw_ring[tx_id];
1201
1202         /* Check if the descriptor ring needs to be cleaned. */
1203         if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh)
1204                 i40e_xmit_cleanup(txq);
1205
1206         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1207                 td_cmd = 0;
1208                 td_tag = 0;
1209                 td_offset = 0;
1210                 tx_flags = 0;
1211
1212                 tx_pkt = *tx_pkts++;
1213                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1214
1215                 ol_flags = tx_pkt->ol_flags;
1216                 l2_len = tx_pkt->l2_len;
1217                 l3_len = tx_pkt->l3_len;
1218                 outer_l2_len = tx_pkt->outer_l2_len;
1219                 outer_l3_len = tx_pkt->outer_l3_len;
1220
1221                 /* Calculate the number of context descriptors needed. */
1222                 nb_ctx = i40e_calc_context_desc(ol_flags);
1223
1224                 /**
1225                  * The number of descriptors that must be allocated for
1226                  * a packet equals to the number of the segments of that
1227                  * packet plus 1 context descriptor if needed.
1228                  */
1229                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1230                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1231
1232                 /* Circular ring */
1233                 if (tx_last >= txq->nb_tx_desc)
1234                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1235
1236                 if (nb_used > txq->nb_tx_free) {
1237                         if (i40e_xmit_cleanup(txq) != 0) {
1238                                 if (nb_tx == 0)
1239                                         return 0;
1240                                 goto end_of_tx;
1241                         }
1242                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1243                                 while (nb_used > txq->nb_tx_free) {
1244                                         if (i40e_xmit_cleanup(txq) != 0) {
1245                                                 if (nb_tx == 0)
1246                                                         return 0;
1247                                                 goto end_of_tx;
1248                                         }
1249                                 }
1250                         }
1251                 }
1252
1253                 /* Descriptor based VLAN insertion */
1254                 if (ol_flags & PKT_TX_VLAN_PKT) {
1255                         tx_flags |= tx_pkt->vlan_tci <<
1256                                         I40E_TX_FLAG_L2TAG1_SHIFT;
1257                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1258                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1259                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1260                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1261                 }
1262
1263                 /* Always enable CRC offload insertion */
1264                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1265
1266                 /* Enable checksum offloading */
1267                 cd_tunneling_params = 0;
1268                 if (unlikely(ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)) {
1269                         i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1270                                 l2_len, l3_len, outer_l2_len,
1271                                 outer_l3_len,
1272                                 &cd_tunneling_params);
1273                 }
1274
1275                 if (unlikely(nb_ctx)) {
1276                         /* Setup TX context descriptor if required */
1277                         volatile struct i40e_tx_context_desc *ctx_txd =
1278                                 (volatile struct i40e_tx_context_desc *)\
1279                                                         &txr[tx_id];
1280                         uint16_t cd_l2tag2 = 0;
1281                         uint64_t cd_type_cmd_tso_mss =
1282                                 I40E_TX_DESC_DTYPE_CONTEXT;
1283
1284                         txn = &sw_ring[txe->next_id];
1285                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1286                         if (txe->mbuf != NULL) {
1287                                 rte_pktmbuf_free_seg(txe->mbuf);
1288                                 txe->mbuf = NULL;
1289                         }
1290 #ifdef RTE_LIBRTE_IEEE1588
1291                         if (ol_flags & PKT_TX_IEEE1588_TMST)
1292                                 cd_type_cmd_tso_mss |=
1293                                         ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1294                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1295 #endif
1296                         ctx_txd->tunneling_params =
1297                                 rte_cpu_to_le_32(cd_tunneling_params);
1298                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1299                         ctx_txd->type_cmd_tso_mss =
1300                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1301                         txe->last_id = tx_last;
1302                         tx_id = txe->next_id;
1303                         txe = txn;
1304                 }
1305
1306                 m_seg = tx_pkt;
1307                 do {
1308                         txd = &txr[tx_id];
1309                         txn = &sw_ring[txe->next_id];
1310
1311                         if (txe->mbuf)
1312                                 rte_pktmbuf_free_seg(txe->mbuf);
1313                         txe->mbuf = m_seg;
1314
1315                         /* Setup TX Descriptor */
1316                         slen = m_seg->data_len;
1317                         buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1318                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1319                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1320                                                 td_offset, slen, td_tag);
1321                         txe->last_id = tx_last;
1322                         tx_id = txe->next_id;
1323                         txe = txn;
1324                         m_seg = m_seg->next;
1325                 } while (m_seg != NULL);
1326
1327                 /* The last packet data descriptor needs End Of Packet (EOP) */
1328                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1329                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1330                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1331
1332                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1333                         PMD_TX_FREE_LOG(DEBUG,
1334                                         "Setting RS bit on TXD id="
1335                                         "%4u (port=%d queue=%d)",
1336                                         tx_last, txq->port_id, txq->queue_id);
1337
1338                         td_cmd |= I40E_TX_DESC_CMD_RS;
1339
1340                         /* Update txq RS bit counters */
1341                         txq->nb_tx_used = 0;
1342                 }
1343
1344                 txd->cmd_type_offset_bsz |=
1345                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1346                                         I40E_TXD_QW1_CMD_SHIFT);
1347         }
1348
1349 end_of_tx:
1350         rte_wmb();
1351
1352         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1353                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1354                    (unsigned) tx_id, (unsigned) nb_tx);
1355
1356         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1357         txq->tx_tail = tx_id;
1358
1359         return nb_tx;
1360 }
1361
1362 static inline int __attribute__((always_inline))
1363 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1364 {
1365         struct i40e_tx_entry *txep;
1366         uint16_t i;
1367
1368         if (!(txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1369                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)))
1370                 return 0;
1371
1372         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1373
1374         for (i = 0; i < txq->tx_rs_thresh; i++)
1375                 rte_prefetch0((txep + i)->mbuf);
1376
1377         if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1378                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1379                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1380                         txep->mbuf = NULL;
1381                 }
1382         } else {
1383                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1384                         rte_pktmbuf_free_seg(txep->mbuf);
1385                         txep->mbuf = NULL;
1386                 }
1387         }
1388
1389         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1390         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1391         if (txq->tx_next_dd >= txq->nb_tx_desc)
1392                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1393
1394         return txq->tx_rs_thresh;
1395 }
1396
1397 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1398                      I40E_TX_DESC_CMD_EOP)
1399
1400 /* Populate 4 descriptors with data from 4 mbufs */
1401 static inline void
1402 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1403 {
1404         uint64_t dma_addr;
1405         uint32_t i;
1406
1407         for (i = 0; i < 4; i++, txdp++, pkts++) {
1408                 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1409                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1410                 txdp->cmd_type_offset_bsz =
1411                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1412                                         (*pkts)->data_len, 0);
1413         }
1414 }
1415
1416 /* Populate 1 descriptor with data from 1 mbuf */
1417 static inline void
1418 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1419 {
1420         uint64_t dma_addr;
1421
1422         dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1423         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1424         txdp->cmd_type_offset_bsz =
1425                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1426                                 (*pkts)->data_len, 0);
1427 }
1428
1429 /* Fill hardware descriptor ring with mbuf data */
1430 static inline void
1431 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1432                      struct rte_mbuf **pkts,
1433                      uint16_t nb_pkts)
1434 {
1435         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1436         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1437         const int N_PER_LOOP = 4;
1438         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1439         int mainpart, leftover;
1440         int i, j;
1441
1442         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1443         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1444         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1445                 for (j = 0; j < N_PER_LOOP; ++j) {
1446                         (txep + i + j)->mbuf = *(pkts + i + j);
1447                 }
1448                 tx4(txdp + i, pkts + i);
1449         }
1450         if (unlikely(leftover > 0)) {
1451                 for (i = 0; i < leftover; ++i) {
1452                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1453                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1454                 }
1455         }
1456 }
1457
1458 static inline uint16_t
1459 tx_xmit_pkts(struct i40e_tx_queue *txq,
1460              struct rte_mbuf **tx_pkts,
1461              uint16_t nb_pkts)
1462 {
1463         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1464         uint16_t n = 0;
1465
1466         /**
1467          * Begin scanning the H/W ring for done descriptors when the number
1468          * of available descriptors drops below tx_free_thresh. For each done
1469          * descriptor, free the associated buffer.
1470          */
1471         if (txq->nb_tx_free < txq->tx_free_thresh)
1472                 i40e_tx_free_bufs(txq);
1473
1474         /* Use available descriptor only */
1475         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1476         if (unlikely(!nb_pkts))
1477                 return 0;
1478
1479         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1480         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1481                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1482                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1483                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1484                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1485                                                 I40E_TXD_QW1_CMD_SHIFT);
1486                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1487                 txq->tx_tail = 0;
1488         }
1489
1490         /* Fill hardware descriptor ring with mbuf data */
1491         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1492         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1493
1494         /* Determin if RS bit needs to be set */
1495         if (txq->tx_tail > txq->tx_next_rs) {
1496                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1497                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1498                                                 I40E_TXD_QW1_CMD_SHIFT);
1499                 txq->tx_next_rs =
1500                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1501                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1502                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1503         }
1504
1505         if (txq->tx_tail >= txq->nb_tx_desc)
1506                 txq->tx_tail = 0;
1507
1508         /* Update the tx tail register */
1509         rte_wmb();
1510         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1511
1512         return nb_pkts;
1513 }
1514
1515 static uint16_t
1516 i40e_xmit_pkts_simple(void *tx_queue,
1517                       struct rte_mbuf **tx_pkts,
1518                       uint16_t nb_pkts)
1519 {
1520         uint16_t nb_tx = 0;
1521
1522         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1523                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1524                                                 tx_pkts, nb_pkts);
1525
1526         while (nb_pkts) {
1527                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1528                                                 I40E_TX_MAX_BURST);
1529
1530                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1531                                                 &tx_pkts[nb_tx], num);
1532                 nb_tx = (uint16_t)(nb_tx + ret);
1533                 nb_pkts = (uint16_t)(nb_pkts - ret);
1534                 if (ret < num)
1535                         break;
1536         }
1537
1538         return nb_tx;
1539 }
1540
1541 /*
1542  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1543  * application used, which assume having sequential ones. But from driver's
1544  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1545  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1546  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1547  * use queue_idx from 0 to 95 to access queues, while real queue would be
1548  * different. This function will do a queue mapping to find VSI the queue
1549  * belongs to.
1550  */
1551 static struct i40e_vsi*
1552 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1553 {
1554         /* the queue in MAIN VSI range */
1555         if (queue_idx < pf->main_vsi->nb_qps)
1556                 return pf->main_vsi;
1557
1558         queue_idx -= pf->main_vsi->nb_qps;
1559
1560         /* queue_idx is greater than VMDQ VSIs range */
1561         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1562                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1563                 return NULL;
1564         }
1565
1566         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1567 }
1568
1569 static uint16_t
1570 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1571 {
1572         /* the queue in MAIN VSI range */
1573         if (queue_idx < pf->main_vsi->nb_qps)
1574                 return queue_idx;
1575
1576         /* It's VMDQ queues */
1577         queue_idx -= pf->main_vsi->nb_qps;
1578
1579         if (pf->nb_cfg_vmdq_vsi)
1580                 return queue_idx % pf->vmdq_nb_qps;
1581         else {
1582                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1583                 return (uint16_t)(-1);
1584         }
1585 }
1586
1587 int
1588 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1589 {
1590         struct i40e_rx_queue *rxq;
1591         int err = -1;
1592         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1593
1594         PMD_INIT_FUNC_TRACE();
1595
1596         if (rx_queue_id < dev->data->nb_rx_queues) {
1597                 rxq = dev->data->rx_queues[rx_queue_id];
1598
1599                 err = i40e_alloc_rx_queue_mbufs(rxq);
1600                 if (err) {
1601                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1602                         return err;
1603                 }
1604
1605                 rte_wmb();
1606
1607                 /* Init the RX tail regieter. */
1608                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1609
1610                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1611
1612                 if (err) {
1613                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1614                                     rx_queue_id);
1615
1616                         i40e_rx_queue_release_mbufs(rxq);
1617                         i40e_reset_rx_queue(rxq);
1618                 }
1619         }
1620
1621         return err;
1622 }
1623
1624 int
1625 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1626 {
1627         struct i40e_rx_queue *rxq;
1628         int err;
1629         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1630
1631         if (rx_queue_id < dev->data->nb_rx_queues) {
1632                 rxq = dev->data->rx_queues[rx_queue_id];
1633
1634                 /*
1635                 * rx_queue_id is queue id aplication refers to, while
1636                 * rxq->reg_idx is the real queue index.
1637                 */
1638                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1639
1640                 if (err) {
1641                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1642                                     rx_queue_id);
1643                         return err;
1644                 }
1645                 i40e_rx_queue_release_mbufs(rxq);
1646                 i40e_reset_rx_queue(rxq);
1647         }
1648
1649         return 0;
1650 }
1651
1652 int
1653 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1654 {
1655         int err = -1;
1656         struct i40e_tx_queue *txq;
1657         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1658
1659         PMD_INIT_FUNC_TRACE();
1660
1661         if (tx_queue_id < dev->data->nb_tx_queues) {
1662                 txq = dev->data->tx_queues[tx_queue_id];
1663
1664                 /*
1665                 * tx_queue_id is queue id aplication refers to, while
1666                 * rxq->reg_idx is the real queue index.
1667                 */
1668                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1669                 if (err)
1670                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1671                                     tx_queue_id);
1672         }
1673
1674         return err;
1675 }
1676
1677 int
1678 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1679 {
1680         struct i40e_tx_queue *txq;
1681         int err;
1682         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1683
1684         if (tx_queue_id < dev->data->nb_tx_queues) {
1685                 txq = dev->data->tx_queues[tx_queue_id];
1686
1687                 /*
1688                 * tx_queue_id is queue id aplication refers to, while
1689                 * txq->reg_idx is the real queue index.
1690                 */
1691                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1692
1693                 if (err) {
1694                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1695                                     tx_queue_id);
1696                         return err;
1697                 }
1698
1699                 i40e_tx_queue_release_mbufs(txq);
1700                 i40e_reset_tx_queue(txq);
1701         }
1702
1703         return 0;
1704 }
1705
1706 int
1707 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1708                         uint16_t queue_idx,
1709                         uint16_t nb_desc,
1710                         unsigned int socket_id,
1711                         const struct rte_eth_rxconf *rx_conf,
1712                         struct rte_mempool *mp)
1713 {
1714         struct i40e_vsi *vsi;
1715         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1716         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1717         struct i40e_rx_queue *rxq;
1718         const struct rte_memzone *rz;
1719         uint32_t ring_size;
1720         uint16_t len;
1721         int use_def_burst_func = 1;
1722
1723         if (hw->mac.type == I40E_MAC_VF) {
1724                 struct i40e_vf *vf =
1725                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1726                 vsi = &vf->vsi;
1727         } else
1728                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1729
1730         if (vsi == NULL) {
1731                 PMD_DRV_LOG(ERR, "VSI not available or queue "
1732                             "index exceeds the maximum");
1733                 return I40E_ERR_PARAM;
1734         }
1735         if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1736                                         (nb_desc > I40E_MAX_RING_DESC) ||
1737                                         (nb_desc < I40E_MIN_RING_DESC)) {
1738                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1739                             "invalid", nb_desc);
1740                 return I40E_ERR_PARAM;
1741         }
1742
1743         /* Free memory if needed */
1744         if (dev->data->rx_queues[queue_idx]) {
1745                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1746                 dev->data->rx_queues[queue_idx] = NULL;
1747         }
1748
1749         /* Allocate the rx queue data structure */
1750         rxq = rte_zmalloc_socket("i40e rx queue",
1751                                  sizeof(struct i40e_rx_queue),
1752                                  RTE_CACHE_LINE_SIZE,
1753                                  socket_id);
1754         if (!rxq) {
1755                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1756                             "rx queue data structure");
1757                 return (-ENOMEM);
1758         }
1759         rxq->mp = mp;
1760         rxq->nb_rx_desc = nb_desc;
1761         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1762         rxq->queue_id = queue_idx;
1763         if (hw->mac.type == I40E_MAC_VF)
1764                 rxq->reg_idx = queue_idx;
1765         else /* PF device */
1766                 rxq->reg_idx = vsi->base_queue +
1767                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
1768
1769         rxq->port_id = dev->data->port_id;
1770         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1771                                                         0 : ETHER_CRC_LEN);
1772         rxq->drop_en = rx_conf->rx_drop_en;
1773         rxq->vsi = vsi;
1774         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1775
1776         /* Allocate the maximun number of RX ring hardware descriptor. */
1777         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1778         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1779         rz = i40e_ring_dma_zone_reserve(dev,
1780                                         "rx_ring",
1781                                         queue_idx,
1782                                         ring_size,
1783                                         socket_id);
1784         if (!rz) {
1785                 i40e_dev_rx_queue_release(rxq);
1786                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1787                 return (-ENOMEM);
1788         }
1789
1790         /* Zero all the descriptors in the ring. */
1791         memset(rz->addr, 0, ring_size);
1792
1793 #ifdef RTE_LIBRTE_XEN_DOM0
1794         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1795 #else
1796         rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1797 #endif
1798
1799         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1800
1801 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1802         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1803 #else
1804         len = nb_desc;
1805 #endif
1806
1807         /* Allocate the software ring. */
1808         rxq->sw_ring =
1809                 rte_zmalloc_socket("i40e rx sw ring",
1810                                    sizeof(struct i40e_rx_entry) * len,
1811                                    RTE_CACHE_LINE_SIZE,
1812                                    socket_id);
1813         if (!rxq->sw_ring) {
1814                 i40e_dev_rx_queue_release(rxq);
1815                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1816                 return (-ENOMEM);
1817         }
1818
1819         i40e_reset_rx_queue(rxq);
1820         rxq->q_set = TRUE;
1821         dev->data->rx_queues[queue_idx] = rxq;
1822
1823         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1824
1825         if (!use_def_burst_func && !dev->data->scattered_rx) {
1826 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1827                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1828                              "satisfied. Rx Burst Bulk Alloc function will be "
1829                              "used on port=%d, queue=%d.",
1830                              rxq->port_id, rxq->queue_id);
1831                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1832 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1833         } else {
1834                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1835                              "not satisfied, Scattered Rx is requested, "
1836                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1837                              "not enabled on port=%d, queue=%d.",
1838                              rxq->port_id, rxq->queue_id);
1839         }
1840
1841         return 0;
1842 }
1843
1844 void
1845 i40e_dev_rx_queue_release(void *rxq)
1846 {
1847         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1848
1849         if (!q) {
1850                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1851                 return;
1852         }
1853
1854         i40e_rx_queue_release_mbufs(q);
1855         rte_free(q->sw_ring);
1856         rte_free(q);
1857 }
1858
1859 uint32_t
1860 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1861 {
1862 #define I40E_RXQ_SCAN_INTERVAL 4
1863         volatile union i40e_rx_desc *rxdp;
1864         struct i40e_rx_queue *rxq;
1865         uint16_t desc = 0;
1866
1867         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1868                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1869                 return 0;
1870         }
1871
1872         rxq = dev->data->rx_queues[rx_queue_id];
1873         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1874         while ((desc < rxq->nb_rx_desc) &&
1875                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1876                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1877                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1878                 /**
1879                  * Check the DD bit of a rx descriptor of each 4 in a group,
1880                  * to avoid checking too frequently and downgrading performance
1881                  * too much.
1882                  */
1883                 desc += I40E_RXQ_SCAN_INTERVAL;
1884                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1885                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1886                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1887                                         desc - rxq->nb_rx_desc]);
1888         }
1889
1890         return desc;
1891 }
1892
1893 int
1894 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1895 {
1896         volatile union i40e_rx_desc *rxdp;
1897         struct i40e_rx_queue *rxq = rx_queue;
1898         uint16_t desc;
1899         int ret;
1900
1901         if (unlikely(offset >= rxq->nb_rx_desc)) {
1902                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1903                 return 0;
1904         }
1905
1906         desc = rxq->rx_tail + offset;
1907         if (desc >= rxq->nb_rx_desc)
1908                 desc -= rxq->nb_rx_desc;
1909
1910         rxdp = &(rxq->rx_ring[desc]);
1911
1912         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1913                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1914                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1915
1916         return ret;
1917 }
1918
1919 int
1920 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1921                         uint16_t queue_idx,
1922                         uint16_t nb_desc,
1923                         unsigned int socket_id,
1924                         const struct rte_eth_txconf *tx_conf)
1925 {
1926         struct i40e_vsi *vsi;
1927         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1929         struct i40e_tx_queue *txq;
1930         const struct rte_memzone *tz;
1931         uint32_t ring_size;
1932         uint16_t tx_rs_thresh, tx_free_thresh;
1933
1934         if (hw->mac.type == I40E_MAC_VF) {
1935                 struct i40e_vf *vf =
1936                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1937                 vsi = &vf->vsi;
1938         } else
1939                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1940
1941         if (vsi == NULL) {
1942                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1943                             "exceeds the maximum", queue_idx);
1944                 return I40E_ERR_PARAM;
1945         }
1946
1947         if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
1948                                         (nb_desc > I40E_MAX_RING_DESC) ||
1949                                         (nb_desc < I40E_MIN_RING_DESC)) {
1950                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1951                             "invalid", nb_desc);
1952                 return I40E_ERR_PARAM;
1953         }
1954
1955         /**
1956          * The following two parameters control the setting of the RS bit on
1957          * transmit descriptors. TX descriptors will have their RS bit set
1958          * after txq->tx_rs_thresh descriptors have been used. The TX
1959          * descriptor ring will be cleaned after txq->tx_free_thresh
1960          * descriptors are used or if the number of descriptors required to
1961          * transmit a packet is greater than the number of free TX descriptors.
1962          *
1963          * The following constraints must be satisfied:
1964          *  - tx_rs_thresh must be greater than 0.
1965          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1966          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1967          *  - tx_rs_thresh must be a divisor of the ring size.
1968          *  - tx_free_thresh must be greater than 0.
1969          *  - tx_free_thresh must be less than the size of the ring minus 3.
1970          *
1971          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1972          * race condition, hence the maximum threshold constraints. When set
1973          * to zero use default values.
1974          */
1975         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1976                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1977         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1978                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1979         if (tx_rs_thresh >= (nb_desc - 2)) {
1980                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1981                              "number of TX descriptors minus 2. "
1982                              "(tx_rs_thresh=%u port=%d queue=%d)",
1983                              (unsigned int)tx_rs_thresh,
1984                              (int)dev->data->port_id,
1985                              (int)queue_idx);
1986                 return I40E_ERR_PARAM;
1987         }
1988         if (tx_free_thresh >= (nb_desc - 3)) {
1989                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1990                              "tx_free_thresh must be less than the "
1991                              "number of TX descriptors minus 3. "
1992                              "(tx_free_thresh=%u port=%d queue=%d)",
1993                              (unsigned int)tx_free_thresh,
1994                              (int)dev->data->port_id,
1995                              (int)queue_idx);
1996                 return I40E_ERR_PARAM;
1997         }
1998         if (tx_rs_thresh > tx_free_thresh) {
1999                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2000                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2001                              " tx_rs_thresh=%u port=%d queue=%d)",
2002                              (unsigned int)tx_free_thresh,
2003                              (unsigned int)tx_rs_thresh,
2004                              (int)dev->data->port_id,
2005                              (int)queue_idx);
2006                 return I40E_ERR_PARAM;
2007         }
2008         if ((nb_desc % tx_rs_thresh) != 0) {
2009                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2010                              "number of TX descriptors. (tx_rs_thresh=%u"
2011                              " port=%d queue=%d)",
2012                              (unsigned int)tx_rs_thresh,
2013                              (int)dev->data->port_id,
2014                              (int)queue_idx);
2015                 return I40E_ERR_PARAM;
2016         }
2017         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2018                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2019                              "tx_rs_thresh is greater than 1. "
2020                              "(tx_rs_thresh=%u port=%d queue=%d)",
2021                              (unsigned int)tx_rs_thresh,
2022                              (int)dev->data->port_id,
2023                              (int)queue_idx);
2024                 return I40E_ERR_PARAM;
2025         }
2026
2027         /* Free memory if needed. */
2028         if (dev->data->tx_queues[queue_idx]) {
2029                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2030                 dev->data->tx_queues[queue_idx] = NULL;
2031         }
2032
2033         /* Allocate the TX queue data structure. */
2034         txq = rte_zmalloc_socket("i40e tx queue",
2035                                   sizeof(struct i40e_tx_queue),
2036                                   RTE_CACHE_LINE_SIZE,
2037                                   socket_id);
2038         if (!txq) {
2039                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2040                             "tx queue structure");
2041                 return (-ENOMEM);
2042         }
2043
2044         /* Allocate TX hardware ring descriptors. */
2045         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2046         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2047         tz = i40e_ring_dma_zone_reserve(dev,
2048                                         "tx_ring",
2049                                         queue_idx,
2050                                         ring_size,
2051                                         socket_id);
2052         if (!tz) {
2053                 i40e_dev_tx_queue_release(txq);
2054                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2055                 return (-ENOMEM);
2056         }
2057
2058         txq->nb_tx_desc = nb_desc;
2059         txq->tx_rs_thresh = tx_rs_thresh;
2060         txq->tx_free_thresh = tx_free_thresh;
2061         txq->pthresh = tx_conf->tx_thresh.pthresh;
2062         txq->hthresh = tx_conf->tx_thresh.hthresh;
2063         txq->wthresh = tx_conf->tx_thresh.wthresh;
2064         txq->queue_id = queue_idx;
2065         if (hw->mac.type == I40E_MAC_VF)
2066                 txq->reg_idx = queue_idx;
2067         else /* PF device */
2068                 txq->reg_idx = vsi->base_queue +
2069                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2070
2071         txq->port_id = dev->data->port_id;
2072         txq->txq_flags = tx_conf->txq_flags;
2073         txq->vsi = vsi;
2074         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2075
2076 #ifdef RTE_LIBRTE_XEN_DOM0
2077         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2078 #else
2079         txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2080 #endif
2081         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2082
2083         /* Allocate software ring */
2084         txq->sw_ring =
2085                 rte_zmalloc_socket("i40e tx sw ring",
2086                                    sizeof(struct i40e_tx_entry) * nb_desc,
2087                                    RTE_CACHE_LINE_SIZE,
2088                                    socket_id);
2089         if (!txq->sw_ring) {
2090                 i40e_dev_tx_queue_release(txq);
2091                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2092                 return (-ENOMEM);
2093         }
2094
2095         i40e_reset_tx_queue(txq);
2096         txq->q_set = TRUE;
2097         dev->data->tx_queues[queue_idx] = txq;
2098
2099         /* Use a simple TX queue without offloads or multi segs if possible */
2100         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
2101                                 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
2102                 PMD_INIT_LOG(INFO, "Using simple tx path");
2103                 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2104         } else {
2105                 PMD_INIT_LOG(INFO, "Using full-featured tx path");
2106                 dev->tx_pkt_burst = i40e_xmit_pkts;
2107         }
2108
2109         return 0;
2110 }
2111
2112 void
2113 i40e_dev_tx_queue_release(void *txq)
2114 {
2115         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2116
2117         if (!q) {
2118                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2119                 return;
2120         }
2121
2122         i40e_tx_queue_release_mbufs(q);
2123         rte_free(q->sw_ring);
2124         rte_free(q);
2125 }
2126
2127 static const struct rte_memzone *
2128 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
2129                            const char *ring_name,
2130                            uint16_t queue_id,
2131                            uint32_t ring_size,
2132                            int socket_id)
2133 {
2134         char z_name[RTE_MEMZONE_NAMESIZE];
2135         const struct rte_memzone *mz;
2136
2137         snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2138                         dev->driver->pci_drv.name, ring_name,
2139                                 dev->data->port_id, queue_id);
2140         mz = rte_memzone_lookup(z_name);
2141         if (mz)
2142                 return mz;
2143
2144 #ifdef RTE_LIBRTE_XEN_DOM0
2145         return rte_memzone_reserve_bounded(z_name, ring_size,
2146                 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2147 #else
2148         return rte_memzone_reserve_aligned(z_name, ring_size,
2149                                 socket_id, 0, I40E_ALIGN);
2150 #endif
2151 }
2152
2153 const struct rte_memzone *
2154 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2155 {
2156         const struct rte_memzone *mz = NULL;
2157
2158         mz = rte_memzone_lookup(name);
2159         if (mz)
2160                 return mz;
2161 #ifdef RTE_LIBRTE_XEN_DOM0
2162         mz = rte_memzone_reserve_bounded(name, len,
2163                 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2164 #else
2165         mz = rte_memzone_reserve_aligned(name, len,
2166                                 socket_id, 0, I40E_ALIGN);
2167 #endif
2168         return mz;
2169 }
2170
2171 void
2172 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2173 {
2174         uint16_t i;
2175
2176         if (!rxq || !rxq->sw_ring) {
2177                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2178                 return;
2179         }
2180
2181         for (i = 0; i < rxq->nb_rx_desc; i++) {
2182                 if (rxq->sw_ring[i].mbuf) {
2183                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2184                         rxq->sw_ring[i].mbuf = NULL;
2185                 }
2186         }
2187 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2188         if (rxq->rx_nb_avail == 0)
2189                 return;
2190         for (i = 0; i < rxq->rx_nb_avail; i++) {
2191                 struct rte_mbuf *mbuf;
2192
2193                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2194                 rte_pktmbuf_free_seg(mbuf);
2195         }
2196         rxq->rx_nb_avail = 0;
2197 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2198 }
2199
2200 void
2201 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2202 {
2203         unsigned i;
2204         uint16_t len;
2205
2206 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2207         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2208                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2209         else
2210 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2211                 len = rxq->nb_rx_desc;
2212
2213         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2214                 ((volatile char *)rxq->rx_ring)[i] = 0;
2215
2216 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2217         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2218         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2219                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2220
2221         rxq->rx_nb_avail = 0;
2222         rxq->rx_next_avail = 0;
2223         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2224 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2225         rxq->rx_tail = 0;
2226         rxq->nb_rx_hold = 0;
2227         rxq->pkt_first_seg = NULL;
2228         rxq->pkt_last_seg = NULL;
2229 }
2230
2231 void
2232 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2233 {
2234         uint16_t i;
2235
2236         if (!txq || !txq->sw_ring) {
2237                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2238                 return;
2239         }
2240
2241         for (i = 0; i < txq->nb_tx_desc; i++) {
2242                 if (txq->sw_ring[i].mbuf) {
2243                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2244                         txq->sw_ring[i].mbuf = NULL;
2245                 }
2246         }
2247 }
2248
2249 void
2250 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2251 {
2252         struct i40e_tx_entry *txe;
2253         uint16_t i, prev, size;
2254
2255         if (!txq) {
2256                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2257                 return;
2258         }
2259
2260         txe = txq->sw_ring;
2261         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2262         for (i = 0; i < size; i++)
2263                 ((volatile char *)txq->tx_ring)[i] = 0;
2264
2265         prev = (uint16_t)(txq->nb_tx_desc - 1);
2266         for (i = 0; i < txq->nb_tx_desc; i++) {
2267                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2268
2269                 txd->cmd_type_offset_bsz =
2270                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2271                 txe[i].mbuf =  NULL;
2272                 txe[i].last_id = i;
2273                 txe[prev].next_id = i;
2274                 prev = i;
2275         }
2276
2277         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2278         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2279
2280         txq->tx_tail = 0;
2281         txq->nb_tx_used = 0;
2282
2283         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2284         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2285 }
2286
2287 /* Init the TX queue in hardware */
2288 int
2289 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2290 {
2291         enum i40e_status_code err = I40E_SUCCESS;
2292         struct i40e_vsi *vsi = txq->vsi;
2293         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2294         uint16_t pf_q = txq->reg_idx;
2295         struct i40e_hmc_obj_txq tx_ctx;
2296         uint32_t qtx_ctl;
2297
2298         /* clear the context structure first */
2299         memset(&tx_ctx, 0, sizeof(tx_ctx));
2300         tx_ctx.new_context = 1;
2301         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2302         tx_ctx.qlen = txq->nb_tx_desc;
2303         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2304         if (vsi->type == I40E_VSI_FDIR)
2305                 tx_ctx.fd_ena = TRUE;
2306
2307         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2308         if (err != I40E_SUCCESS) {
2309                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2310                 return err;
2311         }
2312
2313         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2314         if (err != I40E_SUCCESS) {
2315                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2316                 return err;
2317         }
2318
2319         /* Now associate this queue with this PCI function */
2320         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2321         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2322                                         I40E_QTX_CTL_PF_INDX_MASK);
2323         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2324         I40E_WRITE_FLUSH(hw);
2325
2326         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2327
2328         return err;
2329 }
2330
2331 int
2332 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2333 {
2334         struct i40e_rx_entry *rxe = rxq->sw_ring;
2335         uint64_t dma_addr;
2336         uint16_t i;
2337
2338         for (i = 0; i < rxq->nb_rx_desc; i++) {
2339                 volatile union i40e_rx_desc *rxd;
2340                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2341
2342                 if (unlikely(!mbuf)) {
2343                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2344                         return -ENOMEM;
2345                 }
2346
2347                 rte_mbuf_refcnt_set(mbuf, 1);
2348                 mbuf->next = NULL;
2349                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2350                 mbuf->nb_segs = 1;
2351                 mbuf->port = rxq->port_id;
2352
2353                 dma_addr =
2354                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2355
2356                 rxd = &rxq->rx_ring[i];
2357                 rxd->read.pkt_addr = dma_addr;
2358                 rxd->read.hdr_addr = dma_addr;
2359 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2360                 rxd->read.rsvd1 = 0;
2361                 rxd->read.rsvd2 = 0;
2362 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2363
2364                 rxe[i].mbuf = mbuf;
2365         }
2366
2367         return 0;
2368 }
2369
2370 /*
2371  * Calculate the buffer length, and check the jumbo frame
2372  * and maximum packet length.
2373  */
2374 static int
2375 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2376 {
2377         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2378         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2379         struct rte_eth_dev_data *data = pf->dev_data;
2380         struct rte_pktmbuf_pool_private *mbp_priv =
2381                         rte_mempool_get_priv(rxq->mp);
2382         uint16_t buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2383                                                 RTE_PKTMBUF_HEADROOM);
2384         uint16_t len;
2385
2386         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2387                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2388         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2389                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2390                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2391                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2392                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2393                 rxq->hs_mode = i40e_header_split_enabled;
2394                 break;
2395         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2396         default:
2397                 rxq->rx_hdr_len = 0;
2398                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2399                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2400                 rxq->hs_mode = i40e_header_split_none;
2401                 break;
2402         }
2403
2404         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2405         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2406         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2407                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2408                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2409                         PMD_DRV_LOG(ERR, "maximum packet length must "
2410                                     "be larger than %u and smaller than %u,"
2411                                     "as jumbo frame is enabled",
2412                                     (uint32_t)ETHER_MAX_LEN,
2413                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2414                         return I40E_ERR_CONFIG;
2415                 }
2416         } else {
2417                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2418                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2419                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2420                                     "larger than %u and smaller than %u, "
2421                                     "as jumbo frame is disabled",
2422                                     (uint32_t)ETHER_MIN_LEN,
2423                                     (uint32_t)ETHER_MAX_LEN);
2424                         return I40E_ERR_CONFIG;
2425                 }
2426         }
2427
2428         return 0;
2429 }
2430
2431 /* Init the RX queue in hardware */
2432 int
2433 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2434 {
2435         int err = I40E_SUCCESS;
2436         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2437         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2438         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2439         uint16_t pf_q = rxq->reg_idx;
2440         uint16_t buf_size;
2441         struct i40e_hmc_obj_rxq rx_ctx;
2442         struct rte_pktmbuf_pool_private *mbp_priv;
2443
2444         err = i40e_rx_queue_config(rxq);
2445         if (err < 0) {
2446                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2447                 return err;
2448         }
2449
2450         /* Clear the context structure first */
2451         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2452         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2453         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2454
2455         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2456         rx_ctx.qlen = rxq->nb_rx_desc;
2457 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2458         rx_ctx.dsize = 1;
2459 #endif
2460         rx_ctx.dtype = rxq->hs_mode;
2461         if (rxq->hs_mode)
2462                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2463         else
2464                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2465         rx_ctx.rxmax = rxq->max_pkt_len;
2466         rx_ctx.tphrdesc_ena = 1;
2467         rx_ctx.tphwdesc_ena = 1;
2468         rx_ctx.tphdata_ena = 1;
2469         rx_ctx.tphhead_ena = 1;
2470         rx_ctx.lrxqthresh = 2;
2471         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2472         rx_ctx.l2tsel = 1;
2473         rx_ctx.showiv = 1;
2474         rx_ctx.prefena = 1;
2475
2476         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2477         if (err != I40E_SUCCESS) {
2478                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2479                 return err;
2480         }
2481         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2482         if (err != I40E_SUCCESS) {
2483                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2484                 return err;
2485         }
2486
2487         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2488
2489         mbp_priv = rte_mempool_get_priv(rxq->mp);
2490         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
2491                                         RTE_PKTMBUF_HEADROOM);
2492
2493         /* Check if scattered RX needs to be used. */
2494         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2495                 dev_data->scattered_rx = 1;
2496                 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2497         }
2498
2499         /* Init the RX tail regieter. */
2500         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2501
2502         return 0;
2503 }
2504
2505 void
2506 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2507 {
2508         uint16_t i;
2509
2510         PMD_INIT_FUNC_TRACE();
2511
2512         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2513                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2514                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2515         }
2516
2517         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2518                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2519                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2520         }
2521 }
2522
2523 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2524 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2525
2526 enum i40e_status_code
2527 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2528 {
2529         struct i40e_tx_queue *txq;
2530         const struct rte_memzone *tz = NULL;
2531         uint32_t ring_size;
2532         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2533
2534         if (!pf) {
2535                 PMD_DRV_LOG(ERR, "PF is not available");
2536                 return I40E_ERR_BAD_PTR;
2537         }
2538
2539         /* Allocate the TX queue data structure. */
2540         txq = rte_zmalloc_socket("i40e fdir tx queue",
2541                                   sizeof(struct i40e_tx_queue),
2542                                   RTE_CACHE_LINE_SIZE,
2543                                   SOCKET_ID_ANY);
2544         if (!txq) {
2545                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2546                                         "tx queue structure.");
2547                 return I40E_ERR_NO_MEMORY;
2548         }
2549
2550         /* Allocate TX hardware ring descriptors. */
2551         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2552         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2553
2554         tz = i40e_ring_dma_zone_reserve(dev,
2555                                         "fdir_tx_ring",
2556                                         I40E_FDIR_QUEUE_ID,
2557                                         ring_size,
2558                                         SOCKET_ID_ANY);
2559         if (!tz) {
2560                 i40e_dev_tx_queue_release(txq);
2561                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2562                 return I40E_ERR_NO_MEMORY;
2563         }
2564
2565         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2566         txq->queue_id = I40E_FDIR_QUEUE_ID;
2567         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2568         txq->vsi = pf->fdir.fdir_vsi;
2569
2570 #ifdef RTE_LIBRTE_XEN_DOM0
2571         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2572 #else
2573         txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2574 #endif
2575         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2576         /*
2577          * don't need to allocate software ring and reset for the fdir
2578          * program queue just set the queue has been configured.
2579          */
2580         txq->q_set = TRUE;
2581         pf->fdir.txq = txq;
2582
2583         return I40E_SUCCESS;
2584 }
2585
2586 enum i40e_status_code
2587 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2588 {
2589         struct i40e_rx_queue *rxq;
2590         const struct rte_memzone *rz = NULL;
2591         uint32_t ring_size;
2592         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2593
2594         if (!pf) {
2595                 PMD_DRV_LOG(ERR, "PF is not available");
2596                 return I40E_ERR_BAD_PTR;
2597         }
2598
2599         /* Allocate the RX queue data structure. */
2600         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2601                                   sizeof(struct i40e_rx_queue),
2602                                   RTE_CACHE_LINE_SIZE,
2603                                   SOCKET_ID_ANY);
2604         if (!rxq) {
2605                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2606                                         "rx queue structure.");
2607                 return I40E_ERR_NO_MEMORY;
2608         }
2609
2610         /* Allocate RX hardware ring descriptors. */
2611         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2612         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2613
2614         rz = i40e_ring_dma_zone_reserve(dev,
2615                                         "fdir_rx_ring",
2616                                         I40E_FDIR_QUEUE_ID,
2617                                         ring_size,
2618                                         SOCKET_ID_ANY);
2619         if (!rz) {
2620                 i40e_dev_rx_queue_release(rxq);
2621                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2622                 return I40E_ERR_NO_MEMORY;
2623         }
2624
2625         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2626         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2627         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2628         rxq->vsi = pf->fdir.fdir_vsi;
2629
2630 #ifdef RTE_LIBRTE_XEN_DOM0
2631         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2632 #else
2633         rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
2634 #endif
2635         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2636
2637         /*
2638          * Don't need to allocate software ring and reset for the fdir
2639          * rx queue, just set the queue has been configured.
2640          */
2641         rxq->q_set = TRUE;
2642         pf->fdir.rxq = rxq;
2643
2644         return I40E_SUCCESS;
2645 }