4 * Copyright(c) 2010-2012 Intel Corporation. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * * Neither the name of Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 * version: DPDK.L.1.2.3-3
36 #include <sys/queue.h>
42 #include <rte_common.h>
43 #include <rte_interrupts.h>
44 #include <rte_byteorder.h>
46 #include <rte_debug.h>
48 #include <rte_ether.h>
49 #include <rte_ethdev.h>
50 #include <rte_memory.h>
51 #include <rte_memzone.h>
52 #include <rte_tailq.h>
54 #include <rte_atomic.h>
55 #include <rte_malloc.h>
57 #include "e1000_logs.h"
58 #include "igb/e1000_api.h"
59 #include "igb/e1000_hw.h"
60 #include "e1000_ethdev.h"
62 static int eth_igb_configure(struct rte_eth_dev *dev, uint16_t nb_rx_q,
64 static int eth_igb_start(struct rte_eth_dev *dev);
65 static void eth_igb_stop(struct rte_eth_dev *dev);
66 static void eth_igb_close(struct rte_eth_dev *dev);
67 static void eth_igb_promiscuous_enable(struct rte_eth_dev *dev);
68 static void eth_igb_promiscuous_disable(struct rte_eth_dev *dev);
69 static void eth_igb_allmulticast_enable(struct rte_eth_dev *dev);
70 static void eth_igb_allmulticast_disable(struct rte_eth_dev *dev);
71 static int eth_igb_link_update(struct rte_eth_dev *dev,
72 int wait_to_complete);
73 static void eth_igb_stats_get(struct rte_eth_dev *dev,
74 struct rte_eth_stats *rte_stats);
75 static void eth_igb_stats_reset(struct rte_eth_dev *dev);
76 static void eth_igb_infos_get(struct rte_eth_dev *dev,
77 struct rte_eth_dev_info *dev_info);
78 static int eth_igb_flow_ctrl_set(struct rte_eth_dev *dev,
79 struct rte_eth_fc_conf *fc_conf);
80 static int eth_igb_interrupt_setup(struct rte_eth_dev *dev);
81 static int eth_igb_interrupt_get_status(struct rte_eth_dev *dev);
82 static int eth_igb_interrupt_action(struct rte_eth_dev *dev);
83 static void eth_igb_interrupt_handler(struct rte_intr_handle *handle,
85 static int igb_hardware_init(struct e1000_hw *hw);
86 static void igb_hw_control_acquire(struct e1000_hw *hw);
87 static void igb_hw_control_release(struct e1000_hw *hw);
88 static void igb_init_manageability(struct e1000_hw *hw);
89 static void igb_release_manageability(struct e1000_hw *hw);
90 static void igb_vlan_hw_support_enable(struct rte_eth_dev *dev);
91 static void igb_vlan_hw_support_disable(struct rte_eth_dev *dev);
92 static void eth_igb_vlan_filter_set(struct rte_eth_dev *dev,
95 static int eth_igb_led_on(struct rte_eth_dev *dev);
96 static int eth_igb_led_off(struct rte_eth_dev *dev);
98 static void igb_intr_disable(struct e1000_hw *hw);
99 static int igb_get_rx_buffer_size(struct e1000_hw *hw);
100 static void eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
101 uint32_t index, uint32_t pool);
102 static void eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index);
104 #define IGB_FC_PAUSE_TIME 0x0680
105 #define IGB_LINK_UPDATE_CHECK_TIMEOUT 90 /* 9s */
106 #define IGB_LINK_UPDATE_CHECK_INTERVAL 100 /* ms */
108 static enum e1000_fc_mode igb_fc_setting = e1000_fc_full;
111 * The set of PCI devices this driver supports
113 static struct rte_pci_id pci_id_igb_map[] = {
115 #undef RTE_LIBRTE_IXGBE_PMD
116 #define RTE_PCI_DEV_ID_DECL(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
117 #include "rte_pci_dev_ids.h"
122 static struct eth_dev_ops eth_igb_ops = {
123 .dev_configure = eth_igb_configure,
124 .dev_start = eth_igb_start,
125 .dev_stop = eth_igb_stop,
126 .dev_close = eth_igb_close,
127 .promiscuous_enable = eth_igb_promiscuous_enable,
128 .promiscuous_disable = eth_igb_promiscuous_disable,
129 .allmulticast_enable = eth_igb_allmulticast_enable,
130 .allmulticast_disable = eth_igb_allmulticast_disable,
131 .link_update = eth_igb_link_update,
132 .stats_get = eth_igb_stats_get,
133 .stats_reset = eth_igb_stats_reset,
134 .dev_infos_get = eth_igb_infos_get,
135 .vlan_filter_set = eth_igb_vlan_filter_set,
136 .rx_queue_setup = eth_igb_rx_queue_setup,
137 .tx_queue_setup = eth_igb_tx_queue_setup,
138 .dev_led_on = eth_igb_led_on,
139 .dev_led_off = eth_igb_led_off,
140 .flow_ctrl_set = eth_igb_flow_ctrl_set,
141 .mac_addr_add = eth_igb_rar_set,
142 .mac_addr_remove = eth_igb_rar_clear,
146 * Atomically reads the link status information from global
147 * structure rte_eth_dev.
150 * - Pointer to the structure rte_eth_dev to read from.
151 * - Pointer to the buffer to be saved with the link status.
154 * - On success, zero.
155 * - On failure, negative value.
158 rte_igb_dev_atomic_read_link_status(struct rte_eth_dev *dev,
159 struct rte_eth_link *link)
161 struct rte_eth_link *dst = link;
162 struct rte_eth_link *src = &(dev->data->dev_link);
164 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
165 *(uint64_t *)src) == 0)
172 * Atomically writes the link status information into global
173 * structure rte_eth_dev.
176 * - Pointer to the structure rte_eth_dev to read from.
177 * - Pointer to the buffer to be saved with the link status.
180 * - On success, zero.
181 * - On failure, negative value.
184 rte_igb_dev_atomic_write_link_status(struct rte_eth_dev *dev,
185 struct rte_eth_link *link)
187 struct rte_eth_link *dst = &(dev->data->dev_link);
188 struct rte_eth_link *src = link;
190 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
191 *(uint64_t *)src) == 0)
198 igb_identify_hardware(struct rte_eth_dev *dev)
200 struct e1000_hw *hw =
201 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
203 hw->vendor_id = dev->pci_dev->id.vendor_id;
204 hw->device_id = dev->pci_dev->id.device_id;
205 hw->subsystem_vendor_id = dev->pci_dev->id.subsystem_vendor_id;
206 hw->subsystem_device_id = dev->pci_dev->id.subsystem_device_id;
208 e1000_set_mac_type(hw);
210 /* need to check if it is a vf device below */
214 eth_igb_dev_init(__attribute__((unused)) struct eth_driver *eth_drv,
215 struct rte_eth_dev *eth_dev)
218 struct rte_pci_device *pci_dev;
219 struct e1000_hw *hw =
220 E1000_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
221 struct e1000_vfta * shadow_vfta =
222 E1000_DEV_PRIVATE_TO_VFTA(eth_dev->data->dev_private);
224 pci_dev = eth_dev->pci_dev;
225 eth_dev->dev_ops = ð_igb_ops;
226 eth_dev->rx_pkt_burst = ð_igb_recv_pkts;
227 eth_dev->tx_pkt_burst = ð_igb_xmit_pkts;
229 /* for secondary processes, we don't initialise any further as primary
230 * has already done this work. Only check we don't need a different
232 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
233 if (eth_dev->data->scattered_rx)
234 eth_dev->rx_pkt_burst = ð_igb_recv_scattered_pkts;
238 hw->hw_addr= (void *)pci_dev->mem_resource.addr;
240 igb_identify_hardware(eth_dev);
242 if (e1000_setup_init_funcs(hw, TRUE) != E1000_SUCCESS) {
247 e1000_get_bus_info(hw);
250 hw->phy.autoneg_wait_to_complete = 0;
251 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
254 if (hw->phy.media_type == e1000_media_type_copper) {
255 hw->phy.mdix = 0; /* AUTO_ALL_MODES */
256 hw->phy.disable_polarity_correction = 0;
257 hw->phy.ms_type = e1000_ms_hw_default;
261 * Start from a known state, this is important in reading the nvm
266 /* Make sure we have a good EEPROM before we read from it */
267 if (e1000_validate_nvm_checksum(hw) < 0) {
269 * Some PCI-E parts fail the first check due to
270 * the link being in sleep state, call it again,
271 * if it fails a second time its a real issue.
273 if (e1000_validate_nvm_checksum(hw) < 0) {
274 PMD_INIT_LOG(ERR, "EEPROM checksum invalid");
280 /* Read the permanent MAC address out of the EEPROM */
281 if (e1000_read_mac_addr(hw) != 0) {
282 PMD_INIT_LOG(ERR, "EEPROM error while reading MAC address");
287 /* Allocate memory for storing MAC addresses */
288 eth_dev->data->mac_addrs = rte_zmalloc("e1000",
289 ETHER_ADDR_LEN * hw->mac.rar_entry_count, 0);
290 if (eth_dev->data->mac_addrs == NULL) {
291 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to "
292 "store MAC addresses",
293 ETHER_ADDR_LEN * hw->mac.rar_entry_count);
298 /* Copy the permanent MAC address */
299 ether_addr_copy((struct ether_addr *)hw->mac.addr, ð_dev->data->mac_addrs[0]);
301 /* initialize the vfta */
302 memset(shadow_vfta, 0, sizeof(*shadow_vfta));
304 /* Now initialize the hardware */
305 if (igb_hardware_init(hw) != 0) {
306 PMD_INIT_LOG(ERR, "Hardware initialization failed");
307 rte_free(eth_dev->data->mac_addrs);
308 eth_dev->data->mac_addrs = NULL;
312 hw->mac.get_link_status = 1;
314 /* Indicate SOL/IDER usage */
315 if (e1000_check_reset_block(hw) < 0) {
316 PMD_INIT_LOG(ERR, "PHY reset is blocked due to"
320 PMD_INIT_LOG(INFO, "port_id %d vendorID=0x%x deviceID=0x%x\n",
321 eth_dev->data->port_id, pci_dev->id.vendor_id,
322 pci_dev->id.device_id);
324 rte_intr_callback_register(&(pci_dev->intr_handle),
325 eth_igb_interrupt_handler, (void *)eth_dev);
330 igb_hw_control_release(hw);
335 static struct eth_driver rte_igb_pmd = {
337 .name = "rte_igb_pmd",
338 .id_table = pci_id_igb_map,
339 .drv_flags = RTE_PCI_DRV_NEED_IGB_UIO,
341 .eth_dev_init = eth_igb_dev_init,
342 .dev_private_size = sizeof(struct e1000_adapter),
346 rte_igb_pmd_init(void)
348 rte_eth_driver_register(&rte_igb_pmd);
353 eth_igb_configure(struct rte_eth_dev *dev, uint16_t nb_rx_q, uint16_t nb_tx_q)
355 struct e1000_interrupt *intr =
356 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
359 PMD_INIT_LOG(DEBUG, ">>");
361 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
363 /* Allocate the array of pointers to RX structures */
364 diag = igb_dev_rx_queue_alloc(dev, nb_rx_q);
366 PMD_INIT_LOG(ERR, "ethdev port_id=%u allocation of array of %u"
367 " pointers to RX queues failed",
368 dev->data->port_id, nb_rx_q);
372 /* Allocate the array of pointers to TX structures */
373 diag = igb_dev_tx_queue_alloc(dev, nb_tx_q);
375 PMD_INIT_LOG(ERR, "ethdev port_id=%u allocation of array of %u"
376 " pointers to TX queues failed",
377 dev->data->port_id, nb_tx_q);
382 PMD_INIT_LOG(DEBUG, "<<");
388 eth_igb_start(struct rte_eth_dev *dev)
390 struct e1000_hw *hw =
391 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
394 PMD_INIT_LOG(DEBUG, ">>");
396 igb_intr_disable(hw);
398 /* Power up the phy. Needed to make the link go Up */
399 e1000_power_up_phy(hw);
402 * Packet Buffer Allocation (PBA)
403 * Writing PBA sets the receive portion of the buffer
404 * the remainder is used for the transmit buffer.
406 if (hw->mac.type == e1000_82575) {
409 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
410 E1000_WRITE_REG(hw, E1000_PBA, pba);
413 /* Put the address into the Receive Address Array */
414 e1000_rar_set(hw, hw->mac.addr, 0);
416 /* Initialize the hardware */
417 if (igb_hardware_init(hw)) {
418 PMD_INIT_LOG(ERR, "Unable to initialize the hardware");
422 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
424 /* Configure for OS presence */
425 igb_init_manageability(hw);
427 eth_igb_tx_init(dev);
429 /* This can fail when allocating mbufs for descriptor rings */
430 ret = eth_igb_rx_init(dev);
432 PMD_INIT_LOG(ERR, "Unable to initialize RX hardware");
436 e1000_clear_hw_cntrs_base_generic(hw);
439 * If VLAN filtering is enabled, set up VLAN tag offload and filtering
440 * and restore the VFTA.
442 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
443 igb_vlan_hw_support_enable(dev);
445 igb_vlan_hw_support_disable(dev);
448 * Configure the Interrupt Moderation register (EITR) with the maximum
449 * possible value (0xFFFF) to minimize "System Partial Write" issued by
450 * spurious [DMA] memory updates of RX and TX ring descriptors.
452 * With a EITR granularity of 2 microseconds in the 82576, only 7/8
453 * spurious memory updates per second should be expected.
454 * ((65535 * 2) / 1000.1000 ~= 0.131 second).
456 * Because interrupts are not used at all, the MSI-X is not activated
457 * and interrupt moderation is controlled by EITR[0].
459 * Note that having [almost] disabled memory updates of RX and TX ring
460 * descriptors through the Interrupt Moderation mechanism, memory
461 * updates of ring descriptors are now moderated by the configurable
462 * value of Write-Back Threshold registers.
464 if ((hw->mac.type == e1000_82576) || (hw->mac.type == e1000_82580) ||
465 (hw->mac.type == e1000_i350)) {
468 /* Enable all RX & TX queues in the IVAR registers */
469 ivar = (uint32_t) ((E1000_IVAR_VALID << 16) | E1000_IVAR_VALID);
470 for (i = 0; i < 8; i++)
471 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, ivar);
473 /* Configure EITR with the maximum possible value (0xFFFF) */
474 E1000_WRITE_REG(hw, E1000_EITR(0), 0xFFFF);
477 /* Don't reset the phy next time init gets called */
478 hw->phy.reset_disable = 1;
480 /* Setup link speed and duplex */
481 switch (dev->data->dev_conf.link_speed) {
482 case ETH_LINK_SPEED_AUTONEG:
483 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
484 hw->phy.autoneg_advertised = E1000_ALL_SPEED_DUPLEX;
485 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
486 hw->phy.autoneg_advertised = E1000_ALL_HALF_DUPLEX;
487 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
488 hw->phy.autoneg_advertised = E1000_ALL_FULL_DUPLEX;
490 goto error_invalid_config;
492 case ETH_LINK_SPEED_10:
493 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
494 hw->phy.autoneg_advertised = E1000_ALL_10_SPEED;
495 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
496 hw->phy.autoneg_advertised = ADVERTISE_10_HALF;
497 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
498 hw->phy.autoneg_advertised = ADVERTISE_10_FULL;
500 goto error_invalid_config;
502 case ETH_LINK_SPEED_100:
503 if (dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX)
504 hw->phy.autoneg_advertised = E1000_ALL_100_SPEED;
505 else if (dev->data->dev_conf.link_duplex == ETH_LINK_HALF_DUPLEX)
506 hw->phy.autoneg_advertised = ADVERTISE_100_HALF;
507 else if (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX)
508 hw->phy.autoneg_advertised = ADVERTISE_100_FULL;
510 goto error_invalid_config;
512 case ETH_LINK_SPEED_1000:
513 if ((dev->data->dev_conf.link_duplex == ETH_LINK_AUTONEG_DUPLEX) ||
514 (dev->data->dev_conf.link_duplex == ETH_LINK_FULL_DUPLEX))
515 hw->phy.autoneg_advertised = ADVERTISE_1000_FULL;
517 goto error_invalid_config;
519 case ETH_LINK_SPEED_10000:
521 goto error_invalid_config;
523 e1000_setup_link(hw);
525 PMD_INIT_LOG(DEBUG, "<<");
527 /* check if lsc interrupt feature is enabled */
528 if (dev->data->dev_conf.intr_conf.lsc != 0)
529 return eth_igb_interrupt_setup(dev);
533 error_invalid_config:
534 PMD_INIT_LOG(ERR, "Invalid link_speed/link_duplex (%u/%u) for port %u\n",
535 dev->data->dev_conf.link_speed,
536 dev->data->dev_conf.link_duplex, dev->data->port_id);
540 /*********************************************************************
542 * This routine disables all traffic on the adapter by issuing a
543 * global reset on the MAC.
545 **********************************************************************/
547 eth_igb_stop(struct rte_eth_dev *dev)
549 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
550 struct rte_eth_link link;
552 igb_intr_disable(hw);
554 E1000_WRITE_REG(hw, E1000_WUC, 0);
556 /* Power down the phy. Needed to make the link go Down */
557 e1000_power_down_phy(hw);
559 igb_dev_clear_queues(dev);
561 /* clear the recorded link status */
562 memset(&link, 0, sizeof(link));
563 rte_igb_dev_atomic_write_link_status(dev, &link);
567 eth_igb_close(struct rte_eth_dev *dev)
569 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
570 struct rte_eth_link link;
573 e1000_phy_hw_reset(hw);
574 igb_release_manageability(hw);
575 igb_hw_control_release(hw);
577 igb_dev_clear_queues(dev);
579 memset(&link, 0, sizeof(link));
580 rte_igb_dev_atomic_write_link_status(dev, &link);
584 igb_get_rx_buffer_size(struct e1000_hw *hw)
586 uint32_t rx_buf_size;
587 if (hw->mac.type == e1000_82576) {
588 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xffff) << 10;
589 } else if (hw->mac.type == e1000_82580) {
590 /* PBS needs to be translated according to a lookup table */
591 rx_buf_size = (E1000_READ_REG(hw, E1000_RXPBS) & 0xf);
592 rx_buf_size = (uint32_t) e1000_rxpbs_adjust_82580(rx_buf_size);
593 rx_buf_size = (rx_buf_size << 10);
595 rx_buf_size = (E1000_READ_REG(hw, E1000_PBA) & 0xffff) << 10;
601 /*********************************************************************
603 * Initialize the hardware
605 **********************************************************************/
607 igb_hardware_init(struct e1000_hw *hw)
609 uint32_t rx_buf_size;
612 /* Let the firmware know the OS is in control */
613 igb_hw_control_acquire(hw);
616 * These parameters control the automatic generation (Tx) and
617 * response (Rx) to Ethernet PAUSE frames.
618 * - High water mark should allow for at least two standard size (1518)
619 * frames to be received after sending an XOFF.
620 * - Low water mark works best when it is very near the high water mark.
621 * This allows the receiver to restart by sending XON when it has
622 * drained a bit. Here we use an arbitary value of 1500 which will
623 * restart after one full frame is pulled from the buffer. There
624 * could be several smaller frames in the buffer and if so they will
625 * not trigger the XON until their total number reduces the buffer
627 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
629 rx_buf_size = igb_get_rx_buffer_size(hw);
631 hw->fc.high_water = rx_buf_size - (ETHER_MAX_LEN * 2);
632 hw->fc.low_water = hw->fc.high_water - 1500;
633 hw->fc.pause_time = IGB_FC_PAUSE_TIME;
636 /* Set Flow control, use the tunable location if sane */
637 if ((igb_fc_setting != e1000_fc_none) && (igb_fc_setting < 4))
638 hw->fc.requested_mode = igb_fc_setting;
640 hw->fc.requested_mode = e1000_fc_none;
642 /* Issue a global reset */
644 E1000_WRITE_REG(hw, E1000_WUC, 0);
646 diag = e1000_init_hw(hw);
650 E1000_WRITE_REG(hw, E1000_VET, ETHER_TYPE_VLAN);
651 e1000_get_phy_info(hw);
652 e1000_check_for_link(hw);
657 /* This function is based on igb_update_stats_counters() in igb/if_igb.c */
659 eth_igb_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *rte_stats)
661 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
662 struct e1000_hw_stats *stats =
663 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
666 if(hw->phy.media_type == e1000_media_type_copper ||
667 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
669 E1000_READ_REG(hw,E1000_SYMERRS);
670 stats->sec += E1000_READ_REG(hw, E1000_SEC);
673 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
674 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
675 stats->scc += E1000_READ_REG(hw, E1000_SCC);
676 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
678 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
679 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
680 stats->colc += E1000_READ_REG(hw, E1000_COLC);
681 stats->dc += E1000_READ_REG(hw, E1000_DC);
682 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
683 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
684 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
686 ** For watchdog management we need to know if we have been
687 ** paused during the last interval, so capture that here.
689 pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
690 stats->xoffrxc += pause_frames;
691 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
692 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
693 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
694 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
695 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
696 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
697 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
698 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
699 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
700 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
701 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
702 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
704 /* For the 64-bit byte counters the low dword must be read first. */
705 /* Both registers clear on the read of the high dword */
707 stats->gorc += E1000_READ_REG(hw, E1000_GORCL);
708 stats->gorc += ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
709 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL);
710 stats->gotc += ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
712 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
713 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
714 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
715 stats->roc += E1000_READ_REG(hw, E1000_ROC);
716 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
718 stats->tor += E1000_READ_REG(hw, E1000_TORH);
719 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
721 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
722 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
723 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
724 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
725 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
726 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
727 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
728 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
729 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
730 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
732 /* Interrupt Counts */
734 stats->iac += E1000_READ_REG(hw, E1000_IAC);
735 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
736 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
737 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
738 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
739 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
740 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
741 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
742 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
744 /* Host to Card Statistics */
746 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
747 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
748 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
749 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
750 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
751 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
752 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
753 stats->hgorc += E1000_READ_REG(hw, E1000_HGORCL);
754 stats->hgorc += ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32);
755 stats->hgotc += E1000_READ_REG(hw, E1000_HGOTCL);
756 stats->hgotc += ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32);
757 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
758 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
759 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
761 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
762 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
763 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
764 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
765 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
766 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
768 if (rte_stats == NULL)
772 rte_stats->ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
773 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
776 rte_stats->oerrors = stats->ecol + stats->latecol;
778 rte_stats->ipackets = stats->gprc;
779 rte_stats->opackets = stats->gptc;
780 rte_stats->ibytes = stats->gorc;
781 rte_stats->obytes = stats->gotc;
785 eth_igb_stats_reset(struct rte_eth_dev *dev)
787 struct e1000_hw_stats *hw_stats =
788 E1000_DEV_PRIVATE_TO_STATS(dev->data->dev_private);
790 /* HW registers are cleared on read */
791 eth_igb_stats_get(dev, NULL);
793 /* Reset software totals */
794 memset(hw_stats, 0, sizeof(*hw_stats));
798 eth_igb_infos_get(struct rte_eth_dev *dev,
799 struct rte_eth_dev_info *dev_info)
801 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
803 dev_info->min_rx_bufsize = 256; /* See BSIZE field of RCTL register. */
804 dev_info->max_rx_pktlen = 0x3FFF; /* See RLPML register. */
805 dev_info->max_mac_addrs = hw->mac.rar_entry_count;
807 switch (hw->mac.type) {
809 dev_info->max_rx_queues = 4;
810 dev_info->max_tx_queues = 4;
814 dev_info->max_rx_queues = 16;
815 dev_info->max_tx_queues = 16;
819 dev_info->max_rx_queues = 8;
820 dev_info->max_tx_queues = 8;
824 dev_info->max_rx_queues = 8;
825 dev_info->max_tx_queues = 8;
829 /* Should not happen */
830 dev_info->max_rx_queues = 0;
831 dev_info->max_tx_queues = 0;
835 /* return 0 means link status changed, -1 means not changed */
837 eth_igb_link_update(struct rte_eth_dev *dev, int wait_to_complete)
839 struct e1000_hw *hw =
840 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
841 struct rte_eth_link link, old;
842 int link_check, count;
845 hw->mac.get_link_status = 1;
847 /* possible wait-to-complete in up to 9 seconds */
848 for (count = 0; count < IGB_LINK_UPDATE_CHECK_TIMEOUT; count ++) {
849 /* Read the real link status */
850 switch (hw->phy.media_type) {
851 case e1000_media_type_copper:
852 /* Do the work to read phy */
853 e1000_check_for_link(hw);
854 link_check = !hw->mac.get_link_status;
857 case e1000_media_type_fiber:
858 e1000_check_for_link(hw);
859 link_check = (E1000_READ_REG(hw, E1000_STATUS) &
863 case e1000_media_type_internal_serdes:
864 e1000_check_for_link(hw);
865 link_check = hw->mac.serdes_has_link;
869 case e1000_media_type_unknown:
872 if (link_check || wait_to_complete == 0)
874 rte_delay_ms(IGB_LINK_UPDATE_CHECK_INTERVAL);
876 memset(&link, 0, sizeof(link));
877 rte_igb_dev_atomic_read_link_status(dev, &link);
880 /* Now we check if a transition has happened */
882 hw->mac.ops.get_link_up_info(hw, &link.link_speed,
884 link.link_status = 1;
885 } else if (!link_check) {
887 link.link_duplex = 0;
888 link.link_status = 0;
890 rte_igb_dev_atomic_write_link_status(dev, &link);
893 if (old.link_status == link.link_status)
901 * igb_hw_control_acquire sets CTRL_EXT:DRV_LOAD bit.
902 * For ASF and Pass Through versions of f/w this means
903 * that the driver is loaded.
906 igb_hw_control_acquire(struct e1000_hw *hw)
910 /* Let firmware know the driver has taken over */
911 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
912 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
916 * igb_hw_control_release resets CTRL_EXT:DRV_LOAD bit.
917 * For ASF and Pass Through versions of f/w this means that the
918 * driver is no longer loaded.
921 igb_hw_control_release(struct e1000_hw *hw)
925 /* Let firmware taken over control of h/w */
926 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
927 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
928 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
932 * Bit of a misnomer, what this really means is
933 * to enable OS management of the system... aka
934 * to disable special hardware management features.
937 igb_init_manageability(struct e1000_hw *hw)
939 if (e1000_enable_mng_pass_thru(hw)) {
940 uint32_t manc2h = E1000_READ_REG(hw, E1000_MANC2H);
941 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
943 /* disable hardware interception of ARP */
944 manc &= ~(E1000_MANC_ARP_EN);
946 /* enable receiving management packets to the host */
947 manc |= E1000_MANC_EN_MNG2HOST;
948 manc2h |= 1 << 5; /* Mng Port 623 */
949 manc2h |= 1 << 6; /* Mng Port 664 */
950 E1000_WRITE_REG(hw, E1000_MANC2H, manc2h);
951 E1000_WRITE_REG(hw, E1000_MANC, manc);
956 igb_release_manageability(struct e1000_hw *hw)
958 if (e1000_enable_mng_pass_thru(hw)) {
959 uint32_t manc = E1000_READ_REG(hw, E1000_MANC);
961 manc |= E1000_MANC_ARP_EN;
962 manc &= ~E1000_MANC_EN_MNG2HOST;
964 E1000_WRITE_REG(hw, E1000_MANC, manc);
969 eth_igb_promiscuous_enable(struct rte_eth_dev *dev)
971 struct e1000_hw *hw =
972 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
975 rctl = E1000_READ_REG(hw, E1000_RCTL);
976 rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
977 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
981 eth_igb_promiscuous_disable(struct rte_eth_dev *dev)
983 struct e1000_hw *hw =
984 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
987 rctl = E1000_READ_REG(hw, E1000_RCTL);
988 rctl &= (~E1000_RCTL_UPE);
989 if (dev->data->all_multicast == 1)
990 rctl |= E1000_RCTL_MPE;
992 rctl &= (~E1000_RCTL_MPE);
993 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
997 eth_igb_allmulticast_enable(struct rte_eth_dev *dev)
999 struct e1000_hw *hw =
1000 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1003 rctl = E1000_READ_REG(hw, E1000_RCTL);
1004 rctl |= E1000_RCTL_MPE;
1005 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1009 eth_igb_allmulticast_disable(struct rte_eth_dev *dev)
1011 struct e1000_hw *hw =
1012 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1015 if (dev->data->promiscuous == 1)
1016 return; /* must remain in all_multicast mode */
1017 rctl = E1000_READ_REG(hw, E1000_RCTL);
1018 rctl &= (~E1000_RCTL_MPE);
1019 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1023 eth_igb_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1025 struct e1000_hw *hw =
1026 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1027 struct e1000_vfta * shadow_vfta =
1028 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1033 vid_idx = (uint32_t) ((vlan_id >> E1000_VFTA_ENTRY_SHIFT) &
1034 E1000_VFTA_ENTRY_MASK);
1035 vid_bit = (uint32_t) (1 << (vlan_id & E1000_VFTA_ENTRY_BIT_SHIFT_MASK));
1036 vfta = E1000_READ_REG_ARRAY(hw, E1000_VFTA, vid_idx);
1041 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, vid_idx, vfta);
1043 /* update local VFTA copy */
1044 shadow_vfta->vfta[vid_idx] = vfta;
1048 igb_vlan_hw_support_enable(struct rte_eth_dev *dev)
1050 struct e1000_hw *hw =
1051 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1052 struct e1000_vfta * shadow_vfta =
1053 E1000_DEV_PRIVATE_TO_VFTA(dev->data->dev_private);
1057 /* VLAN Mode Enable */
1058 reg = E1000_READ_REG(hw, E1000_CTRL);
1059 reg |= E1000_CTRL_VME;
1060 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1062 /* Filter Table Enable */
1063 reg = E1000_READ_REG(hw, E1000_RCTL);
1064 reg &= ~E1000_RCTL_CFIEN;
1065 reg |= E1000_RCTL_VFE;
1066 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1068 /* Update maximum frame size */
1069 reg = E1000_READ_REG(hw, E1000_RLPML);
1070 reg += VLAN_TAG_SIZE;
1071 E1000_WRITE_REG(hw, E1000_RLPML, reg);
1073 /* restore VFTA table */
1074 for (i = 0; i < E1000_VFTA_SIZE; i++)
1075 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, i, shadow_vfta->vfta[i]);
1079 igb_vlan_hw_support_disable(struct rte_eth_dev *dev)
1081 struct e1000_hw *hw =
1082 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1085 /* VLAN Mode disable */
1086 reg = E1000_READ_REG(hw, E1000_CTRL);
1087 reg &= ~E1000_CTRL_VME;
1088 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1092 igb_intr_disable(struct e1000_hw *hw)
1094 E1000_WRITE_REG(hw, E1000_IMC, ~0);
1095 E1000_WRITE_FLUSH(hw);
1099 * It enables the interrupt mask and then enable the interrupt.
1102 * Pointer to struct rte_eth_dev.
1105 * - On success, zero.
1106 * - On failure, a negative value.
1109 eth_igb_interrupt_setup(struct rte_eth_dev *dev)
1111 struct e1000_hw *hw =
1112 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1114 E1000_WRITE_REG(hw, E1000_IMS, E1000_ICR_LSC);
1115 E1000_WRITE_FLUSH(hw);
1116 rte_intr_enable(&(dev->pci_dev->intr_handle));
1122 * It reads ICR and gets interrupt causes, check it and set a bit flag
1123 * to update link status.
1126 * Pointer to struct rte_eth_dev.
1129 * - On success, zero.
1130 * - On failure, a negative value.
1133 eth_igb_interrupt_get_status(struct rte_eth_dev *dev)
1136 struct e1000_hw *hw =
1137 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1138 struct e1000_interrupt *intr =
1139 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1141 /* read-on-clear nic registers here */
1142 icr = E1000_READ_REG(hw, E1000_ICR);
1143 if (icr & E1000_ICR_LSC) {
1144 intr->flags |= E1000_FLAG_NEED_LINK_UPDATE;
1151 * It executes link_update after knowing an interrupt is prsent.
1154 * Pointer to struct rte_eth_dev.
1157 * - On success, zero.
1158 * - On failure, a negative value.
1161 eth_igb_interrupt_action(struct rte_eth_dev *dev)
1163 struct e1000_hw *hw =
1164 E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1165 struct e1000_interrupt *intr =
1166 E1000_DEV_PRIVATE_TO_INTR(dev->data->dev_private);
1167 uint32_t tctl, rctl;
1168 struct rte_eth_link link;
1171 if (!(intr->flags & E1000_FLAG_NEED_LINK_UPDATE))
1174 intr->flags &= ~E1000_FLAG_NEED_LINK_UPDATE;
1175 rte_intr_enable(&(dev->pci_dev->intr_handle));
1177 /* set get_link_status to check register later */
1178 hw->mac.get_link_status = 1;
1179 ret = eth_igb_link_update(dev, 0);
1181 /* check if link has changed */
1185 memset(&link, 0, sizeof(link));
1186 rte_igb_dev_atomic_read_link_status(dev, &link);
1187 if (link.link_status) {
1189 " Port %d: Link Up - speed %u Mbps - %s\n",
1190 dev->data->port_id, (unsigned)link.link_speed,
1191 link.link_duplex == ETH_LINK_FULL_DUPLEX ?
1192 "full-duplex" : "half-duplex");
1194 PMD_INIT_LOG(INFO, " Port %d: Link Down\n",
1195 dev->data->port_id);
1197 PMD_INIT_LOG(INFO, "PCI Address: %04d:%02d:%02d:%d",
1198 dev->pci_dev->addr.domain,
1199 dev->pci_dev->addr.bus,
1200 dev->pci_dev->addr.devid,
1201 dev->pci_dev->addr.function);
1202 tctl = E1000_READ_REG(hw, E1000_TCTL);
1203 rctl = E1000_READ_REG(hw, E1000_RCTL);
1204 if (link.link_status) {
1206 tctl |= E1000_TCTL_EN;
1207 rctl |= E1000_RCTL_EN;
1210 tctl &= ~E1000_TCTL_EN;
1211 rctl &= ~E1000_RCTL_EN;
1213 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1214 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1215 E1000_WRITE_FLUSH(hw);
1221 * Interrupt handler which shall be registered at first.
1224 * Pointer to interrupt handle.
1226 * The address of parameter (struct rte_eth_dev *) regsitered before.
1232 eth_igb_interrupt_handler(struct rte_intr_handle *handle, void *param)
1234 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1236 eth_igb_interrupt_get_status(dev);
1237 eth_igb_interrupt_action(dev);
1238 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
1242 eth_igb_led_on(struct rte_eth_dev *dev)
1244 struct e1000_hw *hw;
1246 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1247 return (e1000_led_on(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1251 eth_igb_led_off(struct rte_eth_dev *dev)
1253 struct e1000_hw *hw;
1255 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1256 return (e1000_led_off(hw) == E1000_SUCCESS ? 0 : -ENOTSUP);
1260 eth_igb_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1262 struct e1000_hw *hw;
1264 enum e1000_fc_mode rte_fcmode_2_e1000_fcmode[] = {
1270 uint32_t rx_buf_size;
1271 uint32_t max_high_water;
1273 hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274 rx_buf_size = igb_get_rx_buffer_size(hw);
1275 PMD_INIT_LOG(DEBUG, "Rx packet buffer size = 0x%x \n", rx_buf_size);
1277 /* At least reserve one Ethernet frame for watermark */
1278 max_high_water = rx_buf_size - ETHER_MAX_LEN;
1279 if ((fc_conf->high_water > max_high_water) ||
1280 (fc_conf->high_water < fc_conf->low_water)) {
1281 PMD_INIT_LOG(ERR, "e1000 incorrect high/low water value \n");
1282 PMD_INIT_LOG(ERR, "high water must <= 0x%x \n", max_high_water);
1286 hw->fc.requested_mode = rte_fcmode_2_e1000_fcmode[fc_conf->mode];
1287 hw->fc.pause_time = fc_conf->pause_time;
1288 hw->fc.high_water = fc_conf->high_water;
1289 hw->fc.low_water = fc_conf->low_water;
1290 hw->fc.send_xon = fc_conf->send_xon;
1292 err = e1000_setup_link_generic(hw);
1293 if (err == E1000_SUCCESS) {
1297 PMD_INIT_LOG(ERR, "e1000_setup_link_generic = 0x%x \n", err);
1302 eth_igb_rar_set(struct rte_eth_dev *dev, struct ether_addr *mac_addr,
1303 uint32_t index, __rte_unused uint32_t pool)
1305 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1307 e1000_rar_set(hw, mac_addr->addr_bytes, index);
1311 eth_igb_rar_clear(struct rte_eth_dev *dev, uint32_t index)
1313 uint8_t addr[ETHER_ADDR_LEN];
1314 struct e1000_hw *hw = E1000_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1316 memset(addr, 0, sizeof(addr));
1318 e1000_rar_set(hw, addr, index);