1 /******************************************************************************
3 Copyright (c) 2001-2011, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
38 #include "e1000_osdep.h"
39 #include "e1000_regs.h"
40 #include "e1000_defines.h"
44 #define E1000_DEV_ID_82576 0x10C9
45 #define E1000_DEV_ID_82576_FIBER 0x10E6
46 #define E1000_DEV_ID_82576_SERDES 0x10E7
47 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8
48 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2 0x1526
49 #define E1000_DEV_ID_82576_NS 0x150A
50 #define E1000_DEV_ID_82576_NS_SERDES 0x1518
51 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D
52 #define E1000_DEV_ID_82576_VF 0x10CA
53 #define E1000_DEV_ID_I350_VF 0x1520
54 #define E1000_DEV_ID_82575EB_COPPER 0x10A7
55 #define E1000_DEV_ID_82575EB_FIBER_SERDES 0x10A9
56 #define E1000_DEV_ID_82575GB_QUAD_COPPER 0x10D6
57 #define E1000_DEV_ID_82580_COPPER 0x150E
58 #define E1000_DEV_ID_82580_FIBER 0x150F
59 #define E1000_DEV_ID_82580_SERDES 0x1510
60 #define E1000_DEV_ID_82580_SGMII 0x1511
61 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516
62 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527
63 #define E1000_DEV_ID_I350_COPPER 0x1521
64 #define E1000_DEV_ID_I350_FIBER 0x1522
65 #define E1000_DEV_ID_I350_SERDES 0x1523
66 #define E1000_DEV_ID_I350_SGMII 0x1524
67 #define E1000_DEV_ID_I350_DA4 0x1546
68 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438
69 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A
70 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C
71 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440
72 #define E1000_REVISION_0 0
73 #define E1000_REVISION_1 1
74 #define E1000_REVISION_2 2
75 #define E1000_REVISION_3 3
76 #define E1000_REVISION_4 4
78 #define E1000_FUNC_0 0
79 #define E1000_FUNC_1 1
80 #define E1000_FUNC_2 2
81 #define E1000_FUNC_3 3
83 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0 0
84 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1 3
85 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2 6
86 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3 9
96 e1000_num_macs /* List is 1-based, so subtract 1 for TRUE count. */
99 enum e1000_media_type {
100 e1000_media_type_unknown = 0,
101 e1000_media_type_copper = 1,
102 e1000_media_type_fiber = 2,
103 e1000_media_type_internal_serdes = 3,
104 e1000_num_media_types
107 enum e1000_nvm_type {
108 e1000_nvm_unknown = 0,
110 e1000_nvm_eeprom_spi,
111 e1000_nvm_eeprom_microwire,
116 enum e1000_nvm_override {
117 e1000_nvm_override_none = 0,
118 e1000_nvm_override_spi_small,
119 e1000_nvm_override_spi_large,
120 e1000_nvm_override_microwire_small,
121 e1000_nvm_override_microwire_large
124 enum e1000_phy_type {
125 e1000_phy_unknown = 0,
137 enum e1000_bus_type {
138 e1000_bus_type_unknown = 0,
141 e1000_bus_type_pci_express,
142 e1000_bus_type_reserved
145 enum e1000_bus_speed {
146 e1000_bus_speed_unknown = 0,
152 e1000_bus_speed_2500,
153 e1000_bus_speed_5000,
154 e1000_bus_speed_reserved
157 enum e1000_bus_width {
158 e1000_bus_width_unknown = 0,
159 e1000_bus_width_pcie_x1,
160 e1000_bus_width_pcie_x2,
161 e1000_bus_width_pcie_x4 = 4,
162 e1000_bus_width_pcie_x8 = 8,
165 e1000_bus_width_reserved
168 enum e1000_1000t_rx_status {
169 e1000_1000t_rx_status_not_ok = 0,
170 e1000_1000t_rx_status_ok,
171 e1000_1000t_rx_status_undefined = 0xFF
174 enum e1000_rev_polarity {
175 e1000_rev_polarity_normal = 0,
176 e1000_rev_polarity_reversed,
177 e1000_rev_polarity_undefined = 0xFF
185 e1000_fc_default = 0xFF
189 e1000_ms_hw_default = 0,
190 e1000_ms_force_master,
191 e1000_ms_force_slave,
195 enum e1000_smart_speed {
196 e1000_smart_speed_default = 0,
197 e1000_smart_speed_on,
198 e1000_smart_speed_off
201 enum e1000_serdes_link_state {
202 e1000_serdes_link_down = 0,
203 e1000_serdes_link_autoneg_progress,
204 e1000_serdes_link_autoneg_complete,
205 e1000_serdes_link_forced_up
211 /* Receive Descriptor */
212 struct e1000_rx_desc {
213 __le64 buffer_addr; /* Address of the descriptor's data buffer */
214 __le16 length; /* Length of data DMAed into data buffer */
215 __le16 csum; /* Packet checksum */
216 u8 status; /* Descriptor status */
217 u8 errors; /* Descriptor Errors */
221 /* Receive Descriptor - Extended */
222 union e1000_rx_desc_extended {
229 __le32 mrq; /* Multiple Rx Queues */
231 __le32 rss; /* RSS Hash */
233 __le16 ip_id; /* IP id */
234 __le16 csum; /* Packet Checksum */
239 __le32 status_error; /* ext status/error */
241 __le16 vlan; /* VLAN tag */
243 } wb; /* writeback */
246 #define MAX_PS_BUFFERS 4
247 /* Receive Descriptor - Packet Split */
248 union e1000_rx_desc_packet_split {
250 /* one buffer for protocol header(s), three data buffers */
251 __le64 buffer_addr[MAX_PS_BUFFERS];
255 __le32 mrq; /* Multiple Rx Queues */
257 __le32 rss; /* RSS Hash */
259 __le16 ip_id; /* IP id */
260 __le16 csum; /* Packet Checksum */
265 __le32 status_error; /* ext status/error */
266 __le16 length0; /* length of buffer 0 */
267 __le16 vlan; /* VLAN tag */
270 __le16 header_status;
271 __le16 length[3]; /* length of buffers 1-3 */
274 } wb; /* writeback */
277 /* Transmit Descriptor */
278 struct e1000_tx_desc {
279 __le64 buffer_addr; /* Address of the descriptor's data buffer */
283 __le16 length; /* Data buffer length */
284 u8 cso; /* Checksum offset */
285 u8 cmd; /* Descriptor control */
291 u8 status; /* Descriptor status */
292 u8 css; /* Checksum start */
298 /* Offload Context Descriptor */
299 struct e1000_context_desc {
303 u8 ipcss; /* IP checksum start */
304 u8 ipcso; /* IP checksum offset */
305 __le16 ipcse; /* IP checksum end */
311 u8 tucss; /* TCP checksum start */
312 u8 tucso; /* TCP checksum offset */
313 __le16 tucse; /* TCP checksum end */
316 __le32 cmd_and_length;
320 u8 status; /* Descriptor status */
321 u8 hdr_len; /* Header length */
322 __le16 mss; /* Maximum segment size */
327 /* Offload data descriptor */
328 struct e1000_data_desc {
329 __le64 buffer_addr; /* Address of the descriptor's buffer address */
333 __le16 length; /* Data buffer length */
341 u8 status; /* Descriptor status */
342 u8 popts; /* Packet Options */
348 /* Statistics counters collected by the MAC */
349 struct e1000_hw_stats {
428 struct e1000_vf_stats {
460 struct e1000_phy_stats {
465 struct e1000_host_mng_dhcp_cookie {
476 /* Host Interface "Rev 1" */
477 struct e1000_host_command_header {
484 #define E1000_HI_MAX_DATA_LENGTH 252
485 struct e1000_host_command_info {
486 struct e1000_host_command_header command_header;
487 u8 command_data[E1000_HI_MAX_DATA_LENGTH];
490 /* Host Interface "Rev 2" */
491 struct e1000_host_mng_command_header {
499 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8
500 struct e1000_host_mng_command_info {
501 struct e1000_host_mng_command_header command_header;
502 u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
505 #include "e1000_mac.h"
506 #include "e1000_phy.h"
507 #include "e1000_nvm.h"
508 #include "e1000_manage.h"
509 #include "e1000_mbx.h"
511 struct e1000_mac_operations {
512 /* Function pointers for the MAC. */
513 s32 (*init_params)(struct e1000_hw *);
514 s32 (*id_led_init)(struct e1000_hw *);
515 s32 (*blink_led)(struct e1000_hw *);
516 s32 (*check_for_link)(struct e1000_hw *);
517 bool (*check_mng_mode)(struct e1000_hw *hw);
518 s32 (*cleanup_led)(struct e1000_hw *);
519 void (*clear_hw_cntrs)(struct e1000_hw *);
520 void (*clear_vfta)(struct e1000_hw *);
521 s32 (*get_bus_info)(struct e1000_hw *);
522 void (*set_lan_id)(struct e1000_hw *);
523 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
524 s32 (*led_on)(struct e1000_hw *);
525 s32 (*led_off)(struct e1000_hw *);
526 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
527 s32 (*reset_hw)(struct e1000_hw *);
528 s32 (*init_hw)(struct e1000_hw *);
529 void (*shutdown_serdes)(struct e1000_hw *);
530 void (*power_up_serdes)(struct e1000_hw *);
531 s32 (*setup_link)(struct e1000_hw *);
532 s32 (*setup_physical_interface)(struct e1000_hw *);
533 s32 (*setup_led)(struct e1000_hw *);
534 void (*write_vfta)(struct e1000_hw *, u32, u32);
535 void (*config_collision_dist)(struct e1000_hw *);
536 void (*rar_set)(struct e1000_hw *, u8*, u32);
537 s32 (*read_mac_addr)(struct e1000_hw *);
538 s32 (*validate_mdi_setting)(struct e1000_hw *);
539 s32 (*mng_host_if_write)(struct e1000_hw *, u8*, u16, u16, u8*);
540 s32 (*mng_write_cmd_header)(struct e1000_hw *hw,
541 struct e1000_host_mng_command_header*);
542 s32 (*mng_enable_host_if)(struct e1000_hw *);
543 s32 (*wait_autoneg)(struct e1000_hw *);
546 struct e1000_phy_operations {
547 s32 (*init_params)(struct e1000_hw *);
548 s32 (*acquire)(struct e1000_hw *);
549 s32 (*check_polarity)(struct e1000_hw *);
550 s32 (*check_reset_block)(struct e1000_hw *);
551 s32 (*commit)(struct e1000_hw *);
552 s32 (*force_speed_duplex)(struct e1000_hw *);
553 s32 (*get_cfg_done)(struct e1000_hw *hw);
554 s32 (*get_cable_length)(struct e1000_hw *);
555 s32 (*get_info)(struct e1000_hw *);
556 s32 (*read_reg)(struct e1000_hw *, u32, u16 *);
557 s32 (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
558 void (*release)(struct e1000_hw *);
559 s32 (*reset)(struct e1000_hw *);
560 s32 (*set_d0_lplu_state)(struct e1000_hw *, bool);
561 s32 (*set_d3_lplu_state)(struct e1000_hw *, bool);
562 s32 (*write_reg)(struct e1000_hw *, u32, u16);
563 s32 (*write_reg_locked)(struct e1000_hw *, u32, u16);
564 void (*power_up)(struct e1000_hw *);
565 void (*power_down)(struct e1000_hw *);
568 struct e1000_nvm_operations {
569 s32 (*init_params)(struct e1000_hw *);
570 s32 (*acquire)(struct e1000_hw *);
571 s32 (*read)(struct e1000_hw *, u16, u16, u16 *);
572 void (*release)(struct e1000_hw *);
573 void (*reload)(struct e1000_hw *);
574 s32 (*update)(struct e1000_hw *);
575 s32 (*valid_led_default)(struct e1000_hw *, u16 *);
576 s32 (*validate)(struct e1000_hw *);
577 s32 (*write)(struct e1000_hw *, u16, u16, u16 *);
580 struct e1000_mac_info {
581 struct e1000_mac_operations ops;
582 u8 addr[ETH_ADDR_LEN];
583 u8 perm_addr[ETH_ADDR_LEN];
585 enum e1000_mac_type type;
603 /* Maximum size of the MTA register table in all supported adapters */
604 #define MAX_MTA_REG 128
605 u32 mta_shadow[MAX_MTA_REG];
608 u8 forced_speed_duplex;
612 bool arc_subsystem_valid;
613 bool asf_firmware_present;
616 bool get_link_status;
618 enum e1000_serdes_link_state serdes_link_state;
619 bool serdes_has_link;
620 bool tx_pkt_filtering;
623 struct e1000_phy_info {
624 struct e1000_phy_operations ops;
625 enum e1000_phy_type type;
627 enum e1000_1000t_rx_status local_rx;
628 enum e1000_1000t_rx_status remote_rx;
629 enum e1000_ms_type ms_type;
630 enum e1000_ms_type original_ms_type;
631 enum e1000_rev_polarity cable_polarity;
632 enum e1000_smart_speed smart_speed;
636 u32 reset_delay_us; /* in usec */
639 enum e1000_media_type media_type;
641 u16 autoneg_advertised;
644 u16 max_cable_length;
645 u16 min_cable_length;
649 bool disable_polarity_correction;
651 bool polarity_correction;
653 bool speed_downgraded;
654 bool autoneg_wait_to_complete;
657 struct e1000_nvm_info {
658 struct e1000_nvm_operations ops;
659 enum e1000_nvm_type type;
660 enum e1000_nvm_override override;
672 struct e1000_bus_info {
673 enum e1000_bus_type type;
674 enum e1000_bus_speed speed;
675 enum e1000_bus_width width;
681 struct e1000_fc_info {
682 u32 high_water; /* Flow control high-water mark */
683 u32 low_water; /* Flow control low-water mark */
684 u16 pause_time; /* Flow control pause timer */
685 u16 refresh_time; /* Flow control refresh timer */
686 bool send_xon; /* Flow control send XON */
687 bool strict_ieee; /* Strict IEEE mode */
688 enum e1000_fc_mode current_mode; /* FC mode in effect */
689 enum e1000_fc_mode requested_mode; /* FC mode requested by caller */
692 struct e1000_mbx_operations {
693 s32 (*init_params)(struct e1000_hw *hw);
694 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
695 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
696 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
697 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
698 s32 (*check_for_msg)(struct e1000_hw *, u16);
699 s32 (*check_for_ack)(struct e1000_hw *, u16);
700 s32 (*check_for_rst)(struct e1000_hw *, u16);
703 struct e1000_mbx_stats {
712 struct e1000_mbx_info {
713 struct e1000_mbx_operations ops;
714 struct e1000_mbx_stats stats;
720 struct e1000_dev_spec_82575 {
722 bool global_device_reset;
726 struct e1000_dev_spec_vf {
736 unsigned long io_base;
738 struct e1000_mac_info mac;
739 struct e1000_fc_info fc;
740 struct e1000_phy_info phy;
741 struct e1000_nvm_info nvm;
742 struct e1000_bus_info bus;
743 struct e1000_mbx_info mbx;
744 struct e1000_host_mng_dhcp_cookie mng_cookie;
747 struct e1000_dev_spec_82575 _82575;
748 struct e1000_dev_spec_vf vf;
752 u16 subsystem_vendor_id;
753 u16 subsystem_device_id;
759 #include "e1000_82575.h"
761 /* These functions must be implemented by drivers */
762 s32 e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
763 s32 e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
764 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
765 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);