1 /******************************************************************************
3 Copyright (c) 2001-2011, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
35 #include "e1000_api.h"
37 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw);
38 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw);
39 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw);
40 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw);
41 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw);
44 * e1000_init_mac_ops_generic - Initialize MAC function pointers
45 * @hw: pointer to the HW structure
47 * Setups up the function pointers to no-op functions
49 void e1000_init_mac_ops_generic(struct e1000_hw *hw)
51 struct e1000_mac_info *mac = &hw->mac;
52 DEBUGFUNC("e1000_init_mac_ops_generic");
55 mac->ops.init_params = e1000_null_ops_generic;
56 mac->ops.init_hw = e1000_null_ops_generic;
57 mac->ops.reset_hw = e1000_null_ops_generic;
58 mac->ops.setup_physical_interface = e1000_null_ops_generic;
59 mac->ops.get_bus_info = e1000_null_ops_generic;
60 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pcie;
61 mac->ops.read_mac_addr = e1000_read_mac_addr_generic;
62 mac->ops.config_collision_dist = e1000_config_collision_dist_generic;
63 mac->ops.clear_hw_cntrs = e1000_null_mac_generic;
65 mac->ops.cleanup_led = e1000_null_ops_generic;
66 mac->ops.setup_led = e1000_null_ops_generic;
67 mac->ops.blink_led = e1000_null_ops_generic;
68 mac->ops.led_on = e1000_null_ops_generic;
69 mac->ops.led_off = e1000_null_ops_generic;
71 mac->ops.setup_link = e1000_null_ops_generic;
72 mac->ops.get_link_up_info = e1000_null_link_info;
73 mac->ops.check_for_link = e1000_null_ops_generic;
74 mac->ops.wait_autoneg = e1000_wait_autoneg_generic;
76 mac->ops.check_mng_mode = e1000_null_mng_mode;
77 mac->ops.mng_host_if_write = e1000_mng_host_if_write_generic;
78 mac->ops.mng_write_cmd_header = e1000_mng_write_cmd_header_generic;
79 mac->ops.mng_enable_host_if = e1000_mng_enable_host_if_generic;
81 mac->ops.update_mc_addr_list = e1000_null_update_mc;
82 mac->ops.clear_vfta = e1000_null_mac_generic;
83 mac->ops.write_vfta = e1000_null_write_vfta;
84 mac->ops.rar_set = e1000_rar_set_generic;
85 mac->ops.validate_mdi_setting = e1000_validate_mdi_setting_generic;
89 * e1000_null_ops_generic - No-op function, returns 0
90 * @hw: pointer to the HW structure
92 s32 e1000_null_ops_generic(struct e1000_hw *hw)
94 DEBUGFUNC("e1000_null_ops_generic");
99 * e1000_null_mac_generic - No-op function, return void
100 * @hw: pointer to the HW structure
102 void e1000_null_mac_generic(struct e1000_hw *hw)
104 DEBUGFUNC("e1000_null_mac_generic");
109 * e1000_null_link_info - No-op function, return 0
110 * @hw: pointer to the HW structure
112 s32 e1000_null_link_info(struct e1000_hw *hw, u16 *s, u16 *d)
114 DEBUGFUNC("e1000_null_link_info");
115 return E1000_SUCCESS;
119 * e1000_null_mng_mode - No-op function, return FALSE
120 * @hw: pointer to the HW structure
122 bool e1000_null_mng_mode(struct e1000_hw *hw)
124 DEBUGFUNC("e1000_null_mng_mode");
129 * e1000_null_update_mc - No-op function, return void
130 * @hw: pointer to the HW structure
132 void e1000_null_update_mc(struct e1000_hw *hw, u8 *h, u32 a)
134 DEBUGFUNC("e1000_null_update_mc");
139 * e1000_null_write_vfta - No-op function, return void
140 * @hw: pointer to the HW structure
142 void e1000_null_write_vfta(struct e1000_hw *hw, u32 a, u32 b)
144 DEBUGFUNC("e1000_null_write_vfta");
149 * e1000_null_rar_set - No-op function, return void
150 * @hw: pointer to the HW structure
152 void e1000_null_rar_set(struct e1000_hw *hw, u8 *h, u32 a)
154 DEBUGFUNC("e1000_null_rar_set");
159 * e1000_get_bus_info_pci_generic - Get PCI(x) bus information
160 * @hw: pointer to the HW structure
162 * Determines and stores the system bus information for a particular
163 * network interface. The following bus information is determined and stored:
164 * bus speed, bus width, type (PCI/PCIx), and PCI(-x) function.
166 s32 e1000_get_bus_info_pci_generic(struct e1000_hw *hw)
168 struct e1000_mac_info *mac = &hw->mac;
169 struct e1000_bus_info *bus = &hw->bus;
170 u32 status = E1000_READ_REG(hw, E1000_STATUS);
171 s32 ret_val = E1000_SUCCESS;
173 DEBUGFUNC("e1000_get_bus_info_pci_generic");
176 bus->type = (status & E1000_STATUS_PCIX_MODE)
177 ? e1000_bus_type_pcix
178 : e1000_bus_type_pci;
181 if (bus->type == e1000_bus_type_pci) {
182 bus->speed = (status & E1000_STATUS_PCI66)
184 : e1000_bus_speed_33;
186 switch (status & E1000_STATUS_PCIX_SPEED) {
187 case E1000_STATUS_PCIX_SPEED_66:
188 bus->speed = e1000_bus_speed_66;
190 case E1000_STATUS_PCIX_SPEED_100:
191 bus->speed = e1000_bus_speed_100;
193 case E1000_STATUS_PCIX_SPEED_133:
194 bus->speed = e1000_bus_speed_133;
197 bus->speed = e1000_bus_speed_reserved;
203 bus->width = (status & E1000_STATUS_BUS64)
205 : e1000_bus_width_32;
207 /* Which PCI(-X) function? */
208 mac->ops.set_lan_id(hw);
214 * e1000_get_bus_info_pcie_generic - Get PCIe bus information
215 * @hw: pointer to the HW structure
217 * Determines and stores the system bus information for a particular
218 * network interface. The following bus information is determined and stored:
219 * bus speed, bus width, type (PCIe), and PCIe function.
221 s32 e1000_get_bus_info_pcie_generic(struct e1000_hw *hw)
223 struct e1000_mac_info *mac = &hw->mac;
224 struct e1000_bus_info *bus = &hw->bus;
226 u16 pcie_link_status;
228 DEBUGFUNC("e1000_get_bus_info_pcie_generic");
230 bus->type = e1000_bus_type_pci_express;
232 ret_val = e1000_read_pcie_cap_reg(hw,
236 bus->width = e1000_bus_width_unknown;
237 bus->speed = e1000_bus_speed_unknown;
239 switch (pcie_link_status & PCIE_LINK_SPEED_MASK) {
240 case PCIE_LINK_SPEED_2500:
241 bus->speed = e1000_bus_speed_2500;
243 case PCIE_LINK_SPEED_5000:
244 bus->speed = e1000_bus_speed_5000;
247 bus->speed = e1000_bus_speed_unknown;
251 bus->width = (enum e1000_bus_width)((pcie_link_status &
252 PCIE_LINK_WIDTH_MASK) >>
253 PCIE_LINK_WIDTH_SHIFT);
256 mac->ops.set_lan_id(hw);
258 return E1000_SUCCESS;
262 * e1000_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
264 * @hw: pointer to the HW structure
266 * Determines the LAN function id by reading memory-mapped registers
267 * and swaps the port value if requested.
269 static void e1000_set_lan_id_multi_port_pcie(struct e1000_hw *hw)
271 struct e1000_bus_info *bus = &hw->bus;
275 * The status register reports the correct function number
276 * for the device regardless of function swap state.
278 reg = E1000_READ_REG(hw, E1000_STATUS);
279 bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
283 * e1000_set_lan_id_multi_port_pci - Set LAN id for PCI multiple port devices
284 * @hw: pointer to the HW structure
286 * Determines the LAN function id by reading PCI config space.
288 void e1000_set_lan_id_multi_port_pci(struct e1000_hw *hw)
290 struct e1000_bus_info *bus = &hw->bus;
294 e1000_read_pci_cfg(hw, PCI_HEADER_TYPE_REGISTER, &pci_header_type);
295 if (pci_header_type & PCI_HEADER_TYPE_MULTIFUNC) {
296 status = E1000_READ_REG(hw, E1000_STATUS);
297 bus->func = (status & E1000_STATUS_FUNC_MASK)
298 >> E1000_STATUS_FUNC_SHIFT;
305 * e1000_set_lan_id_single_port - Set LAN id for a single port device
306 * @hw: pointer to the HW structure
308 * Sets the LAN function id to zero for a single port device.
310 void e1000_set_lan_id_single_port(struct e1000_hw *hw)
312 struct e1000_bus_info *bus = &hw->bus;
318 * e1000_clear_vfta_generic - Clear VLAN filter table
319 * @hw: pointer to the HW structure
321 * Clears the register array which contains the VLAN filter table by
322 * setting all the values to 0.
324 void e1000_clear_vfta_generic(struct e1000_hw *hw)
328 DEBUGFUNC("e1000_clear_vfta_generic");
330 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
331 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
332 E1000_WRITE_FLUSH(hw);
337 * e1000_write_vfta_generic - Write value to VLAN filter table
338 * @hw: pointer to the HW structure
339 * @offset: register offset in VLAN filter table
340 * @value: register value written to VLAN filter table
342 * Writes value at the given offset in the register array which stores
343 * the VLAN filter table.
345 void e1000_write_vfta_generic(struct e1000_hw *hw, u32 offset, u32 value)
347 DEBUGFUNC("e1000_write_vfta_generic");
349 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
350 E1000_WRITE_FLUSH(hw);
354 * e1000_init_rx_addrs_generic - Initialize receive address's
355 * @hw: pointer to the HW structure
356 * @rar_count: receive address registers
358 * Setup the receive address registers by setting the base receive address
359 * register to the devices MAC address and clearing all the other receive
360 * address registers to 0.
362 void e1000_init_rx_addrs_generic(struct e1000_hw *hw, u16 rar_count)
365 u8 mac_addr[ETH_ADDR_LEN] = {0};
367 DEBUGFUNC("e1000_init_rx_addrs_generic");
369 /* Setup the receive address */
370 DEBUGOUT("Programming MAC Address into RAR[0]\n");
372 hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
374 /* Zero out the other (rar_entry_count - 1) receive addresses */
375 DEBUGOUT1("Clearing RAR[1-%u]\n", rar_count-1);
376 for (i = 1; i < rar_count; i++)
377 hw->mac.ops.rar_set(hw, mac_addr, i);
381 * e1000_check_alt_mac_addr_generic - Check for alternate MAC addr
382 * @hw: pointer to the HW structure
384 * Checks the nvm for an alternate MAC address. An alternate MAC address
385 * can be setup by pre-boot software and must be treated like a permanent
386 * address and must override the actual permanent MAC address. If an
387 * alternate MAC address is found it is programmed into RAR0, replacing
388 * the permanent address that was installed into RAR0 by the Si on reset.
389 * This function will return SUCCESS unless it encounters an error while
390 * reading the EEPROM.
392 s32 e1000_check_alt_mac_addr_generic(struct e1000_hw *hw)
395 s32 ret_val = E1000_SUCCESS;
396 u16 offset, nvm_alt_mac_addr_offset, nvm_data;
397 u8 alt_mac_addr[ETH_ADDR_LEN];
399 DEBUGFUNC("e1000_check_alt_mac_addr_generic");
401 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &nvm_data);
405 if (!(nvm_data & NVM_COMPAT_LOM))
408 ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
409 &nvm_alt_mac_addr_offset);
411 DEBUGOUT("NVM Read Error\n");
415 if (nvm_alt_mac_addr_offset == 0xFFFF) {
416 /* There is no Alternate MAC Address */
420 if (hw->bus.func == E1000_FUNC_1)
421 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
422 if (hw->bus.func == E1000_FUNC_2)
423 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
425 if (hw->bus.func == E1000_FUNC_3)
426 nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
427 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
428 offset = nvm_alt_mac_addr_offset + (i >> 1);
429 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
431 DEBUGOUT("NVM Read Error\n");
435 alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
436 alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
439 /* if multicast bit is set, the alternate address will not be used */
440 if (alt_mac_addr[0] & 0x01) {
441 DEBUGOUT("Ignoring Alternate Mac Address with MC bit set\n");
446 * We have a valid alternate MAC address, and we want to treat it the
447 * same as the normal permanent MAC address stored by the HW into the
448 * RAR. Do this by mapping this address into RAR0.
450 hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
457 * e1000_rar_set_generic - Set receive address register
458 * @hw: pointer to the HW structure
459 * @addr: pointer to the receive address
460 * @index: receive address array register
462 * Sets the receive address array register at index to the address passed
465 void e1000_rar_set_generic(struct e1000_hw *hw, u8 *addr, u32 index)
467 u32 rar_low, rar_high;
469 DEBUGFUNC("e1000_rar_set_generic");
472 * HW expects these in little endian so we reverse the byte order
473 * from network order (big endian) to little endian
475 rar_low = ((u32) addr[0] |
476 ((u32) addr[1] << 8) |
477 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
479 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
481 /* If MAC address zero, no need to set the AV bit */
482 if (rar_low || rar_high)
483 rar_high |= E1000_RAH_AV;
486 * Some bridges will combine consecutive 32-bit writes into
487 * a single burst write, which will malfunction on some parts.
488 * The flushes avoid this.
490 E1000_WRITE_REG(hw, E1000_RAL(index), rar_low);
491 E1000_WRITE_FLUSH(hw);
492 E1000_WRITE_REG(hw, E1000_RAH(index), rar_high);
493 E1000_WRITE_FLUSH(hw);
497 * e1000_update_mc_addr_list_generic - Update Multicast addresses
498 * @hw: pointer to the HW structure
499 * @mc_addr_list: array of multicast addresses to program
500 * @mc_addr_count: number of multicast addresses to program
502 * Updates entire Multicast Table Array.
503 * The caller must have a packed mc_addr_list of multicast addresses.
505 void e1000_update_mc_addr_list_generic(struct e1000_hw *hw,
506 u8 *mc_addr_list, u32 mc_addr_count)
508 u32 hash_value, hash_bit, hash_reg;
511 DEBUGFUNC("e1000_update_mc_addr_list_generic");
513 /* clear mta_shadow */
514 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
516 /* update mta_shadow from mc_addr_list */
517 for (i = 0; (u32) i < mc_addr_count; i++) {
518 hash_value = e1000_hash_mc_addr_generic(hw, mc_addr_list);
520 hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
521 hash_bit = hash_value & 0x1F;
523 hw->mac.mta_shadow[hash_reg] |= (1 << hash_bit);
524 mc_addr_list += (ETH_ADDR_LEN);
527 /* replace the entire MTA table */
528 for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
529 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);
530 E1000_WRITE_FLUSH(hw);
534 * e1000_hash_mc_addr_generic - Generate a multicast hash value
535 * @hw: pointer to the HW structure
536 * @mc_addr: pointer to a multicast address
538 * Generates a multicast address hash value which is used to determine
539 * the multicast filter table array address and new table value.
541 u32 e1000_hash_mc_addr_generic(struct e1000_hw *hw, u8 *mc_addr)
543 u32 hash_value, hash_mask;
546 DEBUGFUNC("e1000_hash_mc_addr_generic");
548 /* Register count multiplied by bits per register */
549 hash_mask = (hw->mac.mta_reg_count * 32) - 1;
552 * For a mc_filter_type of 0, bit_shift is the number of left-shifts
553 * where 0xFF would still fall within the hash mask.
555 while (hash_mask >> bit_shift != 0xFF)
559 * The portion of the address that is used for the hash table
560 * is determined by the mc_filter_type setting.
561 * The algorithm is such that there is a total of 8 bits of shifting.
562 * The bit_shift for a mc_filter_type of 0 represents the number of
563 * left-shifts where the MSB of mc_addr[5] would still fall within
564 * the hash_mask. Case 0 does this exactly. Since there are a total
565 * of 8 bits of shifting, then mc_addr[4] will shift right the
566 * remaining number of bits. Thus 8 - bit_shift. The rest of the
567 * cases are a variation of this algorithm...essentially raising the
568 * number of bits to shift mc_addr[5] left, while still keeping the
569 * 8-bit shifting total.
571 * For example, given the following Destination MAC Address and an
572 * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
573 * we can see that the bit_shift for case 0 is 4. These are the hash
574 * values resulting from each mc_filter_type...
575 * [0] [1] [2] [3] [4] [5]
579 * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
580 * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
581 * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
582 * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
584 switch (hw->mac.mc_filter_type) {
599 hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
600 (((u16) mc_addr[5]) << bit_shift)));
606 * e1000_pcix_mmrbc_workaround_generic - Fix incorrect MMRBC value
607 * @hw: pointer to the HW structure
609 * In certain situations, a system BIOS may report that the PCIx maximum
610 * memory read byte count (MMRBC) value is higher than than the actual
611 * value. We check the PCIx command register with the current PCIx status
614 void e1000_pcix_mmrbc_workaround_generic(struct e1000_hw *hw)
618 u16 pcix_stat_hi_word;
621 DEBUGFUNC("e1000_pcix_mmrbc_workaround_generic");
623 /* Workaround for PCI-X issue when BIOS sets MMRBC incorrectly */
624 if (hw->bus.type != e1000_bus_type_pcix)
627 e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
628 e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI, &pcix_stat_hi_word);
629 cmd_mmrbc = (pcix_cmd & PCIX_COMMAND_MMRBC_MASK) >>
630 PCIX_COMMAND_MMRBC_SHIFT;
631 stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
632 PCIX_STATUS_HI_MMRBC_SHIFT;
633 if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
634 stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
635 if (cmd_mmrbc > stat_mmrbc) {
636 pcix_cmd &= ~PCIX_COMMAND_MMRBC_MASK;
637 pcix_cmd |= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
638 e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd);
643 * e1000_clear_hw_cntrs_base_generic - Clear base hardware counters
644 * @hw: pointer to the HW structure
646 * Clears the base hardware counters by reading the counter registers.
648 void e1000_clear_hw_cntrs_base_generic(struct e1000_hw *hw)
650 DEBUGFUNC("e1000_clear_hw_cntrs_base_generic");
652 E1000_READ_REG(hw, E1000_CRCERRS);
653 E1000_READ_REG(hw, E1000_SYMERRS);
654 E1000_READ_REG(hw, E1000_MPC);
655 E1000_READ_REG(hw, E1000_SCC);
656 E1000_READ_REG(hw, E1000_ECOL);
657 E1000_READ_REG(hw, E1000_MCC);
658 E1000_READ_REG(hw, E1000_LATECOL);
659 E1000_READ_REG(hw, E1000_COLC);
660 E1000_READ_REG(hw, E1000_DC);
661 E1000_READ_REG(hw, E1000_SEC);
662 E1000_READ_REG(hw, E1000_RLEC);
663 E1000_READ_REG(hw, E1000_XONRXC);
664 E1000_READ_REG(hw, E1000_XONTXC);
665 E1000_READ_REG(hw, E1000_XOFFRXC);
666 E1000_READ_REG(hw, E1000_XOFFTXC);
667 E1000_READ_REG(hw, E1000_FCRUC);
668 E1000_READ_REG(hw, E1000_GPRC);
669 E1000_READ_REG(hw, E1000_BPRC);
670 E1000_READ_REG(hw, E1000_MPRC);
671 E1000_READ_REG(hw, E1000_GPTC);
672 E1000_READ_REG(hw, E1000_GORCL);
673 E1000_READ_REG(hw, E1000_GORCH);
674 E1000_READ_REG(hw, E1000_GOTCL);
675 E1000_READ_REG(hw, E1000_GOTCH);
676 E1000_READ_REG(hw, E1000_RNBC);
677 E1000_READ_REG(hw, E1000_RUC);
678 E1000_READ_REG(hw, E1000_RFC);
679 E1000_READ_REG(hw, E1000_ROC);
680 E1000_READ_REG(hw, E1000_RJC);
681 E1000_READ_REG(hw, E1000_TORL);
682 E1000_READ_REG(hw, E1000_TORH);
683 E1000_READ_REG(hw, E1000_TOTL);
684 E1000_READ_REG(hw, E1000_TOTH);
685 E1000_READ_REG(hw, E1000_TPR);
686 E1000_READ_REG(hw, E1000_TPT);
687 E1000_READ_REG(hw, E1000_MPTC);
688 E1000_READ_REG(hw, E1000_BPTC);
692 * e1000_check_for_copper_link_generic - Check for link (Copper)
693 * @hw: pointer to the HW structure
695 * Checks to see of the link status of the hardware has changed. If a
696 * change in link status has been detected, then we read the PHY registers
697 * to get the current speed/duplex if link exists.
699 s32 e1000_check_for_copper_link_generic(struct e1000_hw *hw)
701 struct e1000_mac_info *mac = &hw->mac;
705 DEBUGFUNC("e1000_check_for_copper_link");
708 * We only want to go out to the PHY registers to see if Auto-Neg
709 * has completed and/or if our link status has changed. The
710 * get_link_status flag is set upon receiving a Link Status
711 * Change or Rx Sequence Error interrupt.
713 if (!mac->get_link_status) {
714 ret_val = E1000_SUCCESS;
719 * First we want to see if the MII Status Register reports
720 * link. If so, then we want to get the current speed/duplex
723 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
728 goto out; /* No link detected */
730 mac->get_link_status = FALSE;
733 * Check if there was DownShift, must be checked
734 * immediately after link-up
736 e1000_check_downshift_generic(hw);
739 * If we are forcing speed/duplex, then we simply return since
740 * we have already determined whether we have link or not.
743 ret_val = -E1000_ERR_CONFIG;
748 * Auto-Neg is enabled. Auto Speed Detection takes care
749 * of MAC speed/duplex configuration. So we only need to
750 * configure Collision Distance in the MAC.
752 mac->ops.config_collision_dist(hw);
755 * Configure Flow Control now that Auto-Neg has completed.
756 * First, we need to restore the desired flow control
757 * settings because we may have had to re-autoneg with a
758 * different link partner.
760 ret_val = e1000_config_fc_after_link_up_generic(hw);
762 DEBUGOUT("Error configuring flow control\n");
769 * e1000_check_for_fiber_link_generic - Check for link (Fiber)
770 * @hw: pointer to the HW structure
772 * Checks for link up on the hardware. If link is not up and we have
773 * a signal, then we need to force link up.
775 s32 e1000_check_for_fiber_link_generic(struct e1000_hw *hw)
777 struct e1000_mac_info *mac = &hw->mac;
781 s32 ret_val = E1000_SUCCESS;
783 DEBUGFUNC("e1000_check_for_fiber_link_generic");
785 ctrl = E1000_READ_REG(hw, E1000_CTRL);
786 status = E1000_READ_REG(hw, E1000_STATUS);
787 rxcw = E1000_READ_REG(hw, E1000_RXCW);
790 * If we don't have link (auto-negotiation failed or link partner
791 * cannot auto-negotiate), the cable is plugged in (we have signal),
792 * and our link partner is not trying to auto-negotiate with us (we
793 * are receiving idles or data), we need to force link up. We also
794 * need to give auto-negotiation time to complete, in case the cable
795 * was just plugged in. The autoneg_failed flag does this.
797 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
798 if ((ctrl & E1000_CTRL_SWDPIN1) && (!(status & E1000_STATUS_LU)) &&
799 (!(rxcw & E1000_RXCW_C))) {
800 if (mac->autoneg_failed == 0) {
801 mac->autoneg_failed = 1;
804 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
806 /* Disable auto-negotiation in the TXCW register */
807 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
809 /* Force link-up and also force full-duplex. */
810 ctrl = E1000_READ_REG(hw, E1000_CTRL);
811 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
812 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
814 /* Configure Flow Control after forcing link up. */
815 ret_val = e1000_config_fc_after_link_up_generic(hw);
817 DEBUGOUT("Error configuring flow control\n");
820 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
822 * If we are forcing link and we are receiving /C/ ordered
823 * sets, re-enable auto-negotiation in the TXCW register
824 * and disable forced link in the Device Control register
825 * in an attempt to auto-negotiate with our link partner.
827 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
828 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
829 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
831 mac->serdes_has_link = TRUE;
839 * e1000_check_for_serdes_link_generic - Check for link (Serdes)
840 * @hw: pointer to the HW structure
842 * Checks for link up on the hardware. If link is not up and we have
843 * a signal, then we need to force link up.
845 s32 e1000_check_for_serdes_link_generic(struct e1000_hw *hw)
847 struct e1000_mac_info *mac = &hw->mac;
851 s32 ret_val = E1000_SUCCESS;
853 DEBUGFUNC("e1000_check_for_serdes_link_generic");
855 ctrl = E1000_READ_REG(hw, E1000_CTRL);
856 status = E1000_READ_REG(hw, E1000_STATUS);
857 rxcw = E1000_READ_REG(hw, E1000_RXCW);
860 * If we don't have link (auto-negotiation failed or link partner
861 * cannot auto-negotiate), and our link partner is not trying to
862 * auto-negotiate with us (we are receiving idles or data),
863 * we need to force link up. We also need to give auto-negotiation
866 /* (ctrl & E1000_CTRL_SWDPIN1) == 1 == have signal */
867 if ((!(status & E1000_STATUS_LU)) && (!(rxcw & E1000_RXCW_C))) {
868 if (mac->autoneg_failed == 0) {
869 mac->autoneg_failed = 1;
872 DEBUGOUT("NOT Rx'ing /C/, disable AutoNeg and force link.\n");
874 /* Disable auto-negotiation in the TXCW register */
875 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
877 /* Force link-up and also force full-duplex. */
878 ctrl = E1000_READ_REG(hw, E1000_CTRL);
879 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
880 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
882 /* Configure Flow Control after forcing link up. */
883 ret_val = e1000_config_fc_after_link_up_generic(hw);
885 DEBUGOUT("Error configuring flow control\n");
888 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
890 * If we are forcing link and we are receiving /C/ ordered
891 * sets, re-enable auto-negotiation in the TXCW register
892 * and disable forced link in the Device Control register
893 * in an attempt to auto-negotiate with our link partner.
895 DEBUGOUT("Rx'ing /C/, enable AutoNeg and stop forcing link.\n");
896 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
897 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
899 mac->serdes_has_link = TRUE;
900 } else if (!(E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW))) {
902 * If we force link for non-auto-negotiation switch, check
903 * link status based on MAC synchronization for internal
906 /* SYNCH bit and IV bit are sticky. */
908 rxcw = E1000_READ_REG(hw, E1000_RXCW);
909 if (rxcw & E1000_RXCW_SYNCH) {
910 if (!(rxcw & E1000_RXCW_IV)) {
911 mac->serdes_has_link = TRUE;
912 DEBUGOUT("SERDES: Link up - forced.\n");
915 mac->serdes_has_link = FALSE;
916 DEBUGOUT("SERDES: Link down - force failed.\n");
920 if (E1000_TXCW_ANE & E1000_READ_REG(hw, E1000_TXCW)) {
921 status = E1000_READ_REG(hw, E1000_STATUS);
922 if (status & E1000_STATUS_LU) {
923 /* SYNCH bit and IV bit are sticky, so reread rxcw. */
925 rxcw = E1000_READ_REG(hw, E1000_RXCW);
926 if (rxcw & E1000_RXCW_SYNCH) {
927 if (!(rxcw & E1000_RXCW_IV)) {
928 mac->serdes_has_link = TRUE;
929 DEBUGOUT("SERDES: Link up - autoneg "
930 "completed sucessfully.\n");
932 mac->serdes_has_link = FALSE;
933 DEBUGOUT("SERDES: Link down - invalid"
934 "codewords detected in autoneg.\n");
937 mac->serdes_has_link = FALSE;
938 DEBUGOUT("SERDES: Link down - no sync.\n");
941 mac->serdes_has_link = FALSE;
942 DEBUGOUT("SERDES: Link down - autoneg failed\n");
951 * e1000_setup_link_generic - Setup flow control and link settings
952 * @hw: pointer to the HW structure
954 * Determines which flow control settings to use, then configures flow
955 * control. Calls the appropriate media-specific link configuration
956 * function. Assuming the adapter has a valid link partner, a valid link
957 * should be established. Assumes the hardware has previously been reset
958 * and the transmitter and receiver are not enabled.
960 s32 e1000_setup_link_generic(struct e1000_hw *hw)
962 s32 ret_val = E1000_SUCCESS;
964 DEBUGFUNC("e1000_setup_link_generic");
967 * In the case of the phy reset being blocked, we already have a link.
968 * We do not need to set it up again.
970 if (e1000_check_reset_block(hw))
974 * If requested flow control is set to default, set flow control
975 * based on the EEPROM flow control settings.
977 if (hw->fc.requested_mode == e1000_fc_default) {
978 ret_val = e1000_set_default_fc_generic(hw);
984 * Save off the requested flow control mode for use later. Depending
985 * on the link partner's capabilities, we may or may not use this mode.
987 hw->fc.current_mode = hw->fc.requested_mode;
989 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
990 hw->fc.current_mode);
992 /* Call the necessary media_type subroutine to configure the link. */
993 ret_val = hw->mac.ops.setup_physical_interface(hw);
998 * Initialize the flow control address, type, and PAUSE timer
999 * registers to their default values. This is done even if flow
1000 * control is disabled, because it does not hurt anything to
1001 * initialize these registers.
1003 DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1004 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
1005 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1006 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
1008 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
1010 ret_val = e1000_set_fc_watermarks_generic(hw);
1017 * e1000_setup_fiber_serdes_link_generic - Setup link for fiber/serdes
1018 * @hw: pointer to the HW structure
1020 * Configures collision distance and flow control for fiber and serdes
1021 * links. Upon successful setup, poll for link.
1023 s32 e1000_setup_fiber_serdes_link_generic(struct e1000_hw *hw)
1025 struct e1000_mac_info *mac = &hw->mac;
1027 s32 ret_val = E1000_SUCCESS;
1029 DEBUGFUNC("e1000_setup_fiber_serdes_link_generic");
1031 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1033 /* Take the link out of reset */
1034 ctrl &= ~E1000_CTRL_LRST;
1036 mac->ops.config_collision_dist(hw);
1038 ret_val = e1000_commit_fc_settings_generic(hw);
1043 * Since auto-negotiation is enabled, take the link out of reset (the
1044 * link will be in reset, because we previously reset the chip). This
1045 * will restart auto-negotiation. If auto-negotiation is successful
1046 * then the link-up status bit will be set and the flow control enable
1047 * bits (RFCE and TFCE) will be set according to their negotiated value.
1049 DEBUGOUT("Auto-negotiation enabled\n");
1051 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1052 E1000_WRITE_FLUSH(hw);
1056 * For these adapters, the SW definable pin 1 is set when the optics
1057 * detect a signal. If we have a signal, then poll for a "Link-Up"
1060 if (hw->phy.media_type == e1000_media_type_internal_serdes ||
1061 (E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1062 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1064 DEBUGOUT("No signal detected\n");
1072 * e1000_config_collision_dist_generic - Configure collision distance
1073 * @hw: pointer to the HW structure
1075 * Configures the collision distance to the default value and is used
1076 * during link setup.
1078 void e1000_config_collision_dist_generic(struct e1000_hw *hw)
1082 DEBUGFUNC("e1000_config_collision_dist_generic");
1084 tctl = E1000_READ_REG(hw, E1000_TCTL);
1086 tctl &= ~E1000_TCTL_COLD;
1087 tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
1089 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1090 E1000_WRITE_FLUSH(hw);
1094 * e1000_poll_fiber_serdes_link_generic - Poll for link up
1095 * @hw: pointer to the HW structure
1097 * Polls for link up by reading the status register, if link fails to come
1098 * up with auto-negotiation, then the link is forced if a signal is detected.
1100 static s32 e1000_poll_fiber_serdes_link_generic(struct e1000_hw *hw)
1102 struct e1000_mac_info *mac = &hw->mac;
1104 s32 ret_val = E1000_SUCCESS;
1106 DEBUGFUNC("e1000_poll_fiber_serdes_link_generic");
1109 * If we have a signal (the cable is plugged in, or assumed TRUE for
1110 * serdes media) then poll for a "Link-Up" indication in the Device
1111 * Status Register. Time-out if a link isn't seen in 500 milliseconds
1112 * seconds (Auto-negotiation should complete in less than 500
1113 * milliseconds even if the other end is doing it in SW).
1115 for (i = 0; i < FIBER_LINK_UP_LIMIT; i++) {
1117 status = E1000_READ_REG(hw, E1000_STATUS);
1118 if (status & E1000_STATUS_LU)
1121 if (i == FIBER_LINK_UP_LIMIT) {
1122 DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1123 mac->autoneg_failed = 1;
1125 * AutoNeg failed to achieve a link, so we'll call
1126 * mac->check_for_link. This routine will force the
1127 * link up if we detect a signal. This will allow us to
1128 * communicate with non-autonegotiating link partners.
1130 ret_val = mac->ops.check_for_link(hw);
1132 DEBUGOUT("Error while checking for link\n");
1135 mac->autoneg_failed = 0;
1137 mac->autoneg_failed = 0;
1138 DEBUGOUT("Valid Link Found\n");
1146 * e1000_commit_fc_settings_generic - Configure flow control
1147 * @hw: pointer to the HW structure
1149 * Write the flow control settings to the Transmit Config Word Register (TXCW)
1150 * base on the flow control settings in e1000_mac_info.
1152 static s32 e1000_commit_fc_settings_generic(struct e1000_hw *hw)
1154 struct e1000_mac_info *mac = &hw->mac;
1156 s32 ret_val = E1000_SUCCESS;
1158 DEBUGFUNC("e1000_commit_fc_settings_generic");
1161 * Check for a software override of the flow control settings, and
1162 * setup the device accordingly. If auto-negotiation is enabled, then
1163 * software will have to set the "PAUSE" bits to the correct value in
1164 * the Transmit Config Word Register (TXCW) and re-start auto-
1165 * negotiation. However, if auto-negotiation is disabled, then
1166 * software will have to manually configure the two flow control enable
1167 * bits in the CTRL register.
1169 * The possible values of the "fc" parameter are:
1170 * 0: Flow control is completely disabled
1171 * 1: Rx flow control is enabled (we can receive pause frames,
1172 * but not send pause frames).
1173 * 2: Tx flow control is enabled (we can send pause frames but we
1174 * do not support receiving pause frames).
1175 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1177 switch (hw->fc.current_mode) {
1179 /* Flow control completely disabled by a software over-ride. */
1180 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD);
1182 case e1000_fc_rx_pause:
1184 * Rx Flow control is enabled and Tx Flow control is disabled
1185 * by a software over-ride. Since there really isn't a way to
1186 * advertise that we are capable of Rx Pause ONLY, we will
1187 * advertise that we support both symmetric and asymmetric Rx
1188 * PAUSE. Later, we will disable the adapter's ability to send
1191 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1193 case e1000_fc_tx_pause:
1195 * Tx Flow control is enabled, and Rx Flow control is disabled,
1196 * by a software over-ride.
1198 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_ASM_DIR);
1202 * Flow control (both Rx and Tx) is enabled by a software
1205 txcw = (E1000_TXCW_ANE | E1000_TXCW_FD | E1000_TXCW_PAUSE_MASK);
1208 DEBUGOUT("Flow control param set incorrectly\n");
1209 ret_val = -E1000_ERR_CONFIG;
1214 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1222 * e1000_set_fc_watermarks_generic - Set flow control high/low watermarks
1223 * @hw: pointer to the HW structure
1225 * Sets the flow control high/low threshold (watermark) registers. If
1226 * flow control XON frame transmission is enabled, then set XON frame
1227 * transmission as well.
1229 s32 e1000_set_fc_watermarks_generic(struct e1000_hw *hw)
1231 u32 fcrtl = 0, fcrth = 0;
1233 DEBUGFUNC("e1000_set_fc_watermarks_generic");
1236 * Set the flow control receive threshold registers. Normally,
1237 * these registers will be set to a default threshold that may be
1238 * adjusted later by the driver's runtime code. However, if the
1239 * ability to transmit pause frames is not enabled, then these
1240 * registers will be set to 0.
1242 if (hw->fc.current_mode & e1000_fc_tx_pause) {
1244 * We need to set up the Receive Threshold high and low water
1245 * marks as well as (optionally) enabling the transmission of
1248 fcrtl = hw->fc.low_water;
1249 if (hw->fc.send_xon)
1250 fcrtl |= E1000_FCRTL_XONE;
1252 fcrth = hw->fc.high_water;
1254 E1000_WRITE_REG(hw, E1000_FCRTL, fcrtl);
1255 E1000_WRITE_REG(hw, E1000_FCRTH, fcrth);
1257 return E1000_SUCCESS;
1261 * e1000_set_default_fc_generic - Set flow control default values
1262 * @hw: pointer to the HW structure
1264 * Read the EEPROM for the default values for flow control and store the
1267 static s32 e1000_set_default_fc_generic(struct e1000_hw *hw)
1269 s32 ret_val = E1000_SUCCESS;
1272 DEBUGFUNC("e1000_set_default_fc_generic");
1275 * Read and store word 0x0F of the EEPROM. This word contains bits
1276 * that determine the hardware's default PAUSE (flow control) mode,
1277 * a bit that determines whether the HW defaults to enabling or
1278 * disabling auto-negotiation, and the direction of the
1279 * SW defined pins. If there is no SW over-ride of the flow
1280 * control setting, then the variable hw->fc will
1281 * be initialized based on a value in the EEPROM.
1283 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &nvm_data);
1286 DEBUGOUT("NVM Read Error\n");
1290 if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
1291 hw->fc.requested_mode = e1000_fc_none;
1292 else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) ==
1294 hw->fc.requested_mode = e1000_fc_tx_pause;
1296 hw->fc.requested_mode = e1000_fc_full;
1303 * e1000_force_mac_fc_generic - Force the MAC's flow control settings
1304 * @hw: pointer to the HW structure
1306 * Force the MAC's flow control settings. Sets the TFCE and RFCE bits in the
1307 * device control register to reflect the adapter settings. TFCE and RFCE
1308 * need to be explicitly set by software when a copper PHY is used because
1309 * autonegotiation is managed by the PHY rather than the MAC. Software must
1310 * also configure these bits when link is forced on a fiber connection.
1312 s32 e1000_force_mac_fc_generic(struct e1000_hw *hw)
1315 s32 ret_val = E1000_SUCCESS;
1317 DEBUGFUNC("e1000_force_mac_fc_generic");
1319 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1322 * Because we didn't get link via the internal auto-negotiation
1323 * mechanism (we either forced link or we got link via PHY
1324 * auto-neg), we have to manually enable/disable transmit an
1325 * receive flow control.
1327 * The "Case" statement below enables/disable flow control
1328 * according to the "hw->fc.current_mode" parameter.
1330 * The possible values of the "fc" parameter are:
1331 * 0: Flow control is completely disabled
1332 * 1: Rx flow control is enabled (we can receive pause
1333 * frames but not send pause frames).
1334 * 2: Tx flow control is enabled (we can send pause frames
1335 * frames but we do not receive pause frames).
1336 * 3: Both Rx and Tx flow control (symmetric) is enabled.
1337 * other: No other values should be possible at this point.
1339 DEBUGOUT1("hw->fc.current_mode = %u\n", hw->fc.current_mode);
1341 switch (hw->fc.current_mode) {
1343 ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
1345 case e1000_fc_rx_pause:
1346 ctrl &= (~E1000_CTRL_TFCE);
1347 ctrl |= E1000_CTRL_RFCE;
1349 case e1000_fc_tx_pause:
1350 ctrl &= (~E1000_CTRL_RFCE);
1351 ctrl |= E1000_CTRL_TFCE;
1354 ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
1357 DEBUGOUT("Flow control param set incorrectly\n");
1358 ret_val = -E1000_ERR_CONFIG;
1362 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1369 * e1000_config_fc_after_link_up_generic - Configures flow control after link
1370 * @hw: pointer to the HW structure
1372 * Checks the status of auto-negotiation after link up to ensure that the
1373 * speed and duplex were not forced. If the link needed to be forced, then
1374 * flow control needs to be forced also. If auto-negotiation is enabled
1375 * and did not fail, then we configure flow control based on our link
1378 s32 e1000_config_fc_after_link_up_generic(struct e1000_hw *hw)
1380 struct e1000_mac_info *mac = &hw->mac;
1381 s32 ret_val = E1000_SUCCESS;
1382 u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
1385 DEBUGFUNC("e1000_config_fc_after_link_up_generic");
1388 * Check for the case where we have fiber media and auto-neg failed
1389 * so we had to force link. In this case, we need to force the
1390 * configuration of the MAC to match the "fc" parameter.
1392 if (mac->autoneg_failed) {
1393 if (hw->phy.media_type == e1000_media_type_fiber ||
1394 hw->phy.media_type == e1000_media_type_internal_serdes)
1395 ret_val = e1000_force_mac_fc_generic(hw);
1397 if (hw->phy.media_type == e1000_media_type_copper)
1398 ret_val = e1000_force_mac_fc_generic(hw);
1402 DEBUGOUT("Error forcing flow control settings\n");
1407 * Check for the case where we have copper media and auto-neg is
1408 * enabled. In this case, we need to check and see if Auto-Neg
1409 * has completed, and if so, how the PHY and link partner has
1410 * flow control configured.
1412 if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
1414 * Read the MII Status Register and check to see if AutoNeg
1415 * has completed. We read this twice because this reg has
1416 * some "sticky" (latched) bits.
1418 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1421 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
1425 if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
1426 DEBUGOUT("Copper PHY and Auto Neg "
1427 "has not completed.\n");
1432 * The AutoNeg process has completed, so we now need to
1433 * read both the Auto Negotiation Advertisement
1434 * Register (Address 4) and the Auto_Negotiation Base
1435 * Page Ability Register (Address 5) to determine how
1436 * flow control was negotiated.
1438 ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
1442 ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
1443 &mii_nway_lp_ability_reg);
1448 * Two bits in the Auto Negotiation Advertisement Register
1449 * (Address 4) and two bits in the Auto Negotiation Base
1450 * Page Ability Register (Address 5) determine flow control
1451 * for both the PHY and the link partner. The following
1452 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1453 * 1999, describes these PAUSE resolution bits and how flow
1454 * control is determined based upon these settings.
1455 * NOTE: DC = Don't Care
1457 * LOCAL DEVICE | LINK PARTNER
1458 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1459 *-------|---------|-------|---------|--------------------
1460 * 0 | 0 | DC | DC | e1000_fc_none
1461 * 0 | 1 | 0 | DC | e1000_fc_none
1462 * 0 | 1 | 1 | 0 | e1000_fc_none
1463 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1464 * 1 | 0 | 0 | DC | e1000_fc_none
1465 * 1 | DC | 1 | DC | e1000_fc_full
1466 * 1 | 1 | 0 | 0 | e1000_fc_none
1467 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1469 * Are both PAUSE bits set to 1? If so, this implies
1470 * Symmetric Flow Control is enabled at both ends. The
1471 * ASM_DIR bits are irrelevant per the spec.
1473 * For Symmetric Flow Control:
1475 * LOCAL DEVICE | LINK PARTNER
1476 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1477 *-------|---------|-------|---------|--------------------
1478 * 1 | DC | 1 | DC | E1000_fc_full
1481 if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1482 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
1484 * Now we need to check if the user selected Rx ONLY
1485 * of pause frames. In this case, we had to advertise
1486 * FULL flow control because we could not advertise Rx
1487 * ONLY. Hence, we must now check to see if we need to
1488 * turn OFF the TRANSMISSION of PAUSE frames.
1490 if (hw->fc.requested_mode == e1000_fc_full) {
1491 hw->fc.current_mode = e1000_fc_full;
1492 DEBUGOUT("Flow Control = FULL.\r\n");
1494 hw->fc.current_mode = e1000_fc_rx_pause;
1495 DEBUGOUT("Flow Control = "
1496 "Rx PAUSE frames only.\r\n");
1500 * For receiving PAUSE frames ONLY.
1502 * LOCAL DEVICE | LINK PARTNER
1503 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1504 *-------|---------|-------|---------|--------------------
1505 * 0 | 1 | 1 | 1 | e1000_fc_tx_pause
1507 else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1508 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1509 (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1510 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1511 hw->fc.current_mode = e1000_fc_tx_pause;
1512 DEBUGOUT("Flow Control = Tx PAUSE frames only.\r\n");
1515 * For transmitting PAUSE frames ONLY.
1517 * LOCAL DEVICE | LINK PARTNER
1518 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1519 *-------|---------|-------|---------|--------------------
1520 * 1 | 1 | 0 | 1 | e1000_fc_rx_pause
1522 else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1523 (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1524 !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1525 (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1526 hw->fc.current_mode = e1000_fc_rx_pause;
1527 DEBUGOUT("Flow Control = Rx PAUSE frames only.\r\n");
1530 * Per the IEEE spec, at this point flow control
1531 * should be disabled.
1533 hw->fc.current_mode = e1000_fc_none;
1534 DEBUGOUT("Flow Control = NONE.\r\n");
1538 * Now we need to do one last check... If we auto-
1539 * negotiated to HALF DUPLEX, flow control should not be
1540 * enabled per IEEE 802.3 spec.
1542 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1544 DEBUGOUT("Error getting link speed and duplex\n");
1548 if (duplex == HALF_DUPLEX)
1549 hw->fc.current_mode = e1000_fc_none;
1552 * Now we call a subroutine to actually force the MAC
1553 * controller to use the correct flow control settings.
1555 ret_val = e1000_force_mac_fc_generic(hw);
1557 DEBUGOUT("Error forcing flow control settings\n");
1567 * e1000_get_speed_and_duplex_copper_generic - Retrieve current speed/duplex
1568 * @hw: pointer to the HW structure
1569 * @speed: stores the current speed
1570 * @duplex: stores the current duplex
1572 * Read the status register for the current speed/duplex and store the current
1573 * speed and duplex for copper connections.
1575 s32 e1000_get_speed_and_duplex_copper_generic(struct e1000_hw *hw, u16 *speed,
1580 DEBUGFUNC("e1000_get_speed_and_duplex_copper_generic");
1582 status = E1000_READ_REG(hw, E1000_STATUS);
1583 if (status & E1000_STATUS_SPEED_1000) {
1584 *speed = SPEED_1000;
1585 DEBUGOUT("1000 Mbs, ");
1586 } else if (status & E1000_STATUS_SPEED_100) {
1588 DEBUGOUT("100 Mbs, ");
1591 DEBUGOUT("10 Mbs, ");
1594 if (status & E1000_STATUS_FD) {
1595 *duplex = FULL_DUPLEX;
1596 DEBUGOUT("Full Duplex\n");
1598 *duplex = HALF_DUPLEX;
1599 DEBUGOUT("Half Duplex\n");
1602 return E1000_SUCCESS;
1606 * e1000_get_speed_and_duplex_fiber_generic - Retrieve current speed/duplex
1607 * @hw: pointer to the HW structure
1608 * @speed: stores the current speed
1609 * @duplex: stores the current duplex
1611 * Sets the speed and duplex to gigabit full duplex (the only possible option)
1612 * for fiber/serdes links.
1614 s32 e1000_get_speed_and_duplex_fiber_serdes_generic(struct e1000_hw *hw,
1615 u16 *speed, u16 *duplex)
1617 DEBUGFUNC("e1000_get_speed_and_duplex_fiber_serdes_generic");
1619 *speed = SPEED_1000;
1620 *duplex = FULL_DUPLEX;
1622 return E1000_SUCCESS;
1626 * e1000_get_hw_semaphore_generic - Acquire hardware semaphore
1627 * @hw: pointer to the HW structure
1629 * Acquire the HW semaphore to access the PHY or NVM
1631 s32 e1000_get_hw_semaphore_generic(struct e1000_hw *hw)
1634 s32 ret_val = E1000_SUCCESS;
1635 s32 timeout = hw->nvm.word_size + 1;
1638 DEBUGFUNC("e1000_get_hw_semaphore_generic");
1640 /* Get the SW semaphore */
1641 while (i < timeout) {
1642 swsm = E1000_READ_REG(hw, E1000_SWSM);
1643 if (!(swsm & E1000_SWSM_SMBI))
1651 DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
1652 ret_val = -E1000_ERR_NVM;
1656 /* Get the FW semaphore. */
1657 for (i = 0; i < timeout; i++) {
1658 swsm = E1000_READ_REG(hw, E1000_SWSM);
1659 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1661 /* Semaphore acquired if bit latched */
1662 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
1669 /* Release semaphores */
1670 e1000_put_hw_semaphore_generic(hw);
1671 DEBUGOUT("Driver can't access the NVM\n");
1672 ret_val = -E1000_ERR_NVM;
1681 * e1000_put_hw_semaphore_generic - Release hardware semaphore
1682 * @hw: pointer to the HW structure
1684 * Release hardware semaphore used to access the PHY or NVM
1686 void e1000_put_hw_semaphore_generic(struct e1000_hw *hw)
1690 DEBUGFUNC("e1000_put_hw_semaphore_generic");
1692 swsm = E1000_READ_REG(hw, E1000_SWSM);
1694 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1696 E1000_WRITE_REG(hw, E1000_SWSM, swsm);
1700 * e1000_get_auto_rd_done_generic - Check for auto read completion
1701 * @hw: pointer to the HW structure
1703 * Check EEPROM for Auto Read done bit.
1705 s32 e1000_get_auto_rd_done_generic(struct e1000_hw *hw)
1708 s32 ret_val = E1000_SUCCESS;
1710 DEBUGFUNC("e1000_get_auto_rd_done_generic");
1712 while (i < AUTO_READ_DONE_TIMEOUT) {
1713 if (E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_AUTO_RD)
1719 if (i == AUTO_READ_DONE_TIMEOUT) {
1720 DEBUGOUT("Auto read by HW from NVM has not completed.\n");
1721 ret_val = -E1000_ERR_RESET;
1730 * e1000_valid_led_default_generic - Verify a valid default LED config
1731 * @hw: pointer to the HW structure
1732 * @data: pointer to the NVM (EEPROM)
1734 * Read the EEPROM for the current default LED configuration. If the
1735 * LED configuration is not valid, set to a valid LED configuration.
1737 s32 e1000_valid_led_default_generic(struct e1000_hw *hw, u16 *data)
1741 DEBUGFUNC("e1000_valid_led_default_generic");
1743 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1745 DEBUGOUT("NVM Read Error\n");
1749 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1750 *data = ID_LED_DEFAULT;
1757 * e1000_id_led_init_generic -
1758 * @hw: pointer to the HW structure
1761 s32 e1000_id_led_init_generic(struct e1000_hw *hw)
1763 struct e1000_mac_info *mac = &hw->mac;
1765 const u32 ledctl_mask = 0x000000FF;
1766 const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1767 const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1769 const u16 led_mask = 0x0F;
1771 DEBUGFUNC("e1000_id_led_init_generic");
1773 ret_val = hw->nvm.ops.valid_led_default(hw, &data);
1777 mac->ledctl_default = E1000_READ_REG(hw, E1000_LEDCTL);
1778 mac->ledctl_mode1 = mac->ledctl_default;
1779 mac->ledctl_mode2 = mac->ledctl_default;
1781 for (i = 0; i < 4; i++) {
1782 temp = (data >> (i << 2)) & led_mask;
1784 case ID_LED_ON1_DEF2:
1785 case ID_LED_ON1_ON2:
1786 case ID_LED_ON1_OFF2:
1787 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1788 mac->ledctl_mode1 |= ledctl_on << (i << 3);
1790 case ID_LED_OFF1_DEF2:
1791 case ID_LED_OFF1_ON2:
1792 case ID_LED_OFF1_OFF2:
1793 mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1794 mac->ledctl_mode1 |= ledctl_off << (i << 3);
1801 case ID_LED_DEF1_ON2:
1802 case ID_LED_ON1_ON2:
1803 case ID_LED_OFF1_ON2:
1804 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1805 mac->ledctl_mode2 |= ledctl_on << (i << 3);
1807 case ID_LED_DEF1_OFF2:
1808 case ID_LED_ON1_OFF2:
1809 case ID_LED_OFF1_OFF2:
1810 mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1811 mac->ledctl_mode2 |= ledctl_off << (i << 3);
1824 * e1000_setup_led_generic - Configures SW controllable LED
1825 * @hw: pointer to the HW structure
1827 * This prepares the SW controllable LED for use and saves the current state
1828 * of the LED so it can be later restored.
1830 s32 e1000_setup_led_generic(struct e1000_hw *hw)
1833 s32 ret_val = E1000_SUCCESS;
1835 DEBUGFUNC("e1000_setup_led_generic");
1837 if (hw->mac.ops.setup_led != e1000_setup_led_generic) {
1838 ret_val = -E1000_ERR_CONFIG;
1842 if (hw->phy.media_type == e1000_media_type_fiber) {
1843 ledctl = E1000_READ_REG(hw, E1000_LEDCTL);
1844 hw->mac.ledctl_default = ledctl;
1846 ledctl &= ~(E1000_LEDCTL_LED0_IVRT |
1847 E1000_LEDCTL_LED0_BLINK |
1848 E1000_LEDCTL_LED0_MODE_MASK);
1849 ledctl |= (E1000_LEDCTL_MODE_LED_OFF <<
1850 E1000_LEDCTL_LED0_MODE_SHIFT);
1851 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
1852 } else if (hw->phy.media_type == e1000_media_type_copper) {
1853 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1861 * e1000_cleanup_led_generic - Set LED config to default operation
1862 * @hw: pointer to the HW structure
1864 * Remove the current LED configuration and set the LED configuration
1865 * to the default value, saved from the EEPROM.
1867 s32 e1000_cleanup_led_generic(struct e1000_hw *hw)
1869 DEBUGFUNC("e1000_cleanup_led_generic");
1871 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default);
1872 return E1000_SUCCESS;
1876 * e1000_blink_led_generic - Blink LED
1877 * @hw: pointer to the HW structure
1879 * Blink the LEDs which are set to be on.
1881 s32 e1000_blink_led_generic(struct e1000_hw *hw)
1883 u32 ledctl_blink = 0;
1886 DEBUGFUNC("e1000_blink_led_generic");
1888 if (hw->phy.media_type == e1000_media_type_fiber) {
1889 /* always blink LED0 for PCI-E fiber */
1890 ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1891 (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1894 * set the blink bit for each LED that's "on" (0x0E)
1897 ledctl_blink = hw->mac.ledctl_mode2;
1898 for (i = 0; i < 4; i++)
1899 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1900 E1000_LEDCTL_MODE_LED_ON)
1901 ledctl_blink |= (E1000_LEDCTL_LED0_BLINK <<
1905 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl_blink);
1907 return E1000_SUCCESS;
1911 * e1000_led_on_generic - Turn LED on
1912 * @hw: pointer to the HW structure
1916 s32 e1000_led_on_generic(struct e1000_hw *hw)
1920 DEBUGFUNC("e1000_led_on_generic");
1922 switch (hw->phy.media_type) {
1923 case e1000_media_type_fiber:
1924 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1925 ctrl &= ~E1000_CTRL_SWDPIN0;
1926 ctrl |= E1000_CTRL_SWDPIO0;
1927 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1929 case e1000_media_type_copper:
1930 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode2);
1936 return E1000_SUCCESS;
1940 * e1000_led_off_generic - Turn LED off
1941 * @hw: pointer to the HW structure
1945 s32 e1000_led_off_generic(struct e1000_hw *hw)
1949 DEBUGFUNC("e1000_led_off_generic");
1951 switch (hw->phy.media_type) {
1952 case e1000_media_type_fiber:
1953 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1954 ctrl |= E1000_CTRL_SWDPIN0;
1955 ctrl |= E1000_CTRL_SWDPIO0;
1956 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1958 case e1000_media_type_copper:
1959 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1);
1965 return E1000_SUCCESS;
1969 * e1000_set_pcie_no_snoop_generic - Set PCI-express capabilities
1970 * @hw: pointer to the HW structure
1971 * @no_snoop: bitmap of snoop events
1973 * Set the PCI-express register to snoop for events enabled in 'no_snoop'.
1975 void e1000_set_pcie_no_snoop_generic(struct e1000_hw *hw, u32 no_snoop)
1979 DEBUGFUNC("e1000_set_pcie_no_snoop_generic");
1981 if (hw->bus.type != e1000_bus_type_pci_express)
1985 gcr = E1000_READ_REG(hw, E1000_GCR);
1986 gcr &= ~(PCIE_NO_SNOOP_ALL);
1988 E1000_WRITE_REG(hw, E1000_GCR, gcr);
1995 * e1000_disable_pcie_master_generic - Disables PCI-express master access
1996 * @hw: pointer to the HW structure
1998 * Returns E1000_SUCCESS if successful, else returns -10
1999 * (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
2000 * the master requests to be disabled.
2002 * Disables PCI-Express master access and verifies there are no pending
2005 s32 e1000_disable_pcie_master_generic(struct e1000_hw *hw)
2008 s32 timeout = MASTER_DISABLE_TIMEOUT;
2009 s32 ret_val = E1000_SUCCESS;
2011 DEBUGFUNC("e1000_disable_pcie_master_generic");
2013 if (hw->bus.type != e1000_bus_type_pci_express)
2016 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2017 ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
2018 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2021 if (!(E1000_READ_REG(hw, E1000_STATUS) &
2022 E1000_STATUS_GIO_MASTER_ENABLE))
2029 DEBUGOUT("Master requests are pending.\n");
2030 ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
2038 * e1000_reset_adaptive_generic - Reset Adaptive Interframe Spacing
2039 * @hw: pointer to the HW structure
2041 * Reset the Adaptive Interframe Spacing throttle to default values.
2043 void e1000_reset_adaptive_generic(struct e1000_hw *hw)
2045 struct e1000_mac_info *mac = &hw->mac;
2047 DEBUGFUNC("e1000_reset_adaptive_generic");
2049 if (!mac->adaptive_ifs) {
2050 DEBUGOUT("Not in Adaptive IFS mode!\n");
2054 mac->current_ifs_val = 0;
2055 mac->ifs_min_val = IFS_MIN;
2056 mac->ifs_max_val = IFS_MAX;
2057 mac->ifs_step_size = IFS_STEP;
2058 mac->ifs_ratio = IFS_RATIO;
2060 mac->in_ifs_mode = FALSE;
2061 E1000_WRITE_REG(hw, E1000_AIT, 0);
2067 * e1000_update_adaptive_generic - Update Adaptive Interframe Spacing
2068 * @hw: pointer to the HW structure
2070 * Update the Adaptive Interframe Spacing Throttle value based on the
2071 * time between transmitted packets and time between collisions.
2073 void e1000_update_adaptive_generic(struct e1000_hw *hw)
2075 struct e1000_mac_info *mac = &hw->mac;
2077 DEBUGFUNC("e1000_update_adaptive_generic");
2079 if (!mac->adaptive_ifs) {
2080 DEBUGOUT("Not in Adaptive IFS mode!\n");
2084 if ((mac->collision_delta * mac->ifs_ratio) > mac->tx_packet_delta) {
2085 if (mac->tx_packet_delta > MIN_NUM_XMITS) {
2086 mac->in_ifs_mode = TRUE;
2087 if (mac->current_ifs_val < mac->ifs_max_val) {
2088 if (!mac->current_ifs_val)
2089 mac->current_ifs_val = mac->ifs_min_val;
2091 mac->current_ifs_val +=
2093 E1000_WRITE_REG(hw, E1000_AIT, mac->current_ifs_val);
2097 if (mac->in_ifs_mode &&
2098 (mac->tx_packet_delta <= MIN_NUM_XMITS)) {
2099 mac->current_ifs_val = 0;
2100 mac->in_ifs_mode = FALSE;
2101 E1000_WRITE_REG(hw, E1000_AIT, 0);
2109 * e1000_validate_mdi_setting_generic - Verify MDI/MDIx settings
2110 * @hw: pointer to the HW structure
2112 * Verify that when not using auto-negotiation that MDI/MDIx is correctly
2113 * set, which is forced to MDI mode only.
2115 static s32 e1000_validate_mdi_setting_generic(struct e1000_hw *hw)
2117 s32 ret_val = E1000_SUCCESS;
2119 DEBUGFUNC("e1000_validate_mdi_setting_generic");
2121 if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
2122 DEBUGOUT("Invalid MDI setting detected\n");
2124 ret_val = -E1000_ERR_CONFIG;
2133 * e1000_write_8bit_ctrl_reg_generic - Write a 8bit CTRL register
2134 * @hw: pointer to the HW structure
2135 * @reg: 32bit register offset such as E1000_SCTL
2136 * @offset: register offset to write to
2137 * @data: data to write at register offset
2139 * Writes an address/data control type register. There are several of these
2140 * and they all have the format address << 8 | data and bit 31 is polled for
2143 s32 e1000_write_8bit_ctrl_reg_generic(struct e1000_hw *hw, u32 reg,
2144 u32 offset, u8 data)
2146 u32 i, regvalue = 0;
2147 s32 ret_val = E1000_SUCCESS;
2149 DEBUGFUNC("e1000_write_8bit_ctrl_reg_generic");
2151 /* Set up the address and data */
2152 regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
2153 E1000_WRITE_REG(hw, reg, regvalue);
2155 /* Poll the ready bit to see if the MDI read completed */
2156 for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
2158 regvalue = E1000_READ_REG(hw, reg);
2159 if (regvalue & E1000_GEN_CTL_READY)
2162 if (!(regvalue & E1000_GEN_CTL_READY)) {
2163 DEBUGOUT1("Reg %08x did not indicate ready\n", reg);
2164 ret_val = -E1000_ERR_PHY;