1 /******************************************************************************
3 Copyright (c) 2001-2011, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
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21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ******************************************************************************/
35 #include "e1000_api.h"
37 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw);
38 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw);
39 /* Cable length tables */
40 static const u16 e1000_m88_cable_length_table[] = {
41 0, 50, 80, 110, 140, 140, E1000_CABLE_LENGTH_UNDEFINED };
42 #define M88E1000_CABLE_LENGTH_TABLE_SIZE \
43 (sizeof(e1000_m88_cable_length_table) / \
44 sizeof(e1000_m88_cable_length_table[0]))
46 static const u16 e1000_igp_2_cable_length_table[] = {
47 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21, 0, 0, 0, 3,
48 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41, 6, 10, 14, 18, 22,
49 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61, 21, 26, 31, 35, 40,
50 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82, 40, 45, 51, 56, 61,
51 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104, 60, 66, 72, 77, 82,
52 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121, 83, 89, 95,
53 100, 105, 109, 113, 116, 119, 122, 124, 104, 109, 114, 118, 121,
55 #define IGP02E1000_CABLE_LENGTH_TABLE_SIZE \
56 (sizeof(e1000_igp_2_cable_length_table) / \
57 sizeof(e1000_igp_2_cable_length_table[0]))
60 * e1000_init_phy_ops_generic - Initialize PHY function pointers
61 * @hw: pointer to the HW structure
63 * Setups up the function pointers to no-op functions
65 void e1000_init_phy_ops_generic(struct e1000_hw *hw)
67 struct e1000_phy_info *phy = &hw->phy;
68 DEBUGFUNC("e1000_init_phy_ops_generic");
70 /* Initialize function pointers */
71 phy->ops.init_params = e1000_null_ops_generic;
72 phy->ops.acquire = e1000_null_ops_generic;
73 phy->ops.check_polarity = e1000_null_ops_generic;
74 phy->ops.check_reset_block = e1000_null_ops_generic;
75 phy->ops.commit = e1000_null_ops_generic;
76 phy->ops.force_speed_duplex = e1000_null_ops_generic;
77 phy->ops.get_cfg_done = e1000_null_ops_generic;
78 phy->ops.get_cable_length = e1000_null_ops_generic;
79 phy->ops.get_info = e1000_null_ops_generic;
80 phy->ops.read_reg = e1000_null_read_reg;
81 phy->ops.read_reg_locked = e1000_null_read_reg;
82 phy->ops.release = e1000_null_phy_generic;
83 phy->ops.reset = e1000_null_ops_generic;
84 phy->ops.set_d0_lplu_state = e1000_null_lplu_state;
85 phy->ops.set_d3_lplu_state = e1000_null_lplu_state;
86 phy->ops.write_reg = e1000_null_write_reg;
87 phy->ops.write_reg_locked = e1000_null_write_reg;
88 phy->ops.power_up = e1000_null_phy_generic;
89 phy->ops.power_down = e1000_null_phy_generic;
93 * e1000_null_read_reg - No-op function, return 0
94 * @hw: pointer to the HW structure
96 s32 e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data)
98 DEBUGFUNC("e1000_null_read_reg");
103 * e1000_null_phy_generic - No-op function, return void
104 * @hw: pointer to the HW structure
106 void e1000_null_phy_generic(struct e1000_hw *hw)
108 DEBUGFUNC("e1000_null_phy_generic");
113 * e1000_null_lplu_state - No-op function, return 0
114 * @hw: pointer to the HW structure
116 s32 e1000_null_lplu_state(struct e1000_hw *hw, bool active)
118 DEBUGFUNC("e1000_null_lplu_state");
119 return E1000_SUCCESS;
123 * e1000_null_write_reg - No-op function, return 0
124 * @hw: pointer to the HW structure
126 s32 e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data)
128 DEBUGFUNC("e1000_null_write_reg");
129 return E1000_SUCCESS;
133 * e1000_check_reset_block_generic - Check if PHY reset is blocked
134 * @hw: pointer to the HW structure
136 * Read the PHY management control register and check whether a PHY reset
137 * is blocked. If a reset is not blocked return E1000_SUCCESS, otherwise
138 * return E1000_BLK_PHY_RESET (12).
140 s32 e1000_check_reset_block_generic(struct e1000_hw *hw)
144 DEBUGFUNC("e1000_check_reset_block");
146 manc = E1000_READ_REG(hw, E1000_MANC);
148 return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
149 E1000_BLK_PHY_RESET : E1000_SUCCESS;
153 * e1000_get_phy_id - Retrieve the PHY ID and revision
154 * @hw: pointer to the HW structure
156 * Reads the PHY registers and stores the PHY ID and possibly the PHY
157 * revision in the hardware structure.
159 s32 e1000_get_phy_id(struct e1000_hw *hw)
161 struct e1000_phy_info *phy = &hw->phy;
162 s32 ret_val = E1000_SUCCESS;
165 DEBUGFUNC("e1000_get_phy_id");
167 if (!(phy->ops.read_reg))
170 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
174 phy->id = (u32)(phy_id << 16);
176 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
180 phy->id |= (u32)(phy_id & PHY_REVISION_MASK);
181 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
188 * e1000_phy_reset_dsp_generic - Reset PHY DSP
189 * @hw: pointer to the HW structure
191 * Reset the digital signal processor.
193 s32 e1000_phy_reset_dsp_generic(struct e1000_hw *hw)
195 s32 ret_val = E1000_SUCCESS;
197 DEBUGFUNC("e1000_phy_reset_dsp_generic");
199 if (!(hw->phy.ops.write_reg))
202 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xC1);
206 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0);
213 * e1000_read_phy_reg_mdic - Read MDI control register
214 * @hw: pointer to the HW structure
215 * @offset: register offset to be read
216 * @data: pointer to the read data
218 * Reads the MDI control register in the PHY at offset and stores the
219 * information read to data.
221 s32 e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data)
223 struct e1000_phy_info *phy = &hw->phy;
225 s32 ret_val = E1000_SUCCESS;
227 DEBUGFUNC("e1000_read_phy_reg_mdic");
229 if (offset > MAX_PHY_REG_ADDRESS) {
230 DEBUGOUT1("PHY Address %d is out of range\n", offset);
231 return -E1000_ERR_PARAM;
235 * Set up Op-code, Phy Address, and register offset in the MDI
236 * Control register. The MAC will take care of interfacing with the
237 * PHY to retrieve the desired data.
239 mdic = ((offset << E1000_MDIC_REG_SHIFT) |
240 (phy->addr << E1000_MDIC_PHY_SHIFT) |
241 (E1000_MDIC_OP_READ));
243 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
246 * Poll the ready bit to see if the MDI read completed
247 * Increasing the time out as testing showed failures with
250 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
252 mdic = E1000_READ_REG(hw, E1000_MDIC);
253 if (mdic & E1000_MDIC_READY)
256 if (!(mdic & E1000_MDIC_READY)) {
257 DEBUGOUT("MDI Read did not complete\n");
258 ret_val = -E1000_ERR_PHY;
261 if (mdic & E1000_MDIC_ERROR) {
262 DEBUGOUT("MDI Error\n");
263 ret_val = -E1000_ERR_PHY;
273 * e1000_write_phy_reg_mdic - Write MDI control register
274 * @hw: pointer to the HW structure
275 * @offset: register offset to write to
276 * @data: data to write to register at offset
278 * Writes data to MDI control register in the PHY at offset.
280 s32 e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data)
282 struct e1000_phy_info *phy = &hw->phy;
284 s32 ret_val = E1000_SUCCESS;
286 DEBUGFUNC("e1000_write_phy_reg_mdic");
288 if (offset > MAX_PHY_REG_ADDRESS) {
289 DEBUGOUT1("PHY Address %d is out of range\n", offset);
290 return -E1000_ERR_PARAM;
294 * Set up Op-code, Phy Address, and register offset in the MDI
295 * Control register. The MAC will take care of interfacing with the
296 * PHY to retrieve the desired data.
298 mdic = (((u32)data) |
299 (offset << E1000_MDIC_REG_SHIFT) |
300 (phy->addr << E1000_MDIC_PHY_SHIFT) |
301 (E1000_MDIC_OP_WRITE));
303 E1000_WRITE_REG(hw, E1000_MDIC, mdic);
306 * Poll the ready bit to see if the MDI read completed
307 * Increasing the time out as testing showed failures with
310 for (i = 0; i < (E1000_GEN_POLL_TIMEOUT * 3); i++) {
312 mdic = E1000_READ_REG(hw, E1000_MDIC);
313 if (mdic & E1000_MDIC_READY)
316 if (!(mdic & E1000_MDIC_READY)) {
317 DEBUGOUT("MDI Write did not complete\n");
318 ret_val = -E1000_ERR_PHY;
321 if (mdic & E1000_MDIC_ERROR) {
322 DEBUGOUT("MDI Error\n");
323 ret_val = -E1000_ERR_PHY;
332 * e1000_read_phy_reg_i2c - Read PHY register using i2c
333 * @hw: pointer to the HW structure
334 * @offset: register offset to be read
335 * @data: pointer to the read data
337 * Reads the PHY register at offset using the i2c interface and stores the
338 * retrieved information in data.
340 s32 e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data)
342 struct e1000_phy_info *phy = &hw->phy;
345 DEBUGFUNC("e1000_read_phy_reg_i2c");
348 * Set up Op-code, Phy Address, and register address in the I2CCMD
349 * register. The MAC will take care of interfacing with the
350 * PHY to retrieve the desired data.
352 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
353 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
354 (E1000_I2CCMD_OPCODE_READ));
356 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
358 /* Poll the ready bit to see if the I2C read completed */
359 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
361 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
362 if (i2ccmd & E1000_I2CCMD_READY)
365 if (!(i2ccmd & E1000_I2CCMD_READY)) {
366 DEBUGOUT("I2CCMD Read did not complete\n");
367 return -E1000_ERR_PHY;
369 if (i2ccmd & E1000_I2CCMD_ERROR) {
370 DEBUGOUT("I2CCMD Error bit set\n");
371 return -E1000_ERR_PHY;
374 /* Need to byte-swap the 16-bit value. */
375 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
377 return E1000_SUCCESS;
381 * e1000_write_phy_reg_i2c - Write PHY register using i2c
382 * @hw: pointer to the HW structure
383 * @offset: register offset to write to
384 * @data: data to write at register offset
386 * Writes the data to PHY register at the offset using the i2c interface.
388 s32 e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data)
390 struct e1000_phy_info *phy = &hw->phy;
392 u16 phy_data_swapped;
394 DEBUGFUNC("e1000_write_phy_reg_i2c");
396 /* Swap the data bytes for the I2C interface */
397 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
400 * Set up Op-code, Phy Address, and register address in the I2CCMD
401 * register. The MAC will take care of interfacing with the
402 * PHY to retrieve the desired data.
404 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
405 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
406 E1000_I2CCMD_OPCODE_WRITE |
409 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
411 /* Poll the ready bit to see if the I2C read completed */
412 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
414 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
415 if (i2ccmd & E1000_I2CCMD_READY)
418 if (!(i2ccmd & E1000_I2CCMD_READY)) {
419 DEBUGOUT("I2CCMD Write did not complete\n");
420 return -E1000_ERR_PHY;
422 if (i2ccmd & E1000_I2CCMD_ERROR) {
423 DEBUGOUT("I2CCMD Error bit set\n");
424 return -E1000_ERR_PHY;
427 return E1000_SUCCESS;
431 * e1000_read_phy_reg_m88 - Read m88 PHY register
432 * @hw: pointer to the HW structure
433 * @offset: register offset to be read
434 * @data: pointer to the read data
436 * Acquires semaphore, if necessary, then reads the PHY register at offset
437 * and storing the retrieved information in data. Release any acquired
438 * semaphores before exiting.
440 s32 e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data)
442 s32 ret_val = E1000_SUCCESS;
444 DEBUGFUNC("e1000_read_phy_reg_m88");
446 if (!(hw->phy.ops.acquire))
449 ret_val = hw->phy.ops.acquire(hw);
453 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
456 hw->phy.ops.release(hw);
463 * e1000_write_phy_reg_m88 - Write m88 PHY register
464 * @hw: pointer to the HW structure
465 * @offset: register offset to write to
466 * @data: data to write at register offset
468 * Acquires semaphore, if necessary, then writes the data to PHY register
469 * at the offset. Release any acquired semaphores before exiting.
471 s32 e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data)
473 s32 ret_val = E1000_SUCCESS;
475 DEBUGFUNC("e1000_write_phy_reg_m88");
477 if (!(hw->phy.ops.acquire))
480 ret_val = hw->phy.ops.acquire(hw);
484 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
487 hw->phy.ops.release(hw);
494 * __e1000_read_phy_reg_igp - Read igp PHY register
495 * @hw: pointer to the HW structure
496 * @offset: register offset to be read
497 * @data: pointer to the read data
498 * @locked: semaphore has already been acquired or not
500 * Acquires semaphore, if necessary, then reads the PHY register at offset
501 * and stores the retrieved information in data. Release any acquired
502 * semaphores before exiting.
504 static s32 __e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data,
507 s32 ret_val = E1000_SUCCESS;
509 DEBUGFUNC("__e1000_read_phy_reg_igp");
512 if (!(hw->phy.ops.acquire))
515 ret_val = hw->phy.ops.acquire(hw);
520 if (offset > MAX_PHY_MULTI_PAGE_REG) {
521 ret_val = e1000_write_phy_reg_mdic(hw,
522 IGP01E1000_PHY_PAGE_SELECT,
528 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
533 hw->phy.ops.release(hw);
539 * e1000_read_phy_reg_igp - Read igp PHY register
540 * @hw: pointer to the HW structure
541 * @offset: register offset to be read
542 * @data: pointer to the read data
544 * Acquires semaphore then reads the PHY register at offset and stores the
545 * retrieved information in data.
546 * Release the acquired semaphore before exiting.
548 s32 e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data)
550 return __e1000_read_phy_reg_igp(hw, offset, data, FALSE);
554 * e1000_read_phy_reg_igp_locked - Read igp PHY register
555 * @hw: pointer to the HW structure
556 * @offset: register offset to be read
557 * @data: pointer to the read data
559 * Reads the PHY register at offset and stores the retrieved information
560 * in data. Assumes semaphore already acquired.
562 s32 e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data)
564 return __e1000_read_phy_reg_igp(hw, offset, data, TRUE);
568 * e1000_write_phy_reg_igp - Write igp PHY register
569 * @hw: pointer to the HW structure
570 * @offset: register offset to write to
571 * @data: data to write at register offset
572 * @locked: semaphore has already been acquired or not
574 * Acquires semaphore, if necessary, then writes the data to PHY register
575 * at the offset. Release any acquired semaphores before exiting.
577 static s32 __e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data,
580 s32 ret_val = E1000_SUCCESS;
582 DEBUGFUNC("e1000_write_phy_reg_igp");
585 if (!(hw->phy.ops.acquire))
588 ret_val = hw->phy.ops.acquire(hw);
593 if (offset > MAX_PHY_MULTI_PAGE_REG) {
594 ret_val = e1000_write_phy_reg_mdic(hw,
595 IGP01E1000_PHY_PAGE_SELECT,
601 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
606 hw->phy.ops.release(hw);
613 * e1000_write_phy_reg_igp - Write igp PHY register
614 * @hw: pointer to the HW structure
615 * @offset: register offset to write to
616 * @data: data to write at register offset
618 * Acquires semaphore then writes the data to PHY register
619 * at the offset. Release any acquired semaphores before exiting.
621 s32 e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data)
623 return __e1000_write_phy_reg_igp(hw, offset, data, FALSE);
627 * e1000_write_phy_reg_igp_locked - Write igp PHY register
628 * @hw: pointer to the HW structure
629 * @offset: register offset to write to
630 * @data: data to write at register offset
632 * Writes the data to PHY register at the offset.
633 * Assumes semaphore already acquired.
635 s32 e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data)
637 return __e1000_write_phy_reg_igp(hw, offset, data, TRUE);
641 * __e1000_read_kmrn_reg - Read kumeran register
642 * @hw: pointer to the HW structure
643 * @offset: register offset to be read
644 * @data: pointer to the read data
645 * @locked: semaphore has already been acquired or not
647 * Acquires semaphore, if necessary. Then reads the PHY register at offset
648 * using the kumeran interface. The information retrieved is stored in data.
649 * Release any acquired semaphores before exiting.
651 static s32 __e1000_read_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 *data,
655 s32 ret_val = E1000_SUCCESS;
657 DEBUGFUNC("__e1000_read_kmrn_reg");
660 if (!(hw->phy.ops.acquire))
663 ret_val = hw->phy.ops.acquire(hw);
668 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
669 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
670 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
674 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
675 *data = (u16)kmrnctrlsta;
678 hw->phy.ops.release(hw);
685 * e1000_read_kmrn_reg_generic - Read kumeran register
686 * @hw: pointer to the HW structure
687 * @offset: register offset to be read
688 * @data: pointer to the read data
690 * Acquires semaphore then reads the PHY register at offset using the
691 * kumeran interface. The information retrieved is stored in data.
692 * Release the acquired semaphore before exiting.
694 s32 e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data)
696 return __e1000_read_kmrn_reg(hw, offset, data, FALSE);
700 * e1000_read_kmrn_reg_locked - Read kumeran register
701 * @hw: pointer to the HW structure
702 * @offset: register offset to be read
703 * @data: pointer to the read data
705 * Reads the PHY register at offset using the kumeran interface. The
706 * information retrieved is stored in data.
707 * Assumes semaphore already acquired.
709 s32 e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data)
711 return __e1000_read_kmrn_reg(hw, offset, data, TRUE);
715 * __e1000_write_kmrn_reg - Write kumeran register
716 * @hw: pointer to the HW structure
717 * @offset: register offset to write to
718 * @data: data to write at register offset
719 * @locked: semaphore has already been acquired or not
721 * Acquires semaphore, if necessary. Then write the data to PHY register
722 * at the offset using the kumeran interface. Release any acquired semaphores
725 static s32 __e1000_write_kmrn_reg(struct e1000_hw *hw, u32 offset, u16 data,
729 s32 ret_val = E1000_SUCCESS;
731 DEBUGFUNC("e1000_write_kmrn_reg_generic");
734 if (!(hw->phy.ops.acquire))
737 ret_val = hw->phy.ops.acquire(hw);
742 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
743 E1000_KMRNCTRLSTA_OFFSET) | data;
744 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
749 hw->phy.ops.release(hw);
756 * e1000_write_kmrn_reg_generic - Write kumeran register
757 * @hw: pointer to the HW structure
758 * @offset: register offset to write to
759 * @data: data to write at register offset
761 * Acquires semaphore then writes the data to the PHY register at the offset
762 * using the kumeran interface. Release the acquired semaphore before exiting.
764 s32 e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data)
766 return __e1000_write_kmrn_reg(hw, offset, data, FALSE);
770 * e1000_write_kmrn_reg_locked - Write kumeran register
771 * @hw: pointer to the HW structure
772 * @offset: register offset to write to
773 * @data: data to write at register offset
775 * Write the data to PHY register at the offset using the kumeran interface.
776 * Assumes semaphore already acquired.
778 s32 e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data)
780 return __e1000_write_kmrn_reg(hw, offset, data, TRUE);
784 * e1000_copper_link_setup_82577 - Setup 82577 PHY for copper link
785 * @hw: pointer to the HW structure
787 * Sets up Carrier-sense on Transmit and downshift values.
789 s32 e1000_copper_link_setup_82577(struct e1000_hw *hw)
794 DEBUGFUNC("e1000_copper_link_setup_82577");
796 if (hw->phy.reset_disable) {
797 ret_val = E1000_SUCCESS;
801 if (hw->phy.type == e1000_phy_82580) {
802 ret_val = hw->phy.ops.reset(hw);
804 DEBUGOUT("Error resetting the PHY.\n");
809 /* Enable CRS on Tx. This must be set for half-duplex operation. */
810 ret_val = hw->phy.ops.read_reg(hw, I82577_CFG_REG, &phy_data);
814 phy_data |= I82577_CFG_ASSERT_CRS_ON_TX;
816 /* Enable downshift */
817 phy_data |= I82577_CFG_ENABLE_DOWNSHIFT;
819 ret_val = hw->phy.ops.write_reg(hw, I82577_CFG_REG, phy_data);
826 * e1000_copper_link_setup_m88 - Setup m88 PHY's for copper link
827 * @hw: pointer to the HW structure
829 * Sets up MDI/MDI-X and polarity for m88 PHY's. If necessary, transmit clock
830 * and downshift values are set also.
832 s32 e1000_copper_link_setup_m88(struct e1000_hw *hw)
834 struct e1000_phy_info *phy = &hw->phy;
838 DEBUGFUNC("e1000_copper_link_setup_m88");
840 if (phy->reset_disable) {
841 ret_val = E1000_SUCCESS;
845 /* Enable CRS on Tx. This must be set for half-duplex operation. */
846 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
850 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
854 * MDI/MDI-X = 0 (default)
855 * 0 - Auto for all speeds
858 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
860 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
864 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
867 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
870 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
874 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
880 * disable_polarity_correction = 0 (default)
881 * Automatic Correction for Reversed Cable Polarity
885 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
886 if (phy->disable_polarity_correction == 1)
887 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
889 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
893 if (phy->revision < E1000_REVISION_4) {
895 * Force TX_CLK in the Extended PHY Specific Control Register
898 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
903 phy_data |= M88E1000_EPSCR_TX_CLK_25;
905 if ((phy->revision == E1000_REVISION_2) &&
906 (phy->id == M88E1111_I_PHY_ID)) {
907 /* 82573L PHY - set the downshift counter to 5x. */
908 phy_data &= ~M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK;
909 phy_data |= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
911 /* Configure Master and Slave downshift values */
912 phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK |
913 M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
914 phy_data |= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X |
915 M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
917 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL,
923 /* Commit the changes. */
924 ret_val = phy->ops.commit(hw);
926 DEBUGOUT("Error committing the PHY changes\n");
935 * e1000_copper_link_setup_m88_gen2 - Setup m88 PHY's for copper link
936 * @hw: pointer to the HW structure
938 * Sets up MDI/MDI-X and polarity for i347-AT4, m88e1322 and m88e1112 PHY's.
939 * Also enables and sets the downshift parameters.
941 s32 e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw)
943 struct e1000_phy_info *phy = &hw->phy;
947 DEBUGFUNC("e1000_copper_link_setup_m88_gen2");
949 if (phy->reset_disable) {
950 ret_val = E1000_SUCCESS;
954 /* Enable CRS on Tx. This must be set for half-duplex operation. */
955 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
961 * MDI/MDI-X = 0 (default)
962 * 0 - Auto for all speeds
965 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
967 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
971 phy_data |= M88E1000_PSCR_MDI_MANUAL_MODE;
974 phy_data |= M88E1000_PSCR_MDIX_MANUAL_MODE;
977 /* M88E1112 does not support this mode) */
978 if (phy->id != M88E1112_E_PHY_ID) {
979 phy_data |= M88E1000_PSCR_AUTO_X_1000T;
984 phy_data |= M88E1000_PSCR_AUTO_X_MODE;
990 * disable_polarity_correction = 0 (default)
991 * Automatic Correction for Reversed Cable Polarity
995 phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
996 if (phy->disable_polarity_correction == 1)
997 phy_data |= M88E1000_PSCR_POLARITY_REVERSAL;
999 /* Enable downshift and setting it to X6 */
1000 phy_data &= ~I347AT4_PSCR_DOWNSHIFT_MASK;
1001 phy_data |= I347AT4_PSCR_DOWNSHIFT_6X;
1002 phy_data |= I347AT4_PSCR_DOWNSHIFT_ENABLE;
1004 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1008 /* Commit the changes. */
1009 ret_val = phy->ops.commit(hw);
1011 DEBUGOUT("Error committing the PHY changes\n");
1020 * e1000_copper_link_setup_igp - Setup igp PHY's for copper link
1021 * @hw: pointer to the HW structure
1023 * Sets up LPLU, MDI/MDI-X, polarity, Smartspeed and Master/Slave config for
1026 s32 e1000_copper_link_setup_igp(struct e1000_hw *hw)
1028 struct e1000_phy_info *phy = &hw->phy;
1032 DEBUGFUNC("e1000_copper_link_setup_igp");
1034 if (phy->reset_disable) {
1035 ret_val = E1000_SUCCESS;
1039 ret_val = hw->phy.ops.reset(hw);
1041 DEBUGOUT("Error resetting the PHY.\n");
1046 * Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1047 * timeout issues when LFS is enabled.
1051 /* disable lplu d0 during driver init */
1052 if (hw->phy.ops.set_d0_lplu_state) {
1053 ret_val = hw->phy.ops.set_d0_lplu_state(hw, FALSE);
1055 DEBUGOUT("Error Disabling LPLU D0\n");
1059 /* Configure mdi-mdix settings */
1060 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &data);
1064 data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1066 switch (phy->mdix) {
1068 data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1071 data |= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1075 data |= IGP01E1000_PSCR_AUTO_MDIX;
1078 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, data);
1082 /* set auto-master slave resolution settings */
1083 if (hw->mac.autoneg) {
1085 * when autonegotiation advertisement is only 1000Mbps then we
1086 * should disable SmartSpeed and enable Auto MasterSlave
1087 * resolution as hardware default.
1089 if (phy->autoneg_advertised == ADVERTISE_1000_FULL) {
1090 /* Disable SmartSpeed */
1091 ret_val = phy->ops.read_reg(hw,
1092 IGP01E1000_PHY_PORT_CONFIG,
1097 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1098 ret_val = phy->ops.write_reg(hw,
1099 IGP01E1000_PHY_PORT_CONFIG,
1104 /* Set auto Master/Slave resolution process */
1105 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1109 data &= ~CR_1000T_MS_ENABLE;
1110 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1115 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL, &data);
1119 /* load defaults for future use */
1120 phy->original_ms_type = (data & CR_1000T_MS_ENABLE) ?
1121 ((data & CR_1000T_MS_VALUE) ?
1122 e1000_ms_force_master :
1123 e1000_ms_force_slave) :
1126 switch (phy->ms_type) {
1127 case e1000_ms_force_master:
1128 data |= (CR_1000T_MS_ENABLE | CR_1000T_MS_VALUE);
1130 case e1000_ms_force_slave:
1131 data |= CR_1000T_MS_ENABLE;
1132 data &= ~(CR_1000T_MS_VALUE);
1135 data &= ~CR_1000T_MS_ENABLE;
1139 ret_val = phy->ops.write_reg(hw, PHY_1000T_CTRL, data);
1149 * e1000_copper_link_autoneg - Setup/Enable autoneg for copper link
1150 * @hw: pointer to the HW structure
1152 * Performs initial bounds checking on autoneg advertisement parameter, then
1153 * configure to advertise the full capability. Setup the PHY to autoneg
1154 * and restart the negotiation process between the link partner. If
1155 * autoneg_wait_to_complete, then wait for autoneg to complete before exiting.
1157 static s32 e1000_copper_link_autoneg(struct e1000_hw *hw)
1159 struct e1000_phy_info *phy = &hw->phy;
1163 DEBUGFUNC("e1000_copper_link_autoneg");
1166 * Perform some bounds checking on the autoneg advertisement
1169 phy->autoneg_advertised &= phy->autoneg_mask;
1172 * If autoneg_advertised is zero, we assume it was not defaulted
1173 * by the calling code so we set to advertise full capability.
1175 if (phy->autoneg_advertised == 0)
1176 phy->autoneg_advertised = phy->autoneg_mask;
1178 DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1179 ret_val = e1000_phy_setup_autoneg(hw);
1181 DEBUGOUT("Error Setting up Auto-Negotiation\n");
1184 DEBUGOUT("Restarting Auto-Neg\n");
1187 * Restart auto-negotiation by setting the Auto Neg Enable bit and
1188 * the Auto Neg Restart bit in the PHY control register.
1190 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
1194 phy_ctrl |= (MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG);
1195 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
1200 * Does the user want to wait for Auto-Neg to complete here, or
1201 * check at a later time (for example, callback routine).
1203 if (phy->autoneg_wait_to_complete) {
1204 ret_val = hw->mac.ops.wait_autoneg(hw);
1206 DEBUGOUT("Error while waiting for "
1207 "autoneg to complete\n");
1212 hw->mac.get_link_status = TRUE;
1219 * e1000_phy_setup_autoneg - Configure PHY for auto-negotiation
1220 * @hw: pointer to the HW structure
1222 * Reads the MII auto-neg advertisement register and/or the 1000T control
1223 * register and if the PHY is already setup for auto-negotiation, then
1224 * return successful. Otherwise, setup advertisement and flow control to
1225 * the appropriate values for the wanted auto-negotiation.
1227 static s32 e1000_phy_setup_autoneg(struct e1000_hw *hw)
1229 struct e1000_phy_info *phy = &hw->phy;
1231 u16 mii_autoneg_adv_reg;
1232 u16 mii_1000t_ctrl_reg = 0;
1234 DEBUGFUNC("e1000_phy_setup_autoneg");
1236 phy->autoneg_advertised &= phy->autoneg_mask;
1238 /* Read the MII Auto-Neg Advertisement Register (Address 4). */
1239 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
1243 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1244 /* Read the MII 1000Base-T Control Register (Address 9). */
1245 ret_val = phy->ops.read_reg(hw, PHY_1000T_CTRL,
1246 &mii_1000t_ctrl_reg);
1252 * Need to parse both autoneg_advertised and fc and set up
1253 * the appropriate PHY registers. First we will parse for
1254 * autoneg_advertised software override. Since we can advertise
1255 * a plethora of combinations, we need to check each bit
1260 * First we clear all the 10/100 mb speed bits in the Auto-Neg
1261 * Advertisement Register (Address 4) and the 1000 mb speed bits in
1262 * the 1000Base-T Control Register (Address 9).
1264 mii_autoneg_adv_reg &= ~(NWAY_AR_100TX_FD_CAPS |
1265 NWAY_AR_100TX_HD_CAPS |
1266 NWAY_AR_10T_FD_CAPS |
1267 NWAY_AR_10T_HD_CAPS);
1268 mii_1000t_ctrl_reg &= ~(CR_1000T_HD_CAPS | CR_1000T_FD_CAPS);
1270 DEBUGOUT1("autoneg_advertised %x\n", phy->autoneg_advertised);
1272 /* Do we want to advertise 10 Mb Half Duplex? */
1273 if (phy->autoneg_advertised & ADVERTISE_10_HALF) {
1274 DEBUGOUT("Advertise 10mb Half duplex\n");
1275 mii_autoneg_adv_reg |= NWAY_AR_10T_HD_CAPS;
1278 /* Do we want to advertise 10 Mb Full Duplex? */
1279 if (phy->autoneg_advertised & ADVERTISE_10_FULL) {
1280 DEBUGOUT("Advertise 10mb Full duplex\n");
1281 mii_autoneg_adv_reg |= NWAY_AR_10T_FD_CAPS;
1284 /* Do we want to advertise 100 Mb Half Duplex? */
1285 if (phy->autoneg_advertised & ADVERTISE_100_HALF) {
1286 DEBUGOUT("Advertise 100mb Half duplex\n");
1287 mii_autoneg_adv_reg |= NWAY_AR_100TX_HD_CAPS;
1290 /* Do we want to advertise 100 Mb Full Duplex? */
1291 if (phy->autoneg_advertised & ADVERTISE_100_FULL) {
1292 DEBUGOUT("Advertise 100mb Full duplex\n");
1293 mii_autoneg_adv_reg |= NWAY_AR_100TX_FD_CAPS;
1296 /* We do not allow the Phy to advertise 1000 Mb Half Duplex */
1297 if (phy->autoneg_advertised & ADVERTISE_1000_HALF)
1298 DEBUGOUT("Advertise 1000mb Half duplex request denied!\n");
1300 /* Do we want to advertise 1000 Mb Full Duplex? */
1301 if (phy->autoneg_advertised & ADVERTISE_1000_FULL) {
1302 DEBUGOUT("Advertise 1000mb Full duplex\n");
1303 mii_1000t_ctrl_reg |= CR_1000T_FD_CAPS;
1307 * Check for a software override of the flow control settings, and
1308 * setup the PHY advertisement registers accordingly. If
1309 * auto-negotiation is enabled, then software will have to set the
1310 * "PAUSE" bits to the correct value in the Auto-Negotiation
1311 * Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-
1314 * The possible values of the "fc" parameter are:
1315 * 0: Flow control is completely disabled
1316 * 1: Rx flow control is enabled (we can receive pause frames
1317 * but not send pause frames).
1318 * 2: Tx flow control is enabled (we can send pause frames
1319 * but we do not support receiving pause frames).
1320 * 3: Both Rx and Tx flow control (symmetric) are enabled.
1321 * other: No software override. The flow control configuration
1322 * in the EEPROM is used.
1324 switch (hw->fc.current_mode) {
1327 * Flow control (Rx & Tx) is completely disabled by a
1328 * software over-ride.
1330 mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1332 case e1000_fc_rx_pause:
1334 * Rx Flow control is enabled, and Tx Flow control is
1335 * disabled, by a software over-ride.
1337 * Since there really isn't a way to advertise that we are
1338 * capable of Rx Pause ONLY, we will advertise that we
1339 * support both symmetric and asymmetric Rx PAUSE. Later
1340 * (in e1000_config_fc_after_link_up) we will disable the
1341 * hw's ability to send PAUSE frames.
1343 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1345 case e1000_fc_tx_pause:
1347 * Tx Flow control is enabled, and Rx Flow control is
1348 * disabled, by a software over-ride.
1350 mii_autoneg_adv_reg |= NWAY_AR_ASM_DIR;
1351 mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
1355 * Flow control (both Rx and Tx) is enabled by a software
1358 mii_autoneg_adv_reg |= (NWAY_AR_ASM_DIR | NWAY_AR_PAUSE);
1361 DEBUGOUT("Flow control param set incorrectly\n");
1362 ret_val = -E1000_ERR_CONFIG;
1366 ret_val = phy->ops.write_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
1370 DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
1372 if (phy->autoneg_mask & ADVERTISE_1000_FULL) {
1373 ret_val = phy->ops.write_reg(hw,
1375 mii_1000t_ctrl_reg);
1385 * e1000_setup_copper_link_generic - Configure copper link settings
1386 * @hw: pointer to the HW structure
1388 * Calls the appropriate function to configure the link for auto-neg or forced
1389 * speed and duplex. Then we check for link, once link is established calls
1390 * to configure collision distance and flow control are called. If link is
1391 * not established, we return -E1000_ERR_PHY (-2).
1393 s32 e1000_setup_copper_link_generic(struct e1000_hw *hw)
1398 DEBUGFUNC("e1000_setup_copper_link_generic");
1400 if (hw->mac.autoneg) {
1402 * Setup autoneg and flow control advertisement and perform
1405 ret_val = e1000_copper_link_autoneg(hw);
1410 * PHY will be set to 10H, 10F, 100H or 100F
1411 * depending on user settings.
1413 DEBUGOUT("Forcing Speed and Duplex\n");
1414 ret_val = hw->phy.ops.force_speed_duplex(hw);
1416 DEBUGOUT("Error Forcing Speed and Duplex\n");
1422 * Check link status. Wait up to 100 microseconds for link to become
1425 ret_val = e1000_phy_has_link_generic(hw,
1426 COPPER_LINK_UP_LIMIT,
1433 DEBUGOUT("Valid link established!!!\n");
1434 e1000_config_collision_dist_generic(hw);
1435 ret_val = e1000_config_fc_after_link_up_generic(hw);
1437 DEBUGOUT("Unable to establish link!!!\n");
1445 * e1000_phy_force_speed_duplex_igp - Force speed/duplex for igp PHY
1446 * @hw: pointer to the HW structure
1448 * Calls the PHY setup function to force speed and duplex. Clears the
1449 * auto-crossover to force MDI manually. Waits for link and returns
1450 * successful if link up is successful, else -E1000_ERR_PHY (-2).
1452 s32 e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw)
1454 struct e1000_phy_info *phy = &hw->phy;
1459 DEBUGFUNC("e1000_phy_force_speed_duplex_igp");
1461 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1465 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1467 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1472 * Clear Auto-Crossover to force MDI manually. IGP requires MDI
1473 * forced whenever speed and duplex are forced.
1475 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1479 phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1480 phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1482 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1486 DEBUGOUT1("IGP PSCR: %X\n", phy_data);
1490 if (phy->autoneg_wait_to_complete) {
1491 DEBUGOUT("Waiting for forced speed/duplex link on IGP phy.\n");
1493 ret_val = e1000_phy_has_link_generic(hw,
1501 DEBUGOUT("Link taking longer than expected.\n");
1504 ret_val = e1000_phy_has_link_generic(hw,
1517 * e1000_phy_force_speed_duplex_m88 - Force speed/duplex for m88 PHY
1518 * @hw: pointer to the HW structure
1520 * Calls the PHY setup function to force speed and duplex. Clears the
1521 * auto-crossover to force MDI manually. Resets the PHY to commit the
1522 * changes. If time expires while waiting for link up, we reset the DSP.
1523 * After reset, TX_CLK and CRS on Tx must be set. Return successful upon
1524 * successful completion, else return corresponding error code.
1526 s32 e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw)
1528 struct e1000_phy_info *phy = &hw->phy;
1533 DEBUGFUNC("e1000_phy_force_speed_duplex_m88");
1536 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
1537 * forced whenever speed and duplex are forced.
1539 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1543 phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1544 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1548 DEBUGOUT1("M88E1000 PSCR: %X\n", phy_data);
1550 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
1554 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
1556 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
1560 /* Reset the phy to commit changes. */
1561 ret_val = hw->phy.ops.commit(hw);
1565 if (phy->autoneg_wait_to_complete) {
1566 DEBUGOUT("Waiting for forced speed/duplex link on M88 phy.\n");
1568 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1574 if (hw->phy.type != e1000_phy_m88 ||
1575 hw->phy.id == I347AT4_E_PHY_ID ||
1576 hw->phy.id == M88E1340M_E_PHY_ID ||
1577 hw->phy.id == M88E1112_E_PHY_ID) {
1578 DEBUGOUT("Link taking longer than expected.\n");
1581 * We didn't get link.
1582 * Reset the DSP and cross our fingers.
1584 ret_val = phy->ops.write_reg(hw,
1585 M88E1000_PHY_PAGE_SELECT,
1589 ret_val = e1000_phy_reset_dsp_generic(hw);
1596 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
1602 if (hw->phy.type != e1000_phy_m88 ||
1603 hw->phy.id == I347AT4_E_PHY_ID ||
1604 hw->phy.id == M88E1340M_E_PHY_ID ||
1605 hw->phy.id == M88E1112_E_PHY_ID)
1608 ret_val = phy->ops.read_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1613 * Resetting the phy means we need to re-force TX_CLK in the
1614 * Extended PHY Specific Control Register to 25MHz clock from
1615 * the reset value of 2.5MHz.
1617 phy_data |= M88E1000_EPSCR_TX_CLK_25;
1618 ret_val = phy->ops.write_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1623 * In addition, we must re-enable CRS on Tx for both half and full
1626 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1630 phy_data |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1631 ret_val = phy->ops.write_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1638 * e1000_phy_force_speed_duplex_ife - Force PHY speed & duplex
1639 * @hw: pointer to the HW structure
1641 * Forces the speed and duplex settings of the PHY.
1642 * This is a function pointer entry point only called by
1643 * PHY setup routines.
1645 s32 e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw)
1647 struct e1000_phy_info *phy = &hw->phy;
1652 DEBUGFUNC("e1000_phy_force_speed_duplex_ife");
1654 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &data);
1658 e1000_phy_force_speed_duplex_setup(hw, &data);
1660 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, data);
1664 /* Disable MDI-X support for 10/100 */
1665 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
1669 data &= ~IFE_PMC_AUTO_MDIX;
1670 data &= ~IFE_PMC_FORCE_MDIX;
1672 ret_val = phy->ops.write_reg(hw, IFE_PHY_MDIX_CONTROL, data);
1676 DEBUGOUT1("IFE PMC: %X\n", data);
1680 if (phy->autoneg_wait_to_complete) {
1681 DEBUGOUT("Waiting for forced speed/duplex link on IFE phy.\n");
1683 ret_val = e1000_phy_has_link_generic(hw,
1691 DEBUGOUT("Link taking longer than expected.\n");
1694 ret_val = e1000_phy_has_link_generic(hw,
1707 * e1000_phy_force_speed_duplex_setup - Configure forced PHY speed/duplex
1708 * @hw: pointer to the HW structure
1709 * @phy_ctrl: pointer to current value of PHY_CONTROL
1711 * Forces speed and duplex on the PHY by doing the following: disable flow
1712 * control, force speed/duplex on the MAC, disable auto speed detection,
1713 * disable auto-negotiation, configure duplex, configure speed, configure
1714 * the collision distance, write configuration to CTRL register. The
1715 * caller must write to the PHY_CONTROL register for these settings to
1718 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl)
1720 struct e1000_mac_info *mac = &hw->mac;
1723 DEBUGFUNC("e1000_phy_force_speed_duplex_setup");
1725 /* Turn off flow control when forcing speed/duplex */
1726 hw->fc.current_mode = e1000_fc_none;
1728 /* Force speed/duplex on the mac */
1729 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1730 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1731 ctrl &= ~E1000_CTRL_SPD_SEL;
1733 /* Disable Auto Speed Detection */
1734 ctrl &= ~E1000_CTRL_ASDE;
1736 /* Disable autoneg on the phy */
1737 *phy_ctrl &= ~MII_CR_AUTO_NEG_EN;
1739 /* Forcing Full or Half Duplex? */
1740 if (mac->forced_speed_duplex & E1000_ALL_HALF_DUPLEX) {
1741 ctrl &= ~E1000_CTRL_FD;
1742 *phy_ctrl &= ~MII_CR_FULL_DUPLEX;
1743 DEBUGOUT("Half Duplex\n");
1745 ctrl |= E1000_CTRL_FD;
1746 *phy_ctrl |= MII_CR_FULL_DUPLEX;
1747 DEBUGOUT("Full Duplex\n");
1750 /* Forcing 10mb or 100mb? */
1751 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED) {
1752 ctrl |= E1000_CTRL_SPD_100;
1753 *phy_ctrl |= MII_CR_SPEED_100;
1754 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_10);
1755 DEBUGOUT("Forcing 100mb\n");
1757 ctrl &= ~(E1000_CTRL_SPD_1000 | E1000_CTRL_SPD_100);
1758 *phy_ctrl |= MII_CR_SPEED_10;
1759 *phy_ctrl &= ~(MII_CR_SPEED_1000 | MII_CR_SPEED_100);
1760 DEBUGOUT("Forcing 10mb\n");
1763 e1000_config_collision_dist_generic(hw);
1765 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1769 * e1000_set_d3_lplu_state_generic - Sets low power link up state for D3
1770 * @hw: pointer to the HW structure
1771 * @active: boolean used to enable/disable lplu
1773 * Success returns 0, Failure returns 1
1775 * The low power link up (lplu) state is set to the power management level D3
1776 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3
1777 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
1778 * is used during Dx states where the power conservation is most important.
1779 * During driver activity, SmartSpeed should be enabled so performance is
1782 s32 e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active)
1784 struct e1000_phy_info *phy = &hw->phy;
1785 s32 ret_val = E1000_SUCCESS;
1788 DEBUGFUNC("e1000_set_d3_lplu_state_generic");
1790 if (!(hw->phy.ops.read_reg))
1793 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1798 data &= ~IGP02E1000_PM_D3_LPLU;
1799 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1804 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1805 * during Dx states where the power conservation is most
1806 * important. During driver activity we should enable
1807 * SmartSpeed, so performance is maintained.
1809 if (phy->smart_speed == e1000_smart_speed_on) {
1810 ret_val = phy->ops.read_reg(hw,
1811 IGP01E1000_PHY_PORT_CONFIG,
1816 data |= IGP01E1000_PSCFR_SMART_SPEED;
1817 ret_val = phy->ops.write_reg(hw,
1818 IGP01E1000_PHY_PORT_CONFIG,
1822 } else if (phy->smart_speed == e1000_smart_speed_off) {
1823 ret_val = phy->ops.read_reg(hw,
1824 IGP01E1000_PHY_PORT_CONFIG,
1829 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1830 ret_val = phy->ops.write_reg(hw,
1831 IGP01E1000_PHY_PORT_CONFIG,
1836 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
1837 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
1838 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
1839 data |= IGP02E1000_PM_D3_LPLU;
1840 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1845 /* When LPLU is enabled, we should disable SmartSpeed */
1846 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1851 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1852 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1861 * e1000_check_downshift_generic - Checks whether a downshift in speed occurred
1862 * @hw: pointer to the HW structure
1864 * Success returns 0, Failure returns 1
1866 * A downshift is detected by querying the PHY link health.
1868 s32 e1000_check_downshift_generic(struct e1000_hw *hw)
1870 struct e1000_phy_info *phy = &hw->phy;
1872 u16 phy_data, offset, mask;
1874 DEBUGFUNC("e1000_check_downshift_generic");
1876 switch (phy->type) {
1878 case e1000_phy_gg82563:
1879 offset = M88E1000_PHY_SPEC_STATUS;
1880 mask = M88E1000_PSSR_DOWNSHIFT;
1882 case e1000_phy_igp_2:
1883 case e1000_phy_igp_3:
1884 offset = IGP01E1000_PHY_LINK_HEALTH;
1885 mask = IGP01E1000_PLHR_SS_DOWNGRADE;
1888 /* speed downshift not supported */
1889 phy->speed_downgraded = FALSE;
1890 ret_val = E1000_SUCCESS;
1894 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
1897 phy->speed_downgraded = (phy_data & mask) ? TRUE : FALSE;
1904 * e1000_check_polarity_m88 - Checks the polarity.
1905 * @hw: pointer to the HW structure
1907 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1909 * Polarity is determined based on the PHY specific status register.
1911 s32 e1000_check_polarity_m88(struct e1000_hw *hw)
1913 struct e1000_phy_info *phy = &hw->phy;
1917 DEBUGFUNC("e1000_check_polarity_m88");
1919 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &data);
1922 phy->cable_polarity = (data & M88E1000_PSSR_REV_POLARITY)
1923 ? e1000_rev_polarity_reversed
1924 : e1000_rev_polarity_normal;
1930 * e1000_check_polarity_igp - Checks the polarity.
1931 * @hw: pointer to the HW structure
1933 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
1935 * Polarity is determined based on the PHY port status register, and the
1936 * current speed (since there is no polarity at 100Mbps).
1938 s32 e1000_check_polarity_igp(struct e1000_hw *hw)
1940 struct e1000_phy_info *phy = &hw->phy;
1942 u16 data, offset, mask;
1944 DEBUGFUNC("e1000_check_polarity_igp");
1947 * Polarity is determined based on the speed of
1950 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
1954 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
1955 IGP01E1000_PSSR_SPEED_1000MBPS) {
1956 offset = IGP01E1000_PHY_PCS_INIT_REG;
1957 mask = IGP01E1000_PHY_POLARITY_MASK;
1960 * This really only applies to 10Mbps since
1961 * there is no polarity for 100Mbps (always 0).
1963 offset = IGP01E1000_PHY_PORT_STATUS;
1964 mask = IGP01E1000_PSSR_POLARITY_REVERSED;
1967 ret_val = phy->ops.read_reg(hw, offset, &data);
1970 phy->cable_polarity = (data & mask)
1971 ? e1000_rev_polarity_reversed
1972 : e1000_rev_polarity_normal;
1979 * e1000_check_polarity_ife - Check cable polarity for IFE PHY
1980 * @hw: pointer to the HW structure
1982 * Polarity is determined on the polarity reversal feature being enabled.
1984 s32 e1000_check_polarity_ife(struct e1000_hw *hw)
1986 struct e1000_phy_info *phy = &hw->phy;
1988 u16 phy_data, offset, mask;
1990 DEBUGFUNC("e1000_check_polarity_ife");
1993 * Polarity is determined based on the reversal feature being enabled.
1995 if (phy->polarity_correction) {
1996 offset = IFE_PHY_EXTENDED_STATUS_CONTROL;
1997 mask = IFE_PESC_POLARITY_REVERSED;
1999 offset = IFE_PHY_SPECIAL_CONTROL;
2000 mask = IFE_PSC_FORCE_POLARITY;
2003 ret_val = phy->ops.read_reg(hw, offset, &phy_data);
2006 phy->cable_polarity = (phy_data & mask)
2007 ? e1000_rev_polarity_reversed
2008 : e1000_rev_polarity_normal;
2014 * e1000_wait_autoneg_generic - Wait for auto-neg completion
2015 * @hw: pointer to the HW structure
2017 * Waits for auto-negotiation to complete or for the auto-negotiation time
2018 * limit to expire, which ever happens first.
2020 s32 e1000_wait_autoneg_generic(struct e1000_hw *hw)
2022 s32 ret_val = E1000_SUCCESS;
2025 DEBUGFUNC("e1000_wait_autoneg_generic");
2027 if (!(hw->phy.ops.read_reg))
2028 return E1000_SUCCESS;
2030 /* Break after autoneg completes or PHY_AUTO_NEG_LIMIT expires. */
2031 for (i = PHY_AUTO_NEG_LIMIT; i > 0; i--) {
2032 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2035 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2038 if (phy_status & MII_SR_AUTONEG_COMPLETE)
2044 * PHY_AUTO_NEG_TIME expiration doesn't guarantee auto-negotiation
2051 * e1000_phy_has_link_generic - Polls PHY for link
2052 * @hw: pointer to the HW structure
2053 * @iterations: number of times to poll for link
2054 * @usec_interval: delay between polling attempts
2055 * @success: pointer to whether polling was successful or not
2057 * Polls the PHY status register for link, 'iterations' number of times.
2059 s32 e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
2060 u32 usec_interval, bool *success)
2062 s32 ret_val = E1000_SUCCESS;
2065 DEBUGFUNC("e1000_phy_has_link_generic");
2067 if (!(hw->phy.ops.read_reg))
2068 return E1000_SUCCESS;
2070 for (i = 0; i < iterations; i++) {
2072 * Some PHYs require the PHY_STATUS register to be read
2073 * twice due to the link bit being sticky. No harm doing
2074 * it across the board.
2076 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2079 * If the first read fails, another entity may have
2080 * ownership of the resources, wait and try again to
2081 * see if they have relinquished the resources yet.
2083 usec_delay(usec_interval);
2084 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &phy_status);
2087 if (phy_status & MII_SR_LINK_STATUS)
2089 if (usec_interval >= 1000)
2090 msec_delay_irq(usec_interval/1000);
2092 usec_delay(usec_interval);
2095 *success = (i < iterations) ? TRUE : FALSE;
2101 * e1000_get_cable_length_m88 - Determine cable length for m88 PHY
2102 * @hw: pointer to the HW structure
2104 * Reads the PHY specific status register to retrieve the cable length
2105 * information. The cable length is determined by averaging the minimum and
2106 * maximum values to get the "average" cable length. The m88 PHY has four
2107 * possible cable length values, which are:
2108 * Register Value Cable Length
2112 * 3 110 - 140 meters
2115 s32 e1000_get_cable_length_m88(struct e1000_hw *hw)
2117 struct e1000_phy_info *phy = &hw->phy;
2119 u16 phy_data, index;
2121 DEBUGFUNC("e1000_get_cable_length_m88");
2123 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2127 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2128 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2129 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2130 ret_val = -E1000_ERR_PHY;
2134 phy->min_cable_length = e1000_m88_cable_length_table[index];
2135 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2137 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2143 s32 e1000_get_cable_length_m88_gen2(struct e1000_hw *hw)
2145 struct e1000_phy_info *phy = &hw->phy;
2147 u16 phy_data, phy_data2, index, default_page, is_cm;
2149 DEBUGFUNC("e1000_get_cable_length_m88_gen2");
2151 switch (hw->phy.id) {
2152 case M88E1340M_E_PHY_ID:
2153 case I347AT4_E_PHY_ID:
2154 /* Remember the original page select and set it to 7 */
2155 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2160 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x07);
2164 /* Get cable length from PHY Cable Diagnostics Control Reg */
2165 ret_val = phy->ops.read_reg(hw, (I347AT4_PCDL + phy->addr),
2170 /* Check if the unit of cable length is meters or cm */
2171 ret_val = phy->ops.read_reg(hw, I347AT4_PCDC, &phy_data2);
2175 is_cm = !(phy_data & I347AT4_PCDC_CABLE_LENGTH_UNIT);
2177 /* Populate the phy structure with cable length in meters */
2178 phy->min_cable_length = phy_data / (is_cm ? 100 : 1);
2179 phy->max_cable_length = phy_data / (is_cm ? 100 : 1);
2180 phy->cable_length = phy_data / (is_cm ? 100 : 1);
2182 /* Reset the page selec to its original value */
2183 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2188 case M88E1112_E_PHY_ID:
2189 /* Remember the original page select and set it to 5 */
2190 ret_val = phy->ops.read_reg(hw, I347AT4_PAGE_SELECT,
2195 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT, 0x05);
2199 ret_val = phy->ops.read_reg(hw, M88E1112_VCT_DSP_DISTANCE,
2204 index = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
2205 M88E1000_PSSR_CABLE_LENGTH_SHIFT;
2206 if (index >= M88E1000_CABLE_LENGTH_TABLE_SIZE - 1) {
2207 ret_val = -E1000_ERR_PHY;
2211 phy->min_cable_length = e1000_m88_cable_length_table[index];
2212 phy->max_cable_length = e1000_m88_cable_length_table[index + 1];
2214 phy->cable_length = (phy->min_cable_length +
2215 phy->max_cable_length) / 2;
2217 /* Reset the page select to its original value */
2218 ret_val = phy->ops.write_reg(hw, I347AT4_PAGE_SELECT,
2225 ret_val = -E1000_ERR_PHY;
2234 * e1000_get_cable_length_igp_2 - Determine cable length for igp2 PHY
2235 * @hw: pointer to the HW structure
2237 * The automatic gain control (agc) normalizes the amplitude of the
2238 * received signal, adjusting for the attenuation produced by the
2239 * cable. By reading the AGC registers, which represent the
2240 * combination of coarse and fine gain value, the value can be put
2241 * into a lookup table to obtain the approximate cable length
2244 s32 e1000_get_cable_length_igp_2(struct e1000_hw *hw)
2246 struct e1000_phy_info *phy = &hw->phy;
2247 s32 ret_val = E1000_SUCCESS;
2248 u16 phy_data, i, agc_value = 0;
2249 u16 cur_agc_index, max_agc_index = 0;
2250 u16 min_agc_index = IGP02E1000_CABLE_LENGTH_TABLE_SIZE - 1;
2251 static const u16 agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] = {
2252 IGP02E1000_PHY_AGC_A,
2253 IGP02E1000_PHY_AGC_B,
2254 IGP02E1000_PHY_AGC_C,
2255 IGP02E1000_PHY_AGC_D
2258 DEBUGFUNC("e1000_get_cable_length_igp_2");
2260 /* Read the AGC registers for all channels */
2261 for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
2262 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &phy_data);
2267 * Getting bits 15:9, which represent the combination of
2268 * coarse and fine gain values. The result is a number
2269 * that can be put into the lookup table to obtain the
2270 * approximate cable length.
2272 cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
2273 IGP02E1000_AGC_LENGTH_MASK;
2275 /* Array index bound check. */
2276 if ((cur_agc_index >= IGP02E1000_CABLE_LENGTH_TABLE_SIZE) ||
2277 (cur_agc_index == 0)) {
2278 ret_val = -E1000_ERR_PHY;
2282 /* Remove min & max AGC values from calculation. */
2283 if (e1000_igp_2_cable_length_table[min_agc_index] >
2284 e1000_igp_2_cable_length_table[cur_agc_index])
2285 min_agc_index = cur_agc_index;
2286 if (e1000_igp_2_cable_length_table[max_agc_index] <
2287 e1000_igp_2_cable_length_table[cur_agc_index])
2288 max_agc_index = cur_agc_index;
2290 agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
2293 agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
2294 e1000_igp_2_cable_length_table[max_agc_index]);
2295 agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
2297 /* Calculate cable length with the error range of +/- 10 meters. */
2298 phy->min_cable_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
2299 (agc_value - IGP02E1000_AGC_RANGE) : 0;
2300 phy->max_cable_length = agc_value + IGP02E1000_AGC_RANGE;
2302 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
2309 * e1000_get_phy_info_m88 - Retrieve PHY information
2310 * @hw: pointer to the HW structure
2312 * Valid for only copper links. Read the PHY status register (sticky read)
2313 * to verify that link is up. Read the PHY special control register to
2314 * determine the polarity and 10base-T extended distance. Read the PHY
2315 * special status register to determine MDI/MDIx and current speed. If
2316 * speed is 1000, then determine cable length, local and remote receiver.
2318 s32 e1000_get_phy_info_m88(struct e1000_hw *hw)
2320 struct e1000_phy_info *phy = &hw->phy;
2325 DEBUGFUNC("e1000_get_phy_info_m88");
2327 if (phy->media_type != e1000_media_type_copper) {
2328 DEBUGOUT("Phy info is only valid for copper media\n");
2329 ret_val = -E1000_ERR_CONFIG;
2333 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2338 DEBUGOUT("Phy info is only valid if link is up\n");
2339 ret_val = -E1000_ERR_CONFIG;
2343 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2347 phy->polarity_correction = (phy_data & M88E1000_PSCR_POLARITY_REVERSAL)
2350 ret_val = e1000_check_polarity_m88(hw);
2354 ret_val = phy->ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2358 phy->is_mdix = (phy_data & M88E1000_PSSR_MDIX) ? TRUE : FALSE;
2360 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
2361 ret_val = hw->phy.ops.get_cable_length(hw);
2365 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data);
2369 phy->local_rx = (phy_data & SR_1000T_LOCAL_RX_STATUS)
2370 ? e1000_1000t_rx_status_ok
2371 : e1000_1000t_rx_status_not_ok;
2373 phy->remote_rx = (phy_data & SR_1000T_REMOTE_RX_STATUS)
2374 ? e1000_1000t_rx_status_ok
2375 : e1000_1000t_rx_status_not_ok;
2377 /* Set values to "undefined" */
2378 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2379 phy->local_rx = e1000_1000t_rx_status_undefined;
2380 phy->remote_rx = e1000_1000t_rx_status_undefined;
2388 * e1000_get_phy_info_igp - Retrieve igp PHY information
2389 * @hw: pointer to the HW structure
2391 * Read PHY status to determine if link is up. If link is up, then
2392 * set/determine 10base-T extended distance and polarity correction. Read
2393 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2394 * determine on the cable length, local and remote receiver.
2396 s32 e1000_get_phy_info_igp(struct e1000_hw *hw)
2398 struct e1000_phy_info *phy = &hw->phy;
2403 DEBUGFUNC("e1000_get_phy_info_igp");
2405 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2410 DEBUGOUT("Phy info is only valid if link is up\n");
2411 ret_val = -E1000_ERR_CONFIG;
2415 phy->polarity_correction = TRUE;
2417 ret_val = e1000_check_polarity_igp(hw);
2421 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_STATUS, &data);
2425 phy->is_mdix = (data & IGP01E1000_PSSR_MDIX) ? TRUE : FALSE;
2427 if ((data & IGP01E1000_PSSR_SPEED_MASK) ==
2428 IGP01E1000_PSSR_SPEED_1000MBPS) {
2429 ret_val = phy->ops.get_cable_length(hw);
2433 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2437 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2438 ? e1000_1000t_rx_status_ok
2439 : e1000_1000t_rx_status_not_ok;
2441 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2442 ? e1000_1000t_rx_status_ok
2443 : e1000_1000t_rx_status_not_ok;
2445 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2446 phy->local_rx = e1000_1000t_rx_status_undefined;
2447 phy->remote_rx = e1000_1000t_rx_status_undefined;
2455 * e1000_get_phy_info_ife - Retrieves various IFE PHY states
2456 * @hw: pointer to the HW structure
2458 * Populates "phy" structure with various feature states.
2460 s32 e1000_get_phy_info_ife(struct e1000_hw *hw)
2462 struct e1000_phy_info *phy = &hw->phy;
2467 DEBUGFUNC("e1000_get_phy_info_ife");
2469 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2474 DEBUGOUT("Phy info is only valid if link is up\n");
2475 ret_val = -E1000_ERR_CONFIG;
2479 ret_val = phy->ops.read_reg(hw, IFE_PHY_SPECIAL_CONTROL, &data);
2482 phy->polarity_correction = (data & IFE_PSC_AUTO_POLARITY_DISABLE)
2485 if (phy->polarity_correction) {
2486 ret_val = e1000_check_polarity_ife(hw);
2490 /* Polarity is forced */
2491 phy->cable_polarity = (data & IFE_PSC_FORCE_POLARITY)
2492 ? e1000_rev_polarity_reversed
2493 : e1000_rev_polarity_normal;
2496 ret_val = phy->ops.read_reg(hw, IFE_PHY_MDIX_CONTROL, &data);
2500 phy->is_mdix = (data & IFE_PMC_MDIX_STATUS) ? TRUE : FALSE;
2502 /* The following parameters are undefined for 10/100 operation. */
2503 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2504 phy->local_rx = e1000_1000t_rx_status_undefined;
2505 phy->remote_rx = e1000_1000t_rx_status_undefined;
2512 * e1000_phy_sw_reset_generic - PHY software reset
2513 * @hw: pointer to the HW structure
2515 * Does a software reset of the PHY by reading the PHY control register and
2516 * setting/write the control register reset bit to the PHY.
2518 s32 e1000_phy_sw_reset_generic(struct e1000_hw *hw)
2520 s32 ret_val = E1000_SUCCESS;
2523 DEBUGFUNC("e1000_phy_sw_reset_generic");
2525 if (!(hw->phy.ops.read_reg))
2528 ret_val = hw->phy.ops.read_reg(hw, PHY_CONTROL, &phy_ctrl);
2532 phy_ctrl |= MII_CR_RESET;
2533 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_ctrl);
2544 * e1000_phy_hw_reset_generic - PHY hardware reset
2545 * @hw: pointer to the HW structure
2547 * Verify the reset block is not blocking us from resetting. Acquire
2548 * semaphore (if necessary) and read/set/write the device control reset
2549 * bit in the PHY. Wait the appropriate delay time for the device to
2550 * reset and release the semaphore (if necessary).
2552 s32 e1000_phy_hw_reset_generic(struct e1000_hw *hw)
2554 struct e1000_phy_info *phy = &hw->phy;
2555 s32 ret_val = E1000_SUCCESS;
2558 DEBUGFUNC("e1000_phy_hw_reset_generic");
2560 ret_val = phy->ops.check_reset_block(hw);
2562 ret_val = E1000_SUCCESS;
2566 ret_val = phy->ops.acquire(hw);
2570 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2571 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PHY_RST);
2572 E1000_WRITE_FLUSH(hw);
2574 usec_delay(phy->reset_delay_us);
2576 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2577 E1000_WRITE_FLUSH(hw);
2581 phy->ops.release(hw);
2583 ret_val = phy->ops.get_cfg_done(hw);
2590 * e1000_get_cfg_done_generic - Generic configuration done
2591 * @hw: pointer to the HW structure
2593 * Generic function to wait 10 milli-seconds for configuration to complete
2594 * and return success.
2596 s32 e1000_get_cfg_done_generic(struct e1000_hw *hw)
2598 DEBUGFUNC("e1000_get_cfg_done_generic");
2602 return E1000_SUCCESS;
2606 * e1000_phy_init_script_igp3 - Inits the IGP3 PHY
2607 * @hw: pointer to the HW structure
2609 * Initializes a Intel Gigabit PHY3 when an EEPROM is not present.
2611 s32 e1000_phy_init_script_igp3(struct e1000_hw *hw)
2613 DEBUGOUT("Running IGP 3 PHY init script\n");
2615 /* PHY init IGP 3 */
2616 /* Enable rise/fall, 10-mode work in class-A */
2617 hw->phy.ops.write_reg(hw, 0x2F5B, 0x9018);
2618 /* Remove all caps from Replica path filter */
2619 hw->phy.ops.write_reg(hw, 0x2F52, 0x0000);
2620 /* Bias trimming for ADC, AFE and Driver (Default) */
2621 hw->phy.ops.write_reg(hw, 0x2FB1, 0x8B24);
2622 /* Increase Hybrid poly bias */
2623 hw->phy.ops.write_reg(hw, 0x2FB2, 0xF8F0);
2624 /* Add 4% to Tx amplitude in Gig mode */
2625 hw->phy.ops.write_reg(hw, 0x2010, 0x10B0);
2626 /* Disable trimming (TTT) */
2627 hw->phy.ops.write_reg(hw, 0x2011, 0x0000);
2628 /* Poly DC correction to 94.6% + 2% for all channels */
2629 hw->phy.ops.write_reg(hw, 0x20DD, 0x249A);
2630 /* ABS DC correction to 95.9% */
2631 hw->phy.ops.write_reg(hw, 0x20DE, 0x00D3);
2632 /* BG temp curve trim */
2633 hw->phy.ops.write_reg(hw, 0x28B4, 0x04CE);
2634 /* Increasing ADC OPAMP stage 1 currents to max */
2635 hw->phy.ops.write_reg(hw, 0x2F70, 0x29E4);
2636 /* Force 1000 ( required for enabling PHY regs configuration) */
2637 hw->phy.ops.write_reg(hw, 0x0000, 0x0140);
2638 /* Set upd_freq to 6 */
2639 hw->phy.ops.write_reg(hw, 0x1F30, 0x1606);
2641 hw->phy.ops.write_reg(hw, 0x1F31, 0xB814);
2642 /* Disable adaptive fixed FFE (Default) */
2643 hw->phy.ops.write_reg(hw, 0x1F35, 0x002A);
2644 /* Enable FFE hysteresis */
2645 hw->phy.ops.write_reg(hw, 0x1F3E, 0x0067);
2646 /* Fixed FFE for short cable lengths */
2647 hw->phy.ops.write_reg(hw, 0x1F54, 0x0065);
2648 /* Fixed FFE for medium cable lengths */
2649 hw->phy.ops.write_reg(hw, 0x1F55, 0x002A);
2650 /* Fixed FFE for long cable lengths */
2651 hw->phy.ops.write_reg(hw, 0x1F56, 0x002A);
2652 /* Enable Adaptive Clip Threshold */
2653 hw->phy.ops.write_reg(hw, 0x1F72, 0x3FB0);
2654 /* AHT reset limit to 1 */
2655 hw->phy.ops.write_reg(hw, 0x1F76, 0xC0FF);
2656 /* Set AHT master delay to 127 msec */
2657 hw->phy.ops.write_reg(hw, 0x1F77, 0x1DEC);
2658 /* Set scan bits for AHT */
2659 hw->phy.ops.write_reg(hw, 0x1F78, 0xF9EF);
2660 /* Set AHT Preset bits */
2661 hw->phy.ops.write_reg(hw, 0x1F79, 0x0210);
2662 /* Change integ_factor of channel A to 3 */
2663 hw->phy.ops.write_reg(hw, 0x1895, 0x0003);
2664 /* Change prop_factor of channels BCD to 8 */
2665 hw->phy.ops.write_reg(hw, 0x1796, 0x0008);
2666 /* Change cg_icount + enable integbp for channels BCD */
2667 hw->phy.ops.write_reg(hw, 0x1798, 0xD008);
2669 * Change cg_icount + enable integbp + change prop_factor_master
2670 * to 8 for channel A
2672 hw->phy.ops.write_reg(hw, 0x1898, 0xD918);
2673 /* Disable AHT in Slave mode on channel A */
2674 hw->phy.ops.write_reg(hw, 0x187A, 0x0800);
2676 * Enable LPLU and disable AN to 1000 in non-D0a states,
2679 hw->phy.ops.write_reg(hw, 0x0019, 0x008D);
2680 /* Enable restart AN on an1000_dis change */
2681 hw->phy.ops.write_reg(hw, 0x001B, 0x2080);
2682 /* Enable wh_fifo read clock in 10/100 modes */
2683 hw->phy.ops.write_reg(hw, 0x0014, 0x0045);
2684 /* Restart AN, Speed selection is 1000 */
2685 hw->phy.ops.write_reg(hw, 0x0000, 0x1340);
2687 return E1000_SUCCESS;
2691 * e1000_get_phy_type_from_id - Get PHY type from id
2692 * @phy_id: phy_id read from the phy
2694 * Returns the phy type from the id.
2696 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id)
2698 enum e1000_phy_type phy_type = e1000_phy_unknown;
2701 case M88E1000_I_PHY_ID:
2702 case M88E1000_E_PHY_ID:
2703 case M88E1111_I_PHY_ID:
2704 case M88E1011_I_PHY_ID:
2705 case I347AT4_E_PHY_ID:
2706 case M88E1112_E_PHY_ID:
2707 case M88E1340M_E_PHY_ID:
2708 phy_type = e1000_phy_m88;
2710 case IGP01E1000_I_PHY_ID: /* IGP 1 & 2 share this */
2711 phy_type = e1000_phy_igp_2;
2713 case GG82563_E_PHY_ID:
2714 phy_type = e1000_phy_gg82563;
2716 case IGP03E1000_E_PHY_ID:
2717 phy_type = e1000_phy_igp_3;
2720 case IFE_PLUS_E_PHY_ID:
2721 case IFE_C_E_PHY_ID:
2722 phy_type = e1000_phy_ife;
2724 case I82580_I_PHY_ID:
2725 phy_type = e1000_phy_82580;
2728 phy_type = e1000_phy_unknown;
2735 * e1000_determine_phy_address - Determines PHY address.
2736 * @hw: pointer to the HW structure
2738 * This uses a trial and error method to loop through possible PHY
2739 * addresses. It tests each by reading the PHY ID registers and
2740 * checking for a match.
2742 s32 e1000_determine_phy_address(struct e1000_hw *hw)
2744 s32 ret_val = -E1000_ERR_PHY_TYPE;
2747 enum e1000_phy_type phy_type = e1000_phy_unknown;
2749 hw->phy.id = phy_type;
2751 for (phy_addr = 0; phy_addr < E1000_MAX_PHY_ADDR; phy_addr++) {
2752 hw->phy.addr = phy_addr;
2756 e1000_get_phy_id(hw);
2757 phy_type = e1000_get_phy_type_from_id(hw->phy.id);
2760 * If phy_type is valid, break - we found our
2763 if (phy_type != e1000_phy_unknown) {
2764 ret_val = E1000_SUCCESS;
2777 * e1000_power_up_phy_copper - Restore copper link in case of PHY power down
2778 * @hw: pointer to the HW structure
2780 * In the case of a PHY power down to save power, or to turn off link during a
2781 * driver unload, or wake on lan is not enabled, restore the link to previous
2784 void e1000_power_up_phy_copper(struct e1000_hw *hw)
2788 /* The PHY will retain its settings across a power down/up cycle */
2789 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2790 mii_reg &= ~MII_CR_POWER_DOWN;
2791 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2795 * e1000_power_down_phy_copper - Restore copper link in case of PHY power down
2796 * @hw: pointer to the HW structure
2798 * In the case of a PHY power down to save power, or to turn off link during a
2799 * driver unload, or wake on lan is not enabled, restore the link to previous
2802 void e1000_power_down_phy_copper(struct e1000_hw *hw)
2806 /* The PHY will retain its settings across a power down/up cycle */
2807 hw->phy.ops.read_reg(hw, PHY_CONTROL, &mii_reg);
2808 mii_reg |= MII_CR_POWER_DOWN;
2809 hw->phy.ops.write_reg(hw, PHY_CONTROL, mii_reg);
2814 * e1000_check_polarity_82577 - Checks the polarity.
2815 * @hw: pointer to the HW structure
2817 * Success returns 0, Failure returns -E1000_ERR_PHY (-2)
2819 * Polarity is determined based on the PHY specific status register.
2821 s32 e1000_check_polarity_82577(struct e1000_hw *hw)
2823 struct e1000_phy_info *phy = &hw->phy;
2827 DEBUGFUNC("e1000_check_polarity_82577");
2829 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
2832 phy->cable_polarity = (data & I82577_PHY_STATUS2_REV_POLARITY)
2833 ? e1000_rev_polarity_reversed
2834 : e1000_rev_polarity_normal;
2840 * e1000_phy_force_speed_duplex_82577 - Force speed/duplex for I82577 PHY
2841 * @hw: pointer to the HW structure
2843 * Calls the PHY setup function to force speed and duplex.
2845 s32 e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw)
2847 struct e1000_phy_info *phy = &hw->phy;
2852 DEBUGFUNC("e1000_phy_force_speed_duplex_82577");
2854 ret_val = phy->ops.read_reg(hw, PHY_CONTROL, &phy_data);
2858 e1000_phy_force_speed_duplex_setup(hw, &phy_data);
2860 ret_val = phy->ops.write_reg(hw, PHY_CONTROL, phy_data);
2866 if (phy->autoneg_wait_to_complete) {
2867 DEBUGOUT("Waiting for forced speed/duplex link on 82577 phy\n");
2869 ret_val = e1000_phy_has_link_generic(hw,
2877 DEBUGOUT("Link taking longer than expected.\n");
2880 ret_val = e1000_phy_has_link_generic(hw,
2893 * e1000_get_phy_info_82577 - Retrieve I82577 PHY information
2894 * @hw: pointer to the HW structure
2896 * Read PHY status to determine if link is up. If link is up, then
2897 * set/determine 10base-T extended distance and polarity correction. Read
2898 * PHY port status to determine MDI/MDIx and speed. Based on the speed,
2899 * determine on the cable length, local and remote receiver.
2901 s32 e1000_get_phy_info_82577(struct e1000_hw *hw)
2903 struct e1000_phy_info *phy = &hw->phy;
2908 DEBUGFUNC("e1000_get_phy_info_82577");
2910 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
2915 DEBUGOUT("Phy info is only valid if link is up\n");
2916 ret_val = -E1000_ERR_CONFIG;
2920 phy->polarity_correction = TRUE;
2922 ret_val = e1000_check_polarity_82577(hw);
2926 ret_val = phy->ops.read_reg(hw, I82577_PHY_STATUS_2, &data);
2930 phy->is_mdix = (data & I82577_PHY_STATUS2_MDIX) ? TRUE : FALSE;
2932 if ((data & I82577_PHY_STATUS2_SPEED_MASK) ==
2933 I82577_PHY_STATUS2_SPEED_1000MBPS) {
2934 ret_val = hw->phy.ops.get_cable_length(hw);
2938 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &data);
2942 phy->local_rx = (data & SR_1000T_LOCAL_RX_STATUS)
2943 ? e1000_1000t_rx_status_ok
2944 : e1000_1000t_rx_status_not_ok;
2946 phy->remote_rx = (data & SR_1000T_REMOTE_RX_STATUS)
2947 ? e1000_1000t_rx_status_ok
2948 : e1000_1000t_rx_status_not_ok;
2950 phy->cable_length = E1000_CABLE_LENGTH_UNDEFINED;
2951 phy->local_rx = e1000_1000t_rx_status_undefined;
2952 phy->remote_rx = e1000_1000t_rx_status_undefined;
2960 * e1000_get_cable_length_82577 - Determine cable length for 82577 PHY
2961 * @hw: pointer to the HW structure
2963 * Reads the diagnostic status register and verifies result is valid before
2964 * placing it in the phy_cable_length field.
2966 s32 e1000_get_cable_length_82577(struct e1000_hw *hw)
2968 struct e1000_phy_info *phy = &hw->phy;
2970 u16 phy_data, length;
2972 DEBUGFUNC("e1000_get_cable_length_82577");
2974 ret_val = phy->ops.read_reg(hw, I82577_PHY_DIAG_STATUS, &phy_data);
2978 length = (phy_data & I82577_DSTATUS_CABLE_LENGTH) >>
2979 I82577_DSTATUS_CABLE_LENGTH_SHIFT;
2981 if (length == E1000_CABLE_LENGTH_UNDEFINED)
2982 ret_val = -E1000_ERR_PHY;
2984 phy->cable_length = length;