1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82598.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
39 #ident "$Id: ixgbe_82598.c,v 1.194 2012/03/28 00:54:08 jtkirshe Exp $"
41 STATIC s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
44 STATIC enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
45 STATIC s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
46 bool autoneg_wait_to_complete);
47 STATIC s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
48 ixgbe_link_speed *speed, bool *link_up,
49 bool link_up_wait_to_complete);
50 STATIC s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
51 ixgbe_link_speed speed,
53 bool autoneg_wait_to_complete);
54 STATIC s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
55 ixgbe_link_speed speed,
57 bool autoneg_wait_to_complete);
58 STATIC s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
59 STATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
60 STATIC s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
61 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
62 u32 headroom, int strategy);
65 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
66 * @hw: pointer to the HW structure
68 * The defaults for 82598 should be in the range of 50us to 50ms,
69 * however the hardware default for these parts is 500us to 1ms which is less
70 * than the 10ms recommended by the pci-e spec. To address this we need to
71 * increase the value to either 10ms to 250ms for capability version 1 config,
72 * or 16ms to 55ms for version 2.
74 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
76 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
79 /* only take action if timeout value is defaulted to 0 */
80 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
84 * if capababilities version is type 1 we can write the
85 * timeout of 10ms to 250ms through the GCR register
87 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
88 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
93 * for version 2 capabilities we need to write the config space
94 * directly in order to set the completion timeout value for
97 pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
98 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
99 IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
101 /* disable completion timeout resend */
102 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
103 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
107 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
108 * @hw: pointer to hardware structure
110 * Initialize the function pointers and assign the MAC type for 82598.
111 * Does not touch the hardware.
113 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
115 struct ixgbe_mac_info *mac = &hw->mac;
116 struct ixgbe_phy_info *phy = &hw->phy;
119 DEBUGFUNC("ixgbe_init_ops_82598");
121 ret_val = ixgbe_init_phy_ops_generic(hw);
122 ret_val = ixgbe_init_ops_generic(hw);
125 phy->ops.init = &ixgbe_init_phy_ops_82598;
128 mac->ops.start_hw = &ixgbe_start_hw_82598;
129 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_82598;
130 mac->ops.reset_hw = &ixgbe_reset_hw_82598;
131 mac->ops.get_media_type = &ixgbe_get_media_type_82598;
132 mac->ops.get_supported_physical_layer =
133 &ixgbe_get_supported_physical_layer_82598;
134 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
135 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
136 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598;
138 /* RAR, Multicast, VLAN */
139 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
140 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;
141 mac->ops.set_vfta = &ixgbe_set_vfta_82598;
142 mac->ops.set_vlvf = NULL;
143 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598;
146 mac->ops.fc_enable = &ixgbe_fc_enable_82598;
148 mac->mcft_size = 128;
150 mac->num_rar_entries = 16;
151 mac->rx_pb_size = 512;
152 mac->max_tx_queues = 32;
153 mac->max_rx_queues = 64;
154 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
157 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
160 mac->ops.check_link = &ixgbe_check_mac_link_82598;
161 mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
162 mac->ops.flap_tx_laser = NULL;
163 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82598;
164 mac->ops.setup_rxpba = &ixgbe_set_rxpba_82598;
166 /* Manageability interface */
167 mac->ops.set_fw_drv_ver = NULL;
173 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
174 * @hw: pointer to hardware structure
176 * Initialize any function pointers that were not able to be
177 * set during init_shared_code because the PHY/SFP type was
178 * not known. Perform the SFP init if necessary.
181 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
183 struct ixgbe_mac_info *mac = &hw->mac;
184 struct ixgbe_phy_info *phy = &hw->phy;
185 s32 ret_val = IXGBE_SUCCESS;
186 u16 list_offset, data_offset;
188 DEBUGFUNC("ixgbe_init_phy_ops_82598");
190 /* Identify the PHY */
191 phy->ops.identify(hw);
193 /* Overwrite the link function pointers if copper PHY */
194 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
195 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
196 mac->ops.get_link_capabilities =
197 &ixgbe_get_copper_link_capabilities_generic;
200 switch (hw->phy.type) {
202 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
203 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
204 phy->ops.get_firmware_version =
205 &ixgbe_get_phy_firmware_version_tnx;
208 phy->ops.reset = &ixgbe_reset_phy_nl;
210 /* Call SFP+ identify routine to get the SFP+ module type */
211 ret_val = phy->ops.identify_sfp(hw);
212 if (ret_val != IXGBE_SUCCESS)
214 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
215 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
219 /* Check to see if SFP+ module is supported */
220 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
223 if (ret_val != IXGBE_SUCCESS) {
224 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
237 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
238 * @hw: pointer to hardware structure
240 * Starts the hardware using the generic start_hw function.
241 * Disables relaxed ordering Then set pcie completion timeout
244 s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
248 s32 ret_val = IXGBE_SUCCESS;
250 DEBUGFUNC("ixgbe_start_hw_82598");
252 ret_val = ixgbe_start_hw_generic(hw);
254 /* Disable relaxed ordering */
255 for (i = 0; ((i < hw->mac.max_tx_queues) &&
256 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
257 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
258 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
259 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
262 for (i = 0; ((i < hw->mac.max_rx_queues) &&
263 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
264 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
265 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
266 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
267 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
270 /* set the completion timeout for interface */
271 if (ret_val == IXGBE_SUCCESS)
272 ixgbe_set_pcie_completion_timeout(hw);
278 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
279 * @hw: pointer to hardware structure
280 * @speed: pointer to link speed
281 * @autoneg: boolean auto-negotiation value
283 * Determines the link capabilities by reading the AUTOC register.
285 STATIC s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
286 ixgbe_link_speed *speed,
289 s32 status = IXGBE_SUCCESS;
292 DEBUGFUNC("ixgbe_get_link_capabilities_82598");
295 * Determine link capabilities based on the stored value of AUTOC,
296 * which represents EEPROM defaults. If AUTOC value has not been
297 * stored, use the current register value.
299 if (hw->mac.orig_link_settings_stored)
300 autoc = hw->mac.orig_autoc;
302 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
304 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
305 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
306 *speed = IXGBE_LINK_SPEED_1GB_FULL;
310 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
311 *speed = IXGBE_LINK_SPEED_10GB_FULL;
315 case IXGBE_AUTOC_LMS_1G_AN:
316 *speed = IXGBE_LINK_SPEED_1GB_FULL;
320 case IXGBE_AUTOC_LMS_KX4_AN:
321 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
322 *speed = IXGBE_LINK_SPEED_UNKNOWN;
323 if (autoc & IXGBE_AUTOC_KX4_SUPP)
324 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
325 if (autoc & IXGBE_AUTOC_KX_SUPP)
326 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
331 status = IXGBE_ERR_LINK_SETUP;
339 * ixgbe_get_media_type_82598 - Determines media type
340 * @hw: pointer to hardware structure
342 * Returns the media type (fiber, copper, backplane)
344 STATIC enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
346 enum ixgbe_media_type media_type;
348 DEBUGFUNC("ixgbe_get_media_type_82598");
350 /* Detect if there is a copper PHY attached. */
351 switch (hw->phy.type) {
352 case ixgbe_phy_cu_unknown:
354 media_type = ixgbe_media_type_copper;
360 /* Media type for I82598 is based on device ID */
361 switch (hw->device_id) {
362 case IXGBE_DEV_ID_82598:
363 case IXGBE_DEV_ID_82598_BX:
364 /* Default device ID is mezzanine card KX/KX4 */
365 media_type = ixgbe_media_type_backplane;
367 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
368 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
369 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
370 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
371 case IXGBE_DEV_ID_82598EB_XF_LR:
372 case IXGBE_DEV_ID_82598EB_SFP_LOM:
373 media_type = ixgbe_media_type_fiber;
375 case IXGBE_DEV_ID_82598EB_CX4:
376 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
377 media_type = ixgbe_media_type_cx4;
379 case IXGBE_DEV_ID_82598AT:
380 case IXGBE_DEV_ID_82598AT2:
381 media_type = ixgbe_media_type_copper;
384 media_type = ixgbe_media_type_unknown;
392 * ixgbe_fc_enable_82598 - Enable flow control
393 * @hw: pointer to hardware structure
395 * Enable flow control according to the current settings.
397 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
399 s32 ret_val = IXGBE_SUCCESS;
408 DEBUGFUNC("ixgbe_fc_enable_82598");
410 /* Validate the water mark configuration */
411 if (!hw->fc.pause_time) {
412 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
416 /* Low water mark of zero causes XOFF floods */
417 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
418 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
419 hw->fc.high_water[i]) {
420 if (!hw->fc.low_water[i] ||
421 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
422 DEBUGOUT("Invalid water mark configuration\n");
423 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
430 * On 82598 having Rx FC on causes resets while doing 1G
431 * so if it's on turn it off once we know link_speed. For
432 * more details see 82598 Specification update.
434 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
435 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
436 switch (hw->fc.requested_mode) {
438 hw->fc.requested_mode = ixgbe_fc_tx_pause;
440 case ixgbe_fc_rx_pause:
441 hw->fc.requested_mode = ixgbe_fc_none;
449 /* Negotiate the fc mode to use */
450 ixgbe_fc_autoneg(hw);
452 /* Disable any previous flow control settings */
453 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
454 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
456 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
457 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
460 * The possible values of fc.current_mode are:
461 * 0: Flow control is completely disabled
462 * 1: Rx flow control is enabled (we can receive pause frames,
463 * but not send pause frames).
464 * 2: Tx flow control is enabled (we can send pause frames but
465 * we do not support receiving pause frames).
466 * 3: Both Rx and Tx flow control (symmetric) are enabled.
469 switch (hw->fc.current_mode) {
472 * Flow control is disabled by software override or autoneg.
473 * The code below will actually disable it in the HW.
476 case ixgbe_fc_rx_pause:
478 * Rx Flow control is enabled and Tx Flow control is
479 * disabled by software override. Since there really
480 * isn't a way to advertise that we are capable of RX
481 * Pause ONLY, we will advertise that we support both
482 * symmetric and asymmetric Rx PAUSE. Later, we will
483 * disable the adapter's ability to send PAUSE frames.
485 fctrl_reg |= IXGBE_FCTRL_RFCE;
487 case ixgbe_fc_tx_pause:
489 * Tx Flow control is enabled, and Rx Flow control is
490 * disabled by software override.
492 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
495 /* Flow control (both Rx and Tx) is enabled by SW override. */
496 fctrl_reg |= IXGBE_FCTRL_RFCE;
497 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
500 DEBUGOUT("Flow control param set incorrectly\n");
501 ret_val = IXGBE_ERR_CONFIG;
506 /* Set 802.3x based flow control settings. */
507 fctrl_reg |= IXGBE_FCTRL_DPF;
508 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
509 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
511 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
512 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
513 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
514 hw->fc.high_water[i]) {
515 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
516 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
517 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
518 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
520 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
521 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
526 /* Configure pause time (2 TCs per register) */
527 reg = hw->fc.pause_time * 0x00010001;
528 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
529 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
531 /* Configure flow control refresh threshold value */
532 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
539 * ixgbe_start_mac_link_82598 - Configures MAC link settings
540 * @hw: pointer to hardware structure
542 * Configures link settings based on values in the ixgbe_hw struct.
543 * Restarts the link. Performs autonegotiation if needed.
545 STATIC s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
546 bool autoneg_wait_to_complete)
551 s32 status = IXGBE_SUCCESS;
553 DEBUGFUNC("ixgbe_start_mac_link_82598");
556 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
557 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
558 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
560 /* Only poll for autoneg to complete if specified to do so */
561 if (autoneg_wait_to_complete) {
562 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
563 IXGBE_AUTOC_LMS_KX4_AN ||
564 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
565 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
566 links_reg = 0; /* Just in case Autoneg time = 0 */
567 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
568 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
569 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
573 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
574 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
575 DEBUGOUT("Autonegotiation did not complete.\n");
580 /* Add delay to filter out noises during initial link setup */
587 * ixgbe_validate_link_ready - Function looks for phy link
588 * @hw: pointer to hardware structure
590 * Function indicates success when phy link is available. If phy is not ready
591 * within 5 seconds of MAC indicating link, the function returns error.
593 STATIC s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
598 if (hw->device_id != IXGBE_DEV_ID_82598AT2)
599 return IXGBE_SUCCESS;
602 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
603 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
604 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg);
606 if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) &&
607 (an_reg & IXGBE_MII_AUTONEG_LINK_UP))
613 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
614 DEBUGOUT("Link was indicated but link is down\n");
615 return IXGBE_ERR_LINK_SETUP;
618 return IXGBE_SUCCESS;
622 * ixgbe_check_mac_link_82598 - Get link/speed status
623 * @hw: pointer to hardware structure
624 * @speed: pointer to link speed
625 * @link_up: true is link is up, false otherwise
626 * @link_up_wait_to_complete: bool used to wait for link up or not
628 * Reads the links register to determine if link is up and the current speed
630 STATIC s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
631 ixgbe_link_speed *speed, bool *link_up,
632 bool link_up_wait_to_complete)
636 u16 link_reg, adapt_comp_reg;
638 DEBUGFUNC("ixgbe_check_mac_link_82598");
641 * SERDES PHY requires us to read link status from undocumented
642 * register 0xC79F. Bit 0 set indicates link is up/ready; clear
643 * indicates link down. OxC00C is read to check that the XAUI lanes
644 * are active. Bit 0 clear indicates active; set indicates inactive.
646 if (hw->phy.type == ixgbe_phy_nl) {
647 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
648 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
649 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
651 if (link_up_wait_to_complete) {
652 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
653 if ((link_reg & 1) &&
654 ((adapt_comp_reg & 1) == 0)) {
661 hw->phy.ops.read_reg(hw, 0xC79F,
664 hw->phy.ops.read_reg(hw, 0xC00C,
669 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
675 if (*link_up == false)
679 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
680 if (link_up_wait_to_complete) {
681 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
682 if (links_reg & IXGBE_LINKS_UP) {
689 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
692 if (links_reg & IXGBE_LINKS_UP)
698 if (links_reg & IXGBE_LINKS_SPEED)
699 *speed = IXGBE_LINK_SPEED_10GB_FULL;
701 *speed = IXGBE_LINK_SPEED_1GB_FULL;
703 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) &&
704 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))
708 return IXGBE_SUCCESS;
712 * ixgbe_setup_mac_link_82598 - Set MAC link speed
713 * @hw: pointer to hardware structure
714 * @speed: new link speed
715 * @autoneg: true if autonegotiation enabled
716 * @autoneg_wait_to_complete: true when waiting for completion is needed
718 * Set the link speed in the AUTOC register and restarts link.
720 STATIC s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
721 ixgbe_link_speed speed, bool autoneg,
722 bool autoneg_wait_to_complete)
724 s32 status = IXGBE_SUCCESS;
725 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
726 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
727 u32 autoc = curr_autoc;
728 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
730 DEBUGFUNC("ixgbe_setup_mac_link_82598");
732 /* Check to see if speed passed in is supported. */
733 ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
734 speed &= link_capabilities;
736 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
737 status = IXGBE_ERR_LINK_SETUP;
739 /* Set KX4/KX support according to speed requested */
740 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
741 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
742 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
743 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
744 autoc |= IXGBE_AUTOC_KX4_SUPP;
745 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
746 autoc |= IXGBE_AUTOC_KX_SUPP;
747 if (autoc != curr_autoc)
748 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
751 if (status == IXGBE_SUCCESS) {
753 * Setup and restart the link based on the new values in
754 * ixgbe_hw This will write the AUTOC register based on the new
757 status = ixgbe_start_mac_link_82598(hw,
758 autoneg_wait_to_complete);
766 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
767 * @hw: pointer to hardware structure
768 * @speed: new link speed
769 * @autoneg: true if autonegotiation enabled
770 * @autoneg_wait_to_complete: true if waiting is needed to complete
772 * Sets the link speed in the AUTOC register in the MAC and restarts link.
774 STATIC s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
775 ixgbe_link_speed speed,
777 bool autoneg_wait_to_complete)
781 DEBUGFUNC("ixgbe_setup_copper_link_82598");
783 /* Setup the PHY according to input speed */
784 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
785 autoneg_wait_to_complete);
787 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
793 * ixgbe_reset_hw_82598 - Performs hardware reset
794 * @hw: pointer to hardware structure
796 * Resets the hardware by resetting the transmit and receive units, masks and
797 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
800 STATIC s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
802 s32 status = IXGBE_SUCCESS;
803 s32 phy_status = IXGBE_SUCCESS;
810 DEBUGFUNC("ixgbe_reset_hw_82598");
812 /* Call adapter stop to disable tx/rx and clear interrupts */
813 status = hw->mac.ops.stop_adapter(hw);
814 if (status != IXGBE_SUCCESS)
818 * Power up the Atlas Tx lanes if they are currently powered down.
819 * Atlas Tx lanes are powered down for MAC loopback tests, but
820 * they are not automatically restored on reset.
822 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
823 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
824 /* Enable Tx Atlas so packets can be transmitted again */
825 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
827 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
828 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
831 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
833 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
834 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
837 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
839 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
840 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
843 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
845 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
846 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
851 if (hw->phy.reset_disable == false) {
852 /* PHY ops must be identified and initialized prior to reset */
854 /* Init PHY and function pointers, perform SFP setup */
855 phy_status = hw->phy.ops.init(hw);
856 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
858 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
861 hw->phy.ops.reset(hw);
866 * Issue global reset to the MAC. This needs to be a SW reset.
867 * If link reset is used, it might reset the MAC when mng is using it
869 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
870 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
871 IXGBE_WRITE_FLUSH(hw);
873 /* Poll for reset bit to self-clear indicating reset is complete */
874 for (i = 0; i < 10; i++) {
876 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
877 if (!(ctrl & IXGBE_CTRL_RST))
880 if (ctrl & IXGBE_CTRL_RST) {
881 status = IXGBE_ERR_RESET_FAILED;
882 DEBUGOUT("Reset polling failed to complete.\n");
888 * Double resets are required for recovery from certain error
889 * conditions. Between resets, it is necessary to stall to allow time
890 * for any pending HW events to complete.
892 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
893 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
897 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
898 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
899 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
902 * Store the original AUTOC value if it has not been
903 * stored off yet. Otherwise restore the stored original
904 * AUTOC value since the reset operation sets back to deaults.
906 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
907 if (hw->mac.orig_link_settings_stored == false) {
908 hw->mac.orig_autoc = autoc;
909 hw->mac.orig_link_settings_stored = true;
910 } else if (autoc != hw->mac.orig_autoc) {
911 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
914 /* Store the permanent mac address */
915 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
918 * Store MAC address from RAR0, clear receive address registers, and
919 * clear the multicast table
921 hw->mac.ops.init_rx_addrs(hw);
924 if (phy_status != IXGBE_SUCCESS)
931 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
932 * @hw: pointer to hardware struct
933 * @rar: receive address register index to associate with a VMDq index
934 * @vmdq: VMDq set index
936 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
939 u32 rar_entries = hw->mac.num_rar_entries;
941 DEBUGFUNC("ixgbe_set_vmdq_82598");
943 /* Make sure we are using a valid rar index range */
944 if (rar >= rar_entries) {
945 DEBUGOUT1("RAR index %d is out of range.\n", rar);
946 return IXGBE_ERR_INVALID_ARGUMENT;
949 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
950 rar_high &= ~IXGBE_RAH_VIND_MASK;
951 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
952 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
953 return IXGBE_SUCCESS;
957 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
958 * @hw: pointer to hardware struct
959 * @rar: receive address register index to associate with a VMDq index
960 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
962 STATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
965 u32 rar_entries = hw->mac.num_rar_entries;
968 /* Make sure we are using a valid rar index range */
969 if (rar >= rar_entries) {
970 DEBUGOUT1("RAR index %d is out of range.\n", rar);
971 return IXGBE_ERR_INVALID_ARGUMENT;
974 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
975 if (rar_high & IXGBE_RAH_VIND_MASK) {
976 rar_high &= ~IXGBE_RAH_VIND_MASK;
977 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
980 return IXGBE_SUCCESS;
984 * ixgbe_set_vfta_82598 - Set VLAN filter table
985 * @hw: pointer to hardware structure
986 * @vlan: VLAN id to write to VLAN filter
987 * @vind: VMDq output index that maps queue to VLAN id in VFTA
988 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
990 * Turn on/off specified VLAN in the VLAN filter table.
992 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1000 DEBUGFUNC("ixgbe_set_vfta_82598");
1003 return IXGBE_ERR_PARAM;
1005 /* Determine 32-bit word position in array */
1006 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
1008 /* Determine the location of the (VMD) queue index */
1009 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
1010 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
1012 /* Set the nibble for VMD queue index */
1013 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
1014 bits &= (~(0x0F << bitindex));
1015 bits |= (vind << bitindex);
1016 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
1018 /* Determine the location of the bit for this VLAN id */
1019 bitindex = vlan & 0x1F; /* lower five bits */
1021 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1023 /* Turn on this VLAN id */
1024 bits |= (1 << bitindex);
1026 /* Turn off this VLAN id */
1027 bits &= ~(1 << bitindex);
1028 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1030 return IXGBE_SUCCESS;
1034 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
1035 * @hw: pointer to hardware structure
1037 * Clears the VLAN filer table, and the VMDq index associated with the filter
1039 STATIC s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
1044 DEBUGFUNC("ixgbe_clear_vfta_82598");
1046 for (offset = 0; offset < hw->mac.vft_size; offset++)
1047 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1049 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
1050 for (offset = 0; offset < hw->mac.vft_size; offset++)
1051 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
1054 return IXGBE_SUCCESS;
1058 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
1059 * @hw: pointer to hardware structure
1060 * @reg: analog register to read
1063 * Performs read operation to Atlas analog register specified.
1065 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
1069 DEBUGFUNC("ixgbe_read_analog_reg8_82598");
1071 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
1072 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
1073 IXGBE_WRITE_FLUSH(hw);
1075 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
1076 *val = (u8)atlas_ctl;
1078 return IXGBE_SUCCESS;
1082 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
1083 * @hw: pointer to hardware structure
1084 * @reg: atlas register to write
1085 * @val: value to write
1087 * Performs write operation to Atlas analog register specified.
1089 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
1093 DEBUGFUNC("ixgbe_write_analog_reg8_82598");
1095 atlas_ctl = (reg << 8) | val;
1096 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1097 IXGBE_WRITE_FLUSH(hw);
1100 return IXGBE_SUCCESS;
1104 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1105 * @hw: pointer to hardware structure
1106 * @byte_offset: EEPROM byte offset to read
1107 * @eeprom_data: value read
1109 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1111 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1114 s32 status = IXGBE_SUCCESS;
1120 DEBUGFUNC("ixgbe_read_i2c_eeprom_82598");
1122 if (hw->phy.type == ixgbe_phy_nl) {
1124 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
1125 * 0xC30D. These registers are used to talk to the SFP+
1126 * module's EEPROM through the SDA/SCL (I2C) interface.
1128 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1129 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1130 hw->phy.ops.write_reg(hw,
1131 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1132 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1136 for (i = 0; i < 100; i++) {
1137 hw->phy.ops.read_reg(hw,
1138 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1139 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1141 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1142 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1147 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1148 DEBUGOUT("EEPROM read did not pass.\n");
1149 status = IXGBE_ERR_SFP_NOT_PRESENT;
1154 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1155 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1157 *eeprom_data = (u8)(sfp_data >> 8);
1159 status = IXGBE_ERR_PHY;
1168 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1169 * @hw: pointer to hardware structure
1171 * Determines physical layer capabilities of the current configuration.
1173 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1175 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1176 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1177 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1178 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1179 u16 ext_ability = 0;
1181 DEBUGFUNC("ixgbe_get_supported_physical_layer_82598");
1183 hw->phy.ops.identify(hw);
1185 /* Copper PHY must be checked before AUTOC LMS to determine correct
1186 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1187 switch (hw->phy.type) {
1189 case ixgbe_phy_cu_unknown:
1190 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1191 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1192 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1193 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1194 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1195 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1196 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1197 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1203 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1204 case IXGBE_AUTOC_LMS_1G_AN:
1205 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1206 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1207 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1209 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1211 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1212 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1213 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1214 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1215 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1217 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1219 case IXGBE_AUTOC_LMS_KX4_AN:
1220 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1221 if (autoc & IXGBE_AUTOC_KX_SUPP)
1222 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1223 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1224 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1230 if (hw->phy.type == ixgbe_phy_nl) {
1231 hw->phy.ops.identify_sfp(hw);
1233 switch (hw->phy.sfp_type) {
1234 case ixgbe_sfp_type_da_cu:
1235 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1237 case ixgbe_sfp_type_sr:
1238 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1240 case ixgbe_sfp_type_lr:
1241 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1244 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1249 switch (hw->device_id) {
1250 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1251 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1253 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1254 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1255 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1256 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1258 case IXGBE_DEV_ID_82598EB_XF_LR:
1259 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1266 return physical_layer;
1270 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1272 * @hw: pointer to the HW structure
1274 * Calls common function and corrects issue with some single port devices
1275 * that enable LAN1 but not LAN0.
1277 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
1279 struct ixgbe_bus_info *bus = &hw->bus;
1283 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie_82598");
1285 ixgbe_set_lan_id_multi_port_pcie(hw);
1287 /* check if LAN0 is disabled */
1288 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
1289 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
1291 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
1293 /* if LAN0 is completely disabled force function to 0 */
1294 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
1295 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
1296 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
1304 * ixgbe_enable_relaxed_ordering_82598 - enable relaxed ordering
1305 * @hw: pointer to hardware structure
1308 void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw)
1313 DEBUGFUNC("ixgbe_enable_relaxed_ordering_82598");
1315 /* Enable relaxed ordering */
1316 for (i = 0; ((i < hw->mac.max_tx_queues) &&
1317 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1318 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
1319 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
1320 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
1323 for (i = 0; ((i < hw->mac.max_rx_queues) &&
1324 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1325 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
1326 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
1327 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
1328 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
1334 * ixgbe_set_rxpba_82598 - Initialize RX packet buffer
1335 * @hw: pointer to hardware structure
1336 * @num_pb: number of packet buffers to allocate
1337 * @headroom: reserve n KB of headroom
1338 * @strategy: packet buffer allocation strategy
1340 static void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
1341 u32 headroom, int strategy)
1343 u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
1349 /* Setup Rx packet buffer sizes */
1351 case PBA_STRATEGY_WEIGHTED:
1352 /* Setup the first four at 80KB */
1353 rxpktsize = IXGBE_RXPBSIZE_80KB;
1355 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1356 /* Setup the last four at 48KB...don't re-init i */
1357 rxpktsize = IXGBE_RXPBSIZE_48KB;
1359 case PBA_STRATEGY_EQUAL:
1361 /* Divide the remaining Rx packet buffer evenly among the TCs */
1362 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1363 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1367 /* Setup Tx packet buffer sizes */
1368 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1369 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);