1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82598.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
39 #ident "$Id: ixgbe_82598.c,v 1.194 2012/03/28 00:54:08 jtkirshe Exp $"
41 #define IXGBE_82598_MAX_TX_QUEUES 32
42 #define IXGBE_82598_MAX_RX_QUEUES 64
43 #define IXGBE_82598_RAR_ENTRIES 16
44 #define IXGBE_82598_MC_TBL_SIZE 128
45 #define IXGBE_82598_VFT_TBL_SIZE 128
46 #define IXGBE_82598_RX_PB_SIZE 512
48 STATIC s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
49 ixgbe_link_speed *speed,
51 STATIC enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
53 bool autoneg_wait_to_complete);
54 STATIC s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
55 ixgbe_link_speed *speed, bool *link_up,
56 bool link_up_wait_to_complete);
57 STATIC s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
58 ixgbe_link_speed speed,
60 bool autoneg_wait_to_complete);
61 STATIC s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
62 ixgbe_link_speed speed,
64 bool autoneg_wait_to_complete);
65 STATIC s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw);
66 STATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq);
67 STATIC s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw);
68 STATIC void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
69 u32 headroom, int strategy);
72 * ixgbe_set_pcie_completion_timeout - set pci-e completion timeout
73 * @hw: pointer to the HW structure
75 * The defaults for 82598 should be in the range of 50us to 50ms,
76 * however the hardware default for these parts is 500us to 1ms which is less
77 * than the 10ms recommended by the pci-e spec. To address this we need to
78 * increase the value to either 10ms to 250ms for capability version 1 config,
79 * or 16ms to 55ms for version 2.
81 void ixgbe_set_pcie_completion_timeout(struct ixgbe_hw *hw)
83 u32 gcr = IXGBE_READ_REG(hw, IXGBE_GCR);
86 /* only take action if timeout value is defaulted to 0 */
87 if (gcr & IXGBE_GCR_CMPL_TMOUT_MASK)
91 * if capababilities version is type 1 we can write the
92 * timeout of 10ms to 250ms through the GCR register
94 if (!(gcr & IXGBE_GCR_CAP_VER2)) {
95 gcr |= IXGBE_GCR_CMPL_TMOUT_10ms;
100 * for version 2 capabilities we need to write the config space
101 * directly in order to set the completion timeout value for
104 pcie_devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
105 pcie_devctl2 |= IXGBE_PCI_DEVICE_CONTROL2_16ms;
106 IXGBE_WRITE_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2, pcie_devctl2);
108 /* disable completion timeout resend */
109 gcr &= ~IXGBE_GCR_CMPL_TMOUT_RESEND;
110 IXGBE_WRITE_REG(hw, IXGBE_GCR, gcr);
114 * ixgbe_init_ops_82598 - Inits func ptrs and MAC type
115 * @hw: pointer to hardware structure
117 * Initialize the function pointers and assign the MAC type for 82598.
118 * Does not touch the hardware.
120 s32 ixgbe_init_ops_82598(struct ixgbe_hw *hw)
122 struct ixgbe_mac_info *mac = &hw->mac;
123 struct ixgbe_phy_info *phy = &hw->phy;
126 DEBUGFUNC("ixgbe_init_ops_82598");
128 ret_val = ixgbe_init_phy_ops_generic(hw);
129 ret_val = ixgbe_init_ops_generic(hw);
132 phy->ops.init = &ixgbe_init_phy_ops_82598;
135 mac->ops.start_hw = &ixgbe_start_hw_82598;
136 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_82598;
137 mac->ops.reset_hw = &ixgbe_reset_hw_82598;
138 mac->ops.get_media_type = &ixgbe_get_media_type_82598;
139 mac->ops.get_supported_physical_layer =
140 &ixgbe_get_supported_physical_layer_82598;
141 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82598;
142 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82598;
143 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie_82598;
145 /* RAR, Multicast, VLAN */
146 mac->ops.set_vmdq = &ixgbe_set_vmdq_82598;
147 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_82598;
148 mac->ops.set_vfta = &ixgbe_set_vfta_82598;
149 mac->ops.set_vlvf = NULL;
150 mac->ops.clear_vfta = &ixgbe_clear_vfta_82598;
153 mac->ops.fc_enable = &ixgbe_fc_enable_82598;
155 mac->mcft_size = IXGBE_82598_MC_TBL_SIZE;
156 mac->vft_size = IXGBE_82598_VFT_TBL_SIZE;
157 mac->num_rar_entries = IXGBE_82598_RAR_ENTRIES;
158 mac->rx_pb_size = IXGBE_82598_RX_PB_SIZE;
159 mac->max_rx_queues = IXGBE_82598_MAX_RX_QUEUES;
160 mac->max_tx_queues = IXGBE_82598_MAX_TX_QUEUES;
161 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
164 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_82598;
167 mac->ops.check_link = &ixgbe_check_mac_link_82598;
168 mac->ops.setup_link = &ixgbe_setup_mac_link_82598;
169 mac->ops.flap_tx_laser = NULL;
170 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82598;
171 mac->ops.setup_rxpba = &ixgbe_set_rxpba_82598;
173 /* Manageability interface */
174 mac->ops.set_fw_drv_ver = NULL;
176 mac->ops.get_rtrup2tc = NULL;
182 * ixgbe_init_phy_ops_82598 - PHY/SFP specific init
183 * @hw: pointer to hardware structure
185 * Initialize any function pointers that were not able to be
186 * set during init_shared_code because the PHY/SFP type was
187 * not known. Perform the SFP init if necessary.
190 s32 ixgbe_init_phy_ops_82598(struct ixgbe_hw *hw)
192 struct ixgbe_mac_info *mac = &hw->mac;
193 struct ixgbe_phy_info *phy = &hw->phy;
194 s32 ret_val = IXGBE_SUCCESS;
195 u16 list_offset, data_offset;
197 DEBUGFUNC("ixgbe_init_phy_ops_82598");
199 /* Identify the PHY */
200 phy->ops.identify(hw);
202 /* Overwrite the link function pointers if copper PHY */
203 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
204 mac->ops.setup_link = &ixgbe_setup_copper_link_82598;
205 mac->ops.get_link_capabilities =
206 &ixgbe_get_copper_link_capabilities_generic;
209 switch (hw->phy.type) {
211 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
212 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
213 phy->ops.get_firmware_version =
214 &ixgbe_get_phy_firmware_version_tnx;
217 phy->ops.reset = &ixgbe_reset_phy_nl;
219 /* Call SFP+ identify routine to get the SFP+ module type */
220 ret_val = phy->ops.identify_sfp(hw);
221 if (ret_val != IXGBE_SUCCESS)
223 else if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) {
224 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
228 /* Check to see if SFP+ module is supported */
229 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw,
232 if (ret_val != IXGBE_SUCCESS) {
233 ret_val = IXGBE_ERR_SFP_NOT_SUPPORTED;
246 * ixgbe_start_hw_82598 - Prepare hardware for Tx/Rx
247 * @hw: pointer to hardware structure
249 * Starts the hardware using the generic start_hw function.
250 * Disables relaxed ordering Then set pcie completion timeout
253 s32 ixgbe_start_hw_82598(struct ixgbe_hw *hw)
257 s32 ret_val = IXGBE_SUCCESS;
259 DEBUGFUNC("ixgbe_start_hw_82598");
261 ret_val = ixgbe_start_hw_generic(hw);
263 /* Disable relaxed ordering */
264 for (i = 0; ((i < hw->mac.max_tx_queues) &&
265 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
266 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
267 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
268 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
271 for (i = 0; ((i < hw->mac.max_rx_queues) &&
272 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
273 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
274 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
275 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
276 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
279 /* set the completion timeout for interface */
280 if (ret_val == IXGBE_SUCCESS)
281 ixgbe_set_pcie_completion_timeout(hw);
287 * ixgbe_get_link_capabilities_82598 - Determines link capabilities
288 * @hw: pointer to hardware structure
289 * @speed: pointer to link speed
290 * @autoneg: boolean auto-negotiation value
292 * Determines the link capabilities by reading the AUTOC register.
294 STATIC s32 ixgbe_get_link_capabilities_82598(struct ixgbe_hw *hw,
295 ixgbe_link_speed *speed,
298 s32 status = IXGBE_SUCCESS;
301 DEBUGFUNC("ixgbe_get_link_capabilities_82598");
304 * Determine link capabilities based on the stored value of AUTOC,
305 * which represents EEPROM defaults. If AUTOC value has not been
306 * stored, use the current register value.
308 if (hw->mac.orig_link_settings_stored)
309 autoc = hw->mac.orig_autoc;
311 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
313 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
314 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
315 *speed = IXGBE_LINK_SPEED_1GB_FULL;
319 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
320 *speed = IXGBE_LINK_SPEED_10GB_FULL;
324 case IXGBE_AUTOC_LMS_1G_AN:
325 *speed = IXGBE_LINK_SPEED_1GB_FULL;
329 case IXGBE_AUTOC_LMS_KX4_AN:
330 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
331 *speed = IXGBE_LINK_SPEED_UNKNOWN;
332 if (autoc & IXGBE_AUTOC_KX4_SUPP)
333 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
334 if (autoc & IXGBE_AUTOC_KX_SUPP)
335 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
340 status = IXGBE_ERR_LINK_SETUP;
348 * ixgbe_get_media_type_82598 - Determines media type
349 * @hw: pointer to hardware structure
351 * Returns the media type (fiber, copper, backplane)
353 STATIC enum ixgbe_media_type ixgbe_get_media_type_82598(struct ixgbe_hw *hw)
355 enum ixgbe_media_type media_type;
357 DEBUGFUNC("ixgbe_get_media_type_82598");
359 /* Detect if there is a copper PHY attached. */
360 switch (hw->phy.type) {
361 case ixgbe_phy_cu_unknown:
363 media_type = ixgbe_media_type_copper;
369 /* Media type for I82598 is based on device ID */
370 switch (hw->device_id) {
371 case IXGBE_DEV_ID_82598:
372 case IXGBE_DEV_ID_82598_BX:
373 /* Default device ID is mezzanine card KX/KX4 */
374 media_type = ixgbe_media_type_backplane;
376 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
377 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
378 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
379 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
380 case IXGBE_DEV_ID_82598EB_XF_LR:
381 case IXGBE_DEV_ID_82598EB_SFP_LOM:
382 media_type = ixgbe_media_type_fiber;
384 case IXGBE_DEV_ID_82598EB_CX4:
385 case IXGBE_DEV_ID_82598_CX4_DUAL_PORT:
386 media_type = ixgbe_media_type_cx4;
388 case IXGBE_DEV_ID_82598AT:
389 case IXGBE_DEV_ID_82598AT2:
390 media_type = ixgbe_media_type_copper;
393 media_type = ixgbe_media_type_unknown;
401 * ixgbe_fc_enable_82598 - Enable flow control
402 * @hw: pointer to hardware structure
404 * Enable flow control according to the current settings.
406 s32 ixgbe_fc_enable_82598(struct ixgbe_hw *hw)
408 s32 ret_val = IXGBE_SUCCESS;
417 DEBUGFUNC("ixgbe_fc_enable_82598");
419 /* Validate the water mark configuration */
420 if (!hw->fc.pause_time) {
421 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
425 /* Low water mark of zero causes XOFF floods */
426 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
427 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
428 hw->fc.high_water[i]) {
429 if (!hw->fc.low_water[i] ||
430 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
431 DEBUGOUT("Invalid water mark configuration\n");
432 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
439 * On 82598 having Rx FC on causes resets while doing 1G
440 * so if it's on turn it off once we know link_speed. For
441 * more details see 82598 Specification update.
443 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
444 if (link_up && link_speed == IXGBE_LINK_SPEED_1GB_FULL) {
445 switch (hw->fc.requested_mode) {
447 hw->fc.requested_mode = ixgbe_fc_tx_pause;
449 case ixgbe_fc_rx_pause:
450 hw->fc.requested_mode = ixgbe_fc_none;
458 /* Negotiate the fc mode to use */
459 ixgbe_fc_autoneg(hw);
461 /* Disable any previous flow control settings */
462 fctrl_reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
463 fctrl_reg &= ~(IXGBE_FCTRL_RFCE | IXGBE_FCTRL_RPFCE);
465 rmcs_reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
466 rmcs_reg &= ~(IXGBE_RMCS_TFCE_PRIORITY | IXGBE_RMCS_TFCE_802_3X);
469 * The possible values of fc.current_mode are:
470 * 0: Flow control is completely disabled
471 * 1: Rx flow control is enabled (we can receive pause frames,
472 * but not send pause frames).
473 * 2: Tx flow control is enabled (we can send pause frames but
474 * we do not support receiving pause frames).
475 * 3: Both Rx and Tx flow control (symmetric) are enabled.
478 switch (hw->fc.current_mode) {
481 * Flow control is disabled by software override or autoneg.
482 * The code below will actually disable it in the HW.
485 case ixgbe_fc_rx_pause:
487 * Rx Flow control is enabled and Tx Flow control is
488 * disabled by software override. Since there really
489 * isn't a way to advertise that we are capable of RX
490 * Pause ONLY, we will advertise that we support both
491 * symmetric and asymmetric Rx PAUSE. Later, we will
492 * disable the adapter's ability to send PAUSE frames.
494 fctrl_reg |= IXGBE_FCTRL_RFCE;
496 case ixgbe_fc_tx_pause:
498 * Tx Flow control is enabled, and Rx Flow control is
499 * disabled by software override.
501 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
504 /* Flow control (both Rx and Tx) is enabled by SW override. */
505 fctrl_reg |= IXGBE_FCTRL_RFCE;
506 rmcs_reg |= IXGBE_RMCS_TFCE_802_3X;
509 DEBUGOUT("Flow control param set incorrectly\n");
510 ret_val = IXGBE_ERR_CONFIG;
515 /* Set 802.3x based flow control settings. */
516 fctrl_reg |= IXGBE_FCTRL_DPF;
517 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl_reg);
518 IXGBE_WRITE_REG(hw, IXGBE_RMCS, rmcs_reg);
520 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
521 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
522 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
523 hw->fc.high_water[i]) {
524 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
525 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
526 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
527 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), fcrth);
529 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
530 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
535 /* Configure pause time (2 TCs per register) */
536 reg = hw->fc.pause_time * 0x00010001;
537 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
538 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
540 /* Configure flow control refresh threshold value */
541 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
548 * ixgbe_start_mac_link_82598 - Configures MAC link settings
549 * @hw: pointer to hardware structure
551 * Configures link settings based on values in the ixgbe_hw struct.
552 * Restarts the link. Performs autonegotiation if needed.
554 STATIC s32 ixgbe_start_mac_link_82598(struct ixgbe_hw *hw,
555 bool autoneg_wait_to_complete)
560 s32 status = IXGBE_SUCCESS;
562 DEBUGFUNC("ixgbe_start_mac_link_82598");
565 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
566 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
567 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
569 /* Only poll for autoneg to complete if specified to do so */
570 if (autoneg_wait_to_complete) {
571 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
572 IXGBE_AUTOC_LMS_KX4_AN ||
573 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
574 IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
575 links_reg = 0; /* Just in case Autoneg time = 0 */
576 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
577 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
578 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
582 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
583 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
584 DEBUGOUT("Autonegotiation did not complete.\n");
589 /* Add delay to filter out noises during initial link setup */
596 * ixgbe_validate_link_ready - Function looks for phy link
597 * @hw: pointer to hardware structure
599 * Function indicates success when phy link is available. If phy is not ready
600 * within 5 seconds of MAC indicating link, the function returns error.
602 STATIC s32 ixgbe_validate_link_ready(struct ixgbe_hw *hw)
607 if (hw->device_id != IXGBE_DEV_ID_82598AT2)
608 return IXGBE_SUCCESS;
611 timeout < IXGBE_VALIDATE_LINK_READY_TIMEOUT; timeout++) {
612 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
613 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &an_reg);
615 if ((an_reg & IXGBE_MII_AUTONEG_COMPLETE) &&
616 (an_reg & IXGBE_MII_AUTONEG_LINK_UP))
622 if (timeout == IXGBE_VALIDATE_LINK_READY_TIMEOUT) {
623 DEBUGOUT("Link was indicated but link is down\n");
624 return IXGBE_ERR_LINK_SETUP;
627 return IXGBE_SUCCESS;
631 * ixgbe_check_mac_link_82598 - Get link/speed status
632 * @hw: pointer to hardware structure
633 * @speed: pointer to link speed
634 * @link_up: true is link is up, false otherwise
635 * @link_up_wait_to_complete: bool used to wait for link up or not
637 * Reads the links register to determine if link is up and the current speed
639 STATIC s32 ixgbe_check_mac_link_82598(struct ixgbe_hw *hw,
640 ixgbe_link_speed *speed, bool *link_up,
641 bool link_up_wait_to_complete)
645 u16 link_reg, adapt_comp_reg;
647 DEBUGFUNC("ixgbe_check_mac_link_82598");
650 * SERDES PHY requires us to read link status from undocumented
651 * register 0xC79F. Bit 0 set indicates link is up/ready; clear
652 * indicates link down. OxC00C is read to check that the XAUI lanes
653 * are active. Bit 0 clear indicates active; set indicates inactive.
655 if (hw->phy.type == ixgbe_phy_nl) {
656 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
657 hw->phy.ops.read_reg(hw, 0xC79F, IXGBE_TWINAX_DEV, &link_reg);
658 hw->phy.ops.read_reg(hw, 0xC00C, IXGBE_TWINAX_DEV,
660 if (link_up_wait_to_complete) {
661 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
662 if ((link_reg & 1) &&
663 ((adapt_comp_reg & 1) == 0)) {
670 hw->phy.ops.read_reg(hw, 0xC79F,
673 hw->phy.ops.read_reg(hw, 0xC00C,
678 if ((link_reg & 1) && ((adapt_comp_reg & 1) == 0))
684 if (*link_up == false)
688 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
689 if (link_up_wait_to_complete) {
690 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
691 if (links_reg & IXGBE_LINKS_UP) {
698 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
701 if (links_reg & IXGBE_LINKS_UP)
707 if (links_reg & IXGBE_LINKS_SPEED)
708 *speed = IXGBE_LINK_SPEED_10GB_FULL;
710 *speed = IXGBE_LINK_SPEED_1GB_FULL;
712 if ((hw->device_id == IXGBE_DEV_ID_82598AT2) && (*link_up == true) &&
713 (ixgbe_validate_link_ready(hw) != IXGBE_SUCCESS))
717 return IXGBE_SUCCESS;
721 * ixgbe_setup_mac_link_82598 - Set MAC link speed
722 * @hw: pointer to hardware structure
723 * @speed: new link speed
724 * @autoneg: true if autonegotiation enabled
725 * @autoneg_wait_to_complete: true when waiting for completion is needed
727 * Set the link speed in the AUTOC register and restarts link.
729 STATIC s32 ixgbe_setup_mac_link_82598(struct ixgbe_hw *hw,
730 ixgbe_link_speed speed, bool autoneg,
731 bool autoneg_wait_to_complete)
733 s32 status = IXGBE_SUCCESS;
734 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
735 u32 curr_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
736 u32 autoc = curr_autoc;
737 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
739 DEBUGFUNC("ixgbe_setup_mac_link_82598");
741 /* Check to see if speed passed in is supported. */
742 ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
743 speed &= link_capabilities;
745 if (speed == IXGBE_LINK_SPEED_UNKNOWN)
746 status = IXGBE_ERR_LINK_SETUP;
748 /* Set KX4/KX support according to speed requested */
749 else if (link_mode == IXGBE_AUTOC_LMS_KX4_AN ||
750 link_mode == IXGBE_AUTOC_LMS_KX4_AN_1G_AN) {
751 autoc &= ~IXGBE_AUTOC_KX4_KX_SUPP_MASK;
752 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
753 autoc |= IXGBE_AUTOC_KX4_SUPP;
754 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
755 autoc |= IXGBE_AUTOC_KX_SUPP;
756 if (autoc != curr_autoc)
757 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
760 if (status == IXGBE_SUCCESS) {
762 * Setup and restart the link based on the new values in
763 * ixgbe_hw This will write the AUTOC register based on the new
766 status = ixgbe_start_mac_link_82598(hw,
767 autoneg_wait_to_complete);
775 * ixgbe_setup_copper_link_82598 - Set the PHY autoneg advertised field
776 * @hw: pointer to hardware structure
777 * @speed: new link speed
778 * @autoneg: true if autonegotiation enabled
779 * @autoneg_wait_to_complete: true if waiting is needed to complete
781 * Sets the link speed in the AUTOC register in the MAC and restarts link.
783 STATIC s32 ixgbe_setup_copper_link_82598(struct ixgbe_hw *hw,
784 ixgbe_link_speed speed,
786 bool autoneg_wait_to_complete)
790 DEBUGFUNC("ixgbe_setup_copper_link_82598");
792 /* Setup the PHY according to input speed */
793 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
794 autoneg_wait_to_complete);
796 ixgbe_start_mac_link_82598(hw, autoneg_wait_to_complete);
802 * ixgbe_reset_hw_82598 - Performs hardware reset
803 * @hw: pointer to hardware structure
805 * Resets the hardware by resetting the transmit and receive units, masks and
806 * clears all interrupts, performing a PHY reset, and performing a link (MAC)
809 STATIC s32 ixgbe_reset_hw_82598(struct ixgbe_hw *hw)
811 s32 status = IXGBE_SUCCESS;
812 s32 phy_status = IXGBE_SUCCESS;
819 DEBUGFUNC("ixgbe_reset_hw_82598");
821 /* Call adapter stop to disable tx/rx and clear interrupts */
822 status = hw->mac.ops.stop_adapter(hw);
823 if (status != IXGBE_SUCCESS)
827 * Power up the Atlas Tx lanes if they are currently powered down.
828 * Atlas Tx lanes are powered down for MAC loopback tests, but
829 * they are not automatically restored on reset.
831 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK, &analog_val);
832 if (analog_val & IXGBE_ATLAS_PDN_TX_REG_EN) {
833 /* Enable Tx Atlas so packets can be transmitted again */
834 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
836 analog_val &= ~IXGBE_ATLAS_PDN_TX_REG_EN;
837 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_LPBK,
840 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
842 analog_val &= ~IXGBE_ATLAS_PDN_TX_10G_QL_ALL;
843 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_10G,
846 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
848 analog_val &= ~IXGBE_ATLAS_PDN_TX_1G_QL_ALL;
849 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_1G,
852 hw->mac.ops.read_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
854 analog_val &= ~IXGBE_ATLAS_PDN_TX_AN_QL_ALL;
855 hw->mac.ops.write_analog_reg8(hw, IXGBE_ATLAS_PDN_AN,
860 if (hw->phy.reset_disable == false) {
861 /* PHY ops must be identified and initialized prior to reset */
863 /* Init PHY and function pointers, perform SFP setup */
864 phy_status = hw->phy.ops.init(hw);
865 if (phy_status == IXGBE_ERR_SFP_NOT_SUPPORTED)
867 if (phy_status == IXGBE_ERR_SFP_NOT_PRESENT)
870 hw->phy.ops.reset(hw);
875 * Issue global reset to the MAC. This needs to be a SW reset.
876 * If link reset is used, it might reset the MAC when mng is using it
878 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL) | IXGBE_CTRL_RST;
879 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
880 IXGBE_WRITE_FLUSH(hw);
882 /* Poll for reset bit to self-clear indicating reset is complete */
883 for (i = 0; i < 10; i++) {
885 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
886 if (!(ctrl & IXGBE_CTRL_RST))
889 if (ctrl & IXGBE_CTRL_RST) {
890 status = IXGBE_ERR_RESET_FAILED;
891 DEBUGOUT("Reset polling failed to complete.\n");
897 * Double resets are required for recovery from certain error
898 * conditions. Between resets, it is necessary to stall to allow time
899 * for any pending HW events to complete.
901 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
902 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
906 gheccr = IXGBE_READ_REG(hw, IXGBE_GHECCR);
907 gheccr &= ~((1 << 21) | (1 << 18) | (1 << 9) | (1 << 6));
908 IXGBE_WRITE_REG(hw, IXGBE_GHECCR, gheccr);
911 * Store the original AUTOC value if it has not been
912 * stored off yet. Otherwise restore the stored original
913 * AUTOC value since the reset operation sets back to deaults.
915 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
916 if (hw->mac.orig_link_settings_stored == false) {
917 hw->mac.orig_autoc = autoc;
918 hw->mac.orig_link_settings_stored = true;
919 } else if (autoc != hw->mac.orig_autoc) {
920 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
923 /* Store the permanent mac address */
924 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
927 * Store MAC address from RAR0, clear receive address registers, and
928 * clear the multicast table
930 hw->mac.ops.init_rx_addrs(hw);
933 if (phy_status != IXGBE_SUCCESS)
940 * ixgbe_set_vmdq_82598 - Associate a VMDq set index with a rx address
941 * @hw: pointer to hardware struct
942 * @rar: receive address register index to associate with a VMDq index
943 * @vmdq: VMDq set index
945 s32 ixgbe_set_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
948 u32 rar_entries = hw->mac.num_rar_entries;
950 DEBUGFUNC("ixgbe_set_vmdq_82598");
952 /* Make sure we are using a valid rar index range */
953 if (rar >= rar_entries) {
954 DEBUGOUT1("RAR index %d is out of range.\n", rar);
955 return IXGBE_ERR_INVALID_ARGUMENT;
958 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
959 rar_high &= ~IXGBE_RAH_VIND_MASK;
960 rar_high |= ((vmdq << IXGBE_RAH_VIND_SHIFT) & IXGBE_RAH_VIND_MASK);
961 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
962 return IXGBE_SUCCESS;
966 * ixgbe_clear_vmdq_82598 - Disassociate a VMDq set index from an rx address
967 * @hw: pointer to hardware struct
968 * @rar: receive address register index to associate with a VMDq index
969 * @vmdq: VMDq clear index (not used in 82598, but elsewhere)
971 STATIC s32 ixgbe_clear_vmdq_82598(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
974 u32 rar_entries = hw->mac.num_rar_entries;
976 UNREFERENCED_1PARAMETER(vmdq);
978 /* Make sure we are using a valid rar index range */
979 if (rar >= rar_entries) {
980 DEBUGOUT1("RAR index %d is out of range.\n", rar);
981 return IXGBE_ERR_INVALID_ARGUMENT;
984 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
985 if (rar_high & IXGBE_RAH_VIND_MASK) {
986 rar_high &= ~IXGBE_RAH_VIND_MASK;
987 IXGBE_WRITE_REG(hw, IXGBE_RAH(rar), rar_high);
990 return IXGBE_SUCCESS;
994 * ixgbe_set_vfta_82598 - Set VLAN filter table
995 * @hw: pointer to hardware structure
996 * @vlan: VLAN id to write to VLAN filter
997 * @vind: VMDq output index that maps queue to VLAN id in VFTA
998 * @vlan_on: boolean flag to turn on/off VLAN in VFTA
1000 * Turn on/off specified VLAN in the VLAN filter table.
1002 s32 ixgbe_set_vfta_82598(struct ixgbe_hw *hw, u32 vlan, u32 vind,
1010 DEBUGFUNC("ixgbe_set_vfta_82598");
1013 return IXGBE_ERR_PARAM;
1015 /* Determine 32-bit word position in array */
1016 regindex = (vlan >> 5) & 0x7F; /* upper seven bits */
1018 /* Determine the location of the (VMD) queue index */
1019 vftabyte = ((vlan >> 3) & 0x03); /* bits (4:3) indicating byte array */
1020 bitindex = (vlan & 0x7) << 2; /* lower 3 bits indicate nibble */
1022 /* Set the nibble for VMD queue index */
1023 bits = IXGBE_READ_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex));
1024 bits &= (~(0x0F << bitindex));
1025 bits |= (vind << bitindex);
1026 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vftabyte, regindex), bits);
1028 /* Determine the location of the bit for this VLAN id */
1029 bitindex = vlan & 0x1F; /* lower five bits */
1031 bits = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
1033 /* Turn on this VLAN id */
1034 bits |= (1 << bitindex);
1036 /* Turn off this VLAN id */
1037 bits &= ~(1 << bitindex);
1038 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), bits);
1040 return IXGBE_SUCCESS;
1044 * ixgbe_clear_vfta_82598 - Clear VLAN filter table
1045 * @hw: pointer to hardware structure
1047 * Clears the VLAN filer table, and the VMDq index associated with the filter
1049 STATIC s32 ixgbe_clear_vfta_82598(struct ixgbe_hw *hw)
1054 DEBUGFUNC("ixgbe_clear_vfta_82598");
1056 for (offset = 0; offset < hw->mac.vft_size; offset++)
1057 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
1059 for (vlanbyte = 0; vlanbyte < 4; vlanbyte++)
1060 for (offset = 0; offset < hw->mac.vft_size; offset++)
1061 IXGBE_WRITE_REG(hw, IXGBE_VFTAVIND(vlanbyte, offset),
1064 return IXGBE_SUCCESS;
1068 * ixgbe_read_analog_reg8_82598 - Reads 8 bit Atlas analog register
1069 * @hw: pointer to hardware structure
1070 * @reg: analog register to read
1073 * Performs read operation to Atlas analog register specified.
1075 s32 ixgbe_read_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 *val)
1079 DEBUGFUNC("ixgbe_read_analog_reg8_82598");
1081 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL,
1082 IXGBE_ATLASCTL_WRITE_CMD | (reg << 8));
1083 IXGBE_WRITE_FLUSH(hw);
1085 atlas_ctl = IXGBE_READ_REG(hw, IXGBE_ATLASCTL);
1086 *val = (u8)atlas_ctl;
1088 return IXGBE_SUCCESS;
1092 * ixgbe_write_analog_reg8_82598 - Writes 8 bit Atlas analog register
1093 * @hw: pointer to hardware structure
1094 * @reg: atlas register to write
1095 * @val: value to write
1097 * Performs write operation to Atlas analog register specified.
1099 s32 ixgbe_write_analog_reg8_82598(struct ixgbe_hw *hw, u32 reg, u8 val)
1103 DEBUGFUNC("ixgbe_write_analog_reg8_82598");
1105 atlas_ctl = (reg << 8) | val;
1106 IXGBE_WRITE_REG(hw, IXGBE_ATLASCTL, atlas_ctl);
1107 IXGBE_WRITE_FLUSH(hw);
1110 return IXGBE_SUCCESS;
1114 * ixgbe_read_i2c_eeprom_82598 - Reads 8 bit word over I2C interface.
1115 * @hw: pointer to hardware structure
1116 * @byte_offset: EEPROM byte offset to read
1117 * @eeprom_data: value read
1119 * Performs 8 byte read operation to SFP module's EEPROM over I2C interface.
1121 s32 ixgbe_read_i2c_eeprom_82598(struct ixgbe_hw *hw, u8 byte_offset,
1124 s32 status = IXGBE_SUCCESS;
1130 DEBUGFUNC("ixgbe_read_i2c_eeprom_82598");
1132 if (hw->phy.type == ixgbe_phy_nl) {
1134 * NetLogic phy SDA/SCL registers are at addresses 0xC30A to
1135 * 0xC30D. These registers are used to talk to the SFP+
1136 * module's EEPROM through the SDA/SCL (I2C) interface.
1138 sfp_addr = (IXGBE_I2C_EEPROM_DEV_ADDR << 8) + byte_offset;
1139 sfp_addr = (sfp_addr | IXGBE_I2C_EEPROM_READ_MASK);
1140 hw->phy.ops.write_reg(hw,
1141 IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR,
1142 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1146 for (i = 0; i < 100; i++) {
1147 hw->phy.ops.read_reg(hw,
1148 IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT,
1149 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
1151 sfp_stat = sfp_stat & IXGBE_I2C_EEPROM_STATUS_MASK;
1152 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS)
1157 if (sfp_stat != IXGBE_I2C_EEPROM_STATUS_PASS) {
1158 DEBUGOUT("EEPROM read did not pass.\n");
1159 status = IXGBE_ERR_SFP_NOT_PRESENT;
1164 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA,
1165 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &sfp_data);
1167 *eeprom_data = (u8)(sfp_data >> 8);
1169 status = IXGBE_ERR_PHY;
1178 * ixgbe_get_supported_physical_layer_82598 - Returns physical layer type
1179 * @hw: pointer to hardware structure
1181 * Determines physical layer capabilities of the current configuration.
1183 u32 ixgbe_get_supported_physical_layer_82598(struct ixgbe_hw *hw)
1185 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1186 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1187 u32 pma_pmd_10g = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1188 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1189 u16 ext_ability = 0;
1191 DEBUGFUNC("ixgbe_get_supported_physical_layer_82598");
1193 hw->phy.ops.identify(hw);
1195 /* Copper PHY must be checked before AUTOC LMS to determine correct
1196 * physical layer because 10GBase-T PHYs use LMS = KX4/KX */
1197 switch (hw->phy.type) {
1199 case ixgbe_phy_cu_unknown:
1200 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1201 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1202 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1203 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1204 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1205 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1206 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1207 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1213 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1214 case IXGBE_AUTOC_LMS_1G_AN:
1215 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1216 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX)
1217 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1219 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_BX;
1221 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
1222 if (pma_pmd_10g == IXGBE_AUTOC_10G_CX4)
1223 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
1224 else if (pma_pmd_10g == IXGBE_AUTOC_10G_KX4)
1225 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1227 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1229 case IXGBE_AUTOC_LMS_KX4_AN:
1230 case IXGBE_AUTOC_LMS_KX4_AN_1G_AN:
1231 if (autoc & IXGBE_AUTOC_KX_SUPP)
1232 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
1233 if (autoc & IXGBE_AUTOC_KX4_SUPP)
1234 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
1240 if (hw->phy.type == ixgbe_phy_nl) {
1241 hw->phy.ops.identify_sfp(hw);
1243 switch (hw->phy.sfp_type) {
1244 case ixgbe_sfp_type_da_cu:
1245 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1247 case ixgbe_sfp_type_sr:
1248 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1250 case ixgbe_sfp_type_lr:
1251 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1254 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1259 switch (hw->device_id) {
1260 case IXGBE_DEV_ID_82598_DA_DUAL_PORT:
1261 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1263 case IXGBE_DEV_ID_82598AF_DUAL_PORT:
1264 case IXGBE_DEV_ID_82598AF_SINGLE_PORT:
1265 case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM:
1266 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1268 case IXGBE_DEV_ID_82598EB_XF_LR:
1269 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1276 return physical_layer;
1280 * ixgbe_set_lan_id_multi_port_pcie_82598 - Set LAN id for PCIe multiple
1282 * @hw: pointer to the HW structure
1284 * Calls common function and corrects issue with some single port devices
1285 * that enable LAN1 but not LAN0.
1287 void ixgbe_set_lan_id_multi_port_pcie_82598(struct ixgbe_hw *hw)
1289 struct ixgbe_bus_info *bus = &hw->bus;
1293 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie_82598");
1295 ixgbe_set_lan_id_multi_port_pcie(hw);
1297 /* check if LAN0 is disabled */
1298 hw->eeprom.ops.read(hw, IXGBE_PCIE_GENERAL_PTR, &pci_gen);
1299 if ((pci_gen != 0) && (pci_gen != 0xFFFF)) {
1301 hw->eeprom.ops.read(hw, pci_gen + IXGBE_PCIE_CTRL2, &pci_ctrl2);
1303 /* if LAN0 is completely disabled force function to 0 */
1304 if ((pci_ctrl2 & IXGBE_PCIE_CTRL2_LAN_DISABLE) &&
1305 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DISABLE_SELECT) &&
1306 !(pci_ctrl2 & IXGBE_PCIE_CTRL2_DUMMY_ENABLE)) {
1314 * ixgbe_enable_relaxed_ordering_82598 - enable relaxed ordering
1315 * @hw: pointer to hardware structure
1318 void ixgbe_enable_relaxed_ordering_82598(struct ixgbe_hw *hw)
1323 DEBUGFUNC("ixgbe_enable_relaxed_ordering_82598");
1325 /* Enable relaxed ordering */
1326 for (i = 0; ((i < hw->mac.max_tx_queues) &&
1327 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1328 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(i));
1329 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
1330 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(i), regval);
1333 for (i = 0; ((i < hw->mac.max_rx_queues) &&
1334 (i < IXGBE_DCA_MAX_QUEUES_82598)); i++) {
1335 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
1336 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
1337 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
1338 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
1344 * ixgbe_set_rxpba_82598 - Initialize RX packet buffer
1345 * @hw: pointer to hardware structure
1346 * @num_pb: number of packet buffers to allocate
1347 * @headroom: reserve n KB of headroom
1348 * @strategy: packet buffer allocation strategy
1350 STATIC void ixgbe_set_rxpba_82598(struct ixgbe_hw *hw, int num_pb,
1351 u32 headroom, int strategy)
1353 u32 rxpktsize = IXGBE_RXPBSIZE_64KB;
1355 UNREFERENCED_1PARAMETER(headroom);
1360 /* Setup Rx packet buffer sizes */
1362 case PBA_STRATEGY_WEIGHTED:
1363 /* Setup the first four at 80KB */
1364 rxpktsize = IXGBE_RXPBSIZE_80KB;
1366 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1367 /* Setup the last four at 48KB...don't re-init i */
1368 rxpktsize = IXGBE_RXPBSIZE_48KB;
1370 case PBA_STRATEGY_EQUAL:
1372 /* Divide the remaining Rx packet buffer evenly among the TCs */
1373 for (; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1374 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
1378 /* Setup Tx packet buffer sizes */
1379 for (i = 0; i < IXGBE_MAX_PACKET_BUFFERS; i++)
1380 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), IXGBE_TXPBSIZE_40KB);