1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_api.h"
36 #include "ixgbe_common.h"
37 #include "ixgbe_phy.h"
39 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
40 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
41 ixgbe_link_speed *speed,
43 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
44 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
45 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
47 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
48 ixgbe_link_speed speed, bool autoneg,
49 bool autoneg_wait_to_complete);
50 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
51 ixgbe_link_speed speed, bool autoneg,
52 bool autoneg_wait_to_complete);
53 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
54 bool autoneg_wait_to_complete);
55 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
56 ixgbe_link_speed speed,
58 bool autoneg_wait_to_complete);
59 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
60 ixgbe_link_speed speed,
62 bool autoneg_wait_to_complete);
63 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw);
64 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw);
65 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
66 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
67 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
68 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
69 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
70 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw);
71 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
72 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);
73 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
74 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
75 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
76 u16 offset, u16 *data);
77 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
78 u16 words, u16 *data);
80 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
82 struct ixgbe_mac_info *mac = &hw->mac;
84 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
86 /* enable the laser control functions for SFP+ fiber */
87 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
88 mac->ops.disable_tx_laser =
89 &ixgbe_disable_tx_laser_multispeed_fiber;
90 mac->ops.enable_tx_laser =
91 &ixgbe_enable_tx_laser_multispeed_fiber;
92 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
95 mac->ops.disable_tx_laser = NULL;
96 mac->ops.enable_tx_laser = NULL;
97 mac->ops.flap_tx_laser = NULL;
100 if (hw->phy.multispeed_fiber) {
101 /* Set up dual speed SFP+ support */
102 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
104 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
105 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
106 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
107 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
108 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
110 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
116 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
117 * @hw: pointer to hardware structure
119 * Initialize any function pointers that were not able to be
120 * set during init_shared_code because the PHY/SFP type was
121 * not known. Perform the SFP init if necessary.
124 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
126 struct ixgbe_mac_info *mac = &hw->mac;
127 struct ixgbe_phy_info *phy = &hw->phy;
128 s32 ret_val = IXGBE_SUCCESS;
130 DEBUGFUNC("ixgbe_init_phy_ops_82599");
132 /* Identify the PHY or SFP module */
133 ret_val = phy->ops.identify(hw);
134 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
135 goto init_phy_ops_out;
137 /* Setup function pointers based on detected SFP module and speeds */
138 ixgbe_init_mac_link_ops_82599(hw);
139 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
140 hw->phy.ops.reset = NULL;
142 /* If copper media, overwrite with copper function pointers */
143 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
144 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
145 mac->ops.get_link_capabilities =
146 &ixgbe_get_copper_link_capabilities_generic;
149 /* Set necessary function pointers based on phy type */
150 switch (hw->phy.type) {
152 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
153 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
154 phy->ops.get_firmware_version =
155 &ixgbe_get_phy_firmware_version_tnx;
164 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
166 s32 ret_val = IXGBE_SUCCESS;
169 u16 list_offset, data_offset, data_value;
171 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
173 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
174 ixgbe_init_mac_link_ops_82599(hw);
176 hw->phy.ops.reset = NULL;
178 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
180 if (ret_val != IXGBE_SUCCESS)
183 /* PHY config will finish before releasing the semaphore */
184 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
185 IXGBE_GSSR_MAC_CSR_SM);
186 if (ret_val != IXGBE_SUCCESS) {
187 ret_val = IXGBE_ERR_SWFW_SYNC;
191 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
192 while (data_value != 0xffff) {
193 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
194 IXGBE_WRITE_FLUSH(hw);
195 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
198 /* Release the semaphore */
199 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
200 /* Delay obtaining semaphore again to allow FW access */
201 msec_delay(hw->eeprom.semaphore_delay);
203 /* Now restart DSP by setting Restart_AN and clearing LMS */
204 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
205 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
206 IXGBE_AUTOC_AN_RESTART));
208 /* Wait for AN to leave state 0 */
209 for (i = 0; i < 10; i++) {
211 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
212 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
215 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
216 DEBUGOUT("sfp module setup not complete\n");
217 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
221 /* Restart DSP by setting Restart_AN and return to SFI mode */
222 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
223 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
224 IXGBE_AUTOC_AN_RESTART));
232 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
233 * @hw: pointer to hardware structure
235 * Initialize the function pointers and assign the MAC type for 82599.
236 * Does not touch the hardware.
239 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
241 struct ixgbe_mac_info *mac = &hw->mac;
242 struct ixgbe_phy_info *phy = &hw->phy;
243 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
246 DEBUGFUNC("ixgbe_init_ops_82599");
248 ret_val = ixgbe_init_phy_ops_generic(hw);
249 ret_val = ixgbe_init_ops_generic(hw);
252 phy->ops.identify = &ixgbe_identify_phy_82599;
253 phy->ops.init = &ixgbe_init_phy_ops_82599;
256 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
257 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
258 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
259 mac->ops.get_supported_physical_layer =
260 &ixgbe_get_supported_physical_layer_82599;
261 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
262 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
263 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
264 mac->ops.start_hw = &ixgbe_start_hw_82599;
265 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
266 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
267 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
268 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
269 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
271 /* RAR, Multicast, VLAN */
272 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
273 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
274 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
275 mac->rar_highwater = 1;
276 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
277 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
278 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
279 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
280 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
281 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
284 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
285 mac->ops.check_link = &ixgbe_check_mac_link_generic;
286 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
287 ixgbe_init_mac_link_ops_82599(hw);
289 mac->mcft_size = 128;
291 mac->num_rar_entries = 128;
292 mac->rx_pb_size = 512;
293 mac->max_tx_queues = 128;
294 mac->max_rx_queues = 128;
295 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
297 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
298 IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE;
300 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
303 eeprom->ops.read = &ixgbe_read_eeprom_82599;
304 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
306 /* Manageability interface */
307 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
313 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
314 * @hw: pointer to hardware structure
315 * @speed: pointer to link speed
316 * @negotiation: TRUE when autoneg or autotry is enabled
318 * Determines the link capabilities by reading the AUTOC register.
320 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
321 ixgbe_link_speed *speed,
324 s32 status = IXGBE_SUCCESS;
327 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
330 /* Check if 1G SFP module. */
331 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
332 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
333 *speed = IXGBE_LINK_SPEED_1GB_FULL;
339 * Determine link capabilities based on the stored value of AUTOC,
340 * which represents EEPROM defaults. If AUTOC value has not
341 * been stored, use the current register values.
343 if (hw->mac.orig_link_settings_stored)
344 autoc = hw->mac.orig_autoc;
346 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
348 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
349 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
350 *speed = IXGBE_LINK_SPEED_1GB_FULL;
351 *negotiation = FALSE;
354 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
355 *speed = IXGBE_LINK_SPEED_10GB_FULL;
356 *negotiation = FALSE;
359 case IXGBE_AUTOC_LMS_1G_AN:
360 *speed = IXGBE_LINK_SPEED_1GB_FULL;
364 case IXGBE_AUTOC_LMS_10G_SERIAL:
365 *speed = IXGBE_LINK_SPEED_10GB_FULL;
366 *negotiation = FALSE;
369 case IXGBE_AUTOC_LMS_KX4_KX_KR:
370 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
371 *speed = IXGBE_LINK_SPEED_UNKNOWN;
372 if (autoc & IXGBE_AUTOC_KR_SUPP)
373 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
374 if (autoc & IXGBE_AUTOC_KX4_SUPP)
375 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
376 if (autoc & IXGBE_AUTOC_KX_SUPP)
377 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
381 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
382 *speed = IXGBE_LINK_SPEED_100_FULL;
383 if (autoc & IXGBE_AUTOC_KR_SUPP)
384 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
385 if (autoc & IXGBE_AUTOC_KX4_SUPP)
386 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
387 if (autoc & IXGBE_AUTOC_KX_SUPP)
388 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
392 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
393 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
394 *negotiation = FALSE;
398 status = IXGBE_ERR_LINK_SETUP;
403 if (hw->phy.multispeed_fiber) {
404 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
405 IXGBE_LINK_SPEED_1GB_FULL;
414 * ixgbe_get_media_type_82599 - Get media type
415 * @hw: pointer to hardware structure
417 * Returns the media type (fiber, copper, backplane)
419 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
421 enum ixgbe_media_type media_type;
423 DEBUGFUNC("ixgbe_get_media_type_82599");
425 /* Detect if there is a copper PHY attached. */
426 switch (hw->phy.type) {
427 case ixgbe_phy_cu_unknown:
429 media_type = ixgbe_media_type_copper;
435 switch (hw->device_id) {
436 case IXGBE_DEV_ID_82599_KX4:
437 case IXGBE_DEV_ID_82599_KX4_MEZZ:
438 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
439 case IXGBE_DEV_ID_82599_KR:
440 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
441 case IXGBE_DEV_ID_82599_XAUI_LOM:
442 /* Default device ID is mezzanine card KX/KX4 */
443 media_type = ixgbe_media_type_backplane;
445 case IXGBE_DEV_ID_82599_SFP:
446 case IXGBE_DEV_ID_82599_SFP_FCOE:
447 case IXGBE_DEV_ID_82599_SFP_EM:
448 case IXGBE_DEV_ID_82599EN_SFP:
449 media_type = ixgbe_media_type_fiber;
451 case IXGBE_DEV_ID_82599_CX4:
452 media_type = ixgbe_media_type_cx4;
454 case IXGBE_DEV_ID_82599_T3_LOM:
455 media_type = ixgbe_media_type_copper;
458 media_type = ixgbe_media_type_unknown;
466 * ixgbe_start_mac_link_82599 - Setup MAC link settings
467 * @hw: pointer to hardware structure
468 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
470 * Configures link settings based on values in the ixgbe_hw struct.
471 * Restarts the link. Performs autonegotiation if needed.
473 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
474 bool autoneg_wait_to_complete)
479 s32 status = IXGBE_SUCCESS;
481 DEBUGFUNC("ixgbe_start_mac_link_82599");
485 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
486 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
487 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
489 /* Only poll for autoneg to complete if specified to do so */
490 if (autoneg_wait_to_complete) {
491 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
492 IXGBE_AUTOC_LMS_KX4_KX_KR ||
493 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
494 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
495 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
496 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
497 links_reg = 0; /* Just in case Autoneg time = 0 */
498 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
499 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
500 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
504 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
505 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
506 DEBUGOUT("Autoneg did not complete.\n");
511 /* Add delay to filter out noises during initial link setup */
518 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
519 * @hw: pointer to hardware structure
521 * The base drivers may require better control over SFP+ module
522 * PHY states. This includes selectively shutting down the Tx
523 * laser on the PHY, effectively halting physical link.
525 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
527 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
529 /* Disable tx laser; allow 100us to go dark per spec */
530 esdp_reg |= IXGBE_ESDP_SDP3;
531 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
532 IXGBE_WRITE_FLUSH(hw);
537 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
538 * @hw: pointer to hardware structure
540 * The base drivers may require better control over SFP+ module
541 * PHY states. This includes selectively turning on the Tx
542 * laser on the PHY, effectively starting physical link.
544 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
546 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
548 /* Enable tx laser; allow 100ms to light up */
549 esdp_reg &= ~IXGBE_ESDP_SDP3;
550 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
551 IXGBE_WRITE_FLUSH(hw);
556 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
557 * @hw: pointer to hardware structure
559 * When the driver changes the link speeds that it can support,
560 * it sets autotry_restart to TRUE to indicate that we need to
561 * initiate a new autotry session with the link partner. To do
562 * so, we set the speed then disable and re-enable the tx laser, to
563 * alert the link partner that it also needs to restart autotry on its
564 * end. This is consistent with TRUE clause 37 autoneg, which also
565 * involves a loss of signal.
567 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
569 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
571 if (hw->mac.autotry_restart) {
572 ixgbe_disable_tx_laser_multispeed_fiber(hw);
573 ixgbe_enable_tx_laser_multispeed_fiber(hw);
574 hw->mac.autotry_restart = FALSE;
579 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
580 * @hw: pointer to hardware structure
581 * @speed: new link speed
582 * @autoneg: TRUE if autonegotiation enabled
583 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
585 * Set the link speed in the AUTOC register and restarts link.
587 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
588 ixgbe_link_speed speed, bool autoneg,
589 bool autoneg_wait_to_complete)
591 s32 status = IXGBE_SUCCESS;
592 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
593 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
595 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
597 bool link_up = FALSE;
600 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
602 /* Mask off requested but non-supported speeds */
603 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);
604 if (status != IXGBE_SUCCESS)
610 * Try each speed one by one, highest priority first. We do this in
611 * software because 10gb fiber doesn't support speed autonegotiation.
613 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
615 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
617 /* If we already have link at this speed, just jump out */
618 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
619 if (status != IXGBE_SUCCESS)
622 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
625 /* Set the module link speed */
626 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
627 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
628 IXGBE_WRITE_FLUSH(hw);
630 /* Allow module to change analog characteristics (1G->10G) */
633 status = ixgbe_setup_mac_link_82599(hw,
634 IXGBE_LINK_SPEED_10GB_FULL,
636 autoneg_wait_to_complete);
637 if (status != IXGBE_SUCCESS)
640 /* Flap the tx laser if it has not already been done */
641 ixgbe_flap_tx_laser(hw);
644 * Wait for the controller to acquire link. Per IEEE 802.3ap,
645 * Section 73.10.2, we may have to wait up to 500ms if KR is
646 * attempted. 82599 uses the same timing for 10g SFI.
648 for (i = 0; i < 5; i++) {
649 /* Wait for the link partner to also set speed */
652 /* If we have link, just jump out */
653 status = ixgbe_check_link(hw, &link_speed,
655 if (status != IXGBE_SUCCESS)
663 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
665 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
666 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
668 /* If we already have link at this speed, just jump out */
669 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
670 if (status != IXGBE_SUCCESS)
673 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
676 /* Set the module link speed */
677 esdp_reg &= ~IXGBE_ESDP_SDP5;
678 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
679 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
680 IXGBE_WRITE_FLUSH(hw);
682 /* Allow module to change analog characteristics (10G->1G) */
685 status = ixgbe_setup_mac_link_82599(hw,
686 IXGBE_LINK_SPEED_1GB_FULL,
688 autoneg_wait_to_complete);
689 if (status != IXGBE_SUCCESS)
692 /* Flap the tx laser if it has not already been done */
693 ixgbe_flap_tx_laser(hw);
695 /* Wait for the link partner to also set speed */
698 /* If we have link, just jump out */
699 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
700 if (status != IXGBE_SUCCESS)
708 * We didn't get link. Configure back to the highest speed we tried,
709 * (if there was more than one). We call ourselves back with just the
710 * single highest speed that the user requested.
713 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
714 highest_link_speed, autoneg, autoneg_wait_to_complete);
717 /* Set autoneg_advertised value based on input link speed */
718 hw->phy.autoneg_advertised = 0;
720 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
721 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
723 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
724 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
730 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
731 * @hw: pointer to hardware structure
732 * @speed: new link speed
733 * @autoneg: TRUE if autonegotiation enabled
734 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
736 * Implements the Intel SmartSpeed algorithm.
738 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
739 ixgbe_link_speed speed, bool autoneg,
740 bool autoneg_wait_to_complete)
742 s32 status = IXGBE_SUCCESS;
743 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
745 bool link_up = FALSE;
746 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
748 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
750 /* Set autoneg_advertised value based on input link speed */
751 hw->phy.autoneg_advertised = 0;
753 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
754 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
756 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
757 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
759 if (speed & IXGBE_LINK_SPEED_100_FULL)
760 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
763 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
764 * autoneg advertisement if link is unable to be established at the
765 * highest negotiated rate. This can sometimes happen due to integrity
766 * issues with the physical media connection.
769 /* First, try to get link with full advertisement */
770 hw->phy.smart_speed_active = FALSE;
771 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
772 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
773 autoneg_wait_to_complete);
774 if (status != IXGBE_SUCCESS)
778 * Wait for the controller to acquire link. Per IEEE 802.3ap,
779 * Section 73.10.2, we may have to wait up to 500ms if KR is
780 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
781 * Table 9 in the AN MAS.
783 for (i = 0; i < 5; i++) {
786 /* If we have link, just jump out */
787 status = ixgbe_check_link(hw, &link_speed, &link_up,
789 if (status != IXGBE_SUCCESS)
798 * We didn't get link. If we advertised KR plus one of KX4/KX
799 * (or BX4/BX), then disable KR and try again.
801 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
802 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
805 /* Turn SmartSpeed on to disable KR support */
806 hw->phy.smart_speed_active = TRUE;
807 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
808 autoneg_wait_to_complete);
809 if (status != IXGBE_SUCCESS)
813 * Wait for the controller to acquire link. 600ms will allow for
814 * the AN link_fail_inhibit_timer as well for multiple cycles of
815 * parallel detect, both 10g and 1g. This allows for the maximum
816 * connect attempts as defined in the AN MAS table 73-7.
818 for (i = 0; i < 6; i++) {
821 /* If we have link, just jump out */
822 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
823 if (status != IXGBE_SUCCESS)
830 /* We didn't get link. Turn SmartSpeed back off. */
831 hw->phy.smart_speed_active = FALSE;
832 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
833 autoneg_wait_to_complete);
836 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
837 DEBUGOUT("Smartspeed has downgraded the link speed "
838 "from the maximum advertised\n");
843 * ixgbe_setup_mac_link_82599 - Set MAC link speed
844 * @hw: pointer to hardware structure
845 * @speed: new link speed
846 * @autoneg: TRUE if autonegotiation enabled
847 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
849 * Set the link speed in the AUTOC register and restarts link.
851 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
852 ixgbe_link_speed speed, bool autoneg,
853 bool autoneg_wait_to_complete)
855 s32 status = IXGBE_SUCCESS;
856 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
857 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
858 u32 start_autoc = autoc;
860 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
861 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
862 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
865 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
867 DEBUGFUNC("ixgbe_setup_mac_link_82599");
869 /* Check to see if speed passed in is supported. */
870 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
871 if (status != IXGBE_SUCCESS)
874 speed &= link_capabilities;
876 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
877 status = IXGBE_ERR_LINK_SETUP;
881 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
882 if (hw->mac.orig_link_settings_stored)
883 orig_autoc = hw->mac.orig_autoc;
887 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
888 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
889 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
890 /* Set KX4/KX/KR support according to speed requested */
891 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
892 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
893 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
894 autoc |= IXGBE_AUTOC_KX4_SUPP;
895 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
896 (hw->phy.smart_speed_active == FALSE))
897 autoc |= IXGBE_AUTOC_KR_SUPP;
898 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
899 autoc |= IXGBE_AUTOC_KX_SUPP;
900 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
901 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
902 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
903 /* Switch from 1G SFI to 10G SFI if requested */
904 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
905 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
906 autoc &= ~IXGBE_AUTOC_LMS_MASK;
907 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
909 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
910 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
911 /* Switch from 10G SFI to 1G SFI if requested */
912 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
913 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
914 autoc &= ~IXGBE_AUTOC_LMS_MASK;
916 autoc |= IXGBE_AUTOC_LMS_1G_AN;
918 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
922 if (autoc != start_autoc) {
924 autoc |= IXGBE_AUTOC_AN_RESTART;
925 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
927 /* Only poll for autoneg to complete if specified to do so */
928 if (autoneg_wait_to_complete) {
929 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
930 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
931 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
932 links_reg = 0; /*Just in case Autoneg time=0*/
933 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
935 IXGBE_READ_REG(hw, IXGBE_LINKS);
936 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
940 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
942 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
943 DEBUGOUT("Autoneg did not complete.\n");
948 /* Add delay to filter out noises during initial link setup */
957 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
958 * @hw: pointer to hardware structure
959 * @speed: new link speed
960 * @autoneg: TRUE if autonegotiation enabled
961 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
963 * Restarts link on PHY and MAC based on settings passed in.
965 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
966 ixgbe_link_speed speed,
968 bool autoneg_wait_to_complete)
972 DEBUGFUNC("ixgbe_setup_copper_link_82599");
974 /* Setup the PHY according to input speed */
975 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
976 autoneg_wait_to_complete);
978 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
984 * ixgbe_reset_hw_82599 - Perform hardware reset
985 * @hw: pointer to hardware structure
987 * Resets the hardware by resetting the transmit and receive units, masks
988 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
991 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
993 ixgbe_link_speed link_speed;
995 u32 ctrl, i, autoc, autoc2;
996 bool link_up = FALSE;
998 DEBUGFUNC("ixgbe_reset_hw_82599");
1000 /* Call adapter stop to disable tx/rx and clear interrupts */
1001 status = hw->mac.ops.stop_adapter(hw);
1002 if (status != IXGBE_SUCCESS)
1005 /* flush pending Tx transactions */
1006 ixgbe_clear_tx_pending(hw);
1008 /* PHY ops must be identified and initialized prior to reset */
1010 /* Identify PHY and related function pointers */
1011 status = hw->phy.ops.init(hw);
1013 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1016 /* Setup SFP module if there is one present. */
1017 if (hw->phy.sfp_setup_needed) {
1018 status = hw->mac.ops.setup_sfp(hw);
1019 hw->phy.sfp_setup_needed = FALSE;
1022 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1026 if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL)
1027 hw->phy.ops.reset(hw);
1031 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1032 * If link reset is used when link is up, it might reset the PHY when
1033 * mng is using it. If link is down or the flag to force full link
1034 * reset is set, then perform link reset.
1036 ctrl = IXGBE_CTRL_LNK_RST;
1037 if (!hw->force_full_reset) {
1038 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
1040 ctrl = IXGBE_CTRL_RST;
1043 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1044 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1045 IXGBE_WRITE_FLUSH(hw);
1047 /* Poll for reset bit to self-clear indicating reset is complete */
1048 for (i = 0; i < 10; i++) {
1050 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1051 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1055 if (ctrl & IXGBE_CTRL_RST_MASK) {
1056 status = IXGBE_ERR_RESET_FAILED;
1057 DEBUGOUT("Reset polling failed to complete.\n");
1063 * Double resets are required for recovery from certain error
1064 * conditions. Between resets, it is necessary to stall to allow time
1065 * for any pending HW events to complete.
1067 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1068 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1073 * Store the original AUTOC/AUTOC2 values if they have not been
1074 * stored off yet. Otherwise restore the stored original
1075 * values since the reset operation sets back to defaults.
1077 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1078 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1079 if (hw->mac.orig_link_settings_stored == FALSE) {
1080 hw->mac.orig_autoc = autoc;
1081 hw->mac.orig_autoc2 = autoc2;
1082 hw->mac.orig_link_settings_stored = TRUE;
1084 if (autoc != hw->mac.orig_autoc)
1085 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
1086 IXGBE_AUTOC_AN_RESTART));
1088 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1089 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1090 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1091 autoc2 |= (hw->mac.orig_autoc2 &
1092 IXGBE_AUTOC2_UPPER_MASK);
1093 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1097 /* Store the permanent mac address */
1098 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1101 * Store MAC address from RAR0, clear receive address registers, and
1102 * clear the multicast table. Also reset num_rar_entries to 128,
1103 * since we modify this value when programming the SAN MAC address.
1105 hw->mac.num_rar_entries = 128;
1106 hw->mac.ops.init_rx_addrs(hw);
1108 /* Store the permanent SAN mac address */
1109 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1111 /* Add the SAN MAC address to the RAR only if it's a valid address */
1112 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1113 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1114 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1116 /* Reserve the last RAR for the SAN MAC address */
1117 hw->mac.num_rar_entries--;
1120 /* Store the alternative WWNN/WWPN prefix */
1121 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1122 &hw->mac.wwpn_prefix);
1129 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1130 * @hw: pointer to hardware structure
1132 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1135 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1136 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1138 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1141 * Before starting reinitialization process,
1142 * FDIRCMD.CMD must be zero.
1144 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1145 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1146 IXGBE_FDIRCMD_CMD_MASK))
1150 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1151 DEBUGOUT("Flow Director previous command isn't complete, "
1152 "aborting table re-initialization. \n");
1153 return IXGBE_ERR_FDIR_REINIT_FAILED;
1156 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1157 IXGBE_WRITE_FLUSH(hw);
1159 * 82599 adapters flow director init flow cannot be restarted,
1160 * Workaround 82599 silicon errata by performing the following steps
1161 * before re-writing the FDIRCTRL control register with the same value.
1162 * - write 1 to bit 8 of FDIRCMD register &
1163 * - write 0 to bit 8 of FDIRCMD register
1165 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1166 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1167 IXGBE_FDIRCMD_CLEARHT));
1168 IXGBE_WRITE_FLUSH(hw);
1169 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1170 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1171 ~IXGBE_FDIRCMD_CLEARHT));
1172 IXGBE_WRITE_FLUSH(hw);
1174 * Clear FDIR Hash register to clear any leftover hashes
1175 * waiting to be programmed.
1177 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1178 IXGBE_WRITE_FLUSH(hw);
1180 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1181 IXGBE_WRITE_FLUSH(hw);
1183 /* Poll init-done after we write FDIRCTRL register */
1184 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1185 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1186 IXGBE_FDIRCTRL_INIT_DONE)
1190 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1191 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1192 return IXGBE_ERR_FDIR_REINIT_FAILED;
1195 /* Clear FDIR statistics registers (read to clear) */
1196 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1197 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1198 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1199 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1200 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1202 return IXGBE_SUCCESS;
1206 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1207 * @hw: pointer to hardware structure
1208 * @fdirctrl: value to write to flow director control register
1210 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1214 DEBUGFUNC("ixgbe_fdir_enable_82599");
1216 /* Prime the keys for hashing */
1217 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1218 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1221 * Poll init-done after we write the register. Estimated times:
1222 * 10G: PBALLOC = 11b, timing is 60us
1223 * 1G: PBALLOC = 11b, timing is 600us
1224 * 100M: PBALLOC = 11b, timing is 6ms
1226 * Multiple these timings by 4 if under full Rx load
1228 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1229 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1230 * this might not finish in our poll time, but we can live with that
1233 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1234 IXGBE_WRITE_FLUSH(hw);
1235 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1236 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1237 IXGBE_FDIRCTRL_INIT_DONE)
1242 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1243 DEBUGOUT("Flow Director poll time exceeded!\n");
1247 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1248 * @hw: pointer to hardware structure
1249 * @fdirctrl: value to write to flow director control register, initially
1250 * contains just the value of the Rx packet buffer allocation
1252 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1254 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1257 * Continue setup of fdirctrl register bits:
1258 * Move the flexible bytes to use the ethertype - shift 6 words
1259 * Set the maximum length per hash bucket to 0xA filters
1260 * Send interrupt when 64 filters are left
1262 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1263 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1264 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1266 /* write hashes and fdirctrl register, poll for completion */
1267 ixgbe_fdir_enable_82599(hw, fdirctrl);
1269 return IXGBE_SUCCESS;
1273 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1274 * @hw: pointer to hardware structure
1275 * @fdirctrl: value to write to flow director control register, initially
1276 * contains just the value of the Rx packet buffer allocation
1278 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1280 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1283 * Continue setup of fdirctrl register bits:
1284 * Turn perfect match filtering on
1285 * Report hash in RSS field of Rx wb descriptor
1286 * Initialize the drop queue
1287 * Move the flexible bytes to use the ethertype - shift 6 words
1288 * Set the maximum length per hash bucket to 0xA filters
1289 * Send interrupt when 64 (0x4 * 16) filters are left
1291 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1292 IXGBE_FDIRCTRL_REPORT_STATUS |
1293 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1294 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1295 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1296 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1298 /* write hashes and fdirctrl register, poll for completion */
1299 ixgbe_fdir_enable_82599(hw, fdirctrl);
1301 return IXGBE_SUCCESS;
1305 * These defines allow us to quickly generate all of the necessary instructions
1306 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1307 * for values 0 through 15
1309 #define IXGBE_ATR_COMMON_HASH_KEY \
1310 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1311 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1314 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1315 common_hash ^= lo_hash_dword >> n; \
1316 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1317 bucket_hash ^= lo_hash_dword >> n; \
1318 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1319 sig_hash ^= lo_hash_dword << (16 - n); \
1320 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1321 common_hash ^= hi_hash_dword >> n; \
1322 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1323 bucket_hash ^= hi_hash_dword >> n; \
1324 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1325 sig_hash ^= hi_hash_dword << (16 - n); \
1329 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1330 * @stream: input bitstream to compute the hash on
1332 * This function is almost identical to the function above but contains
1333 * several optomizations such as unwinding all of the loops, letting the
1334 * compiler work out all of the conditional ifs since the keys are static
1335 * defines, and computing two keys at once since the hashed dword stream
1336 * will be the same for both keys.
1338 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1339 union ixgbe_atr_hash_dword common)
1341 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1342 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1344 /* record the flow_vm_vlan bits as they are a key part to the hash */
1345 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1347 /* generate common hash dword */
1348 hi_hash_dword = IXGBE_NTOHL(common.dword);
1350 /* low dword is word swapped version of common */
1351 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1353 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1354 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1356 /* Process bits 0 and 16 */
1357 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1360 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1361 * delay this because bit 0 of the stream should not be processed
1362 * so we do not add the vlan until after bit 0 was processed
1364 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1366 /* Process remaining 30 bit of the key */
1367 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1368 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1369 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1370 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1371 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1372 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1373 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1374 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1375 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1376 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1377 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1378 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1379 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1380 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1381 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1383 /* combine common_hash result with signature and bucket hashes */
1384 bucket_hash ^= common_hash;
1385 bucket_hash &= IXGBE_ATR_HASH_MASK;
1387 sig_hash ^= common_hash << 16;
1388 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1390 /* return completed signature hash */
1391 return sig_hash ^ bucket_hash;
1395 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1396 * @hw: pointer to hardware structure
1397 * @input: unique input dword
1398 * @common: compressed common input dword
1399 * @queue: queue index to direct traffic to
1401 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1402 union ixgbe_atr_hash_dword input,
1403 union ixgbe_atr_hash_dword common,
1409 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1412 * Get the flow_type in order to program FDIRCMD properly
1413 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1415 switch (input.formatted.flow_type) {
1416 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1417 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1418 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1419 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1420 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1421 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1424 DEBUGOUT(" Error on flow type input\n");
1425 return IXGBE_ERR_CONFIG;
1428 /* configure FDIRCMD register */
1429 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1430 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1431 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1432 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1435 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1436 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1438 fdirhashcmd = (u64)fdircmd << 32;
1439 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1440 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1442 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1444 return IXGBE_SUCCESS;
1447 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1450 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1451 bucket_hash ^= lo_hash_dword >> n; \
1452 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1453 bucket_hash ^= hi_hash_dword >> n; \
1457 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1458 * @atr_input: input bitstream to compute the hash on
1459 * @input_mask: mask for the input bitstream
1461 * This function serves two main purposes. First it applys the input_mask
1462 * to the atr_input resulting in a cleaned up atr_input data stream.
1463 * Secondly it computes the hash and stores it in the bkt_hash field at
1464 * the end of the input byte stream. This way it will be available for
1465 * future use without needing to recompute the hash.
1467 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1468 union ixgbe_atr_input *input_mask)
1471 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1472 u32 bucket_hash = 0;
1474 /* Apply masks to input data */
1475 input->dword_stream[0] &= input_mask->dword_stream[0];
1476 input->dword_stream[1] &= input_mask->dword_stream[1];
1477 input->dword_stream[2] &= input_mask->dword_stream[2];
1478 input->dword_stream[3] &= input_mask->dword_stream[3];
1479 input->dword_stream[4] &= input_mask->dword_stream[4];
1480 input->dword_stream[5] &= input_mask->dword_stream[5];
1481 input->dword_stream[6] &= input_mask->dword_stream[6];
1482 input->dword_stream[7] &= input_mask->dword_stream[7];
1483 input->dword_stream[8] &= input_mask->dword_stream[8];
1484 input->dword_stream[9] &= input_mask->dword_stream[9];
1485 input->dword_stream[10] &= input_mask->dword_stream[10];
1487 /* record the flow_vm_vlan bits as they are a key part to the hash */
1488 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1490 /* generate common hash dword */
1491 hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
1492 input->dword_stream[2] ^
1493 input->dword_stream[3] ^
1494 input->dword_stream[4] ^
1495 input->dword_stream[5] ^
1496 input->dword_stream[6] ^
1497 input->dword_stream[7] ^
1498 input->dword_stream[8] ^
1499 input->dword_stream[9] ^
1500 input->dword_stream[10]);
1502 /* low dword is word swapped version of common */
1503 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1505 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1506 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1508 /* Process bits 0 and 16 */
1509 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1512 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1513 * delay this because bit 0 of the stream should not be processed
1514 * so we do not add the vlan until after bit 0 was processed
1516 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1518 /* Process remaining 30 bit of the key */
1519 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1520 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1521 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1522 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1523 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1524 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1525 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1526 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1527 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1528 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1529 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1530 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1531 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1532 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1533 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1536 * Limit hash to 13 bits since max bucket count is 8K.
1537 * Store result at the end of the input stream.
1539 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1543 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1544 * @input_mask: mask to be bit swapped
1546 * The source and destination port masks for flow director are bit swapped
1547 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1548 * generate a correctly swapped value we need to bit swap the mask and that
1549 * is what is accomplished by this function.
1551 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1553 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1554 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1555 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1556 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1557 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1558 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1559 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1563 * These two macros are meant to address the fact that we have registers
1564 * that are either all or in part big-endian. As a result on big-endian
1565 * systems we will end up byte swapping the value to little-endian before
1566 * it is byte swapped again and written to the hardware in the original
1567 * big-endian format.
1569 #define IXGBE_STORE_AS_BE32(_value) \
1570 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1571 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1573 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1574 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1576 #define IXGBE_STORE_AS_BE16(_value) \
1577 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1579 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1580 union ixgbe_atr_input *input_mask)
1582 /* mask IPv6 since it is currently not supported */
1583 u32 fdirm = IXGBE_FDIRM_DIPv6;
1586 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1589 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1590 * are zero, then assume a full mask for that field. Also assume that
1591 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1592 * cannot be masked out in this implementation.
1594 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1598 /* verify bucket hash is cleared on hash generation */
1599 if (input_mask->formatted.bkt_hash) {
1600 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1603 /* Program FDIRM and verify partial masks */
1604 switch (input_mask->formatted.vm_pool & 0x7F) {
1606 fdirm |= IXGBE_FDIRM_POOL;
1610 DEBUGOUT(" Error on vm pool mask\n");
1611 return IXGBE_ERR_CONFIG;
1614 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1616 fdirm |= IXGBE_FDIRM_L4P;
1617 if (input_mask->formatted.dst_port ||
1618 input_mask->formatted.src_port) {
1619 DEBUGOUT(" Error on src/dst port mask\n");
1620 return IXGBE_ERR_CONFIG;
1622 case IXGBE_ATR_L4TYPE_MASK:
1625 DEBUGOUT(" Error on flow type mask\n");
1626 return IXGBE_ERR_CONFIG;
1629 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1631 /* mask VLAN ID, fall through to mask VLAN priority */
1632 fdirm |= IXGBE_FDIRM_VLANID;
1634 /* mask VLAN priority */
1635 fdirm |= IXGBE_FDIRM_VLANP;
1638 /* mask VLAN ID only, fall through */
1639 fdirm |= IXGBE_FDIRM_VLANID;
1641 /* no VLAN fields masked */
1644 DEBUGOUT(" Error on VLAN mask\n");
1645 return IXGBE_ERR_CONFIG;
1648 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1650 /* Mask Flex Bytes, fall through */
1651 fdirm |= IXGBE_FDIRM_FLEX;
1655 DEBUGOUT(" Error on flexible byte mask\n");
1656 return IXGBE_ERR_CONFIG;
1659 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1660 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1662 /* store the TCP/UDP port masks, bit reversed from port layout */
1663 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1665 /* write both the same so that UDP and TCP use the same mask */
1666 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1667 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1669 /* store source and destination IP masks (big-enian) */
1670 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1671 ~input_mask->formatted.src_ip[0]);
1672 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1673 ~input_mask->formatted.dst_ip[0]);
1675 return IXGBE_SUCCESS;
1678 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1679 union ixgbe_atr_input *input,
1680 u16 soft_id, u8 queue)
1682 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1684 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1686 /* currently IPv6 is not supported, must be programmed with 0 */
1687 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1688 input->formatted.src_ip[0]);
1689 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1690 input->formatted.src_ip[1]);
1691 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1692 input->formatted.src_ip[2]);
1694 /* record the source address (big-endian) */
1695 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1697 /* record the first 32 bits of the destination address (big-endian) */
1698 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1700 /* record source and destination port (little-endian)*/
1701 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1702 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1703 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1704 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1706 /* record vlan (little-endian) and flex_bytes(big-endian) */
1707 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1708 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1709 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1710 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1712 /* configure FDIRHASH register */
1713 fdirhash = input->formatted.bkt_hash;
1714 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1715 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1718 * flush all previous writes to make certain registers are
1719 * programmed prior to issuing the command
1721 IXGBE_WRITE_FLUSH(hw);
1723 /* configure FDIRCMD register */
1724 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1725 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1726 if (queue == IXGBE_FDIR_DROP_QUEUE)
1727 fdircmd |= IXGBE_FDIRCMD_DROP;
1728 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1729 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1730 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1732 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1734 return IXGBE_SUCCESS;
1737 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1738 union ixgbe_atr_input *input,
1744 s32 err = IXGBE_SUCCESS;
1746 /* configure FDIRHASH register */
1747 fdirhash = input->formatted.bkt_hash;
1748 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1749 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1751 /* flush hash to HW */
1752 IXGBE_WRITE_FLUSH(hw);
1754 /* Query if filter is present */
1755 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1757 for (retry_count = 10; retry_count; retry_count--) {
1758 /* allow 10us for query to process */
1760 /* verify query completed successfully */
1761 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1762 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1767 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1769 /* if filter exists in hardware then remove it */
1770 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1771 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1772 IXGBE_WRITE_FLUSH(hw);
1773 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1774 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1781 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1782 * @hw: pointer to hardware structure
1783 * @input: input bitstream
1784 * @input_mask: mask for the input bitstream
1785 * @soft_id: software index for the filters
1786 * @queue: queue index to direct traffic to
1788 * Note that the caller to this function must lock before calling, since the
1789 * hardware writes must be protected from one another.
1791 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1792 union ixgbe_atr_input *input,
1793 union ixgbe_atr_input *input_mask,
1794 u16 soft_id, u8 queue)
1796 s32 err = IXGBE_ERR_CONFIG;
1798 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1801 * Check flow_type formatting, and bail out before we touch the hardware
1802 * if there's a configuration issue
1804 switch (input->formatted.flow_type) {
1805 case IXGBE_ATR_FLOW_TYPE_IPV4:
1806 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1807 if (input->formatted.dst_port || input->formatted.src_port) {
1808 DEBUGOUT(" Error on src/dst port\n");
1809 return IXGBE_ERR_CONFIG;
1812 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1813 if (input->formatted.dst_port || input->formatted.src_port) {
1814 DEBUGOUT(" Error on src/dst port\n");
1815 return IXGBE_ERR_CONFIG;
1817 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1818 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1819 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
1820 IXGBE_ATR_L4TYPE_MASK;
1823 DEBUGOUT(" Error on flow type input\n");
1827 /* program input mask into the HW */
1828 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
1832 /* apply mask and compute/store hash */
1833 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
1835 /* program filters to filter memory */
1836 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
1841 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1842 * @hw: pointer to hardware structure
1843 * @reg: analog register to read
1846 * Performs read operation to Omer analog register specified.
1848 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1852 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
1854 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1856 IXGBE_WRITE_FLUSH(hw);
1858 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1859 *val = (u8)core_ctl;
1861 return IXGBE_SUCCESS;
1865 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1866 * @hw: pointer to hardware structure
1867 * @reg: atlas register to write
1868 * @val: value to write
1870 * Performs write operation to Omer analog register specified.
1872 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1876 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
1878 core_ctl = (reg << 8) | val;
1879 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1880 IXGBE_WRITE_FLUSH(hw);
1883 return IXGBE_SUCCESS;
1887 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1888 * @hw: pointer to hardware structure
1890 * Starts the hardware using the generic start_hw function
1891 * and the generation start_hw function.
1892 * Then performs revision-specific operations, if any.
1894 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1896 s32 ret_val = IXGBE_SUCCESS;
1898 DEBUGFUNC("ixgbe_start_hw_82599");
1900 ret_val = ixgbe_start_hw_generic(hw);
1901 if (ret_val != IXGBE_SUCCESS)
1904 ret_val = ixgbe_start_hw_gen2(hw);
1905 if (ret_val != IXGBE_SUCCESS)
1908 /* We need to run link autotry after the driver loads */
1909 hw->mac.autotry_restart = TRUE;
1911 if (ret_val == IXGBE_SUCCESS)
1912 ret_val = ixgbe_verify_fw_version_82599(hw);
1918 * ixgbe_identify_phy_82599 - Get physical layer module
1919 * @hw: pointer to hardware structure
1921 * Determines the physical layer module found on the current adapter.
1922 * If PHY already detected, maintains current PHY type in hw struct,
1923 * otherwise executes the PHY detection routine.
1925 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1927 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1929 DEBUGFUNC("ixgbe_identify_phy_82599");
1931 /* Detect PHY if not unknown - returns success if already detected. */
1932 status = ixgbe_identify_phy_generic(hw);
1933 if (status != IXGBE_SUCCESS) {
1934 /* 82599 10GBASE-T requires an external PHY */
1935 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1938 status = ixgbe_identify_sfp_module_generic(hw);
1941 /* Set PHY type none if no PHY detected */
1942 if (hw->phy.type == ixgbe_phy_unknown) {
1943 hw->phy.type = ixgbe_phy_none;
1944 status = IXGBE_SUCCESS;
1947 /* Return error if SFP module has been detected but is not supported */
1948 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1949 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1956 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1957 * @hw: pointer to hardware structure
1959 * Determines physical layer capabilities of the current configuration.
1961 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1963 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1964 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1965 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1966 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1967 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1968 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1969 u16 ext_ability = 0;
1970 u8 comp_codes_10g = 0;
1971 u8 comp_codes_1g = 0;
1973 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
1975 hw->phy.ops.identify(hw);
1977 switch (hw->phy.type) {
1979 case ixgbe_phy_cu_unknown:
1980 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1981 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1982 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1983 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1984 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1985 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1986 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1987 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1993 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1994 case IXGBE_AUTOC_LMS_1G_AN:
1995 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1996 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1997 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1998 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2001 /* SFI mode so read SFP module */
2004 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2005 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2006 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2007 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2008 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2009 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2010 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2013 case IXGBE_AUTOC_LMS_10G_SERIAL:
2014 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2015 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2017 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2020 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2021 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2022 if (autoc & IXGBE_AUTOC_KX_SUPP)
2023 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2024 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2025 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2026 if (autoc & IXGBE_AUTOC_KR_SUPP)
2027 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2036 /* SFP check must be done last since DA modules are sometimes used to
2037 * test KR mode - we need to id KR mode correctly before SFP module.
2038 * Call identify_sfp because the pluggable module may have changed */
2039 hw->phy.ops.identify_sfp(hw);
2040 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2043 switch (hw->phy.type) {
2044 case ixgbe_phy_sfp_passive_tyco:
2045 case ixgbe_phy_sfp_passive_unknown:
2046 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2048 case ixgbe_phy_sfp_ftl_active:
2049 case ixgbe_phy_sfp_active_unknown:
2050 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2052 case ixgbe_phy_sfp_avago:
2053 case ixgbe_phy_sfp_ftl:
2054 case ixgbe_phy_sfp_intel:
2055 case ixgbe_phy_sfp_unknown:
2056 hw->phy.ops.read_i2c_eeprom(hw,
2057 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2058 hw->phy.ops.read_i2c_eeprom(hw,
2059 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2060 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2061 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2062 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2063 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2064 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2065 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2072 return physical_layer;
2076 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2077 * @hw: pointer to hardware structure
2078 * @regval: register value to write to RXCTRL
2080 * Enables the Rx DMA unit for 82599
2082 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2084 #define IXGBE_MAX_SECRX_POLL 30
2088 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2091 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2092 * If traffic is incoming before we enable the Rx unit, it could hang
2093 * the Rx DMA unit. Therefore, make sure the security engine is
2094 * completely disabled prior to enabling the Rx unit.
2096 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2097 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2098 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2099 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2100 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2101 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2104 /* Use interrupt-safe sleep just in case */
2108 /* For informational purposes only */
2109 if (i >= IXGBE_MAX_SECRX_POLL)
2110 DEBUGOUT("Rx unit being enabled before security "
2111 "path fully disabled. Continuing with init.\n");
2113 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2114 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2115 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2116 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2117 IXGBE_WRITE_FLUSH(hw);
2119 return IXGBE_SUCCESS;
2123 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2124 * @hw: pointer to hardware structure
2126 * Verifies that installed the firmware version is 0.6 or higher
2127 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2129 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2130 * if the FW version is not supported.
2132 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2134 s32 status = IXGBE_ERR_EEPROM_VERSION;
2135 u16 fw_offset, fw_ptp_cfg_offset;
2138 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2140 /* firmware check is only necessary for SFI devices */
2141 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2142 status = IXGBE_SUCCESS;
2143 goto fw_version_out;
2146 /* get the offset to the Firmware Module block */
2147 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2149 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2150 goto fw_version_out;
2152 /* get the offset to the Pass Through Patch Configuration block */
2153 hw->eeprom.ops.read(hw, (fw_offset +
2154 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2155 &fw_ptp_cfg_offset);
2157 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2158 goto fw_version_out;
2160 /* get the firmware version */
2161 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2162 IXGBE_FW_PATCH_VERSION_4),
2165 if (fw_version > 0x5)
2166 status = IXGBE_SUCCESS;
2173 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2174 * @hw: pointer to hardware structure
2176 * Returns TRUE if the LESM FW module is present and enabled. Otherwise
2177 * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled.
2179 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2181 bool lesm_enabled = FALSE;
2182 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2185 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2187 /* get the offset to the Firmware Module block */
2188 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2190 if ((status != IXGBE_SUCCESS) ||
2191 (fw_offset == 0) || (fw_offset == 0xFFFF))
2194 /* get the offset to the LESM Parameters block */
2195 status = hw->eeprom.ops.read(hw, (fw_offset +
2196 IXGBE_FW_LESM_PARAMETERS_PTR),
2197 &fw_lesm_param_offset);
2199 if ((status != IXGBE_SUCCESS) ||
2200 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2203 /* get the lesm state word */
2204 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2205 IXGBE_FW_LESM_STATE_1),
2208 if ((status == IXGBE_SUCCESS) &&
2209 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2210 lesm_enabled = TRUE;
2213 return lesm_enabled;
2217 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2218 * fastest available method
2220 * @hw: pointer to hardware structure
2221 * @offset: offset of word in EEPROM to read
2222 * @words: number of words
2223 * @data: word(s) read from the EEPROM
2225 * Retrieves 16 bit word(s) read from EEPROM
2227 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2228 u16 words, u16 *data)
2230 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2231 s32 ret_val = IXGBE_ERR_CONFIG;
2233 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2236 * If EEPROM is detected and can be addressed using 14 bits,
2237 * use EERD otherwise use bit bang
2239 if ((eeprom->type == ixgbe_eeprom_spi) &&
2240 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2241 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2244 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2252 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2253 * fastest available method
2255 * @hw: pointer to hardware structure
2256 * @offset: offset of word in the EEPROM to read
2257 * @data: word read from the EEPROM
2259 * Reads a 16 bit word from the EEPROM
2261 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2262 u16 offset, u16 *data)
2264 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2265 s32 ret_val = IXGBE_ERR_CONFIG;
2267 DEBUGFUNC("ixgbe_read_eeprom_82599");
2270 * If EEPROM is detected and can be addressed using 14 bits,
2271 * use EERD otherwise use bit bang
2273 if ((eeprom->type == ixgbe_eeprom_spi) &&
2274 (offset <= IXGBE_EERD_MAX_ADDR))
2275 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2277 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);