1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82599.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
39 #ident "$Id: ixgbe_82599.c,v 1.334 2013/12/04 22:34:00 jtkirshe Exp $"
41 #define IXGBE_82599_MAX_TX_QUEUES 128
42 #define IXGBE_82599_MAX_RX_QUEUES 128
43 #define IXGBE_82599_RAR_ENTRIES 128
44 #define IXGBE_82599_MC_TBL_SIZE 128
45 #define IXGBE_82599_VFT_TBL_SIZE 128
46 #define IXGBE_82599_RX_PB_SIZE 512
48 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
49 ixgbe_link_speed speed,
50 bool autoneg_wait_to_complete);
51 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
53 u16 offset, u16 *data);
54 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
56 STATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
57 u8 dev_addr, u8 *data);
58 STATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
59 u8 dev_addr, u8 data);
61 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
63 struct ixgbe_mac_info *mac = &hw->mac;
65 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
68 * enable the laser control functions for SFP+ fiber
71 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
72 !ixgbe_mng_enabled(hw)) {
73 mac->ops.disable_tx_laser =
74 &ixgbe_disable_tx_laser_multispeed_fiber;
75 mac->ops.enable_tx_laser =
76 &ixgbe_enable_tx_laser_multispeed_fiber;
77 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
80 mac->ops.disable_tx_laser = NULL;
81 mac->ops.enable_tx_laser = NULL;
82 mac->ops.flap_tx_laser = NULL;
85 if (hw->phy.multispeed_fiber) {
86 /* Set up dual speed SFP+ support */
87 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
89 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
90 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
91 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
92 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
93 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
95 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
101 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
102 * @hw: pointer to hardware structure
104 * Initialize any function pointers that were not able to be
105 * set during init_shared_code because the PHY/SFP type was
106 * not known. Perform the SFP init if necessary.
109 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
111 struct ixgbe_mac_info *mac = &hw->mac;
112 struct ixgbe_phy_info *phy = &hw->phy;
113 s32 ret_val = IXGBE_SUCCESS;
116 DEBUGFUNC("ixgbe_init_phy_ops_82599");
118 if (hw->device_id == IXGBE_DEV_ID_82599_QSFP_SF_QP) {
119 /* Store flag indicating I2C bus access control unit. */
120 hw->phy.qsfp_shared_i2c_bus = TRUE;
122 /* Initialize access to QSFP+ I2C bus */
123 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
124 esdp |= IXGBE_ESDP_SDP0_DIR;
125 esdp &= ~IXGBE_ESDP_SDP1_DIR;
126 esdp &= ~IXGBE_ESDP_SDP0;
127 esdp &= ~IXGBE_ESDP_SDP0_NATIVE;
128 esdp &= ~IXGBE_ESDP_SDP1_NATIVE;
129 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
130 IXGBE_WRITE_FLUSH(hw);
132 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_82599;
133 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_82599;
135 /* Identify the PHY or SFP module */
136 ret_val = phy->ops.identify(hw);
137 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
138 goto init_phy_ops_out;
140 /* Setup function pointers based on detected SFP module and speeds */
141 ixgbe_init_mac_link_ops_82599(hw);
142 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
143 hw->phy.ops.reset = NULL;
145 /* If copper media, overwrite with copper function pointers */
146 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
147 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
148 mac->ops.get_link_capabilities =
149 &ixgbe_get_copper_link_capabilities_generic;
152 /* Set necessary function pointers based on PHY type */
153 switch (hw->phy.type) {
155 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
156 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
157 phy->ops.get_firmware_version =
158 &ixgbe_get_phy_firmware_version_tnx;
167 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
169 s32 ret_val = IXGBE_SUCCESS;
170 u16 list_offset, data_offset, data_value;
172 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
174 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
175 ixgbe_init_mac_link_ops_82599(hw);
177 hw->phy.ops.reset = NULL;
179 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
181 if (ret_val != IXGBE_SUCCESS)
184 /* PHY config will finish before releasing the semaphore */
185 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
186 IXGBE_GSSR_MAC_CSR_SM);
187 if (ret_val != IXGBE_SUCCESS) {
188 ret_val = IXGBE_ERR_SWFW_SYNC;
192 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
194 while (data_value != 0xffff) {
195 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
196 IXGBE_WRITE_FLUSH(hw);
197 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
201 /* Release the semaphore */
202 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
203 /* Delay obtaining semaphore again to allow FW access
204 * prot_autoc_write uses the semaphore too.
206 msec_delay(hw->eeprom.semaphore_delay);
208 /* Restart DSP and set SFI mode */
209 ret_val = hw->mac.ops.prot_autoc_write(hw,
210 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
214 DEBUGOUT("sfp module setup not complete\n");
215 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
225 /* Release the semaphore */
226 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
227 /* Delay obtaining semaphore again to allow FW access */
228 msec_delay(hw->eeprom.semaphore_delay);
229 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
230 "eeprom read at offset %d failed", data_offset);
231 return IXGBE_ERR_PHY;
235 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
236 * @hw: pointer to hardware structure
237 * @locked: Return the if we locked for this read.
238 * @reg_val: Value we read from AUTOC
240 * For this part (82599) we need to wrap read-modify-writes with a possible
241 * FW/SW lock. It is assumed this lock will be freed with the next
242 * prot_autoc_write_82599().
244 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
249 /* If LESM is on then we need to hold the SW/FW semaphore. */
250 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
251 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
252 IXGBE_GSSR_MAC_CSR_SM);
253 if (ret_val != IXGBE_SUCCESS)
254 return IXGBE_ERR_SWFW_SYNC;
259 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
260 return IXGBE_SUCCESS;
264 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
265 * @hw: pointer to hardware structure
266 * @reg_val: value to write to AUTOC
267 * @locked: bool to indicate whether the SW/FW lock was already taken by
268 * previous proc_autoc_read_82599.
270 * This part (82599) may need to hold the SW/FW lock around all writes to
271 * AUTOC. Likewise after a write we need to do a pipeline reset.
273 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
275 s32 ret_val = IXGBE_SUCCESS;
277 /* Blocked by MNG FW so bail */
278 if (ixgbe_check_reset_blocked(hw))
281 /* We only need to get the lock if:
282 * - We didn't do it already (in the read part of a read-modify-write)
285 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
286 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
287 IXGBE_GSSR_MAC_CSR_SM);
288 if (ret_val != IXGBE_SUCCESS)
289 return IXGBE_ERR_SWFW_SYNC;
294 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
295 ret_val = ixgbe_reset_pipeline_82599(hw);
298 /* Free the SW/FW semaphore as we either grabbed it here or
299 * already had it when this function was called.
302 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
308 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
309 * @hw: pointer to hardware structure
311 * Initialize the function pointers and assign the MAC type for 82599.
312 * Does not touch the hardware.
315 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
317 struct ixgbe_mac_info *mac = &hw->mac;
318 struct ixgbe_phy_info *phy = &hw->phy;
319 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
322 DEBUGFUNC("ixgbe_init_ops_82599");
324 ixgbe_init_phy_ops_generic(hw);
325 ret_val = ixgbe_init_ops_generic(hw);
328 phy->ops.identify = &ixgbe_identify_phy_82599;
329 phy->ops.init = &ixgbe_init_phy_ops_82599;
332 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
333 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
334 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
335 mac->ops.get_supported_physical_layer =
336 &ixgbe_get_supported_physical_layer_82599;
337 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
338 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
339 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
340 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
341 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
342 mac->ops.start_hw = &ixgbe_start_hw_82599;
343 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
344 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
345 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
346 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
347 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
348 mac->ops.prot_autoc_read = &prot_autoc_read_82599;
349 mac->ops.prot_autoc_write = &prot_autoc_write_82599;
351 /* RAR, Multicast, VLAN */
352 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
353 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
354 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
355 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
356 mac->rar_highwater = 1;
357 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
358 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
359 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
360 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
361 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
362 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
363 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
366 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
367 mac->ops.check_link = &ixgbe_check_mac_link_generic;
368 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
369 ixgbe_init_mac_link_ops_82599(hw);
371 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
372 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
373 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
374 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
375 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
376 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
377 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
379 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
380 IXGBE_FWSM_MODE_MASK) ? true : false;
382 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
385 eeprom->ops.read = &ixgbe_read_eeprom_82599;
386 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
388 /* Manageability interface */
389 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
391 mac->ops.get_thermal_sensor_data =
392 &ixgbe_get_thermal_sensor_data_generic;
393 mac->ops.init_thermal_sensor_thresh =
394 &ixgbe_init_thermal_sensor_thresh_generic;
396 mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
402 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
403 * @hw: pointer to hardware structure
404 * @speed: pointer to link speed
405 * @autoneg: true when autoneg or autotry is enabled
407 * Determines the link capabilities by reading the AUTOC register.
409 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
410 ixgbe_link_speed *speed,
413 s32 status = IXGBE_SUCCESS;
416 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
419 /* Check if 1G SFP module. */
420 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
421 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
422 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
423 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
424 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
425 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
426 *speed = IXGBE_LINK_SPEED_1GB_FULL;
432 * Determine link capabilities based on the stored value of AUTOC,
433 * which represents EEPROM defaults. If AUTOC value has not
434 * been stored, use the current register values.
436 if (hw->mac.orig_link_settings_stored)
437 autoc = hw->mac.orig_autoc;
439 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
441 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
442 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
443 *speed = IXGBE_LINK_SPEED_1GB_FULL;
447 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
448 *speed = IXGBE_LINK_SPEED_10GB_FULL;
452 case IXGBE_AUTOC_LMS_1G_AN:
453 *speed = IXGBE_LINK_SPEED_1GB_FULL;
457 case IXGBE_AUTOC_LMS_10G_SERIAL:
458 *speed = IXGBE_LINK_SPEED_10GB_FULL;
462 case IXGBE_AUTOC_LMS_KX4_KX_KR:
463 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
464 *speed = IXGBE_LINK_SPEED_UNKNOWN;
465 if (autoc & IXGBE_AUTOC_KR_SUPP)
466 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
467 if (autoc & IXGBE_AUTOC_KX4_SUPP)
468 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
469 if (autoc & IXGBE_AUTOC_KX_SUPP)
470 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
474 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
475 *speed = IXGBE_LINK_SPEED_100_FULL;
476 if (autoc & IXGBE_AUTOC_KR_SUPP)
477 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
478 if (autoc & IXGBE_AUTOC_KX4_SUPP)
479 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
480 if (autoc & IXGBE_AUTOC_KX_SUPP)
481 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
485 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
486 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
491 status = IXGBE_ERR_LINK_SETUP;
496 if (hw->phy.multispeed_fiber) {
497 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
498 IXGBE_LINK_SPEED_1GB_FULL;
500 /* QSFP must not enable full auto-negotiation
501 * Limited autoneg is enabled at 1G
503 if (hw->phy.media_type == ixgbe_media_type_fiber_qsfp)
514 * ixgbe_get_media_type_82599 - Get media type
515 * @hw: pointer to hardware structure
517 * Returns the media type (fiber, copper, backplane)
519 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
521 enum ixgbe_media_type media_type;
523 DEBUGFUNC("ixgbe_get_media_type_82599");
525 /* Detect if there is a copper PHY attached. */
526 switch (hw->phy.type) {
527 case ixgbe_phy_cu_unknown:
529 media_type = ixgbe_media_type_copper;
535 switch (hw->device_id) {
536 case IXGBE_DEV_ID_82599_KX4:
537 case IXGBE_DEV_ID_82599_KX4_MEZZ:
538 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
539 case IXGBE_DEV_ID_82599_KR:
540 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
541 case IXGBE_DEV_ID_82599_XAUI_LOM:
542 /* Default device ID is mezzanine card KX/KX4 */
543 media_type = ixgbe_media_type_backplane;
545 case IXGBE_DEV_ID_82599_SFP:
546 case IXGBE_DEV_ID_82599_SFP_FCOE:
547 case IXGBE_DEV_ID_82599_SFP_EM:
548 case IXGBE_DEV_ID_82599_SFP_SF2:
549 case IXGBE_DEV_ID_82599_SFP_SF_QP:
550 case IXGBE_DEV_ID_82599EN_SFP:
551 media_type = ixgbe_media_type_fiber;
553 case IXGBE_DEV_ID_82599_CX4:
554 media_type = ixgbe_media_type_cx4;
556 case IXGBE_DEV_ID_82599_T3_LOM:
557 media_type = ixgbe_media_type_copper;
559 case IXGBE_DEV_ID_82599_LS:
560 media_type = ixgbe_media_type_fiber_lco;
562 case IXGBE_DEV_ID_82599_QSFP_SF_QP:
563 media_type = ixgbe_media_type_fiber_qsfp;
566 media_type = ixgbe_media_type_unknown;
574 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
575 * @hw: pointer to hardware structure
577 * Disables link during D3 power down sequence.
580 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
582 u32 autoc2_reg, fwsm;
585 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
586 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
588 /* Check to see if MNG FW could be enabled */
589 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
591 if (((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) &&
593 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
594 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
595 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
596 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
601 * ixgbe_start_mac_link_82599 - Setup MAC link settings
602 * @hw: pointer to hardware structure
603 * @autoneg_wait_to_complete: true when waiting for completion is needed
605 * Configures link settings based on values in the ixgbe_hw struct.
606 * Restarts the link. Performs autonegotiation if needed.
608 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
609 bool autoneg_wait_to_complete)
614 s32 status = IXGBE_SUCCESS;
615 bool got_lock = false;
617 DEBUGFUNC("ixgbe_start_mac_link_82599");
620 /* reset_pipeline requires us to hold this lock as it writes to
623 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
624 status = hw->mac.ops.acquire_swfw_sync(hw,
625 IXGBE_GSSR_MAC_CSR_SM);
626 if (status != IXGBE_SUCCESS)
633 ixgbe_reset_pipeline_82599(hw);
636 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
638 /* Only poll for autoneg to complete if specified to do so */
639 if (autoneg_wait_to_complete) {
640 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
641 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
642 IXGBE_AUTOC_LMS_KX4_KX_KR ||
643 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
644 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
645 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
646 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
647 links_reg = 0; /* Just in case Autoneg time = 0 */
648 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
649 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
650 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
654 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
655 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
656 DEBUGOUT("Autoneg did not complete.\n");
661 /* Add delay to filter out noises during initial link setup */
669 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
670 * @hw: pointer to hardware structure
672 * The base drivers may require better control over SFP+ module
673 * PHY states. This includes selectively shutting down the Tx
674 * laser on the PHY, effectively halting physical link.
676 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
678 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
680 /* Blocked by MNG FW so bail */
681 if (ixgbe_check_reset_blocked(hw))
684 /* Disable Tx laser; allow 100us to go dark per spec */
685 esdp_reg |= IXGBE_ESDP_SDP3;
686 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
687 IXGBE_WRITE_FLUSH(hw);
692 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
693 * @hw: pointer to hardware structure
695 * The base drivers may require better control over SFP+ module
696 * PHY states. This includes selectively turning on the Tx
697 * laser on the PHY, effectively starting physical link.
699 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
701 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
703 /* Enable Tx laser; allow 100ms to light up */
704 esdp_reg &= ~IXGBE_ESDP_SDP3;
705 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
706 IXGBE_WRITE_FLUSH(hw);
711 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
712 * @hw: pointer to hardware structure
714 * When the driver changes the link speeds that it can support,
715 * it sets autotry_restart to true to indicate that we need to
716 * initiate a new autotry session with the link partner. To do
717 * so, we set the speed then disable and re-enable the Tx laser, to
718 * alert the link partner that it also needs to restart autotry on its
719 * end. This is consistent with true clause 37 autoneg, which also
720 * involves a loss of signal.
722 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
724 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
726 /* Blocked by MNG FW so bail */
727 if (ixgbe_check_reset_blocked(hw))
730 if (hw->mac.autotry_restart) {
731 ixgbe_disable_tx_laser_multispeed_fiber(hw);
732 ixgbe_enable_tx_laser_multispeed_fiber(hw);
733 hw->mac.autotry_restart = false;
739 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
740 * @hw: pointer to hardware structure
741 * @speed: new link speed
742 * @autoneg_wait_to_complete: true when waiting for completion is needed
744 * Set the link speed in the AUTOC register and restarts link.
746 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
747 ixgbe_link_speed speed,
748 bool autoneg_wait_to_complete)
750 s32 status = IXGBE_SUCCESS;
751 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
752 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
754 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
756 bool autoneg, link_up = false;
758 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
760 /* Mask off requested but non-supported speeds */
761 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
762 if (status != IXGBE_SUCCESS)
768 * Try each speed one by one, highest priority first. We do this in
769 * software because 10gb fiber doesn't support speed autonegotiation.
771 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
773 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
775 /* If we already have link at this speed, just jump out */
776 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
777 if (status != IXGBE_SUCCESS)
780 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
783 /* Set the module link speed */
784 switch (hw->phy.media_type) {
785 case ixgbe_media_type_fiber:
786 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
787 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
788 IXGBE_WRITE_FLUSH(hw);
790 case ixgbe_media_type_fiber_qsfp:
791 /* QSFP module automatically detects MAC link speed */
794 DEBUGOUT("Unexpected media type.\n");
798 /* Allow module to change analog characteristics (1G->10G) */
801 status = ixgbe_setup_mac_link_82599(hw,
802 IXGBE_LINK_SPEED_10GB_FULL,
803 autoneg_wait_to_complete);
804 if (status != IXGBE_SUCCESS)
807 /* Flap the tx laser if it has not already been done */
808 ixgbe_flap_tx_laser(hw);
811 * Wait for the controller to acquire link. Per IEEE 802.3ap,
812 * Section 73.10.2, we may have to wait up to 500ms if KR is
813 * attempted. 82599 uses the same timing for 10g SFI.
815 for (i = 0; i < 5; i++) {
816 /* Wait for the link partner to also set speed */
819 /* If we have link, just jump out */
820 status = ixgbe_check_link(hw, &link_speed,
822 if (status != IXGBE_SUCCESS)
830 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
832 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
833 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
835 /* If we already have link at this speed, just jump out */
836 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
837 if (status != IXGBE_SUCCESS)
840 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
843 /* Set the module link speed */
844 switch (hw->phy.media_type) {
845 case ixgbe_media_type_fiber:
846 esdp_reg &= ~IXGBE_ESDP_SDP5;
847 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
848 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
849 IXGBE_WRITE_FLUSH(hw);
851 case ixgbe_media_type_fiber_qsfp:
852 /* QSFP module automatically detects link speed */
855 DEBUGOUT("Unexpected media type.\n");
859 /* Allow module to change analog characteristics (10G->1G) */
862 status = ixgbe_setup_mac_link_82599(hw,
863 IXGBE_LINK_SPEED_1GB_FULL,
864 autoneg_wait_to_complete);
865 if (status != IXGBE_SUCCESS)
868 /* Flap the Tx laser if it has not already been done */
869 ixgbe_flap_tx_laser(hw);
871 /* Wait for the link partner to also set speed */
874 /* If we have link, just jump out */
875 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
876 if (status != IXGBE_SUCCESS)
884 * We didn't get link. Configure back to the highest speed we tried,
885 * (if there was more than one). We call ourselves back with just the
886 * single highest speed that the user requested.
889 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
890 highest_link_speed, autoneg_wait_to_complete);
893 /* Set autoneg_advertised value based on input link speed */
894 hw->phy.autoneg_advertised = 0;
896 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
897 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
899 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
900 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
906 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
907 * @hw: pointer to hardware structure
908 * @speed: new link speed
909 * @autoneg_wait_to_complete: true when waiting for completion is needed
911 * Implements the Intel SmartSpeed algorithm.
913 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
914 ixgbe_link_speed speed,
915 bool autoneg_wait_to_complete)
917 s32 status = IXGBE_SUCCESS;
918 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
920 bool link_up = false;
921 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
923 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
925 /* Set autoneg_advertised value based on input link speed */
926 hw->phy.autoneg_advertised = 0;
928 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
929 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
931 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
932 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
934 if (speed & IXGBE_LINK_SPEED_100_FULL)
935 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
938 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
939 * autoneg advertisement if link is unable to be established at the
940 * highest negotiated rate. This can sometimes happen due to integrity
941 * issues with the physical media connection.
944 /* First, try to get link with full advertisement */
945 hw->phy.smart_speed_active = false;
946 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
947 status = ixgbe_setup_mac_link_82599(hw, speed,
948 autoneg_wait_to_complete);
949 if (status != IXGBE_SUCCESS)
953 * Wait for the controller to acquire link. Per IEEE 802.3ap,
954 * Section 73.10.2, we may have to wait up to 500ms if KR is
955 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
956 * Table 9 in the AN MAS.
958 for (i = 0; i < 5; i++) {
961 /* If we have link, just jump out */
962 status = ixgbe_check_link(hw, &link_speed, &link_up,
964 if (status != IXGBE_SUCCESS)
973 * We didn't get link. If we advertised KR plus one of KX4/KX
974 * (or BX4/BX), then disable KR and try again.
976 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
977 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
980 /* Turn SmartSpeed on to disable KR support */
981 hw->phy.smart_speed_active = true;
982 status = ixgbe_setup_mac_link_82599(hw, speed,
983 autoneg_wait_to_complete);
984 if (status != IXGBE_SUCCESS)
988 * Wait for the controller to acquire link. 600ms will allow for
989 * the AN link_fail_inhibit_timer as well for multiple cycles of
990 * parallel detect, both 10g and 1g. This allows for the maximum
991 * connect attempts as defined in the AN MAS table 73-7.
993 for (i = 0; i < 6; i++) {
996 /* If we have link, just jump out */
997 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
998 if (status != IXGBE_SUCCESS)
1005 /* We didn't get link. Turn SmartSpeed back off. */
1006 hw->phy.smart_speed_active = false;
1007 status = ixgbe_setup_mac_link_82599(hw, speed,
1008 autoneg_wait_to_complete);
1011 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
1012 DEBUGOUT("Smartspeed has downgraded the link speed "
1013 "from the maximum advertised\n");
1018 * ixgbe_setup_mac_link_82599 - Set MAC link speed
1019 * @hw: pointer to hardware structure
1020 * @speed: new link speed
1021 * @autoneg_wait_to_complete: true when waiting for completion is needed
1023 * Set the link speed in the AUTOC register and restarts link.
1025 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
1026 ixgbe_link_speed speed,
1027 bool autoneg_wait_to_complete)
1029 bool autoneg = false;
1030 s32 status = IXGBE_SUCCESS;
1031 u32 pma_pmd_1g, link_mode;
1032 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */
1033 u32 orig_autoc = 0; /* holds the cached value of AUTOC register */
1034 u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */
1035 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1036 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1039 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
1041 DEBUGFUNC("ixgbe_setup_mac_link_82599");
1043 /* Check to see if speed passed in is supported. */
1044 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
1048 speed &= link_capabilities;
1050 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
1051 status = IXGBE_ERR_LINK_SETUP;
1055 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
1056 if (hw->mac.orig_link_settings_stored)
1057 orig_autoc = hw->mac.orig_autoc;
1061 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
1062 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1064 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1065 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1066 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1067 /* Set KX4/KX/KR support according to speed requested */
1068 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
1069 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1070 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
1071 autoc |= IXGBE_AUTOC_KX4_SUPP;
1072 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
1073 (hw->phy.smart_speed_active == false))
1074 autoc |= IXGBE_AUTOC_KR_SUPP;
1076 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1077 autoc |= IXGBE_AUTOC_KX_SUPP;
1078 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
1079 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
1080 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
1081 /* Switch from 1G SFI to 10G SFI if requested */
1082 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
1083 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
1084 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1085 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
1087 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
1088 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
1089 /* Switch from 10G SFI to 1G SFI if requested */
1090 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1091 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
1092 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1093 if (autoneg || hw->phy.type == ixgbe_phy_qsfp_intel)
1094 autoc |= IXGBE_AUTOC_LMS_1G_AN;
1096 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
1100 if (autoc != current_autoc) {
1102 status = hw->mac.ops.prot_autoc_write(hw, autoc, false);
1103 if (status != IXGBE_SUCCESS)
1106 /* Only poll for autoneg to complete if specified to do so */
1107 if (autoneg_wait_to_complete) {
1108 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1109 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1110 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1111 links_reg = 0; /*Just in case Autoneg time=0*/
1112 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1114 IXGBE_READ_REG(hw, IXGBE_LINKS);
1115 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
1119 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
1121 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
1122 DEBUGOUT("Autoneg did not complete.\n");
1127 /* Add delay to filter out noises during initial link setup */
1136 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
1137 * @hw: pointer to hardware structure
1138 * @speed: new link speed
1139 * @autoneg_wait_to_complete: true if waiting is needed to complete
1141 * Restarts link on PHY and MAC based on settings passed in.
1143 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1144 ixgbe_link_speed speed,
1145 bool autoneg_wait_to_complete)
1149 DEBUGFUNC("ixgbe_setup_copper_link_82599");
1151 /* Setup the PHY according to input speed */
1152 status = hw->phy.ops.setup_link_speed(hw, speed,
1153 autoneg_wait_to_complete);
1155 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1161 * ixgbe_reset_hw_82599 - Perform hardware reset
1162 * @hw: pointer to hardware structure
1164 * Resets the hardware by resetting the transmit and receive units, masks
1165 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1168 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1170 ixgbe_link_speed link_speed;
1173 u32 i, autoc, autoc2;
1175 bool link_up = false;
1177 DEBUGFUNC("ixgbe_reset_hw_82599");
1179 /* Call adapter stop to disable tx/rx and clear interrupts */
1180 status = hw->mac.ops.stop_adapter(hw);
1181 if (status != IXGBE_SUCCESS)
1184 /* flush pending Tx transactions */
1185 ixgbe_clear_tx_pending(hw);
1187 /* PHY ops must be identified and initialized prior to reset */
1189 /* Identify PHY and related function pointers */
1190 status = hw->phy.ops.init(hw);
1192 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1195 /* Setup SFP module if there is one present. */
1196 if (hw->phy.sfp_setup_needed) {
1197 status = hw->mac.ops.setup_sfp(hw);
1198 hw->phy.sfp_setup_needed = false;
1201 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1205 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1206 hw->phy.ops.reset(hw);
1208 /* remember AUTOC from before we reset */
1209 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
1213 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1214 * If link reset is used when link is up, it might reset the PHY when
1215 * mng is using it. If link is down or the flag to force full link
1216 * reset is set, then perform link reset.
1218 ctrl = IXGBE_CTRL_LNK_RST;
1219 if (!hw->force_full_reset) {
1220 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1222 ctrl = IXGBE_CTRL_RST;
1225 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1226 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1227 IXGBE_WRITE_FLUSH(hw);
1229 /* Poll for reset bit to self-clear meaning reset is complete */
1230 for (i = 0; i < 10; i++) {
1232 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1233 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1237 if (ctrl & IXGBE_CTRL_RST_MASK) {
1238 status = IXGBE_ERR_RESET_FAILED;
1239 DEBUGOUT("Reset polling failed to complete.\n");
1245 * Double resets are required for recovery from certain error
1246 * conditions. Between resets, it is necessary to stall to
1247 * allow time for any pending HW events to complete.
1249 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1250 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1255 * Store the original AUTOC/AUTOC2 values if they have not been
1256 * stored off yet. Otherwise restore the stored original
1257 * values since the reset operation sets back to defaults.
1259 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1260 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1262 /* Enable link if disabled in NVM */
1263 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1264 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1265 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1266 IXGBE_WRITE_FLUSH(hw);
1269 if (hw->mac.orig_link_settings_stored == false) {
1270 hw->mac.orig_autoc = autoc;
1271 hw->mac.orig_autoc2 = autoc2;
1272 hw->mac.orig_link_settings_stored = true;
1275 /* If MNG FW is running on a multi-speed device that
1276 * doesn't autoneg with out driver support we need to
1277 * leave LMS in the state it was before we MAC reset.
1278 * Likewise if we support WoL we don't want change the
1281 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
1283 hw->mac.orig_autoc =
1284 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1287 if (autoc != hw->mac.orig_autoc) {
1288 status = hw->mac.ops.prot_autoc_write(hw,
1291 if (status != IXGBE_SUCCESS)
1295 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1296 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1297 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1298 autoc2 |= (hw->mac.orig_autoc2 &
1299 IXGBE_AUTOC2_UPPER_MASK);
1300 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1304 /* Store the permanent mac address */
1305 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1308 * Store MAC address from RAR0, clear receive address registers, and
1309 * clear the multicast table. Also reset num_rar_entries to 128,
1310 * since we modify this value when programming the SAN MAC address.
1312 hw->mac.num_rar_entries = 128;
1313 hw->mac.ops.init_rx_addrs(hw);
1315 /* Store the permanent SAN mac address */
1316 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1318 /* Add the SAN MAC address to the RAR only if it's a valid address */
1319 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1320 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1321 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1323 /* Save the SAN MAC RAR index */
1324 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1326 /* Reserve the last RAR for the SAN MAC address */
1327 hw->mac.num_rar_entries--;
1330 /* Store the alternative WWNN/WWPN prefix */
1331 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1332 &hw->mac.wwpn_prefix);
1339 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
1340 * @hw: pointer to hardware structure
1342 STATIC s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw)
1346 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1347 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1348 IXGBE_FDIRCMD_CMD_MASK))
1349 return IXGBE_SUCCESS;
1353 return IXGBE_ERR_FDIR_CMD_INCOMPLETE;
1357 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1358 * @hw: pointer to hardware structure
1360 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1364 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1365 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1367 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1370 * Before starting reinitialization process,
1371 * FDIRCMD.CMD must be zero.
1373 err = ixgbe_fdir_check_cmd_complete(hw);
1375 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n");
1379 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1380 IXGBE_WRITE_FLUSH(hw);
1382 * 82599 adapters flow director init flow cannot be restarted,
1383 * Workaround 82599 silicon errata by performing the following steps
1384 * before re-writing the FDIRCTRL control register with the same value.
1385 * - write 1 to bit 8 of FDIRCMD register &
1386 * - write 0 to bit 8 of FDIRCMD register
1388 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1389 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1390 IXGBE_FDIRCMD_CLEARHT));
1391 IXGBE_WRITE_FLUSH(hw);
1392 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1393 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1394 ~IXGBE_FDIRCMD_CLEARHT));
1395 IXGBE_WRITE_FLUSH(hw);
1397 * Clear FDIR Hash register to clear any leftover hashes
1398 * waiting to be programmed.
1400 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1401 IXGBE_WRITE_FLUSH(hw);
1403 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1404 IXGBE_WRITE_FLUSH(hw);
1406 /* Poll init-done after we write FDIRCTRL register */
1407 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1408 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1409 IXGBE_FDIRCTRL_INIT_DONE)
1413 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1414 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1415 return IXGBE_ERR_FDIR_REINIT_FAILED;
1418 /* Clear FDIR statistics registers (read to clear) */
1419 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1420 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1421 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1422 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1423 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1425 return IXGBE_SUCCESS;
1429 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1430 * @hw: pointer to hardware structure
1431 * @fdirctrl: value to write to flow director control register
1433 STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1437 DEBUGFUNC("ixgbe_fdir_enable_82599");
1439 /* Prime the keys for hashing */
1440 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1441 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1444 * Poll init-done after we write the register. Estimated times:
1445 * 10G: PBALLOC = 11b, timing is 60us
1446 * 1G: PBALLOC = 11b, timing is 600us
1447 * 100M: PBALLOC = 11b, timing is 6ms
1449 * Multiple these timings by 4 if under full Rx load
1451 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1452 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1453 * this might not finish in our poll time, but we can live with that
1456 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1457 IXGBE_WRITE_FLUSH(hw);
1458 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1459 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1460 IXGBE_FDIRCTRL_INIT_DONE)
1465 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1466 DEBUGOUT("Flow Director poll time exceeded!\n");
1470 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1471 * @hw: pointer to hardware structure
1472 * @fdirctrl: value to write to flow director control register, initially
1473 * contains just the value of the Rx packet buffer allocation
1475 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1477 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1480 * Continue setup of fdirctrl register bits:
1481 * Move the flexible bytes to use the ethertype - shift 6 words
1482 * Set the maximum length per hash bucket to 0xA filters
1483 * Send interrupt when 64 filters are left
1485 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1486 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1487 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1489 /* write hashes and fdirctrl register, poll for completion */
1490 ixgbe_fdir_enable_82599(hw, fdirctrl);
1492 return IXGBE_SUCCESS;
1496 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1497 * @hw: pointer to hardware structure
1498 * @fdirctrl: value to write to flow director control register, initially
1499 * contains just the value of the Rx packet buffer allocation
1500 * @cloud_mode: true - cloud mode, false - other mode
1502 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
1505 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1508 * Continue setup of fdirctrl register bits:
1509 * Turn perfect match filtering on
1510 * Report hash in RSS field of Rx wb descriptor
1511 * Initialize the drop queue
1512 * Move the flexible bytes to use the ethertype - shift 6 words
1513 * Set the maximum length per hash bucket to 0xA filters
1514 * Send interrupt when 64 (0x4 * 16) filters are left
1516 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1517 IXGBE_FDIRCTRL_REPORT_STATUS |
1518 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1519 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1520 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1521 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1524 fdirctrl |=(IXGBE_FDIRCTRL_FILTERMODE_CLOUD <<
1525 IXGBE_FDIRCTRL_FILTERMODE_SHIFT);
1527 /* write hashes and fdirctrl register, poll for completion */
1528 ixgbe_fdir_enable_82599(hw, fdirctrl);
1530 return IXGBE_SUCCESS;
1534 * These defines allow us to quickly generate all of the necessary instructions
1535 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1536 * for values 0 through 15
1538 #define IXGBE_ATR_COMMON_HASH_KEY \
1539 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1540 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1543 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1544 common_hash ^= lo_hash_dword >> n; \
1545 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1546 bucket_hash ^= lo_hash_dword >> n; \
1547 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1548 sig_hash ^= lo_hash_dword << (16 - n); \
1549 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1550 common_hash ^= hi_hash_dword >> n; \
1551 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1552 bucket_hash ^= hi_hash_dword >> n; \
1553 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1554 sig_hash ^= hi_hash_dword << (16 - n); \
1558 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1559 * @stream: input bitstream to compute the hash on
1561 * This function is almost identical to the function above but contains
1562 * several optimizations such as unwinding all of the loops, letting the
1563 * compiler work out all of the conditional ifs since the keys are static
1564 * defines, and computing two keys at once since the hashed dword stream
1565 * will be the same for both keys.
1567 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1568 union ixgbe_atr_hash_dword common)
1570 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1571 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1573 /* record the flow_vm_vlan bits as they are a key part to the hash */
1574 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1576 /* generate common hash dword */
1577 hi_hash_dword = IXGBE_NTOHL(common.dword);
1579 /* low dword is word swapped version of common */
1580 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1582 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1583 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1585 /* Process bits 0 and 16 */
1586 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1589 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1590 * delay this because bit 0 of the stream should not be processed
1591 * so we do not add the VLAN until after bit 0 was processed
1593 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1595 /* Process remaining 30 bit of the key */
1596 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1597 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1598 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1599 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1600 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1601 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1602 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1603 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1604 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1605 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1606 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1607 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1608 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1609 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1610 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1612 /* combine common_hash result with signature and bucket hashes */
1613 bucket_hash ^= common_hash;
1614 bucket_hash &= IXGBE_ATR_HASH_MASK;
1616 sig_hash ^= common_hash << 16;
1617 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1619 /* return completed signature hash */
1620 return sig_hash ^ bucket_hash;
1624 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1625 * @hw: pointer to hardware structure
1626 * @input: unique input dword
1627 * @common: compressed common input dword
1628 * @queue: queue index to direct traffic to
1630 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1631 union ixgbe_atr_hash_dword input,
1632 union ixgbe_atr_hash_dword common,
1639 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1642 * Get the flow_type in order to program FDIRCMD properly
1643 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1644 * fifth is FDIRCMD.TUNNEL_FILTER
1646 switch (input.formatted.flow_type) {
1647 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1648 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1649 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1650 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1651 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1652 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1655 DEBUGOUT(" Error on flow type input\n");
1656 return IXGBE_ERR_CONFIG;
1659 /* configure FDIRCMD register */
1660 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1661 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1662 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1663 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1666 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1667 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1669 fdirhashcmd = (u64)fdircmd << 32;
1670 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1671 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1673 err = ixgbe_fdir_check_cmd_complete(hw);
1675 DEBUGOUT("Flow Director command did not complete!\n");
1679 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1681 return IXGBE_SUCCESS;
1684 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1687 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1688 bucket_hash ^= lo_hash_dword >> n; \
1689 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1690 bucket_hash ^= hi_hash_dword >> n; \
1694 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1695 * @atr_input: input bitstream to compute the hash on
1696 * @input_mask: mask for the input bitstream
1698 * This function serves two main purposes. First it applies the input_mask
1699 * to the atr_input resulting in a cleaned up atr_input data stream.
1700 * Secondly it computes the hash and stores it in the bkt_hash field at
1701 * the end of the input byte stream. This way it will be available for
1702 * future use without needing to recompute the hash.
1704 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1705 union ixgbe_atr_input *input_mask)
1708 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1709 u32 bucket_hash = 0;
1713 /* Apply masks to input data */
1714 for (i = 0; i < 14; i++)
1715 input->dword_stream[i] &= input_mask->dword_stream[i];
1717 /* record the flow_vm_vlan bits as they are a key part to the hash */
1718 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1720 /* generate common hash dword */
1721 for (i = 1; i <= 13; i++)
1722 hi_dword ^= input->dword_stream[i];
1723 hi_hash_dword = IXGBE_NTOHL(hi_dword);
1725 /* low dword is word swapped version of common */
1726 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1728 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1729 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1731 /* Process bits 0 and 16 */
1732 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1735 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1736 * delay this because bit 0 of the stream should not be processed
1737 * so we do not add the VLAN until after bit 0 was processed
1739 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1741 /* Process remaining 30 bit of the key */
1742 for (i = 1; i <= 15; i++)
1743 IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
1746 * Limit hash to 13 bits since max bucket count is 8K.
1747 * Store result at the end of the input stream.
1749 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1753 * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks
1754 * @input_mask: mask to be bit swapped
1756 * The source and destination port masks for flow director are bit swapped
1757 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1758 * generate a correctly swapped value we need to bit swap the mask and that
1759 * is what is accomplished by this function.
1761 STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1763 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1764 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1765 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1766 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1767 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1768 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1769 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1773 * These two macros are meant to address the fact that we have registers
1774 * that are either all or in part big-endian. As a result on big-endian
1775 * systems we will end up byte swapping the value to little-endian before
1776 * it is byte swapped again and written to the hardware in the original
1777 * big-endian format.
1779 #define IXGBE_STORE_AS_BE32(_value) \
1780 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1781 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1783 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1784 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1786 #define IXGBE_STORE_AS_BE16(_value) \
1787 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1789 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1790 union ixgbe_atr_input *input_mask, bool cloud_mode)
1792 /* mask IPv6 since it is currently not supported */
1793 u32 fdirm = IXGBE_FDIRM_DIPv6;
1796 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1799 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1800 * are zero, then assume a full mask for that field. Also assume that
1801 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1802 * cannot be masked out in this implementation.
1804 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1808 /* verify bucket hash is cleared on hash generation */
1809 if (input_mask->formatted.bkt_hash)
1810 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1812 /* Program FDIRM and verify partial masks */
1813 switch (input_mask->formatted.vm_pool & 0x7F) {
1815 fdirm |= IXGBE_FDIRM_POOL;
1819 DEBUGOUT(" Error on vm pool mask\n");
1820 return IXGBE_ERR_CONFIG;
1823 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1825 fdirm |= IXGBE_FDIRM_L4P;
1826 if (input_mask->formatted.dst_port ||
1827 input_mask->formatted.src_port) {
1828 DEBUGOUT(" Error on src/dst port mask\n");
1829 return IXGBE_ERR_CONFIG;
1831 case IXGBE_ATR_L4TYPE_MASK:
1834 DEBUGOUT(" Error on flow type mask\n");
1835 return IXGBE_ERR_CONFIG;
1838 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1840 /* mask VLAN ID, fall through to mask VLAN priority */
1841 fdirm |= IXGBE_FDIRM_VLANID;
1843 /* mask VLAN priority */
1844 fdirm |= IXGBE_FDIRM_VLANP;
1847 /* mask VLAN ID only, fall through */
1848 fdirm |= IXGBE_FDIRM_VLANID;
1850 /* no VLAN fields masked */
1853 DEBUGOUT(" Error on VLAN mask\n");
1854 return IXGBE_ERR_CONFIG;
1857 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1859 /* Mask Flex Bytes, fall through */
1860 fdirm |= IXGBE_FDIRM_FLEX;
1864 DEBUGOUT(" Error on flexible byte mask\n");
1865 return IXGBE_ERR_CONFIG;
1869 fdirm |= IXGBE_FDIRM_L3P;
1870 fdirip6m = ((u32) 0xFFFFU << IXGBE_FDIRIP6M_DIPM_SHIFT);
1871 fdirip6m |= IXGBE_FDIRIP6M_ALWAYS_MASK;
1873 switch (input_mask->formatted.inner_mac[0] & 0xFF) {
1875 /* Mask inner MAC, fall through */
1876 fdirip6m |= IXGBE_FDIRIP6M_INNER_MAC;
1880 DEBUGOUT(" Error on inner_mac byte mask\n");
1881 return IXGBE_ERR_CONFIG;
1884 switch (input_mask->formatted.tni_vni & 0xFFFFFFFF) {
1887 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI;
1890 fdirip6m |= IXGBE_FDIRIP6M_TNI_VNI_24;
1895 DEBUGOUT(" Error on TNI/VNI byte mask\n");
1896 return IXGBE_ERR_CONFIG;
1899 switch (input_mask->formatted.tunnel_type & 0xFFFF) {
1901 /* Mask turnnel type, fall through */
1902 fdirip6m |= IXGBE_FDIRIP6M_TUNNEL_TYPE;
1906 DEBUGOUT(" Error on tunnel type byte mask\n");
1907 return IXGBE_ERR_CONFIG;
1909 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIP6M, fdirip6m);
1912 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1913 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1915 /* store the TCP/UDP port masks, bit reversed from port layout */
1916 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1918 /* write both the same so that UDP and TCP use the same mask */
1919 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1920 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1921 /* also use it for SCTP */
1922 switch (hw->mac.type) {
1923 case ixgbe_mac_X550:
1924 case ixgbe_mac_X550EM_x:
1925 IXGBE_WRITE_REG(hw, IXGBE_FDIRSCTPM, ~fdirtcpm);
1931 /* store source and destination IP masks (big-endian) */
1932 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1933 ~input_mask->formatted.src_ip[0]);
1934 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1935 ~input_mask->formatted.dst_ip[0]);
1937 return IXGBE_SUCCESS;
1940 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1941 union ixgbe_atr_input *input,
1942 u16 soft_id, u8 queue, bool cloud_mode)
1944 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1945 u32 addr_low, addr_high;
1949 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1951 /* currently IPv6 is not supported, must be programmed with 0 */
1952 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1953 input->formatted.src_ip[0]);
1954 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1955 input->formatted.src_ip[1]);
1956 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1957 input->formatted.src_ip[2]);
1959 /* record the source address (big-endian) */
1960 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1962 /* record the first 32 bits of the destination address (big-endian) */
1963 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1965 /* record source and destination port (little-endian)*/
1966 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1967 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1968 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1969 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1971 /* record VLAN (little-endian) and flex_bytes(big-endian) */
1972 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1973 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1974 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1975 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1978 if (input->formatted.tunnel_type != 0)
1979 cloud_type = 0x80000000;
1981 addr_low = ((u32)input->formatted.inner_mac[0] |
1982 ((u32)input->formatted.inner_mac[1] << 8) |
1983 ((u32)input->formatted.inner_mac[2] << 16) |
1984 ((u32)input->formatted.inner_mac[3] << 24));
1985 addr_high = ((u32)input->formatted.inner_mac[4] |
1986 ((u32)input->formatted.inner_mac[5] << 8));
1987 cloud_type |= addr_high;
1988 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0), addr_low);
1989 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1), cloud_type);
1990 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2), input->formatted.tni_vni);
1993 /* configure FDIRHASH register */
1994 fdirhash = input->formatted.bkt_hash;
1995 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1996 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1999 * flush all previous writes to make certain registers are
2000 * programmed prior to issuing the command
2002 IXGBE_WRITE_FLUSH(hw);
2004 /* configure FDIRCMD register */
2005 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
2006 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
2007 if (queue == IXGBE_FDIR_DROP_QUEUE)
2008 fdircmd |= IXGBE_FDIRCMD_DROP;
2009 if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK)
2010 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
2011 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
2012 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
2013 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
2015 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
2016 err = ixgbe_fdir_check_cmd_complete(hw);
2018 DEBUGOUT("Flow Director command did not complete!\n");
2022 return IXGBE_SUCCESS;
2025 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
2026 union ixgbe_atr_input *input,
2033 /* configure FDIRHASH register */
2034 fdirhash = input->formatted.bkt_hash;
2035 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
2036 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2038 /* flush hash to HW */
2039 IXGBE_WRITE_FLUSH(hw);
2041 /* Query if filter is present */
2042 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
2044 err = ixgbe_fdir_check_cmd_complete(hw);
2046 DEBUGOUT("Flow Director command did not complete!\n");
2050 /* if filter exists in hardware then remove it */
2051 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
2052 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
2053 IXGBE_WRITE_FLUSH(hw);
2054 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
2055 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
2058 return IXGBE_SUCCESS;
2062 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
2063 * @hw: pointer to hardware structure
2064 * @input: input bitstream
2065 * @input_mask: mask for the input bitstream
2066 * @soft_id: software index for the filters
2067 * @queue: queue index to direct traffic to
2069 * Note that the caller to this function must lock before calling, since the
2070 * hardware writes must be protected from one another.
2072 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
2073 union ixgbe_atr_input *input,
2074 union ixgbe_atr_input *input_mask,
2075 u16 soft_id, u8 queue, bool cloud_mode)
2077 s32 err = IXGBE_ERR_CONFIG;
2079 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
2082 * Check flow_type formatting, and bail out before we touch the hardware
2083 * if there's a configuration issue
2085 switch (input->formatted.flow_type) {
2086 case IXGBE_ATR_FLOW_TYPE_IPV4:
2087 case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4:
2088 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
2089 if (input->formatted.dst_port || input->formatted.src_port) {
2090 DEBUGOUT(" Error on src/dst port\n");
2091 return IXGBE_ERR_CONFIG;
2094 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2095 case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4:
2096 if (input->formatted.dst_port || input->formatted.src_port) {
2097 DEBUGOUT(" Error on src/dst port\n");
2098 return IXGBE_ERR_CONFIG;
2100 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2101 case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:
2102 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2103 case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4:
2104 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2105 IXGBE_ATR_L4TYPE_MASK;
2108 DEBUGOUT(" Error on flow type input\n");
2112 /* program input mask into the HW */
2113 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode);
2117 /* apply mask and compute/store hash */
2118 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
2120 /* program filters to filter memory */
2121 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
2122 soft_id, queue, cloud_mode);
2126 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2127 * @hw: pointer to hardware structure
2128 * @reg: analog register to read
2131 * Performs read operation to Omer analog register specified.
2133 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
2137 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
2139 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2141 IXGBE_WRITE_FLUSH(hw);
2143 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2144 *val = (u8)core_ctl;
2146 return IXGBE_SUCCESS;
2150 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2151 * @hw: pointer to hardware structure
2152 * @reg: atlas register to write
2153 * @val: value to write
2155 * Performs write operation to Omer analog register specified.
2157 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2161 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
2163 core_ctl = (reg << 8) | val;
2164 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2165 IXGBE_WRITE_FLUSH(hw);
2168 return IXGBE_SUCCESS;
2172 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2173 * @hw: pointer to hardware structure
2175 * Starts the hardware using the generic start_hw function
2176 * and the generation start_hw function.
2177 * Then performs revision-specific operations, if any.
2179 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2181 s32 ret_val = IXGBE_SUCCESS;
2183 DEBUGFUNC("ixgbe_start_hw_82599");
2185 ret_val = ixgbe_start_hw_generic(hw);
2186 if (ret_val != IXGBE_SUCCESS)
2189 ret_val = ixgbe_start_hw_gen2(hw);
2190 if (ret_val != IXGBE_SUCCESS)
2193 /* We need to run link autotry after the driver loads */
2194 hw->mac.autotry_restart = true;
2196 if (ret_val == IXGBE_SUCCESS)
2197 ret_val = ixgbe_verify_fw_version_82599(hw);
2203 * ixgbe_identify_phy_82599 - Get physical layer module
2204 * @hw: pointer to hardware structure
2206 * Determines the physical layer module found on the current adapter.
2207 * If PHY already detected, maintains current PHY type in hw struct,
2208 * otherwise executes the PHY detection routine.
2210 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2214 DEBUGFUNC("ixgbe_identify_phy_82599");
2216 /* Detect PHY if not unknown - returns success if already detected. */
2217 status = ixgbe_identify_phy_generic(hw);
2218 if (status != IXGBE_SUCCESS) {
2219 /* 82599 10GBASE-T requires an external PHY */
2220 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2223 status = ixgbe_identify_module_generic(hw);
2226 /* Set PHY type none if no PHY detected */
2227 if (hw->phy.type == ixgbe_phy_unknown) {
2228 hw->phy.type = ixgbe_phy_none;
2229 return IXGBE_SUCCESS;
2232 /* Return error if SFP module has been detected but is not supported */
2233 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2234 return IXGBE_ERR_SFP_NOT_SUPPORTED;
2240 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2241 * @hw: pointer to hardware structure
2243 * Determines physical layer capabilities of the current configuration.
2245 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2247 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2248 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2249 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2250 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2251 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2252 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2253 u16 ext_ability = 0;
2255 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2257 hw->phy.ops.identify(hw);
2259 switch (hw->phy.type) {
2261 case ixgbe_phy_cu_unknown:
2262 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2263 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2264 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2265 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2266 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2267 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2268 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
2269 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2275 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2276 case IXGBE_AUTOC_LMS_1G_AN:
2277 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2278 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2279 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2280 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2283 /* SFI mode so read SFP module */
2286 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2287 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2288 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2289 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2290 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2291 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2292 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2295 case IXGBE_AUTOC_LMS_10G_SERIAL:
2296 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2297 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2299 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2302 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2303 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2304 if (autoc & IXGBE_AUTOC_KX_SUPP)
2305 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2306 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2307 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2308 if (autoc & IXGBE_AUTOC_KR_SUPP)
2309 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2318 /* SFP check must be done last since DA modules are sometimes used to
2319 * test KR mode - we need to id KR mode correctly before SFP module.
2320 * Call identify_sfp because the pluggable module may have changed */
2321 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw);
2323 return physical_layer;
2327 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2328 * @hw: pointer to hardware structure
2329 * @regval: register value to write to RXCTRL
2331 * Enables the Rx DMA unit for 82599
2333 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2336 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2339 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2340 * If traffic is incoming before we enable the Rx unit, it could hang
2341 * the Rx DMA unit. Therefore, make sure the security engine is
2342 * completely disabled prior to enabling the Rx unit.
2345 hw->mac.ops.disable_sec_rx_path(hw);
2347 if (regval & IXGBE_RXCTRL_RXEN)
2348 ixgbe_enable_rx(hw);
2350 ixgbe_disable_rx(hw);
2352 hw->mac.ops.enable_sec_rx_path(hw);
2354 return IXGBE_SUCCESS;
2358 * ixgbe_verify_fw_version_82599 - verify FW version for 82599
2359 * @hw: pointer to hardware structure
2361 * Verifies that installed the firmware version is 0.6 or higher
2362 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2364 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2365 * if the FW version is not supported.
2367 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2369 s32 status = IXGBE_ERR_EEPROM_VERSION;
2370 u16 fw_offset, fw_ptp_cfg_offset;
2373 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2375 /* firmware check is only necessary for SFI devices */
2376 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2377 status = IXGBE_SUCCESS;
2378 goto fw_version_out;
2381 /* get the offset to the Firmware Module block */
2382 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
2383 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2384 "eeprom read at offset %d failed", IXGBE_FW_PTR);
2385 return IXGBE_ERR_EEPROM_VERSION;
2388 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2389 goto fw_version_out;
2391 /* get the offset to the Pass Through Patch Configuration block */
2392 if (hw->eeprom.ops.read(hw, (fw_offset +
2393 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2394 &fw_ptp_cfg_offset)) {
2395 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2396 "eeprom read at offset %d failed",
2398 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);
2399 return IXGBE_ERR_EEPROM_VERSION;
2402 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2403 goto fw_version_out;
2405 /* get the firmware version */
2406 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2407 IXGBE_FW_PATCH_VERSION_4), &fw_version)) {
2408 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2409 "eeprom read at offset %d failed",
2410 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);
2411 return IXGBE_ERR_EEPROM_VERSION;
2414 if (fw_version > 0x5)
2415 status = IXGBE_SUCCESS;
2422 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2423 * @hw: pointer to hardware structure
2425 * Returns true if the LESM FW module is present and enabled. Otherwise
2426 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2428 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2430 bool lesm_enabled = false;
2431 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2434 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2436 /* get the offset to the Firmware Module block */
2437 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2439 if ((status != IXGBE_SUCCESS) ||
2440 (fw_offset == 0) || (fw_offset == 0xFFFF))
2443 /* get the offset to the LESM Parameters block */
2444 status = hw->eeprom.ops.read(hw, (fw_offset +
2445 IXGBE_FW_LESM_PARAMETERS_PTR),
2446 &fw_lesm_param_offset);
2448 if ((status != IXGBE_SUCCESS) ||
2449 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2452 /* get the LESM state word */
2453 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2454 IXGBE_FW_LESM_STATE_1),
2457 if ((status == IXGBE_SUCCESS) &&
2458 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2459 lesm_enabled = true;
2462 return lesm_enabled;
2466 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2467 * fastest available method
2469 * @hw: pointer to hardware structure
2470 * @offset: offset of word in EEPROM to read
2471 * @words: number of words
2472 * @data: word(s) read from the EEPROM
2474 * Retrieves 16 bit word(s) read from EEPROM
2476 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2477 u16 words, u16 *data)
2479 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2480 s32 ret_val = IXGBE_ERR_CONFIG;
2482 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2485 * If EEPROM is detected and can be addressed using 14 bits,
2486 * use EERD otherwise use bit bang
2488 if ((eeprom->type == ixgbe_eeprom_spi) &&
2489 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2490 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2493 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2501 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2502 * fastest available method
2504 * @hw: pointer to hardware structure
2505 * @offset: offset of word in the EEPROM to read
2506 * @data: word read from the EEPROM
2508 * Reads a 16 bit word from the EEPROM
2510 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2511 u16 offset, u16 *data)
2513 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2514 s32 ret_val = IXGBE_ERR_CONFIG;
2516 DEBUGFUNC("ixgbe_read_eeprom_82599");
2519 * If EEPROM is detected and can be addressed using 14 bits,
2520 * use EERD otherwise use bit bang
2522 if ((eeprom->type == ixgbe_eeprom_spi) &&
2523 (offset <= IXGBE_EERD_MAX_ADDR))
2524 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2526 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2532 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2534 * @hw: pointer to hardware structure
2536 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2537 * full pipeline reset. This function assumes the SW/FW lock is held.
2539 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2543 u32 i, autoc_reg, autoc2_reg;
2545 /* Enable link if disabled in NVM */
2546 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2547 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2548 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2549 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2550 IXGBE_WRITE_FLUSH(hw);
2553 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2554 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2555 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2556 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
2557 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));
2558 /* Wait for AN to leave state 0 */
2559 for (i = 0; i < 10; i++) {
2561 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2562 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2566 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2567 DEBUGOUT("auto negotiation not completed\n");
2568 ret_val = IXGBE_ERR_RESET_FAILED;
2569 goto reset_pipeline_out;
2572 ret_val = IXGBE_SUCCESS;
2575 /* Write AUTOC register with original LMS field and Restart_AN */
2576 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2577 IXGBE_WRITE_FLUSH(hw);
2584 * ixgbe_read_i2c_byte_82599 - Reads 8 bit word over I2C
2585 * @hw: pointer to hardware structure
2586 * @byte_offset: byte offset to read
2589 * Performs byte read operation to SFP module's EEPROM over I2C interface at
2590 * a specified device address.
2592 STATIC s32 ixgbe_read_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2593 u8 dev_addr, u8 *data)
2599 DEBUGFUNC("ixgbe_read_i2c_byte_82599");
2601 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2602 /* Acquire I2C bus ownership. */
2603 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2604 esdp |= IXGBE_ESDP_SDP0;
2605 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2606 IXGBE_WRITE_FLUSH(hw);
2609 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2610 if (esdp & IXGBE_ESDP_SDP1)
2618 DEBUGOUT("Driver can't access resource,"
2619 " acquiring I2C bus timeout.\n");
2620 status = IXGBE_ERR_I2C;
2621 goto release_i2c_access;
2625 status = ixgbe_read_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2629 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2630 /* Release I2C bus ownership. */
2631 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2632 esdp &= ~IXGBE_ESDP_SDP0;
2633 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2634 IXGBE_WRITE_FLUSH(hw);
2641 * ixgbe_write_i2c_byte_82599 - Writes 8 bit word over I2C
2642 * @hw: pointer to hardware structure
2643 * @byte_offset: byte offset to write
2644 * @data: value to write
2646 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2647 * a specified device address.
2649 STATIC s32 ixgbe_write_i2c_byte_82599(struct ixgbe_hw *hw, u8 byte_offset,
2650 u8 dev_addr, u8 data)
2656 DEBUGFUNC("ixgbe_write_i2c_byte_82599");
2658 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2659 /* Acquire I2C bus ownership. */
2660 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2661 esdp |= IXGBE_ESDP_SDP0;
2662 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2663 IXGBE_WRITE_FLUSH(hw);
2666 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2667 if (esdp & IXGBE_ESDP_SDP1)
2675 DEBUGOUT("Driver can't access resource,"
2676 " acquiring I2C bus timeout.\n");
2677 status = IXGBE_ERR_I2C;
2678 goto release_i2c_access;
2682 status = ixgbe_write_i2c_byte_generic(hw, byte_offset, dev_addr, data);
2686 if (hw->phy.qsfp_shared_i2c_bus == TRUE) {
2687 /* Release I2C bus ownership. */
2688 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2689 esdp &= ~IXGBE_ESDP_SDP0;
2690 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp);
2691 IXGBE_WRITE_FLUSH(hw);