1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82599.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
39 #ident "$Id: ixgbe_82599.c,v 1.334 2013/12/04 22:34:00 jtkirshe Exp $"
41 #define IXGBE_82599_MAX_TX_QUEUES 128
42 #define IXGBE_82599_MAX_RX_QUEUES 128
43 #define IXGBE_82599_RAR_ENTRIES 128
44 #define IXGBE_82599_MC_TBL_SIZE 128
45 #define IXGBE_82599_VFT_TBL_SIZE 128
46 #define IXGBE_82599_RX_PB_SIZE 512
48 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
49 ixgbe_link_speed speed,
50 bool autoneg_wait_to_complete);
51 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
53 u16 offset, u16 *data);
54 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
57 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
59 struct ixgbe_mac_info *mac = &hw->mac;
61 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
64 * enable the laser control functions for SFP+ fiber
67 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
68 !ixgbe_mng_enabled(hw)) {
69 mac->ops.disable_tx_laser =
70 &ixgbe_disable_tx_laser_multispeed_fiber;
71 mac->ops.enable_tx_laser =
72 &ixgbe_enable_tx_laser_multispeed_fiber;
73 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
76 mac->ops.disable_tx_laser = NULL;
77 mac->ops.enable_tx_laser = NULL;
78 mac->ops.flap_tx_laser = NULL;
81 if (hw->phy.multispeed_fiber) {
82 /* Set up dual speed SFP+ support */
83 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
85 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
86 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
87 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
88 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
89 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
91 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
97 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
98 * @hw: pointer to hardware structure
100 * Initialize any function pointers that were not able to be
101 * set during init_shared_code because the PHY/SFP type was
102 * not known. Perform the SFP init if necessary.
105 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
107 struct ixgbe_mac_info *mac = &hw->mac;
108 struct ixgbe_phy_info *phy = &hw->phy;
109 s32 ret_val = IXGBE_SUCCESS;
111 DEBUGFUNC("ixgbe_init_phy_ops_82599");
113 /* Identify the PHY or SFP module */
114 ret_val = phy->ops.identify(hw);
115 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
116 goto init_phy_ops_out;
118 /* Setup function pointers based on detected SFP module and speeds */
119 ixgbe_init_mac_link_ops_82599(hw);
120 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
121 hw->phy.ops.reset = NULL;
123 /* If copper media, overwrite with copper function pointers */
124 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
125 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
126 mac->ops.get_link_capabilities =
127 &ixgbe_get_copper_link_capabilities_generic;
130 /* Set necessary function pointers based on PHY type */
131 switch (hw->phy.type) {
133 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
134 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
135 phy->ops.get_firmware_version =
136 &ixgbe_get_phy_firmware_version_tnx;
145 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
147 s32 ret_val = IXGBE_SUCCESS;
148 u16 list_offset, data_offset, data_value;
150 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
152 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
153 ixgbe_init_mac_link_ops_82599(hw);
155 hw->phy.ops.reset = NULL;
157 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
159 if (ret_val != IXGBE_SUCCESS)
162 /* PHY config will finish before releasing the semaphore */
163 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
164 IXGBE_GSSR_MAC_CSR_SM);
165 if (ret_val != IXGBE_SUCCESS) {
166 ret_val = IXGBE_ERR_SWFW_SYNC;
170 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
172 while (data_value != 0xffff) {
173 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
174 IXGBE_WRITE_FLUSH(hw);
175 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
179 /* Release the semaphore */
180 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
181 /* Delay obtaining semaphore again to allow FW access
182 * prot_autoc_write uses the semaphore too.
184 msec_delay(hw->eeprom.semaphore_delay);
186 /* Restart DSP and set SFI mode */
187 ret_val = hw->mac.ops.prot_autoc_write(hw,
188 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
192 DEBUGOUT("sfp module setup not complete\n");
193 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
203 /* Release the semaphore */
204 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
205 /* Delay obtaining semaphore again to allow FW access */
206 msec_delay(hw->eeprom.semaphore_delay);
207 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
208 "eeprom read at offset %d failed", data_offset);
209 return IXGBE_ERR_PHY;
213 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
214 * @hw: pointer to hardware structure
215 * @locked: Return the if we locked for this read.
216 * @reg_val: Value we read from AUTOC
218 * For this part (82599) we need to wrap read-modify-writes with a possible
219 * FW/SW lock. It is assumed this lock will be freed with the next
220 * prot_autoc_write_82599().
222 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
227 /* If LESM is on then we need to hold the SW/FW semaphore. */
228 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
229 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
230 IXGBE_GSSR_MAC_CSR_SM);
231 if (ret_val != IXGBE_SUCCESS)
232 return IXGBE_ERR_SWFW_SYNC;
237 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
238 return IXGBE_SUCCESS;
242 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
243 * @hw: pointer to hardware structure
244 * @reg_val: value to write to AUTOC
245 * @locked: bool to indicate whether the SW/FW lock was already taken by
246 * previous proc_autoc_read_82599.
248 * This part (82599) may need to hold the SW/FW lock around all writes to
249 * AUTOC. Likewise after a write we need to do a pipeline reset.
251 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
253 s32 ret_val = IXGBE_SUCCESS;
255 /* Blocked by MNG FW so bail */
256 if (ixgbe_check_reset_blocked(hw))
259 /* We only need to get the lock if:
260 * - We didn't do it already (in the read part of a read-modify-write)
263 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
264 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
265 IXGBE_GSSR_MAC_CSR_SM);
266 if (ret_val != IXGBE_SUCCESS)
267 return IXGBE_ERR_SWFW_SYNC;
272 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
273 ret_val = ixgbe_reset_pipeline_82599(hw);
276 /* Free the SW/FW semaphore as we either grabbed it here or
277 * already had it when this function was called.
280 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
286 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
287 * @hw: pointer to hardware structure
289 * Initialize the function pointers and assign the MAC type for 82599.
290 * Does not touch the hardware.
293 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
295 struct ixgbe_mac_info *mac = &hw->mac;
296 struct ixgbe_phy_info *phy = &hw->phy;
297 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
300 DEBUGFUNC("ixgbe_init_ops_82599");
302 ixgbe_init_phy_ops_generic(hw);
303 ret_val = ixgbe_init_ops_generic(hw);
306 phy->ops.identify = &ixgbe_identify_phy_82599;
307 phy->ops.init = &ixgbe_init_phy_ops_82599;
310 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
311 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
312 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
313 mac->ops.get_supported_physical_layer =
314 &ixgbe_get_supported_physical_layer_82599;
315 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
316 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
317 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
318 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
319 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
320 mac->ops.start_hw = &ixgbe_start_hw_82599;
321 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
322 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
323 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
324 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
325 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
326 mac->ops.prot_autoc_read = &prot_autoc_read_82599;
327 mac->ops.prot_autoc_write = &prot_autoc_write_82599;
329 /* RAR, Multicast, VLAN */
330 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
331 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
332 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
333 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
334 mac->rar_highwater = 1;
335 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
336 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
337 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
338 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
339 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
340 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
341 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
344 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
345 mac->ops.check_link = &ixgbe_check_mac_link_generic;
346 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
347 ixgbe_init_mac_link_ops_82599(hw);
349 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
350 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
351 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
352 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
353 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
354 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
355 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
357 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
358 IXGBE_FWSM_MODE_MASK) ? true : false;
360 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
363 eeprom->ops.read = &ixgbe_read_eeprom_82599;
364 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
366 /* Manageability interface */
367 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
370 mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
376 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
377 * @hw: pointer to hardware structure
378 * @speed: pointer to link speed
379 * @autoneg: true when autoneg or autotry is enabled
381 * Determines the link capabilities by reading the AUTOC register.
383 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
384 ixgbe_link_speed *speed,
387 s32 status = IXGBE_SUCCESS;
390 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
393 /* Check if 1G SFP module. */
394 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
395 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
396 #ifdef SUPPORT_1000BASE_LX
397 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
398 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
400 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
401 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
402 *speed = IXGBE_LINK_SPEED_1GB_FULL;
408 * Determine link capabilities based on the stored value of AUTOC,
409 * which represents EEPROM defaults. If AUTOC value has not
410 * been stored, use the current register values.
412 if (hw->mac.orig_link_settings_stored)
413 autoc = hw->mac.orig_autoc;
415 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
417 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
418 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
419 *speed = IXGBE_LINK_SPEED_1GB_FULL;
423 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
424 *speed = IXGBE_LINK_SPEED_10GB_FULL;
428 case IXGBE_AUTOC_LMS_1G_AN:
429 *speed = IXGBE_LINK_SPEED_1GB_FULL;
433 case IXGBE_AUTOC_LMS_10G_SERIAL:
434 *speed = IXGBE_LINK_SPEED_10GB_FULL;
438 case IXGBE_AUTOC_LMS_KX4_KX_KR:
439 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
440 *speed = IXGBE_LINK_SPEED_UNKNOWN;
441 if (autoc & IXGBE_AUTOC_KR_SUPP)
442 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
443 if (autoc & IXGBE_AUTOC_KX4_SUPP)
444 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
445 if (autoc & IXGBE_AUTOC_KX_SUPP)
446 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
450 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
451 *speed = IXGBE_LINK_SPEED_100_FULL;
452 if (autoc & IXGBE_AUTOC_KR_SUPP)
453 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
454 if (autoc & IXGBE_AUTOC_KX4_SUPP)
455 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
456 if (autoc & IXGBE_AUTOC_KX_SUPP)
457 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
461 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
462 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
467 status = IXGBE_ERR_LINK_SETUP;
472 if (hw->phy.multispeed_fiber) {
473 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
474 IXGBE_LINK_SPEED_1GB_FULL;
484 * ixgbe_get_media_type_82599 - Get media type
485 * @hw: pointer to hardware structure
487 * Returns the media type (fiber, copper, backplane)
489 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
491 enum ixgbe_media_type media_type;
493 DEBUGFUNC("ixgbe_get_media_type_82599");
495 /* Detect if there is a copper PHY attached. */
496 switch (hw->phy.type) {
497 case ixgbe_phy_cu_unknown:
499 media_type = ixgbe_media_type_copper;
505 switch (hw->device_id) {
506 case IXGBE_DEV_ID_82599_KX4:
507 case IXGBE_DEV_ID_82599_KX4_MEZZ:
508 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
509 case IXGBE_DEV_ID_82599_KR:
510 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
511 case IXGBE_DEV_ID_82599_XAUI_LOM:
512 /* Default device ID is mezzanine card KX/KX4 */
513 media_type = ixgbe_media_type_backplane;
515 case IXGBE_DEV_ID_82599_SFP:
516 case IXGBE_DEV_ID_82599_SFP_FCOE:
517 case IXGBE_DEV_ID_82599_SFP_EM:
518 case IXGBE_DEV_ID_82599_SFP_SF2:
519 case IXGBE_DEV_ID_82599_SFP_SF_QP:
520 case IXGBE_DEV_ID_82599EN_SFP:
521 media_type = ixgbe_media_type_fiber;
523 case IXGBE_DEV_ID_82599_CX4:
524 media_type = ixgbe_media_type_cx4;
526 case IXGBE_DEV_ID_82599_T3_LOM:
527 media_type = ixgbe_media_type_copper;
530 media_type = ixgbe_media_type_unknown;
538 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
539 * @hw: pointer to hardware structure
541 * Disables link during D3 power down sequence.
544 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
546 u32 autoc2_reg, fwsm;
549 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
550 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
552 /* Check to see if MNG FW could be enabled */
553 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
555 if (((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) &&
557 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
558 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
559 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
560 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
565 * ixgbe_start_mac_link_82599 - Setup MAC link settings
566 * @hw: pointer to hardware structure
567 * @autoneg_wait_to_complete: true when waiting for completion is needed
569 * Configures link settings based on values in the ixgbe_hw struct.
570 * Restarts the link. Performs autonegotiation if needed.
572 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
573 bool autoneg_wait_to_complete)
578 s32 status = IXGBE_SUCCESS;
579 bool got_lock = false;
581 DEBUGFUNC("ixgbe_start_mac_link_82599");
584 /* reset_pipeline requires us to hold this lock as it writes to
587 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
588 status = hw->mac.ops.acquire_swfw_sync(hw,
589 IXGBE_GSSR_MAC_CSR_SM);
590 if (status != IXGBE_SUCCESS)
597 ixgbe_reset_pipeline_82599(hw);
600 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
602 /* Only poll for autoneg to complete if specified to do so */
603 if (autoneg_wait_to_complete) {
604 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
605 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
606 IXGBE_AUTOC_LMS_KX4_KX_KR ||
607 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
608 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
609 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
610 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
611 links_reg = 0; /* Just in case Autoneg time = 0 */
612 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
613 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
614 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
618 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
619 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
620 DEBUGOUT("Autoneg did not complete.\n");
625 /* Add delay to filter out noises during initial link setup */
633 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
634 * @hw: pointer to hardware structure
636 * The base drivers may require better control over SFP+ module
637 * PHY states. This includes selectively shutting down the Tx
638 * laser on the PHY, effectively halting physical link.
640 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
642 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
644 /* Blocked by MNG FW so bail */
645 if (ixgbe_check_reset_blocked(hw))
648 /* Disable Tx laser; allow 100us to go dark per spec */
649 esdp_reg |= IXGBE_ESDP_SDP3;
650 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
651 IXGBE_WRITE_FLUSH(hw);
656 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
657 * @hw: pointer to hardware structure
659 * The base drivers may require better control over SFP+ module
660 * PHY states. This includes selectively turning on the Tx
661 * laser on the PHY, effectively starting physical link.
663 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
665 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
667 /* Enable Tx laser; allow 100ms to light up */
668 esdp_reg &= ~IXGBE_ESDP_SDP3;
669 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
670 IXGBE_WRITE_FLUSH(hw);
675 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
676 * @hw: pointer to hardware structure
678 * When the driver changes the link speeds that it can support,
679 * it sets autotry_restart to true to indicate that we need to
680 * initiate a new autotry session with the link partner. To do
681 * so, we set the speed then disable and re-enable the Tx laser, to
682 * alert the link partner that it also needs to restart autotry on its
683 * end. This is consistent with true clause 37 autoneg, which also
684 * involves a loss of signal.
686 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
688 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
690 /* Blocked by MNG FW so bail */
691 if (ixgbe_check_reset_blocked(hw))
694 if (hw->mac.autotry_restart) {
695 ixgbe_disable_tx_laser_multispeed_fiber(hw);
696 ixgbe_enable_tx_laser_multispeed_fiber(hw);
697 hw->mac.autotry_restart = false;
703 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
704 * @hw: pointer to hardware structure
705 * @speed: new link speed
706 * @autoneg_wait_to_complete: true when waiting for completion is needed
708 * Set the link speed in the AUTOC register and restarts link.
710 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
711 ixgbe_link_speed speed,
712 bool autoneg_wait_to_complete)
714 s32 status = IXGBE_SUCCESS;
715 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
716 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
718 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
720 bool autoneg, link_up = false;
722 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
724 /* Mask off requested but non-supported speeds */
725 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
726 if (status != IXGBE_SUCCESS)
732 * Try each speed one by one, highest priority first. We do this in
733 * software because 10gb fiber doesn't support speed autonegotiation.
735 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
737 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
739 /* If we already have link at this speed, just jump out */
740 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
741 if (status != IXGBE_SUCCESS)
744 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
747 /* Set the module link speed */
748 switch (hw->phy.media_type) {
749 case ixgbe_media_type_fiber:
750 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
751 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
752 IXGBE_WRITE_FLUSH(hw);
755 DEBUGOUT("Unexpected media type.\n");
759 /* Allow module to change analog characteristics (1G->10G) */
762 status = ixgbe_setup_mac_link_82599(hw,
763 IXGBE_LINK_SPEED_10GB_FULL,
764 autoneg_wait_to_complete);
765 if (status != IXGBE_SUCCESS)
768 /* Flap the tx laser if it has not already been done */
769 ixgbe_flap_tx_laser(hw);
772 * Wait for the controller to acquire link. Per IEEE 802.3ap,
773 * Section 73.10.2, we may have to wait up to 500ms if KR is
774 * attempted. 82599 uses the same timing for 10g SFI.
776 for (i = 0; i < 5; i++) {
777 /* Wait for the link partner to also set speed */
780 /* If we have link, just jump out */
781 status = ixgbe_check_link(hw, &link_speed,
783 if (status != IXGBE_SUCCESS)
791 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
793 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
794 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
796 /* If we already have link at this speed, just jump out */
797 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
798 if (status != IXGBE_SUCCESS)
801 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
804 /* Set the module link speed */
805 switch (hw->phy.media_type) {
806 case ixgbe_media_type_fiber:
807 esdp_reg &= ~IXGBE_ESDP_SDP5;
808 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
809 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
810 IXGBE_WRITE_FLUSH(hw);
813 DEBUGOUT("Unexpected media type.\n");
817 /* Allow module to change analog characteristics (10G->1G) */
820 status = ixgbe_setup_mac_link_82599(hw,
821 IXGBE_LINK_SPEED_1GB_FULL,
822 autoneg_wait_to_complete);
823 if (status != IXGBE_SUCCESS)
826 /* Flap the Tx laser if it has not already been done */
827 ixgbe_flap_tx_laser(hw);
829 /* Wait for the link partner to also set speed */
832 /* If we have link, just jump out */
833 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
834 if (status != IXGBE_SUCCESS)
842 * We didn't get link. Configure back to the highest speed we tried,
843 * (if there was more than one). We call ourselves back with just the
844 * single highest speed that the user requested.
847 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
848 highest_link_speed, autoneg_wait_to_complete);
851 /* Set autoneg_advertised value based on input link speed */
852 hw->phy.autoneg_advertised = 0;
854 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
855 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
857 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
858 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
864 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
865 * @hw: pointer to hardware structure
866 * @speed: new link speed
867 * @autoneg_wait_to_complete: true when waiting for completion is needed
869 * Implements the Intel SmartSpeed algorithm.
871 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
872 ixgbe_link_speed speed,
873 bool autoneg_wait_to_complete)
875 s32 status = IXGBE_SUCCESS;
876 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
878 bool link_up = false;
879 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
881 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
883 /* Set autoneg_advertised value based on input link speed */
884 hw->phy.autoneg_advertised = 0;
886 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
887 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
889 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
890 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
892 if (speed & IXGBE_LINK_SPEED_100_FULL)
893 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
896 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
897 * autoneg advertisement if link is unable to be established at the
898 * highest negotiated rate. This can sometimes happen due to integrity
899 * issues with the physical media connection.
902 /* First, try to get link with full advertisement */
903 hw->phy.smart_speed_active = false;
904 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
905 status = ixgbe_setup_mac_link_82599(hw, speed,
906 autoneg_wait_to_complete);
907 if (status != IXGBE_SUCCESS)
911 * Wait for the controller to acquire link. Per IEEE 802.3ap,
912 * Section 73.10.2, we may have to wait up to 500ms if KR is
913 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
914 * Table 9 in the AN MAS.
916 for (i = 0; i < 5; i++) {
919 /* If we have link, just jump out */
920 status = ixgbe_check_link(hw, &link_speed, &link_up,
922 if (status != IXGBE_SUCCESS)
931 * We didn't get link. If we advertised KR plus one of KX4/KX
932 * (or BX4/BX), then disable KR and try again.
934 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
935 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
938 /* Turn SmartSpeed on to disable KR support */
939 hw->phy.smart_speed_active = true;
940 status = ixgbe_setup_mac_link_82599(hw, speed,
941 autoneg_wait_to_complete);
942 if (status != IXGBE_SUCCESS)
946 * Wait for the controller to acquire link. 600ms will allow for
947 * the AN link_fail_inhibit_timer as well for multiple cycles of
948 * parallel detect, both 10g and 1g. This allows for the maximum
949 * connect attempts as defined in the AN MAS table 73-7.
951 for (i = 0; i < 6; i++) {
954 /* If we have link, just jump out */
955 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
956 if (status != IXGBE_SUCCESS)
963 /* We didn't get link. Turn SmartSpeed back off. */
964 hw->phy.smart_speed_active = false;
965 status = ixgbe_setup_mac_link_82599(hw, speed,
966 autoneg_wait_to_complete);
969 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
970 DEBUGOUT("Smartspeed has downgraded the link speed "
971 "from the maximum advertised\n");
976 * ixgbe_setup_mac_link_82599 - Set MAC link speed
977 * @hw: pointer to hardware structure
978 * @speed: new link speed
979 * @autoneg_wait_to_complete: true when waiting for completion is needed
981 * Set the link speed in the AUTOC register and restarts link.
983 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
984 ixgbe_link_speed speed,
985 bool autoneg_wait_to_complete)
987 bool autoneg = false;
988 s32 status = IXGBE_SUCCESS;
989 u32 pma_pmd_1g, link_mode;
990 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */
991 u32 orig_autoc = 0; /* holds the cached value of AUTOC register */
992 u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */
993 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
994 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
997 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
999 DEBUGFUNC("ixgbe_setup_mac_link_82599");
1001 /* Check to see if speed passed in is supported. */
1002 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
1006 speed &= link_capabilities;
1008 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
1009 status = IXGBE_ERR_LINK_SETUP;
1013 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
1014 if (hw->mac.orig_link_settings_stored)
1015 orig_autoc = hw->mac.orig_autoc;
1019 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
1020 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1022 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1023 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1024 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1025 /* Set KX4/KX/KR support according to speed requested */
1026 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
1027 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1028 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
1029 autoc |= IXGBE_AUTOC_KX4_SUPP;
1030 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
1031 (hw->phy.smart_speed_active == false))
1032 autoc |= IXGBE_AUTOC_KR_SUPP;
1034 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1035 autoc |= IXGBE_AUTOC_KX_SUPP;
1036 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
1037 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
1038 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
1039 /* Switch from 1G SFI to 10G SFI if requested */
1040 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
1041 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
1042 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1043 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
1045 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
1046 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
1047 /* Switch from 10G SFI to 1G SFI if requested */
1048 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1049 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
1050 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1052 autoc |= IXGBE_AUTOC_LMS_1G_AN;
1054 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
1058 if (autoc != current_autoc) {
1060 status = hw->mac.ops.prot_autoc_write(hw, autoc, false);
1061 if (status != IXGBE_SUCCESS)
1064 /* Only poll for autoneg to complete if specified to do so */
1065 if (autoneg_wait_to_complete) {
1066 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1067 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1068 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1069 links_reg = 0; /*Just in case Autoneg time=0*/
1070 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1072 IXGBE_READ_REG(hw, IXGBE_LINKS);
1073 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
1077 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
1079 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
1080 DEBUGOUT("Autoneg did not complete.\n");
1085 /* Add delay to filter out noises during initial link setup */
1094 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
1095 * @hw: pointer to hardware structure
1096 * @speed: new link speed
1097 * @autoneg_wait_to_complete: true if waiting is needed to complete
1099 * Restarts link on PHY and MAC based on settings passed in.
1101 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1102 ixgbe_link_speed speed,
1103 bool autoneg_wait_to_complete)
1107 DEBUGFUNC("ixgbe_setup_copper_link_82599");
1109 /* Setup the PHY according to input speed */
1110 status = hw->phy.ops.setup_link_speed(hw, speed,
1111 autoneg_wait_to_complete);
1113 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1119 * ixgbe_reset_hw_82599 - Perform hardware reset
1120 * @hw: pointer to hardware structure
1122 * Resets the hardware by resetting the transmit and receive units, masks
1123 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1126 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1128 ixgbe_link_speed link_speed;
1131 u32 i, autoc, autoc2;
1133 bool link_up = false;
1135 DEBUGFUNC("ixgbe_reset_hw_82599");
1137 /* Call adapter stop to disable tx/rx and clear interrupts */
1138 status = hw->mac.ops.stop_adapter(hw);
1139 if (status != IXGBE_SUCCESS)
1142 /* flush pending Tx transactions */
1143 ixgbe_clear_tx_pending(hw);
1145 /* PHY ops must be identified and initialized prior to reset */
1147 /* Identify PHY and related function pointers */
1148 status = hw->phy.ops.init(hw);
1150 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1153 /* Setup SFP module if there is one present. */
1154 if (hw->phy.sfp_setup_needed) {
1155 status = hw->mac.ops.setup_sfp(hw);
1156 hw->phy.sfp_setup_needed = false;
1159 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1163 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1164 hw->phy.ops.reset(hw);
1166 /* remember AUTOC from before we reset */
1167 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
1171 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1172 * If link reset is used when link is up, it might reset the PHY when
1173 * mng is using it. If link is down or the flag to force full link
1174 * reset is set, then perform link reset.
1176 ctrl = IXGBE_CTRL_LNK_RST;
1177 if (!hw->force_full_reset) {
1178 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1180 ctrl = IXGBE_CTRL_RST;
1183 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1184 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1185 IXGBE_WRITE_FLUSH(hw);
1187 /* Poll for reset bit to self-clear meaning reset is complete */
1188 for (i = 0; i < 10; i++) {
1190 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1191 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1195 if (ctrl & IXGBE_CTRL_RST_MASK) {
1196 status = IXGBE_ERR_RESET_FAILED;
1197 DEBUGOUT("Reset polling failed to complete.\n");
1203 * Double resets are required for recovery from certain error
1204 * conditions. Between resets, it is necessary to stall to
1205 * allow time for any pending HW events to complete.
1207 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1208 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1213 * Store the original AUTOC/AUTOC2 values if they have not been
1214 * stored off yet. Otherwise restore the stored original
1215 * values since the reset operation sets back to defaults.
1217 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1218 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1220 /* Enable link if disabled in NVM */
1221 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1222 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1223 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1224 IXGBE_WRITE_FLUSH(hw);
1227 if (hw->mac.orig_link_settings_stored == false) {
1228 hw->mac.orig_autoc = autoc;
1229 hw->mac.orig_autoc2 = autoc2;
1230 hw->mac.orig_link_settings_stored = true;
1233 /* If MNG FW is running on a multi-speed device that
1234 * doesn't autoneg with out driver support we need to
1235 * leave LMS in the state it was before we MAC reset.
1236 * Likewise if we support WoL we don't want change the
1239 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
1241 hw->mac.orig_autoc =
1242 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1245 if (autoc != hw->mac.orig_autoc) {
1246 status = hw->mac.ops.prot_autoc_write(hw,
1249 if (status != IXGBE_SUCCESS)
1253 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1254 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1255 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1256 autoc2 |= (hw->mac.orig_autoc2 &
1257 IXGBE_AUTOC2_UPPER_MASK);
1258 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1262 /* Store the permanent mac address */
1263 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1266 * Store MAC address from RAR0, clear receive address registers, and
1267 * clear the multicast table. Also reset num_rar_entries to 128,
1268 * since we modify this value when programming the SAN MAC address.
1270 hw->mac.num_rar_entries = 128;
1271 hw->mac.ops.init_rx_addrs(hw);
1273 /* Store the permanent SAN mac address */
1274 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1276 /* Add the SAN MAC address to the RAR only if it's a valid address */
1277 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1278 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1279 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1281 /* Save the SAN MAC RAR index */
1282 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1284 /* Reserve the last RAR for the SAN MAC address */
1285 hw->mac.num_rar_entries--;
1288 /* Store the alternative WWNN/WWPN prefix */
1289 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1290 &hw->mac.wwpn_prefix);
1297 * ixgbe_fdir_check_cmd_complete - poll to check whether FDIRCMD is complete
1298 * @hw: pointer to hardware structure
1300 STATIC s32 ixgbe_fdir_check_cmd_complete(struct ixgbe_hw *hw)
1304 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1305 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1306 IXGBE_FDIRCMD_CMD_MASK))
1307 return IXGBE_SUCCESS;
1311 return IXGBE_ERR_FDIR_CMD_INCOMPLETE;
1315 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1316 * @hw: pointer to hardware structure
1318 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1322 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1323 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1325 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1328 * Before starting reinitialization process,
1329 * FDIRCMD.CMD must be zero.
1331 err = ixgbe_fdir_check_cmd_complete(hw);
1333 DEBUGOUT("Flow Director previous command did not complete, aborting table re-initialization.\n");
1337 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1338 IXGBE_WRITE_FLUSH(hw);
1340 * 82599 adapters flow director init flow cannot be restarted,
1341 * Workaround 82599 silicon errata by performing the following steps
1342 * before re-writing the FDIRCTRL control register with the same value.
1343 * - write 1 to bit 8 of FDIRCMD register &
1344 * - write 0 to bit 8 of FDIRCMD register
1346 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1347 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1348 IXGBE_FDIRCMD_CLEARHT));
1349 IXGBE_WRITE_FLUSH(hw);
1350 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1351 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1352 ~IXGBE_FDIRCMD_CLEARHT));
1353 IXGBE_WRITE_FLUSH(hw);
1355 * Clear FDIR Hash register to clear any leftover hashes
1356 * waiting to be programmed.
1358 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1359 IXGBE_WRITE_FLUSH(hw);
1361 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1362 IXGBE_WRITE_FLUSH(hw);
1364 /* Poll init-done after we write FDIRCTRL register */
1365 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1366 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1367 IXGBE_FDIRCTRL_INIT_DONE)
1371 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1372 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1373 return IXGBE_ERR_FDIR_REINIT_FAILED;
1376 /* Clear FDIR statistics registers (read to clear) */
1377 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1378 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1379 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1380 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1381 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1383 return IXGBE_SUCCESS;
1387 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1388 * @hw: pointer to hardware structure
1389 * @fdirctrl: value to write to flow director control register
1391 STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1395 DEBUGFUNC("ixgbe_fdir_enable_82599");
1397 /* Prime the keys for hashing */
1398 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1399 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1402 * Poll init-done after we write the register. Estimated times:
1403 * 10G: PBALLOC = 11b, timing is 60us
1404 * 1G: PBALLOC = 11b, timing is 600us
1405 * 100M: PBALLOC = 11b, timing is 6ms
1407 * Multiple these timings by 4 if under full Rx load
1409 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1410 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1411 * this might not finish in our poll time, but we can live with that
1414 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1415 IXGBE_WRITE_FLUSH(hw);
1416 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1417 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1418 IXGBE_FDIRCTRL_INIT_DONE)
1423 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1424 DEBUGOUT("Flow Director poll time exceeded!\n");
1428 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1429 * @hw: pointer to hardware structure
1430 * @fdirctrl: value to write to flow director control register, initially
1431 * contains just the value of the Rx packet buffer allocation
1433 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1435 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1438 * Continue setup of fdirctrl register bits:
1439 * Move the flexible bytes to use the ethertype - shift 6 words
1440 * Set the maximum length per hash bucket to 0xA filters
1441 * Send interrupt when 64 filters are left
1443 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1444 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1445 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1447 /* write hashes and fdirctrl register, poll for completion */
1448 ixgbe_fdir_enable_82599(hw, fdirctrl);
1450 return IXGBE_SUCCESS;
1454 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1455 * @hw: pointer to hardware structure
1456 * @fdirctrl: value to write to flow director control register, initially
1457 * contains just the value of the Rx packet buffer allocation
1458 * @cloud_mode: true - cloud mode, false - other mode
1460 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
1463 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1466 * Continue setup of fdirctrl register bits:
1467 * Turn perfect match filtering on
1468 * Report hash in RSS field of Rx wb descriptor
1469 * Initialize the drop queue
1470 * Move the flexible bytes to use the ethertype - shift 6 words
1471 * Set the maximum length per hash bucket to 0xA filters
1472 * Send interrupt when 64 (0x4 * 16) filters are left
1474 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1475 IXGBE_FDIRCTRL_REPORT_STATUS |
1476 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1477 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1478 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1479 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1482 /* write hashes and fdirctrl register, poll for completion */
1483 ixgbe_fdir_enable_82599(hw, fdirctrl);
1485 return IXGBE_SUCCESS;
1489 * These defines allow us to quickly generate all of the necessary instructions
1490 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1491 * for values 0 through 15
1493 #define IXGBE_ATR_COMMON_HASH_KEY \
1494 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1495 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1498 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1499 common_hash ^= lo_hash_dword >> n; \
1500 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1501 bucket_hash ^= lo_hash_dword >> n; \
1502 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1503 sig_hash ^= lo_hash_dword << (16 - n); \
1504 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1505 common_hash ^= hi_hash_dword >> n; \
1506 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1507 bucket_hash ^= hi_hash_dword >> n; \
1508 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1509 sig_hash ^= hi_hash_dword << (16 - n); \
1513 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1514 * @stream: input bitstream to compute the hash on
1516 * This function is almost identical to the function above but contains
1517 * several optimizations such as unwinding all of the loops, letting the
1518 * compiler work out all of the conditional ifs since the keys are static
1519 * defines, and computing two keys at once since the hashed dword stream
1520 * will be the same for both keys.
1522 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1523 union ixgbe_atr_hash_dword common)
1525 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1526 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1528 /* record the flow_vm_vlan bits as they are a key part to the hash */
1529 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1531 /* generate common hash dword */
1532 hi_hash_dword = IXGBE_NTOHL(common.dword);
1534 /* low dword is word swapped version of common */
1535 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1537 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1538 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1540 /* Process bits 0 and 16 */
1541 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1544 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1545 * delay this because bit 0 of the stream should not be processed
1546 * so we do not add the VLAN until after bit 0 was processed
1548 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1550 /* Process remaining 30 bit of the key */
1551 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1552 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1553 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1554 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1555 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1556 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1557 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1558 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1559 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1560 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1561 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1562 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1563 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1564 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1565 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1567 /* combine common_hash result with signature and bucket hashes */
1568 bucket_hash ^= common_hash;
1569 bucket_hash &= IXGBE_ATR_HASH_MASK;
1571 sig_hash ^= common_hash << 16;
1572 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1574 /* return completed signature hash */
1575 return sig_hash ^ bucket_hash;
1579 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1580 * @hw: pointer to hardware structure
1581 * @input: unique input dword
1582 * @common: compressed common input dword
1583 * @queue: queue index to direct traffic to
1585 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1586 union ixgbe_atr_hash_dword input,
1587 union ixgbe_atr_hash_dword common,
1594 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1597 * Get the flow_type in order to program FDIRCMD properly
1598 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1599 * fifth is FDIRCMD.TUNNEL_FILTER
1601 switch (input.formatted.flow_type) {
1602 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1603 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1604 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1605 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1606 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1607 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1610 DEBUGOUT(" Error on flow type input\n");
1611 return IXGBE_ERR_CONFIG;
1614 /* configure FDIRCMD register */
1615 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1616 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1617 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1618 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1621 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1622 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1624 fdirhashcmd = (u64)fdircmd << 32;
1625 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1626 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1628 err = ixgbe_fdir_check_cmd_complete(hw);
1630 DEBUGOUT("Flow Director command did not complete!\n");
1634 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1636 return IXGBE_SUCCESS;
1639 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1642 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1643 bucket_hash ^= lo_hash_dword >> n; \
1644 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1645 bucket_hash ^= hi_hash_dword >> n; \
1649 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1650 * @atr_input: input bitstream to compute the hash on
1651 * @input_mask: mask for the input bitstream
1653 * This function serves two main purposes. First it applies the input_mask
1654 * to the atr_input resulting in a cleaned up atr_input data stream.
1655 * Secondly it computes the hash and stores it in the bkt_hash field at
1656 * the end of the input byte stream. This way it will be available for
1657 * future use without needing to recompute the hash.
1659 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1660 union ixgbe_atr_input *input_mask)
1663 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1664 u32 bucket_hash = 0;
1668 /* Apply masks to input data */
1669 for (i = 0; i < 14; i++)
1670 input->dword_stream[i] &= input_mask->dword_stream[i];
1672 /* record the flow_vm_vlan bits as they are a key part to the hash */
1673 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1675 /* generate common hash dword */
1676 for (i = 1; i <= 13; i++)
1677 hi_dword ^= input->dword_stream[i];
1678 hi_hash_dword = IXGBE_NTOHL(hi_dword);
1680 /* low dword is word swapped version of common */
1681 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1683 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1684 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1686 /* Process bits 0 and 16 */
1687 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1690 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1691 * delay this because bit 0 of the stream should not be processed
1692 * so we do not add the VLAN until after bit 0 was processed
1694 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1696 /* Process remaining 30 bit of the key */
1697 for (i = 1; i <= 15; i++)
1698 IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
1701 * Limit hash to 13 bits since max bucket count is 8K.
1702 * Store result at the end of the input stream.
1704 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1708 * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks
1709 * @input_mask: mask to be bit swapped
1711 * The source and destination port masks for flow director are bit swapped
1712 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1713 * generate a correctly swapped value we need to bit swap the mask and that
1714 * is what is accomplished by this function.
1716 STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1718 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1719 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1720 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1721 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1722 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1723 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1724 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1728 * These two macros are meant to address the fact that we have registers
1729 * that are either all or in part big-endian. As a result on big-endian
1730 * systems we will end up byte swapping the value to little-endian before
1731 * it is byte swapped again and written to the hardware in the original
1732 * big-endian format.
1734 #define IXGBE_STORE_AS_BE32(_value) \
1735 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1736 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1738 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1739 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1741 #define IXGBE_STORE_AS_BE16(_value) \
1742 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1744 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1745 union ixgbe_atr_input *input_mask, bool cloud_mode)
1747 /* mask IPv6 since it is currently not supported */
1748 u32 fdirm = IXGBE_FDIRM_DIPv6;
1750 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1753 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1754 * are zero, then assume a full mask for that field. Also assume that
1755 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1756 * cannot be masked out in this implementation.
1758 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1762 /* verify bucket hash is cleared on hash generation */
1763 if (input_mask->formatted.bkt_hash)
1764 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1766 /* Program FDIRM and verify partial masks */
1767 switch (input_mask->formatted.vm_pool & 0x7F) {
1769 fdirm |= IXGBE_FDIRM_POOL;
1773 DEBUGOUT(" Error on vm pool mask\n");
1774 return IXGBE_ERR_CONFIG;
1777 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1779 fdirm |= IXGBE_FDIRM_L4P;
1780 if (input_mask->formatted.dst_port ||
1781 input_mask->formatted.src_port) {
1782 DEBUGOUT(" Error on src/dst port mask\n");
1783 return IXGBE_ERR_CONFIG;
1785 case IXGBE_ATR_L4TYPE_MASK:
1788 DEBUGOUT(" Error on flow type mask\n");
1789 return IXGBE_ERR_CONFIG;
1792 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1794 /* mask VLAN ID, fall through to mask VLAN priority */
1795 fdirm |= IXGBE_FDIRM_VLANID;
1797 /* mask VLAN priority */
1798 fdirm |= IXGBE_FDIRM_VLANP;
1801 /* mask VLAN ID only, fall through */
1802 fdirm |= IXGBE_FDIRM_VLANID;
1804 /* no VLAN fields masked */
1807 DEBUGOUT(" Error on VLAN mask\n");
1808 return IXGBE_ERR_CONFIG;
1811 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1813 /* Mask Flex Bytes, fall through */
1814 fdirm |= IXGBE_FDIRM_FLEX;
1818 DEBUGOUT(" Error on flexible byte mask\n");
1819 return IXGBE_ERR_CONFIG;
1823 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1824 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1826 /* store the TCP/UDP port masks, bit reversed from port layout */
1827 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1829 /* write both the same so that UDP and TCP use the same mask */
1830 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1831 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1833 /* store source and destination IP masks (big-endian) */
1834 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1835 ~input_mask->formatted.src_ip[0]);
1836 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1837 ~input_mask->formatted.dst_ip[0]);
1839 return IXGBE_SUCCESS;
1842 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1843 union ixgbe_atr_input *input,
1844 u16 soft_id, u8 queue, bool cloud_mode)
1846 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1848 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1850 /* currently IPv6 is not supported, must be programmed with 0 */
1851 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1852 input->formatted.src_ip[0]);
1853 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1854 input->formatted.src_ip[1]);
1855 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1856 input->formatted.src_ip[2]);
1858 /* record the source address (big-endian) */
1859 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1861 /* record the first 32 bits of the destination address (big-endian) */
1862 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1864 /* record source and destination port (little-endian)*/
1865 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1866 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1867 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1868 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1870 /* record VLAN (little-endian) and flex_bytes(big-endian) */
1871 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1872 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1873 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1874 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1877 /* configure FDIRHASH register */
1878 fdirhash = input->formatted.bkt_hash;
1879 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1880 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1883 * flush all previous writes to make certain registers are
1884 * programmed prior to issuing the command
1886 IXGBE_WRITE_FLUSH(hw);
1888 /* configure FDIRCMD register */
1889 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1890 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1891 if (queue == IXGBE_FDIR_DROP_QUEUE)
1892 fdircmd |= IXGBE_FDIRCMD_DROP;
1893 if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK)
1894 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
1895 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1896 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1897 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1899 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1901 return IXGBE_SUCCESS;
1904 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1905 union ixgbe_atr_input *input,
1912 /* configure FDIRHASH register */
1913 fdirhash = input->formatted.bkt_hash;
1914 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1915 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1917 /* flush hash to HW */
1918 IXGBE_WRITE_FLUSH(hw);
1920 /* Query if filter is present */
1921 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1923 err = ixgbe_fdir_check_cmd_complete(hw);
1925 DEBUGOUT("Flow Director command did not complete!\n");
1929 /* if filter exists in hardware then remove it */
1930 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1931 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1932 IXGBE_WRITE_FLUSH(hw);
1933 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1934 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1937 return IXGBE_SUCCESS;
1941 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1942 * @hw: pointer to hardware structure
1943 * @input: input bitstream
1944 * @input_mask: mask for the input bitstream
1945 * @soft_id: software index for the filters
1946 * @queue: queue index to direct traffic to
1948 * Note that the caller to this function must lock before calling, since the
1949 * hardware writes must be protected from one another.
1951 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1952 union ixgbe_atr_input *input,
1953 union ixgbe_atr_input *input_mask,
1954 u16 soft_id, u8 queue, bool cloud_mode)
1956 s32 err = IXGBE_ERR_CONFIG;
1958 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1961 * Check flow_type formatting, and bail out before we touch the hardware
1962 * if there's a configuration issue
1964 switch (input->formatted.flow_type) {
1965 case IXGBE_ATR_FLOW_TYPE_IPV4:
1966 case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4:
1967 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1968 if (input->formatted.dst_port || input->formatted.src_port) {
1969 DEBUGOUT(" Error on src/dst port\n");
1970 return IXGBE_ERR_CONFIG;
1973 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1974 case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4:
1975 if (input->formatted.dst_port || input->formatted.src_port) {
1976 DEBUGOUT(" Error on src/dst port\n");
1977 return IXGBE_ERR_CONFIG;
1979 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1980 case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:
1981 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1982 case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4:
1983 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
1984 IXGBE_ATR_L4TYPE_MASK;
1987 DEBUGOUT(" Error on flow type input\n");
1991 /* program input mask into the HW */
1992 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode);
1996 /* apply mask and compute/store hash */
1997 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
1999 /* program filters to filter memory */
2000 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
2001 soft_id, queue, cloud_mode);
2005 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2006 * @hw: pointer to hardware structure
2007 * @reg: analog register to read
2010 * Performs read operation to Omer analog register specified.
2012 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
2016 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
2018 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2020 IXGBE_WRITE_FLUSH(hw);
2022 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2023 *val = (u8)core_ctl;
2025 return IXGBE_SUCCESS;
2029 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2030 * @hw: pointer to hardware structure
2031 * @reg: atlas register to write
2032 * @val: value to write
2034 * Performs write operation to Omer analog register specified.
2036 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2040 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
2042 core_ctl = (reg << 8) | val;
2043 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2044 IXGBE_WRITE_FLUSH(hw);
2047 return IXGBE_SUCCESS;
2051 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2052 * @hw: pointer to hardware structure
2054 * Starts the hardware using the generic start_hw function
2055 * and the generation start_hw function.
2056 * Then performs revision-specific operations, if any.
2058 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2060 s32 ret_val = IXGBE_SUCCESS;
2062 DEBUGFUNC("ixgbe_start_hw_82599");
2064 ret_val = ixgbe_start_hw_generic(hw);
2065 if (ret_val != IXGBE_SUCCESS)
2068 ret_val = ixgbe_start_hw_gen2(hw);
2069 if (ret_val != IXGBE_SUCCESS)
2072 /* We need to run link autotry after the driver loads */
2073 hw->mac.autotry_restart = true;
2075 if (ret_val == IXGBE_SUCCESS)
2076 ret_val = ixgbe_verify_fw_version_82599(hw);
2082 * ixgbe_identify_phy_82599 - Get physical layer module
2083 * @hw: pointer to hardware structure
2085 * Determines the physical layer module found on the current adapter.
2086 * If PHY already detected, maintains current PHY type in hw struct,
2087 * otherwise executes the PHY detection routine.
2089 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2093 DEBUGFUNC("ixgbe_identify_phy_82599");
2095 /* Detect PHY if not unknown - returns success if already detected. */
2096 status = ixgbe_identify_phy_generic(hw);
2097 if (status != IXGBE_SUCCESS) {
2098 /* 82599 10GBASE-T requires an external PHY */
2099 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2102 status = ixgbe_identify_module_generic(hw);
2105 /* Set PHY type none if no PHY detected */
2106 if (hw->phy.type == ixgbe_phy_unknown) {
2107 hw->phy.type = ixgbe_phy_none;
2108 return IXGBE_SUCCESS;
2111 /* Return error if SFP module has been detected but is not supported */
2112 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2113 return IXGBE_ERR_SFP_NOT_SUPPORTED;
2119 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2120 * @hw: pointer to hardware structure
2122 * Determines physical layer capabilities of the current configuration.
2124 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2126 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2127 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2128 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2129 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2130 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2131 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2132 u16 ext_ability = 0;
2133 u8 comp_codes_10g = 0;
2134 u8 comp_codes_1g = 0;
2136 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2138 hw->phy.ops.identify(hw);
2140 switch (hw->phy.type) {
2142 case ixgbe_phy_cu_unknown:
2143 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2144 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2145 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2146 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2147 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2148 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2149 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
2150 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2156 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2157 case IXGBE_AUTOC_LMS_1G_AN:
2158 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2159 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2160 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2161 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2164 /* SFI mode so read SFP module */
2167 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2168 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2169 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2170 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2171 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2172 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2173 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2176 case IXGBE_AUTOC_LMS_10G_SERIAL:
2177 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2178 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2180 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2183 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2184 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2185 if (autoc & IXGBE_AUTOC_KX_SUPP)
2186 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2187 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2188 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2189 if (autoc & IXGBE_AUTOC_KR_SUPP)
2190 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2199 /* SFP check must be done last since DA modules are sometimes used to
2200 * test KR mode - we need to id KR mode correctly before SFP module.
2201 * Call identify_sfp because the pluggable module may have changed */
2202 hw->phy.ops.identify_sfp(hw);
2203 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2206 switch (hw->phy.type) {
2207 case ixgbe_phy_sfp_passive_tyco:
2208 case ixgbe_phy_sfp_passive_unknown:
2209 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2211 case ixgbe_phy_sfp_ftl_active:
2212 case ixgbe_phy_sfp_active_unknown:
2213 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2215 case ixgbe_phy_sfp_avago:
2216 case ixgbe_phy_sfp_ftl:
2217 case ixgbe_phy_sfp_intel:
2218 case ixgbe_phy_sfp_unknown:
2219 hw->phy.ops.read_i2c_eeprom(hw,
2220 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2221 hw->phy.ops.read_i2c_eeprom(hw,
2222 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2223 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2224 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2225 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2226 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2227 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2228 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2229 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
2230 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
2237 return physical_layer;
2241 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2242 * @hw: pointer to hardware structure
2243 * @regval: register value to write to RXCTRL
2245 * Enables the Rx DMA unit for 82599
2247 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2250 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2253 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2254 * If traffic is incoming before we enable the Rx unit, it could hang
2255 * the Rx DMA unit. Therefore, make sure the security engine is
2256 * completely disabled prior to enabling the Rx unit.
2259 hw->mac.ops.disable_sec_rx_path(hw);
2261 if (regval & IXGBE_RXCTRL_RXEN)
2262 ixgbe_enable_rx(hw);
2264 ixgbe_disable_rx(hw);
2266 hw->mac.ops.enable_sec_rx_path(hw);
2268 return IXGBE_SUCCESS;
2272 * ixgbe_verify_fw_version_82599 - verify FW version for 82599
2273 * @hw: pointer to hardware structure
2275 * Verifies that installed the firmware version is 0.6 or higher
2276 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2278 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2279 * if the FW version is not supported.
2281 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2283 s32 status = IXGBE_ERR_EEPROM_VERSION;
2284 u16 fw_offset, fw_ptp_cfg_offset;
2287 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2289 /* firmware check is only necessary for SFI devices */
2290 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2291 status = IXGBE_SUCCESS;
2292 goto fw_version_out;
2295 /* get the offset to the Firmware Module block */
2296 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
2297 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2298 "eeprom read at offset %d failed", IXGBE_FW_PTR);
2299 return IXGBE_ERR_EEPROM_VERSION;
2302 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2303 goto fw_version_out;
2305 /* get the offset to the Pass Through Patch Configuration block */
2306 if (hw->eeprom.ops.read(hw, (fw_offset +
2307 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2308 &fw_ptp_cfg_offset)) {
2309 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2310 "eeprom read at offset %d failed",
2312 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);
2313 return IXGBE_ERR_EEPROM_VERSION;
2316 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2317 goto fw_version_out;
2319 /* get the firmware version */
2320 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2321 IXGBE_FW_PATCH_VERSION_4), &fw_version)) {
2322 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2323 "eeprom read at offset %d failed",
2324 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);
2325 return IXGBE_ERR_EEPROM_VERSION;
2328 if (fw_version > 0x5)
2329 status = IXGBE_SUCCESS;
2336 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2337 * @hw: pointer to hardware structure
2339 * Returns true if the LESM FW module is present and enabled. Otherwise
2340 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2342 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2344 bool lesm_enabled = false;
2345 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2348 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2350 /* get the offset to the Firmware Module block */
2351 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2353 if ((status != IXGBE_SUCCESS) ||
2354 (fw_offset == 0) || (fw_offset == 0xFFFF))
2357 /* get the offset to the LESM Parameters block */
2358 status = hw->eeprom.ops.read(hw, (fw_offset +
2359 IXGBE_FW_LESM_PARAMETERS_PTR),
2360 &fw_lesm_param_offset);
2362 if ((status != IXGBE_SUCCESS) ||
2363 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2366 /* get the LESM state word */
2367 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2368 IXGBE_FW_LESM_STATE_1),
2371 if ((status == IXGBE_SUCCESS) &&
2372 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2373 lesm_enabled = true;
2376 return lesm_enabled;
2380 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2381 * fastest available method
2383 * @hw: pointer to hardware structure
2384 * @offset: offset of word in EEPROM to read
2385 * @words: number of words
2386 * @data: word(s) read from the EEPROM
2388 * Retrieves 16 bit word(s) read from EEPROM
2390 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2391 u16 words, u16 *data)
2393 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2394 s32 ret_val = IXGBE_ERR_CONFIG;
2396 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2399 * If EEPROM is detected and can be addressed using 14 bits,
2400 * use EERD otherwise use bit bang
2402 if ((eeprom->type == ixgbe_eeprom_spi) &&
2403 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2404 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2407 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2415 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2416 * fastest available method
2418 * @hw: pointer to hardware structure
2419 * @offset: offset of word in the EEPROM to read
2420 * @data: word read from the EEPROM
2422 * Reads a 16 bit word from the EEPROM
2424 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2425 u16 offset, u16 *data)
2427 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2428 s32 ret_val = IXGBE_ERR_CONFIG;
2430 DEBUGFUNC("ixgbe_read_eeprom_82599");
2433 * If EEPROM is detected and can be addressed using 14 bits,
2434 * use EERD otherwise use bit bang
2436 if ((eeprom->type == ixgbe_eeprom_spi) &&
2437 (offset <= IXGBE_EERD_MAX_ADDR))
2438 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2440 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2446 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2448 * @hw: pointer to hardware structure
2450 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2451 * full pipeline reset. This function assumes the SW/FW lock is held.
2453 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2457 u32 i, autoc_reg, autoc2_reg;
2459 /* Enable link if disabled in NVM */
2460 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2461 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2462 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2463 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2464 IXGBE_WRITE_FLUSH(hw);
2467 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2468 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2469 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2470 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
2471 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));
2472 /* Wait for AN to leave state 0 */
2473 for (i = 0; i < 10; i++) {
2475 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2476 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2480 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2481 DEBUGOUT("auto negotiation not completed\n");
2482 ret_val = IXGBE_ERR_RESET_FAILED;
2483 goto reset_pipeline_out;
2486 ret_val = IXGBE_SUCCESS;
2489 /* Write AUTOC register with original LMS field and Restart_AN */
2490 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2491 IXGBE_WRITE_FLUSH(hw);