1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82599.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
39 #ident "$Id: ixgbe_82599.c,v 1.301 2012/11/08 11:33:27 jtkirshe Exp $"
41 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed speed,
44 bool autoneg_wait_to_complete);
45 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
46 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
47 u16 offset, u16 *data);
48 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
49 u16 words, u16 *data);
51 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
53 struct ixgbe_mac_info *mac = &hw->mac;
55 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
57 /* enable the laser control functions for SFP+ fiber */
58 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
59 mac->ops.disable_tx_laser =
60 &ixgbe_disable_tx_laser_multispeed_fiber;
61 mac->ops.enable_tx_laser =
62 &ixgbe_enable_tx_laser_multispeed_fiber;
63 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
66 mac->ops.disable_tx_laser = NULL;
67 mac->ops.enable_tx_laser = NULL;
68 mac->ops.flap_tx_laser = NULL;
71 if (hw->phy.multispeed_fiber) {
72 /* Set up dual speed SFP+ support */
73 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
75 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
76 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
77 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
78 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
79 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
81 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
87 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
88 * @hw: pointer to hardware structure
90 * Initialize any function pointers that were not able to be
91 * set during init_shared_code because the PHY/SFP type was
92 * not known. Perform the SFP init if necessary.
95 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
97 struct ixgbe_mac_info *mac = &hw->mac;
98 struct ixgbe_phy_info *phy = &hw->phy;
99 s32 ret_val = IXGBE_SUCCESS;
101 DEBUGFUNC("ixgbe_init_phy_ops_82599");
103 /* Identify the PHY or SFP module */
104 ret_val = phy->ops.identify(hw);
105 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
106 goto init_phy_ops_out;
108 /* Setup function pointers based on detected SFP module and speeds */
109 ixgbe_init_mac_link_ops_82599(hw);
110 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
111 hw->phy.ops.reset = NULL;
113 /* If copper media, overwrite with copper function pointers */
114 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
115 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
116 mac->ops.get_link_capabilities =
117 &ixgbe_get_copper_link_capabilities_generic;
120 /* Set necessary function pointers based on phy type */
121 switch (hw->phy.type) {
123 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
124 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
125 phy->ops.get_firmware_version =
126 &ixgbe_get_phy_firmware_version_tnx;
135 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
137 s32 ret_val = IXGBE_SUCCESS;
138 u16 list_offset, data_offset, data_value;
139 bool got_lock = false;
141 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
143 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
144 ixgbe_init_mac_link_ops_82599(hw);
146 hw->phy.ops.reset = NULL;
148 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
150 if (ret_val != IXGBE_SUCCESS)
153 /* PHY config will finish before releasing the semaphore */
154 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
155 IXGBE_GSSR_MAC_CSR_SM);
156 if (ret_val != IXGBE_SUCCESS) {
157 ret_val = IXGBE_ERR_SWFW_SYNC;
161 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
162 while (data_value != 0xffff) {
163 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
164 IXGBE_WRITE_FLUSH(hw);
165 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
168 /* Release the semaphore */
169 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
170 /* Delay obtaining semaphore again to allow FW access */
171 msec_delay(hw->eeprom.semaphore_delay);
173 /* Need SW/FW semaphore around AUTOC writes if LESM on,
174 * likewise reset_pipeline requires lock as it also writes
177 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
178 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
179 IXGBE_GSSR_MAC_CSR_SM);
180 if (ret_val != IXGBE_SUCCESS) {
181 ret_val = IXGBE_ERR_SWFW_SYNC;
188 /* Restart DSP and set SFI mode */
189 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
190 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL));
192 ret_val = ixgbe_reset_pipeline_82599(hw);
195 hw->mac.ops.release_swfw_sync(hw,
196 IXGBE_GSSR_MAC_CSR_SM);
201 DEBUGOUT("sfp module setup not complete\n");
202 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
213 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
214 * @hw: pointer to hardware structure
216 * Initialize the function pointers and assign the MAC type for 82599.
217 * Does not touch the hardware.
220 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
222 struct ixgbe_mac_info *mac = &hw->mac;
223 struct ixgbe_phy_info *phy = &hw->phy;
224 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
227 DEBUGFUNC("ixgbe_init_ops_82599");
229 ret_val = ixgbe_init_phy_ops_generic(hw);
230 ret_val = ixgbe_init_ops_generic(hw);
233 phy->ops.identify = &ixgbe_identify_phy_82599;
234 phy->ops.init = &ixgbe_init_phy_ops_82599;
237 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
238 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
239 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
240 mac->ops.get_supported_physical_layer =
241 &ixgbe_get_supported_physical_layer_82599;
242 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
243 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
244 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
245 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
246 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
247 mac->ops.start_hw = &ixgbe_start_hw_82599;
248 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
249 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
250 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
251 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
252 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
254 /* RAR, Multicast, VLAN */
255 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
256 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
257 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
258 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
259 mac->rar_highwater = 1;
260 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
261 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
262 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
263 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
264 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
265 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
266 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
269 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
270 mac->ops.check_link = &ixgbe_check_mac_link_generic;
271 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
272 ixgbe_init_mac_link_ops_82599(hw);
274 mac->mcft_size = 128;
276 mac->num_rar_entries = 128;
277 mac->rx_pb_size = 512;
278 mac->max_tx_queues = 128;
279 mac->max_rx_queues = 128;
280 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
282 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
283 IXGBE_FWSM_MODE_MASK) ? true : false;
285 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
288 eeprom->ops.read = &ixgbe_read_eeprom_82599;
289 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
291 /* Manageability interface */
292 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
299 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
300 * @hw: pointer to hardware structure
301 * @speed: pointer to link speed
302 * @negotiation: true when autoneg or autotry is enabled
304 * Determines the link capabilities by reading the AUTOC register.
306 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
307 ixgbe_link_speed *speed,
310 s32 status = IXGBE_SUCCESS;
313 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
316 /* Check if 1G SFP module. */
317 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
318 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
319 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
320 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
321 *speed = IXGBE_LINK_SPEED_1GB_FULL;
327 * Determine link capabilities based on the stored value of AUTOC,
328 * which represents EEPROM defaults. If AUTOC value has not
329 * been stored, use the current register values.
331 if (hw->mac.orig_link_settings_stored)
332 autoc = hw->mac.orig_autoc;
334 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
336 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
337 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
338 *speed = IXGBE_LINK_SPEED_1GB_FULL;
339 *negotiation = false;
342 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
343 *speed = IXGBE_LINK_SPEED_10GB_FULL;
344 *negotiation = false;
347 case IXGBE_AUTOC_LMS_1G_AN:
348 *speed = IXGBE_LINK_SPEED_1GB_FULL;
352 case IXGBE_AUTOC_LMS_10G_SERIAL:
353 *speed = IXGBE_LINK_SPEED_10GB_FULL;
354 *negotiation = false;
357 case IXGBE_AUTOC_LMS_KX4_KX_KR:
358 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
359 *speed = IXGBE_LINK_SPEED_UNKNOWN;
360 if (autoc & IXGBE_AUTOC_KR_SUPP)
361 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
362 if (autoc & IXGBE_AUTOC_KX4_SUPP)
363 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
364 if (autoc & IXGBE_AUTOC_KX_SUPP)
365 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
369 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
370 *speed = IXGBE_LINK_SPEED_100_FULL;
371 if (autoc & IXGBE_AUTOC_KR_SUPP)
372 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
373 if (autoc & IXGBE_AUTOC_KX4_SUPP)
374 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
375 if (autoc & IXGBE_AUTOC_KX_SUPP)
376 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
380 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
381 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
382 *negotiation = false;
386 status = IXGBE_ERR_LINK_SETUP;
391 if (hw->phy.multispeed_fiber) {
392 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
393 IXGBE_LINK_SPEED_1GB_FULL;
402 * ixgbe_get_media_type_82599 - Get media type
403 * @hw: pointer to hardware structure
405 * Returns the media type (fiber, copper, backplane)
407 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
409 enum ixgbe_media_type media_type;
411 DEBUGFUNC("ixgbe_get_media_type_82599");
413 /* Detect if there is a copper PHY attached. */
414 switch (hw->phy.type) {
415 case ixgbe_phy_cu_unknown:
417 media_type = ixgbe_media_type_copper;
423 switch (hw->device_id) {
424 case IXGBE_DEV_ID_82599_KX4:
425 case IXGBE_DEV_ID_82599_KX4_MEZZ:
426 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
427 case IXGBE_DEV_ID_82599_KR:
428 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
429 case IXGBE_DEV_ID_82599_XAUI_LOM:
430 /* Default device ID is mezzanine card KX/KX4 */
431 media_type = ixgbe_media_type_backplane;
433 case IXGBE_DEV_ID_82599_SFP:
434 case IXGBE_DEV_ID_82599_SFP_FCOE:
435 case IXGBE_DEV_ID_82599_SFP_EM:
436 case IXGBE_DEV_ID_82599_SFP_SF2:
437 case IXGBE_DEV_ID_82599_SFP_SF_QP:
438 case IXGBE_DEV_ID_82599EN_SFP:
439 media_type = ixgbe_media_type_fiber;
441 case IXGBE_DEV_ID_82599_CX4:
442 media_type = ixgbe_media_type_cx4;
444 case IXGBE_DEV_ID_82599_T3_LOM:
445 media_type = ixgbe_media_type_copper;
448 media_type = ixgbe_media_type_unknown;
456 * ixgbe_start_mac_link_82599 - Setup MAC link settings
457 * @hw: pointer to hardware structure
458 * @autoneg_wait_to_complete: true when waiting for completion is needed
460 * Configures link settings based on values in the ixgbe_hw struct.
461 * Restarts the link. Performs autonegotiation if needed.
463 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
464 bool autoneg_wait_to_complete)
469 s32 status = IXGBE_SUCCESS;
470 bool got_lock = false;
472 DEBUGFUNC("ixgbe_start_mac_link_82599");
475 /* reset_pipeline requires us to hold this lock as it writes to
478 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
479 status = hw->mac.ops.acquire_swfw_sync(hw,
480 IXGBE_GSSR_MAC_CSR_SM);
481 if (status != IXGBE_SUCCESS)
488 ixgbe_reset_pipeline_82599(hw);
491 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
493 /* Only poll for autoneg to complete if specified to do so */
494 if (autoneg_wait_to_complete) {
495 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
496 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
497 IXGBE_AUTOC_LMS_KX4_KX_KR ||
498 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
499 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
500 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
501 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
502 links_reg = 0; /* Just in case Autoneg time = 0 */
503 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
504 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
505 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
509 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
510 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
511 DEBUGOUT("Autoneg did not complete.\n");
516 /* Add delay to filter out noises during initial link setup */
524 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
525 * @hw: pointer to hardware structure
527 * The base drivers may require better control over SFP+ module
528 * PHY states. This includes selectively shutting down the Tx
529 * laser on the PHY, effectively halting physical link.
531 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
533 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
535 /* Disable tx laser; allow 100us to go dark per spec */
536 esdp_reg |= IXGBE_ESDP_SDP3;
537 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
538 IXGBE_WRITE_FLUSH(hw);
543 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
544 * @hw: pointer to hardware structure
546 * The base drivers may require better control over SFP+ module
547 * PHY states. This includes selectively turning on the Tx
548 * laser on the PHY, effectively starting physical link.
550 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
552 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
554 /* Enable tx laser; allow 100ms to light up */
555 esdp_reg &= ~IXGBE_ESDP_SDP3;
556 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
557 IXGBE_WRITE_FLUSH(hw);
562 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
563 * @hw: pointer to hardware structure
565 * When the driver changes the link speeds that it can support,
566 * it sets autotry_restart to true to indicate that we need to
567 * initiate a new autotry session with the link partner. To do
568 * so, we set the speed then disable and re-enable the tx laser, to
569 * alert the link partner that it also needs to restart autotry on its
570 * end. This is consistent with true clause 37 autoneg, which also
571 * involves a loss of signal.
573 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
575 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
577 if (hw->mac.autotry_restart) {
578 ixgbe_disable_tx_laser_multispeed_fiber(hw);
579 ixgbe_enable_tx_laser_multispeed_fiber(hw);
580 hw->mac.autotry_restart = false;
585 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
586 * @hw: pointer to hardware structure
587 * @speed: new link speed
588 * @autoneg: true if autonegotiation enabled
589 * @autoneg_wait_to_complete: true when waiting for completion is needed
591 * Set the link speed in the AUTOC register and restarts link.
593 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
594 ixgbe_link_speed speed, bool autoneg,
595 bool autoneg_wait_to_complete)
597 s32 status = IXGBE_SUCCESS;
598 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
599 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
601 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
603 bool link_up = false;
606 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
608 /* Mask off requested but non-supported speeds */
609 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);
610 if (status != IXGBE_SUCCESS)
616 * Try each speed one by one, highest priority first. We do this in
617 * software because 10gb fiber doesn't support speed autonegotiation.
619 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
621 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
623 /* If we already have link at this speed, just jump out */
624 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
625 if (status != IXGBE_SUCCESS)
628 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
631 /* Set the module link speed */
632 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
633 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
634 IXGBE_WRITE_FLUSH(hw);
636 /* Allow module to change analog characteristics (1G->10G) */
639 status = ixgbe_setup_mac_link_82599(hw,
640 IXGBE_LINK_SPEED_10GB_FULL,
642 autoneg_wait_to_complete);
643 if (status != IXGBE_SUCCESS)
646 /* Flap the tx laser if it has not already been done */
647 ixgbe_flap_tx_laser(hw);
650 * Wait for the controller to acquire link. Per IEEE 802.3ap,
651 * Section 73.10.2, we may have to wait up to 500ms if KR is
652 * attempted. 82599 uses the same timing for 10g SFI.
654 for (i = 0; i < 5; i++) {
655 /* Wait for the link partner to also set speed */
658 /* If we have link, just jump out */
659 status = ixgbe_check_link(hw, &link_speed,
661 if (status != IXGBE_SUCCESS)
669 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
671 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
672 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
674 /* If we already have link at this speed, just jump out */
675 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
676 if (status != IXGBE_SUCCESS)
679 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
682 /* Set the module link speed */
683 esdp_reg &= ~IXGBE_ESDP_SDP5;
684 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
685 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
686 IXGBE_WRITE_FLUSH(hw);
688 /* Allow module to change analog characteristics (10G->1G) */
691 status = ixgbe_setup_mac_link_82599(hw,
692 IXGBE_LINK_SPEED_1GB_FULL,
694 autoneg_wait_to_complete);
695 if (status != IXGBE_SUCCESS)
698 /* Flap the tx laser if it has not already been done */
699 ixgbe_flap_tx_laser(hw);
701 /* Wait for the link partner to also set speed */
704 /* If we have link, just jump out */
705 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
706 if (status != IXGBE_SUCCESS)
714 * We didn't get link. Configure back to the highest speed we tried,
715 * (if there was more than one). We call ourselves back with just the
716 * single highest speed that the user requested.
719 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
720 highest_link_speed, autoneg, autoneg_wait_to_complete);
723 /* Set autoneg_advertised value based on input link speed */
724 hw->phy.autoneg_advertised = 0;
726 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
727 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
729 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
730 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
736 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
737 * @hw: pointer to hardware structure
738 * @speed: new link speed
739 * @autoneg: true if autonegotiation enabled
740 * @autoneg_wait_to_complete: true when waiting for completion is needed
742 * Implements the Intel SmartSpeed algorithm.
744 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
745 ixgbe_link_speed speed, bool autoneg,
746 bool autoneg_wait_to_complete)
748 s32 status = IXGBE_SUCCESS;
749 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
751 bool link_up = false;
752 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
754 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
756 /* Set autoneg_advertised value based on input link speed */
757 hw->phy.autoneg_advertised = 0;
759 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
760 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
762 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
763 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
765 if (speed & IXGBE_LINK_SPEED_100_FULL)
766 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
769 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
770 * autoneg advertisement if link is unable to be established at the
771 * highest negotiated rate. This can sometimes happen due to integrity
772 * issues with the physical media connection.
775 /* First, try to get link with full advertisement */
776 hw->phy.smart_speed_active = false;
777 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
778 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
779 autoneg_wait_to_complete);
780 if (status != IXGBE_SUCCESS)
784 * Wait for the controller to acquire link. Per IEEE 802.3ap,
785 * Section 73.10.2, we may have to wait up to 500ms if KR is
786 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
787 * Table 9 in the AN MAS.
789 for (i = 0; i < 5; i++) {
792 /* If we have link, just jump out */
793 status = ixgbe_check_link(hw, &link_speed, &link_up,
795 if (status != IXGBE_SUCCESS)
804 * We didn't get link. If we advertised KR plus one of KX4/KX
805 * (or BX4/BX), then disable KR and try again.
807 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
808 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
811 /* Turn SmartSpeed on to disable KR support */
812 hw->phy.smart_speed_active = true;
813 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
814 autoneg_wait_to_complete);
815 if (status != IXGBE_SUCCESS)
819 * Wait for the controller to acquire link. 600ms will allow for
820 * the AN link_fail_inhibit_timer as well for multiple cycles of
821 * parallel detect, both 10g and 1g. This allows for the maximum
822 * connect attempts as defined in the AN MAS table 73-7.
824 for (i = 0; i < 6; i++) {
827 /* If we have link, just jump out */
828 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
829 if (status != IXGBE_SUCCESS)
836 /* We didn't get link. Turn SmartSpeed back off. */
837 hw->phy.smart_speed_active = false;
838 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
839 autoneg_wait_to_complete);
842 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
843 DEBUGOUT("Smartspeed has downgraded the link speed "
844 "from the maximum advertised\n");
849 * ixgbe_setup_mac_link_82599 - Set MAC link speed
850 * @hw: pointer to hardware structure
851 * @speed: new link speed
852 * @autoneg: true if autonegotiation enabled
853 * @autoneg_wait_to_complete: true when waiting for completion is needed
855 * Set the link speed in the AUTOC register and restarts link.
857 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
858 ixgbe_link_speed speed, bool autoneg,
859 bool autoneg_wait_to_complete)
861 s32 status = IXGBE_SUCCESS;
862 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
863 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
864 u32 start_autoc = autoc;
866 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
867 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
868 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
871 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
872 bool got_lock = false;
874 DEBUGFUNC("ixgbe_setup_mac_link_82599");
876 /* Check to see if speed passed in is supported. */
877 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
881 speed &= link_capabilities;
883 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
884 status = IXGBE_ERR_LINK_SETUP;
888 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
889 if (hw->mac.orig_link_settings_stored)
890 orig_autoc = hw->mac.orig_autoc;
894 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
895 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
896 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
897 /* Set KX4/KX/KR support according to speed requested */
898 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
899 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
900 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
901 autoc |= IXGBE_AUTOC_KX4_SUPP;
902 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
903 (hw->phy.smart_speed_active == false))
904 autoc |= IXGBE_AUTOC_KR_SUPP;
906 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
907 autoc |= IXGBE_AUTOC_KX_SUPP;
908 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
909 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
910 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
911 /* Switch from 1G SFI to 10G SFI if requested */
912 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
913 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
914 autoc &= ~IXGBE_AUTOC_LMS_MASK;
915 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
917 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
918 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
919 /* Switch from 10G SFI to 1G SFI if requested */
920 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
921 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
922 autoc &= ~IXGBE_AUTOC_LMS_MASK;
924 autoc |= IXGBE_AUTOC_LMS_1G_AN;
926 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
930 if (autoc != start_autoc) {
931 /* Need SW/FW semaphore around AUTOC writes if LESM is on,
932 * likewise reset_pipeline requires us to hold this lock as
933 * it also writes to AUTOC.
935 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
936 status = hw->mac.ops.acquire_swfw_sync(hw,
937 IXGBE_GSSR_MAC_CSR_SM);
938 if (status != IXGBE_SUCCESS) {
939 status = IXGBE_ERR_SWFW_SYNC;
947 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
948 ixgbe_reset_pipeline_82599(hw);
951 hw->mac.ops.release_swfw_sync(hw,
952 IXGBE_GSSR_MAC_CSR_SM);
956 /* Only poll for autoneg to complete if specified to do so */
957 if (autoneg_wait_to_complete) {
958 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
959 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
960 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
961 links_reg = 0; /*Just in case Autoneg time=0*/
962 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
964 IXGBE_READ_REG(hw, IXGBE_LINKS);
965 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
969 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
971 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
972 DEBUGOUT("Autoneg did not complete.\n");
977 /* Add delay to filter out noises during initial link setup */
986 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
987 * @hw: pointer to hardware structure
988 * @speed: new link speed
989 * @autoneg: true if autonegotiation enabled
990 * @autoneg_wait_to_complete: true if waiting is needed to complete
992 * Restarts link on PHY and MAC based on settings passed in.
994 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
995 ixgbe_link_speed speed,
997 bool autoneg_wait_to_complete)
1001 DEBUGFUNC("ixgbe_setup_copper_link_82599");
1003 /* Setup the PHY according to input speed */
1004 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
1005 autoneg_wait_to_complete);
1007 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1013 * ixgbe_reset_hw_82599 - Perform hardware reset
1014 * @hw: pointer to hardware structure
1016 * Resets the hardware by resetting the transmit and receive units, masks
1017 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1020 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1022 ixgbe_link_speed link_speed;
1024 u32 ctrl, i, autoc, autoc2;
1025 bool link_up = false;
1027 DEBUGFUNC("ixgbe_reset_hw_82599");
1029 /* Call adapter stop to disable tx/rx and clear interrupts */
1030 status = hw->mac.ops.stop_adapter(hw);
1031 if (status != IXGBE_SUCCESS)
1034 /* flush pending Tx transactions */
1035 ixgbe_clear_tx_pending(hw);
1037 /* PHY ops must be identified and initialized prior to reset */
1039 /* Identify PHY and related function pointers */
1040 status = hw->phy.ops.init(hw);
1042 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1045 /* Setup SFP module if there is one present. */
1046 if (hw->phy.sfp_setup_needed) {
1047 status = hw->mac.ops.setup_sfp(hw);
1048 hw->phy.sfp_setup_needed = false;
1051 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1055 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1056 hw->phy.ops.reset(hw);
1060 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1061 * If link reset is used when link is up, it might reset the PHY when
1062 * mng is using it. If link is down or the flag to force full link
1063 * reset is set, then perform link reset.
1065 ctrl = IXGBE_CTRL_LNK_RST;
1066 if (!hw->force_full_reset) {
1067 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1069 ctrl = IXGBE_CTRL_RST;
1072 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1073 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1074 IXGBE_WRITE_FLUSH(hw);
1076 /* Poll for reset bit to self-clear indicating reset is complete */
1077 for (i = 0; i < 10; i++) {
1079 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1080 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1084 if (ctrl & IXGBE_CTRL_RST_MASK) {
1085 status = IXGBE_ERR_RESET_FAILED;
1086 DEBUGOUT("Reset polling failed to complete.\n");
1092 * Double resets are required for recovery from certain error
1093 * conditions. Between resets, it is necessary to stall to allow time
1094 * for any pending HW events to complete.
1096 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1097 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1102 * Store the original AUTOC/AUTOC2 values if they have not been
1103 * stored off yet. Otherwise restore the stored original
1104 * values since the reset operation sets back to defaults.
1106 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1107 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1109 /* Enable link if disabled in NVM */
1110 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1111 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1112 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1113 IXGBE_WRITE_FLUSH(hw);
1116 if (hw->mac.orig_link_settings_stored == false) {
1117 hw->mac.orig_autoc = autoc;
1118 hw->mac.orig_autoc2 = autoc2;
1119 hw->mac.orig_link_settings_stored = true;
1121 if (autoc != hw->mac.orig_autoc) {
1122 /* Need SW/FW semaphore around AUTOC writes if LESM is
1123 * on, likewise reset_pipeline requires us to hold
1124 * this lock as it also writes to AUTOC.
1126 bool got_lock = false;
1127 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1128 status = hw->mac.ops.acquire_swfw_sync(hw,
1129 IXGBE_GSSR_MAC_CSR_SM);
1130 if (status != IXGBE_SUCCESS) {
1131 status = IXGBE_ERR_SWFW_SYNC;
1138 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
1139 ixgbe_reset_pipeline_82599(hw);
1142 hw->mac.ops.release_swfw_sync(hw,
1143 IXGBE_GSSR_MAC_CSR_SM);
1146 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1147 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1148 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1149 autoc2 |= (hw->mac.orig_autoc2 &
1150 IXGBE_AUTOC2_UPPER_MASK);
1151 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1155 /* Store the permanent mac address */
1156 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1159 * Store MAC address from RAR0, clear receive address registers, and
1160 * clear the multicast table. Also reset num_rar_entries to 128,
1161 * since we modify this value when programming the SAN MAC address.
1163 hw->mac.num_rar_entries = 128;
1164 hw->mac.ops.init_rx_addrs(hw);
1166 /* Store the permanent SAN mac address */
1167 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1169 /* Add the SAN MAC address to the RAR only if it's a valid address */
1170 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1171 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1172 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1174 /* Save the SAN MAC RAR index */
1175 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1177 /* Reserve the last RAR for the SAN MAC address */
1178 hw->mac.num_rar_entries--;
1181 /* Store the alternative WWNN/WWPN prefix */
1182 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1183 &hw->mac.wwpn_prefix);
1190 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1191 * @hw: pointer to hardware structure
1193 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1196 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1197 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1199 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1202 * Before starting reinitialization process,
1203 * FDIRCMD.CMD must be zero.
1205 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1206 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1207 IXGBE_FDIRCMD_CMD_MASK))
1211 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1212 DEBUGOUT("Flow Director previous command isn't complete, "
1213 "aborting table re-initialization.\n");
1214 return IXGBE_ERR_FDIR_REINIT_FAILED;
1217 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1218 IXGBE_WRITE_FLUSH(hw);
1220 * 82599 adapters flow director init flow cannot be restarted,
1221 * Workaround 82599 silicon errata by performing the following steps
1222 * before re-writing the FDIRCTRL control register with the same value.
1223 * - write 1 to bit 8 of FDIRCMD register &
1224 * - write 0 to bit 8 of FDIRCMD register
1226 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1227 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1228 IXGBE_FDIRCMD_CLEARHT));
1229 IXGBE_WRITE_FLUSH(hw);
1230 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1231 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1232 ~IXGBE_FDIRCMD_CLEARHT));
1233 IXGBE_WRITE_FLUSH(hw);
1235 * Clear FDIR Hash register to clear any leftover hashes
1236 * waiting to be programmed.
1238 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1239 IXGBE_WRITE_FLUSH(hw);
1241 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1242 IXGBE_WRITE_FLUSH(hw);
1244 /* Poll init-done after we write FDIRCTRL register */
1245 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1246 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1247 IXGBE_FDIRCTRL_INIT_DONE)
1251 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1252 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1253 return IXGBE_ERR_FDIR_REINIT_FAILED;
1256 /* Clear FDIR statistics registers (read to clear) */
1257 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1258 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1259 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1260 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1261 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1263 return IXGBE_SUCCESS;
1267 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1268 * @hw: pointer to hardware structure
1269 * @fdirctrl: value to write to flow director control register
1271 STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1275 DEBUGFUNC("ixgbe_fdir_enable_82599");
1277 /* Prime the keys for hashing */
1278 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1279 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1282 * Poll init-done after we write the register. Estimated times:
1283 * 10G: PBALLOC = 11b, timing is 60us
1284 * 1G: PBALLOC = 11b, timing is 600us
1285 * 100M: PBALLOC = 11b, timing is 6ms
1287 * Multiple these timings by 4 if under full Rx load
1289 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1290 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1291 * this might not finish in our poll time, but we can live with that
1294 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1295 IXGBE_WRITE_FLUSH(hw);
1296 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1297 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1298 IXGBE_FDIRCTRL_INIT_DONE)
1303 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1304 DEBUGOUT("Flow Director poll time exceeded!\n");
1308 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1309 * @hw: pointer to hardware structure
1310 * @fdirctrl: value to write to flow director control register, initially
1311 * contains just the value of the Rx packet buffer allocation
1313 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1315 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1318 * Continue setup of fdirctrl register bits:
1319 * Move the flexible bytes to use the ethertype - shift 6 words
1320 * Set the maximum length per hash bucket to 0xA filters
1321 * Send interrupt when 64 filters are left
1323 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1324 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1325 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1327 /* write hashes and fdirctrl register, poll for completion */
1328 ixgbe_fdir_enable_82599(hw, fdirctrl);
1330 return IXGBE_SUCCESS;
1334 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1335 * @hw: pointer to hardware structure
1336 * @fdirctrl: value to write to flow director control register, initially
1337 * contains just the value of the Rx packet buffer allocation
1339 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1341 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1344 * Continue setup of fdirctrl register bits:
1345 * Turn perfect match filtering on
1346 * Report hash in RSS field of Rx wb descriptor
1347 * Initialize the drop queue
1348 * Move the flexible bytes to use the ethertype - shift 6 words
1349 * Set the maximum length per hash bucket to 0xA filters
1350 * Send interrupt when 64 (0x4 * 16) filters are left
1352 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1353 IXGBE_FDIRCTRL_REPORT_STATUS |
1354 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1355 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1356 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1357 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1359 /* write hashes and fdirctrl register, poll for completion */
1360 ixgbe_fdir_enable_82599(hw, fdirctrl);
1362 return IXGBE_SUCCESS;
1366 * These defines allow us to quickly generate all of the necessary instructions
1367 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1368 * for values 0 through 15
1370 #define IXGBE_ATR_COMMON_HASH_KEY \
1371 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1372 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1375 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1376 common_hash ^= lo_hash_dword >> n; \
1377 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1378 bucket_hash ^= lo_hash_dword >> n; \
1379 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1380 sig_hash ^= lo_hash_dword << (16 - n); \
1381 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1382 common_hash ^= hi_hash_dword >> n; \
1383 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1384 bucket_hash ^= hi_hash_dword >> n; \
1385 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1386 sig_hash ^= hi_hash_dword << (16 - n); \
1390 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1391 * @stream: input bitstream to compute the hash on
1393 * This function is almost identical to the function above but contains
1394 * several optomizations such as unwinding all of the loops, letting the
1395 * compiler work out all of the conditional ifs since the keys are static
1396 * defines, and computing two keys at once since the hashed dword stream
1397 * will be the same for both keys.
1399 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1400 union ixgbe_atr_hash_dword common)
1402 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1403 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1405 /* record the flow_vm_vlan bits as they are a key part to the hash */
1406 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1408 /* generate common hash dword */
1409 hi_hash_dword = IXGBE_NTOHL(common.dword);
1411 /* low dword is word swapped version of common */
1412 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1414 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1415 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1417 /* Process bits 0 and 16 */
1418 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1421 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1422 * delay this because bit 0 of the stream should not be processed
1423 * so we do not add the vlan until after bit 0 was processed
1425 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1427 /* Process remaining 30 bit of the key */
1428 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1429 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1430 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1431 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1432 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1433 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1434 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1435 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1436 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1437 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1438 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1439 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1440 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1441 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1442 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1444 /* combine common_hash result with signature and bucket hashes */
1445 bucket_hash ^= common_hash;
1446 bucket_hash &= IXGBE_ATR_HASH_MASK;
1448 sig_hash ^= common_hash << 16;
1449 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1451 /* return completed signature hash */
1452 return sig_hash ^ bucket_hash;
1456 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1457 * @hw: pointer to hardware structure
1458 * @input: unique input dword
1459 * @common: compressed common input dword
1460 * @queue: queue index to direct traffic to
1462 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1463 union ixgbe_atr_hash_dword input,
1464 union ixgbe_atr_hash_dword common,
1470 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1473 * Get the flow_type in order to program FDIRCMD properly
1474 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1476 switch (input.formatted.flow_type) {
1477 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1478 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1479 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1480 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1481 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1482 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1485 DEBUGOUT(" Error on flow type input\n");
1486 return IXGBE_ERR_CONFIG;
1489 /* configure FDIRCMD register */
1490 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1491 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1492 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1493 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1496 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1497 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1499 fdirhashcmd = (u64)fdircmd << 32;
1500 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1501 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1503 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1505 return IXGBE_SUCCESS;
1508 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1511 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1512 bucket_hash ^= lo_hash_dword >> n; \
1513 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1514 bucket_hash ^= hi_hash_dword >> n; \
1518 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1519 * @atr_input: input bitstream to compute the hash on
1520 * @input_mask: mask for the input bitstream
1522 * This function serves two main purposes. First it applys the input_mask
1523 * to the atr_input resulting in a cleaned up atr_input data stream.
1524 * Secondly it computes the hash and stores it in the bkt_hash field at
1525 * the end of the input byte stream. This way it will be available for
1526 * future use without needing to recompute the hash.
1528 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1529 union ixgbe_atr_input *input_mask)
1532 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1533 u32 bucket_hash = 0;
1535 /* Apply masks to input data */
1536 input->dword_stream[0] &= input_mask->dword_stream[0];
1537 input->dword_stream[1] &= input_mask->dword_stream[1];
1538 input->dword_stream[2] &= input_mask->dword_stream[2];
1539 input->dword_stream[3] &= input_mask->dword_stream[3];
1540 input->dword_stream[4] &= input_mask->dword_stream[4];
1541 input->dword_stream[5] &= input_mask->dword_stream[5];
1542 input->dword_stream[6] &= input_mask->dword_stream[6];
1543 input->dword_stream[7] &= input_mask->dword_stream[7];
1544 input->dword_stream[8] &= input_mask->dword_stream[8];
1545 input->dword_stream[9] &= input_mask->dword_stream[9];
1546 input->dword_stream[10] &= input_mask->dword_stream[10];
1548 /* record the flow_vm_vlan bits as they are a key part to the hash */
1549 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1551 /* generate common hash dword */
1552 hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
1553 input->dword_stream[2] ^
1554 input->dword_stream[3] ^
1555 input->dword_stream[4] ^
1556 input->dword_stream[5] ^
1557 input->dword_stream[6] ^
1558 input->dword_stream[7] ^
1559 input->dword_stream[8] ^
1560 input->dword_stream[9] ^
1561 input->dword_stream[10]);
1563 /* low dword is word swapped version of common */
1564 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1566 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1567 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1569 /* Process bits 0 and 16 */
1570 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1573 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1574 * delay this because bit 0 of the stream should not be processed
1575 * so we do not add the vlan until after bit 0 was processed
1577 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1579 /* Process remaining 30 bit of the key */
1580 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1581 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1582 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1583 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1584 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1585 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1586 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1587 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1588 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1589 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1590 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1591 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1592 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1593 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1594 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1597 * Limit hash to 13 bits since max bucket count is 8K.
1598 * Store result at the end of the input stream.
1600 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1604 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1605 * @input_mask: mask to be bit swapped
1607 * The source and destination port masks for flow director are bit swapped
1608 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1609 * generate a correctly swapped value we need to bit swap the mask and that
1610 * is what is accomplished by this function.
1612 STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1614 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1615 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1616 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1617 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1618 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1619 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1620 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1624 * These two macros are meant to address the fact that we have registers
1625 * that are either all or in part big-endian. As a result on big-endian
1626 * systems we will end up byte swapping the value to little-endian before
1627 * it is byte swapped again and written to the hardware in the original
1628 * big-endian format.
1630 #define IXGBE_STORE_AS_BE32(_value) \
1631 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1632 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1634 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1635 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1637 #define IXGBE_STORE_AS_BE16(_value) \
1638 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1640 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1641 union ixgbe_atr_input *input_mask)
1643 /* mask IPv6 since it is currently not supported */
1644 u32 fdirm = IXGBE_FDIRM_DIPv6;
1647 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1650 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1651 * are zero, then assume a full mask for that field. Also assume that
1652 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1653 * cannot be masked out in this implementation.
1655 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1659 /* verify bucket hash is cleared on hash generation */
1660 if (input_mask->formatted.bkt_hash)
1661 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1663 /* Program FDIRM and verify partial masks */
1664 switch (input_mask->formatted.vm_pool & 0x7F) {
1666 fdirm |= IXGBE_FDIRM_POOL;
1670 DEBUGOUT(" Error on vm pool mask\n");
1671 return IXGBE_ERR_CONFIG;
1674 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1676 fdirm |= IXGBE_FDIRM_L4P;
1677 if (input_mask->formatted.dst_port ||
1678 input_mask->formatted.src_port) {
1679 DEBUGOUT(" Error on src/dst port mask\n");
1680 return IXGBE_ERR_CONFIG;
1682 case IXGBE_ATR_L4TYPE_MASK:
1685 DEBUGOUT(" Error on flow type mask\n");
1686 return IXGBE_ERR_CONFIG;
1689 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1691 /* mask VLAN ID, fall through to mask VLAN priority */
1692 fdirm |= IXGBE_FDIRM_VLANID;
1694 /* mask VLAN priority */
1695 fdirm |= IXGBE_FDIRM_VLANP;
1698 /* mask VLAN ID only, fall through */
1699 fdirm |= IXGBE_FDIRM_VLANID;
1701 /* no VLAN fields masked */
1704 DEBUGOUT(" Error on VLAN mask\n");
1705 return IXGBE_ERR_CONFIG;
1708 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1710 /* Mask Flex Bytes, fall through */
1711 fdirm |= IXGBE_FDIRM_FLEX;
1715 DEBUGOUT(" Error on flexible byte mask\n");
1716 return IXGBE_ERR_CONFIG;
1719 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1720 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1722 /* store the TCP/UDP port masks, bit reversed from port layout */
1723 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1725 /* write both the same so that UDP and TCP use the same mask */
1726 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1727 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1729 /* store source and destination IP masks (big-enian) */
1730 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1731 ~input_mask->formatted.src_ip[0]);
1732 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1733 ~input_mask->formatted.dst_ip[0]);
1735 return IXGBE_SUCCESS;
1738 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1739 union ixgbe_atr_input *input,
1740 u16 soft_id, u8 queue)
1742 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1744 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1746 /* currently IPv6 is not supported, must be programmed with 0 */
1747 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1748 input->formatted.src_ip[0]);
1749 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1750 input->formatted.src_ip[1]);
1751 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1752 input->formatted.src_ip[2]);
1754 /* record the source address (big-endian) */
1755 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1757 /* record the first 32 bits of the destination address (big-endian) */
1758 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1760 /* record source and destination port (little-endian)*/
1761 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1762 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1763 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1764 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1766 /* record vlan (little-endian) and flex_bytes(big-endian) */
1767 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1768 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1769 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1770 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1772 /* configure FDIRHASH register */
1773 fdirhash = input->formatted.bkt_hash;
1774 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1775 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1778 * flush all previous writes to make certain registers are
1779 * programmed prior to issuing the command
1781 IXGBE_WRITE_FLUSH(hw);
1783 /* configure FDIRCMD register */
1784 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1785 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1786 if (queue == IXGBE_FDIR_DROP_QUEUE)
1787 fdircmd |= IXGBE_FDIRCMD_DROP;
1788 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1789 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1790 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1792 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1794 return IXGBE_SUCCESS;
1797 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1798 union ixgbe_atr_input *input,
1804 s32 err = IXGBE_SUCCESS;
1806 /* configure FDIRHASH register */
1807 fdirhash = input->formatted.bkt_hash;
1808 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1809 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1811 /* flush hash to HW */
1812 IXGBE_WRITE_FLUSH(hw);
1814 /* Query if filter is present */
1815 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1817 for (retry_count = 10; retry_count; retry_count--) {
1818 /* allow 10us for query to process */
1820 /* verify query completed successfully */
1821 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1822 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1827 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1829 /* if filter exists in hardware then remove it */
1830 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1831 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1832 IXGBE_WRITE_FLUSH(hw);
1833 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1834 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1841 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1842 * @hw: pointer to hardware structure
1843 * @input: input bitstream
1844 * @input_mask: mask for the input bitstream
1845 * @soft_id: software index for the filters
1846 * @queue: queue index to direct traffic to
1848 * Note that the caller to this function must lock before calling, since the
1849 * hardware writes must be protected from one another.
1851 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1852 union ixgbe_atr_input *input,
1853 union ixgbe_atr_input *input_mask,
1854 u16 soft_id, u8 queue)
1856 s32 err = IXGBE_ERR_CONFIG;
1858 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1861 * Check flow_type formatting, and bail out before we touch the hardware
1862 * if there's a configuration issue
1864 switch (input->formatted.flow_type) {
1865 case IXGBE_ATR_FLOW_TYPE_IPV4:
1866 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1867 if (input->formatted.dst_port || input->formatted.src_port) {
1868 DEBUGOUT(" Error on src/dst port\n");
1869 return IXGBE_ERR_CONFIG;
1872 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1873 if (input->formatted.dst_port || input->formatted.src_port) {
1874 DEBUGOUT(" Error on src/dst port\n");
1875 return IXGBE_ERR_CONFIG;
1877 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1878 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1879 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
1880 IXGBE_ATR_L4TYPE_MASK;
1883 DEBUGOUT(" Error on flow type input\n");
1887 /* program input mask into the HW */
1888 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
1892 /* apply mask and compute/store hash */
1893 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
1895 /* program filters to filter memory */
1896 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
1901 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1902 * @hw: pointer to hardware structure
1903 * @reg: analog register to read
1906 * Performs read operation to Omer analog register specified.
1908 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1912 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
1914 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1916 IXGBE_WRITE_FLUSH(hw);
1918 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1919 *val = (u8)core_ctl;
1921 return IXGBE_SUCCESS;
1925 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1926 * @hw: pointer to hardware structure
1927 * @reg: atlas register to write
1928 * @val: value to write
1930 * Performs write operation to Omer analog register specified.
1932 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1936 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
1938 core_ctl = (reg << 8) | val;
1939 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1940 IXGBE_WRITE_FLUSH(hw);
1943 return IXGBE_SUCCESS;
1947 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1948 * @hw: pointer to hardware structure
1950 * Starts the hardware using the generic start_hw function
1951 * and the generation start_hw function.
1952 * Then performs revision-specific operations, if any.
1954 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1956 s32 ret_val = IXGBE_SUCCESS;
1958 DEBUGFUNC("ixgbe_start_hw_82599");
1960 ret_val = ixgbe_start_hw_generic(hw);
1961 if (ret_val != IXGBE_SUCCESS)
1964 ret_val = ixgbe_start_hw_gen2(hw);
1965 if (ret_val != IXGBE_SUCCESS)
1968 /* We need to run link autotry after the driver loads */
1969 hw->mac.autotry_restart = true;
1971 if (ret_val == IXGBE_SUCCESS)
1972 ret_val = ixgbe_verify_fw_version_82599(hw);
1978 * ixgbe_identify_phy_82599 - Get physical layer module
1979 * @hw: pointer to hardware structure
1981 * Determines the physical layer module found on the current adapter.
1982 * If PHY already detected, maintains current PHY type in hw struct,
1983 * otherwise executes the PHY detection routine.
1985 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1987 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1989 DEBUGFUNC("ixgbe_identify_phy_82599");
1991 /* Detect PHY if not unknown - returns success if already detected. */
1992 status = ixgbe_identify_phy_generic(hw);
1993 if (status != IXGBE_SUCCESS) {
1994 /* 82599 10GBASE-T requires an external PHY */
1995 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1998 status = ixgbe_identify_module_generic(hw);
2001 /* Set PHY type none if no PHY detected */
2002 if (hw->phy.type == ixgbe_phy_unknown) {
2003 hw->phy.type = ixgbe_phy_none;
2004 status = IXGBE_SUCCESS;
2007 /* Return error if SFP module has been detected but is not supported */
2008 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2009 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
2016 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2017 * @hw: pointer to hardware structure
2019 * Determines physical layer capabilities of the current configuration.
2021 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2023 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2024 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2025 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2026 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2027 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2028 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2029 u16 ext_ability = 0;
2030 u8 comp_codes_10g = 0;
2031 u8 comp_codes_1g = 0;
2033 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2035 hw->phy.ops.identify(hw);
2037 switch (hw->phy.type) {
2039 case ixgbe_phy_cu_unknown:
2040 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2041 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2042 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2043 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2044 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2045 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2046 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
2047 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2053 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2054 case IXGBE_AUTOC_LMS_1G_AN:
2055 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2056 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2057 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2058 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2061 /* SFI mode so read SFP module */
2064 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2065 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2066 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2067 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2068 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2069 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2070 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2073 case IXGBE_AUTOC_LMS_10G_SERIAL:
2074 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2075 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2077 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2080 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2081 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2082 if (autoc & IXGBE_AUTOC_KX_SUPP)
2083 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2084 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2085 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2086 if (autoc & IXGBE_AUTOC_KR_SUPP)
2087 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2096 /* SFP check must be done last since DA modules are sometimes used to
2097 * test KR mode - we need to id KR mode correctly before SFP module.
2098 * Call identify_sfp because the pluggable module may have changed */
2099 hw->phy.ops.identify_sfp(hw);
2100 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2103 switch (hw->phy.type) {
2104 case ixgbe_phy_sfp_passive_tyco:
2105 case ixgbe_phy_sfp_passive_unknown:
2106 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2108 case ixgbe_phy_sfp_ftl_active:
2109 case ixgbe_phy_sfp_active_unknown:
2110 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2112 case ixgbe_phy_sfp_avago:
2113 case ixgbe_phy_sfp_ftl:
2114 case ixgbe_phy_sfp_intel:
2115 case ixgbe_phy_sfp_unknown:
2116 hw->phy.ops.read_i2c_eeprom(hw,
2117 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2118 hw->phy.ops.read_i2c_eeprom(hw,
2119 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2120 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2121 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2122 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2123 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2124 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2125 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2126 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
2127 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
2134 return physical_layer;
2138 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2139 * @hw: pointer to hardware structure
2140 * @regval: register value to write to RXCTRL
2142 * Enables the Rx DMA unit for 82599
2144 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2147 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2150 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2151 * If traffic is incoming before we enable the Rx unit, it could hang
2152 * the Rx DMA unit. Therefore, make sure the security engine is
2153 * completely disabled prior to enabling the Rx unit.
2156 hw->mac.ops.disable_sec_rx_path(hw);
2158 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2160 hw->mac.ops.enable_sec_rx_path(hw);
2162 return IXGBE_SUCCESS;
2166 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2167 * @hw: pointer to hardware structure
2169 * Verifies that installed the firmware version is 0.6 or higher
2170 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2172 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2173 * if the FW version is not supported.
2175 s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2177 s32 status = IXGBE_ERR_EEPROM_VERSION;
2178 u16 fw_offset, fw_ptp_cfg_offset;
2181 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2183 /* firmware check is only necessary for SFI devices */
2184 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2185 status = IXGBE_SUCCESS;
2186 goto fw_version_out;
2189 /* get the offset to the Firmware Module block */
2190 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2192 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2193 goto fw_version_out;
2195 /* get the offset to the Pass Through Patch Configuration block */
2196 hw->eeprom.ops.read(hw, (fw_offset +
2197 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2198 &fw_ptp_cfg_offset);
2200 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2201 goto fw_version_out;
2203 /* get the firmware version */
2204 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2205 IXGBE_FW_PATCH_VERSION_4), &fw_version);
2207 if (fw_version > 0x5)
2208 status = IXGBE_SUCCESS;
2215 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2216 * @hw: pointer to hardware structure
2218 * Returns true if the LESM FW module is present and enabled. Otherwise
2219 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2221 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2223 bool lesm_enabled = false;
2224 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2227 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2229 /* get the offset to the Firmware Module block */
2230 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2232 if ((status != IXGBE_SUCCESS) ||
2233 (fw_offset == 0) || (fw_offset == 0xFFFF))
2236 /* get the offset to the LESM Parameters block */
2237 status = hw->eeprom.ops.read(hw, (fw_offset +
2238 IXGBE_FW_LESM_PARAMETERS_PTR),
2239 &fw_lesm_param_offset);
2241 if ((status != IXGBE_SUCCESS) ||
2242 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2245 /* get the lesm state word */
2246 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2247 IXGBE_FW_LESM_STATE_1),
2250 if ((status == IXGBE_SUCCESS) &&
2251 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2252 lesm_enabled = true;
2255 return lesm_enabled;
2259 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2260 * fastest available method
2262 * @hw: pointer to hardware structure
2263 * @offset: offset of word in EEPROM to read
2264 * @words: number of words
2265 * @data: word(s) read from the EEPROM
2267 * Retrieves 16 bit word(s) read from EEPROM
2269 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2270 u16 words, u16 *data)
2272 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2273 s32 ret_val = IXGBE_ERR_CONFIG;
2275 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2278 * If EEPROM is detected and can be addressed using 14 bits,
2279 * use EERD otherwise use bit bang
2281 if ((eeprom->type == ixgbe_eeprom_spi) &&
2282 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2283 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2286 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2294 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2295 * fastest available method
2297 * @hw: pointer to hardware structure
2298 * @offset: offset of word in the EEPROM to read
2299 * @data: word read from the EEPROM
2301 * Reads a 16 bit word from the EEPROM
2303 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2304 u16 offset, u16 *data)
2306 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2307 s32 ret_val = IXGBE_ERR_CONFIG;
2309 DEBUGFUNC("ixgbe_read_eeprom_82599");
2312 * If EEPROM is detected and can be addressed using 14 bits,
2313 * use EERD otherwise use bit bang
2315 if ((eeprom->type == ixgbe_eeprom_spi) &&
2316 (offset <= IXGBE_EERD_MAX_ADDR))
2317 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2319 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2325 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2327 * @hw: pointer to hardware structure
2329 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2330 * full pipeline reset
2332 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2334 s32 i, autoc_reg, autoc2_reg, ret_val;
2337 /* Enable link if disabled in NVM */
2338 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2339 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2340 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2341 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2342 IXGBE_WRITE_FLUSH(hw);
2345 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2346 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2347 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2348 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
2349 /* Wait for AN to leave state 0 */
2350 for (i = 0; i < 10; i++) {
2352 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2353 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2357 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2358 DEBUGOUT("auto negotiation not completed\n");
2359 ret_val = IXGBE_ERR_RESET_FAILED;
2360 goto reset_pipeline_out;
2363 ret_val = IXGBE_SUCCESS;
2366 /* Write AUTOC register with original LMS field and Restart_AN */
2367 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2368 IXGBE_WRITE_FLUSH(hw);