1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82599.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
39 #ident "$Id: ixgbe_82599.c,v 1.301 2012/11/08 11:33:27 jtkirshe Exp $"
41 #define IXGBE_82599_MAX_TX_QUEUES 128
42 #define IXGBE_82599_MAX_RX_QUEUES 128
43 #define IXGBE_82599_RAR_ENTRIES 128
44 #define IXGBE_82599_MC_TBL_SIZE 128
45 #define IXGBE_82599_VFT_TBL_SIZE 128
46 #define IXGBE_82599_RX_PB_SIZE 512
48 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
49 ixgbe_link_speed speed,
51 bool autoneg_wait_to_complete);
52 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
53 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
54 u16 offset, u16 *data);
55 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
56 u16 words, u16 *data);
58 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
60 u32 fwsm, manc, factps;
62 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
63 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
66 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
67 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
70 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
71 if (factps & IXGBE_FACTPS_MNGCG)
77 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
79 struct ixgbe_mac_info *mac = &hw->mac;
81 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
84 * enable the laser control functions for SFP+ fiber
87 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
88 !ixgbe_mng_enabled(hw)) {
89 mac->ops.disable_tx_laser =
90 &ixgbe_disable_tx_laser_multispeed_fiber;
91 mac->ops.enable_tx_laser =
92 &ixgbe_enable_tx_laser_multispeed_fiber;
93 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
96 mac->ops.disable_tx_laser = NULL;
97 mac->ops.enable_tx_laser = NULL;
98 mac->ops.flap_tx_laser = NULL;
101 if (hw->phy.multispeed_fiber) {
102 /* Set up dual speed SFP+ support */
103 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
105 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
106 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
107 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
108 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
109 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
111 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
117 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
118 * @hw: pointer to hardware structure
120 * Initialize any function pointers that were not able to be
121 * set during init_shared_code because the PHY/SFP type was
122 * not known. Perform the SFP init if necessary.
125 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
127 struct ixgbe_mac_info *mac = &hw->mac;
128 struct ixgbe_phy_info *phy = &hw->phy;
129 s32 ret_val = IXGBE_SUCCESS;
131 DEBUGFUNC("ixgbe_init_phy_ops_82599");
133 /* Identify the PHY or SFP module */
134 ret_val = phy->ops.identify(hw);
135 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
136 goto init_phy_ops_out;
138 /* Setup function pointers based on detected SFP module and speeds */
139 ixgbe_init_mac_link_ops_82599(hw);
140 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
141 hw->phy.ops.reset = NULL;
143 /* If copper media, overwrite with copper function pointers */
144 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
145 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
146 mac->ops.get_link_capabilities =
147 &ixgbe_get_copper_link_capabilities_generic;
150 /* Set necessary function pointers based on phy type */
151 switch (hw->phy.type) {
153 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
154 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
155 phy->ops.get_firmware_version =
156 &ixgbe_get_phy_firmware_version_tnx;
165 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
167 s32 ret_val = IXGBE_SUCCESS;
168 u16 list_offset, data_offset, data_value;
169 bool got_lock = false;
171 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
173 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
174 ixgbe_init_mac_link_ops_82599(hw);
176 hw->phy.ops.reset = NULL;
178 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
180 if (ret_val != IXGBE_SUCCESS)
183 /* PHY config will finish before releasing the semaphore */
184 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
185 IXGBE_GSSR_MAC_CSR_SM);
186 if (ret_val != IXGBE_SUCCESS) {
187 ret_val = IXGBE_ERR_SWFW_SYNC;
191 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
192 while (data_value != 0xffff) {
193 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
194 IXGBE_WRITE_FLUSH(hw);
195 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
198 /* Release the semaphore */
199 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
200 /* Delay obtaining semaphore again to allow FW access */
201 msec_delay(hw->eeprom.semaphore_delay);
203 /* Need SW/FW semaphore around AUTOC writes if LESM on,
204 * likewise reset_pipeline requires lock as it also writes
207 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
208 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
209 IXGBE_GSSR_MAC_CSR_SM);
210 if (ret_val != IXGBE_SUCCESS) {
211 ret_val = IXGBE_ERR_SWFW_SYNC;
218 /* Restart DSP and set SFI mode */
219 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
220 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL));
222 ret_val = ixgbe_reset_pipeline_82599(hw);
225 hw->mac.ops.release_swfw_sync(hw,
226 IXGBE_GSSR_MAC_CSR_SM);
231 DEBUGOUT("sfp module setup not complete\n");
232 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
243 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
244 * @hw: pointer to hardware structure
246 * Initialize the function pointers and assign the MAC type for 82599.
247 * Does not touch the hardware.
250 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
252 struct ixgbe_mac_info *mac = &hw->mac;
253 struct ixgbe_phy_info *phy = &hw->phy;
254 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
257 DEBUGFUNC("ixgbe_init_ops_82599");
259 ret_val = ixgbe_init_phy_ops_generic(hw);
260 ret_val = ixgbe_init_ops_generic(hw);
263 phy->ops.identify = &ixgbe_identify_phy_82599;
264 phy->ops.init = &ixgbe_init_phy_ops_82599;
267 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
268 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
269 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
270 mac->ops.get_supported_physical_layer =
271 &ixgbe_get_supported_physical_layer_82599;
272 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
273 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
274 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
275 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
276 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
277 mac->ops.start_hw = &ixgbe_start_hw_82599;
278 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
279 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
280 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
281 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
282 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
284 /* RAR, Multicast, VLAN */
285 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
286 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
287 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
288 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
289 mac->rar_highwater = 1;
290 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
291 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
292 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
293 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
294 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
295 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
296 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
299 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
300 mac->ops.check_link = &ixgbe_check_mac_link_generic;
301 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
302 ixgbe_init_mac_link_ops_82599(hw);
304 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
305 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
306 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
307 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
308 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
309 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
310 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
312 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
313 IXGBE_FWSM_MODE_MASK) ? true : false;
315 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
318 eeprom->ops.read = &ixgbe_read_eeprom_82599;
319 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
321 /* Manageability interface */
322 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
325 mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
331 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
332 * @hw: pointer to hardware structure
333 * @speed: pointer to link speed
334 * @negotiation: true when autoneg or autotry is enabled
336 * Determines the link capabilities by reading the AUTOC register.
338 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
339 ixgbe_link_speed *speed,
342 s32 status = IXGBE_SUCCESS;
345 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
348 /* Check if 1G SFP module. */
349 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
350 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
351 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
352 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
353 *speed = IXGBE_LINK_SPEED_1GB_FULL;
359 * Determine link capabilities based on the stored value of AUTOC,
360 * which represents EEPROM defaults. If AUTOC value has not
361 * been stored, use the current register values.
363 if (hw->mac.orig_link_settings_stored)
364 autoc = hw->mac.orig_autoc;
366 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
368 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
369 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
370 *speed = IXGBE_LINK_SPEED_1GB_FULL;
371 *negotiation = false;
374 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
375 *speed = IXGBE_LINK_SPEED_10GB_FULL;
376 *negotiation = false;
379 case IXGBE_AUTOC_LMS_1G_AN:
380 *speed = IXGBE_LINK_SPEED_1GB_FULL;
384 case IXGBE_AUTOC_LMS_10G_SERIAL:
385 *speed = IXGBE_LINK_SPEED_10GB_FULL;
386 *negotiation = false;
389 case IXGBE_AUTOC_LMS_KX4_KX_KR:
390 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
391 *speed = IXGBE_LINK_SPEED_UNKNOWN;
392 if (autoc & IXGBE_AUTOC_KR_SUPP)
393 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
394 if (autoc & IXGBE_AUTOC_KX4_SUPP)
395 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
396 if (autoc & IXGBE_AUTOC_KX_SUPP)
397 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
401 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
402 *speed = IXGBE_LINK_SPEED_100_FULL;
403 if (autoc & IXGBE_AUTOC_KR_SUPP)
404 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
405 if (autoc & IXGBE_AUTOC_KX4_SUPP)
406 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
407 if (autoc & IXGBE_AUTOC_KX_SUPP)
408 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
412 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
413 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
414 *negotiation = false;
418 status = IXGBE_ERR_LINK_SETUP;
423 if (hw->phy.multispeed_fiber) {
424 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
425 IXGBE_LINK_SPEED_1GB_FULL;
434 * ixgbe_get_media_type_82599 - Get media type
435 * @hw: pointer to hardware structure
437 * Returns the media type (fiber, copper, backplane)
439 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
441 enum ixgbe_media_type media_type;
443 DEBUGFUNC("ixgbe_get_media_type_82599");
445 /* Detect if there is a copper PHY attached. */
446 switch (hw->phy.type) {
447 case ixgbe_phy_cu_unknown:
449 media_type = ixgbe_media_type_copper;
455 switch (hw->device_id) {
456 case IXGBE_DEV_ID_82599_KX4:
457 case IXGBE_DEV_ID_82599_KX4_MEZZ:
458 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
459 case IXGBE_DEV_ID_82599_KR:
460 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
461 case IXGBE_DEV_ID_82599_XAUI_LOM:
462 /* Default device ID is mezzanine card KX/KX4 */
463 media_type = ixgbe_media_type_backplane;
465 case IXGBE_DEV_ID_82599_SFP:
466 case IXGBE_DEV_ID_82599_SFP_FCOE:
467 case IXGBE_DEV_ID_82599_SFP_EM:
468 case IXGBE_DEV_ID_82599_SFP_SF2:
469 case IXGBE_DEV_ID_82599_SFP_SF_QP:
470 case IXGBE_DEV_ID_82599EN_SFP:
471 #ifdef RTE_NIC_BYPASS
472 case IXGBE_DEV_ID_82599_BYPASS:
474 media_type = ixgbe_media_type_fiber;
476 case IXGBE_DEV_ID_82599_CX4:
477 media_type = ixgbe_media_type_cx4;
479 case IXGBE_DEV_ID_82599_T3_LOM:
480 media_type = ixgbe_media_type_copper;
483 media_type = ixgbe_media_type_unknown;
491 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
492 * @hw: pointer to hardware structure
494 * Disables link during D3 power down sequence.
497 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
499 u32 autoc2_reg, fwsm;
502 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
503 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
505 /* Check to see if MNG FW could be enabled */
506 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
508 if (((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) &&
510 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
511 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
512 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
513 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
518 * ixgbe_start_mac_link_82599 - Setup MAC link settings
519 * @hw: pointer to hardware structure
520 * @autoneg_wait_to_complete: true when waiting for completion is needed
522 * Configures link settings based on values in the ixgbe_hw struct.
523 * Restarts the link. Performs autonegotiation if needed.
525 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
526 bool autoneg_wait_to_complete)
531 s32 status = IXGBE_SUCCESS;
532 bool got_lock = false;
534 DEBUGFUNC("ixgbe_start_mac_link_82599");
537 /* reset_pipeline requires us to hold this lock as it writes to
540 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
541 status = hw->mac.ops.acquire_swfw_sync(hw,
542 IXGBE_GSSR_MAC_CSR_SM);
543 if (status != IXGBE_SUCCESS)
550 ixgbe_reset_pipeline_82599(hw);
553 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
555 /* Only poll for autoneg to complete if specified to do so */
556 if (autoneg_wait_to_complete) {
557 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
558 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
559 IXGBE_AUTOC_LMS_KX4_KX_KR ||
560 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
561 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
562 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
563 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
564 links_reg = 0; /* Just in case Autoneg time = 0 */
565 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
566 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
567 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
571 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
572 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
573 DEBUGOUT("Autoneg did not complete.\n");
578 /* Add delay to filter out noises during initial link setup */
586 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
587 * @hw: pointer to hardware structure
589 * The base drivers may require better control over SFP+ module
590 * PHY states. This includes selectively shutting down the Tx
591 * laser on the PHY, effectively halting physical link.
593 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
595 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
597 /* Disable tx laser; allow 100us to go dark per spec */
598 esdp_reg |= IXGBE_ESDP_SDP3;
599 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
600 IXGBE_WRITE_FLUSH(hw);
605 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
606 * @hw: pointer to hardware structure
608 * The base drivers may require better control over SFP+ module
609 * PHY states. This includes selectively turning on the Tx
610 * laser on the PHY, effectively starting physical link.
612 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
614 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
616 /* Enable tx laser; allow 100ms to light up */
617 esdp_reg &= ~IXGBE_ESDP_SDP3;
618 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
619 IXGBE_WRITE_FLUSH(hw);
624 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
625 * @hw: pointer to hardware structure
627 * When the driver changes the link speeds that it can support,
628 * it sets autotry_restart to true to indicate that we need to
629 * initiate a new autotry session with the link partner. To do
630 * so, we set the speed then disable and re-enable the tx laser, to
631 * alert the link partner that it also needs to restart autotry on its
632 * end. This is consistent with true clause 37 autoneg, which also
633 * involves a loss of signal.
635 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
637 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
639 if (hw->mac.autotry_restart) {
640 ixgbe_disable_tx_laser_multispeed_fiber(hw);
641 ixgbe_enable_tx_laser_multispeed_fiber(hw);
642 hw->mac.autotry_restart = false;
647 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
648 * @hw: pointer to hardware structure
649 * @speed: new link speed
650 * @autoneg: true if autonegotiation enabled
651 * @autoneg_wait_to_complete: true when waiting for completion is needed
653 * Set the link speed in the AUTOC register and restarts link.
655 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
656 ixgbe_link_speed speed, bool autoneg,
657 bool autoneg_wait_to_complete)
659 s32 status = IXGBE_SUCCESS;
660 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
661 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
663 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
665 bool link_up = false;
668 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
670 /* Mask off requested but non-supported speeds */
671 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);
672 if (status != IXGBE_SUCCESS)
678 * Try each speed one by one, highest priority first. We do this in
679 * software because 10gb fiber doesn't support speed autonegotiation.
681 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
683 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
685 /* If we already have link at this speed, just jump out */
686 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
687 if (status != IXGBE_SUCCESS)
690 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
693 /* Set the module link speed */
694 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
695 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
696 IXGBE_WRITE_FLUSH(hw);
698 /* Allow module to change analog characteristics (1G->10G) */
701 status = ixgbe_setup_mac_link_82599(hw,
702 IXGBE_LINK_SPEED_10GB_FULL,
704 autoneg_wait_to_complete);
705 if (status != IXGBE_SUCCESS)
708 /* Flap the tx laser if it has not already been done */
709 ixgbe_flap_tx_laser(hw);
712 * Wait for the controller to acquire link. Per IEEE 802.3ap,
713 * Section 73.10.2, we may have to wait up to 500ms if KR is
714 * attempted. 82599 uses the same timing for 10g SFI.
716 for (i = 0; i < 5; i++) {
717 /* Wait for the link partner to also set speed */
720 /* If we have link, just jump out */
721 status = ixgbe_check_link(hw, &link_speed,
723 if (status != IXGBE_SUCCESS)
731 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
733 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
734 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
736 /* If we already have link at this speed, just jump out */
737 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
738 if (status != IXGBE_SUCCESS)
741 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
744 /* Set the module link speed */
745 esdp_reg &= ~IXGBE_ESDP_SDP5;
746 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
747 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
748 IXGBE_WRITE_FLUSH(hw);
750 /* Allow module to change analog characteristics (10G->1G) */
753 status = ixgbe_setup_mac_link_82599(hw,
754 IXGBE_LINK_SPEED_1GB_FULL,
756 autoneg_wait_to_complete);
757 if (status != IXGBE_SUCCESS)
760 /* Flap the tx laser if it has not already been done */
761 ixgbe_flap_tx_laser(hw);
763 /* Wait for the link partner to also set speed */
766 /* If we have link, just jump out */
767 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
768 if (status != IXGBE_SUCCESS)
776 * We didn't get link. Configure back to the highest speed we tried,
777 * (if there was more than one). We call ourselves back with just the
778 * single highest speed that the user requested.
781 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
782 highest_link_speed, autoneg, autoneg_wait_to_complete);
785 /* Set autoneg_advertised value based on input link speed */
786 hw->phy.autoneg_advertised = 0;
788 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
789 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
791 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
792 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
798 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
799 * @hw: pointer to hardware structure
800 * @speed: new link speed
801 * @autoneg: true if autonegotiation enabled
802 * @autoneg_wait_to_complete: true when waiting for completion is needed
804 * Implements the Intel SmartSpeed algorithm.
806 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
807 ixgbe_link_speed speed, bool autoneg,
808 bool autoneg_wait_to_complete)
810 s32 status = IXGBE_SUCCESS;
811 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
813 bool link_up = false;
814 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
816 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
818 /* Set autoneg_advertised value based on input link speed */
819 hw->phy.autoneg_advertised = 0;
821 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
822 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
824 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
825 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
827 if (speed & IXGBE_LINK_SPEED_100_FULL)
828 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
831 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
832 * autoneg advertisement if link is unable to be established at the
833 * highest negotiated rate. This can sometimes happen due to integrity
834 * issues with the physical media connection.
837 /* First, try to get link with full advertisement */
838 hw->phy.smart_speed_active = false;
839 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
840 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
841 autoneg_wait_to_complete);
842 if (status != IXGBE_SUCCESS)
846 * Wait for the controller to acquire link. Per IEEE 802.3ap,
847 * Section 73.10.2, we may have to wait up to 500ms if KR is
848 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
849 * Table 9 in the AN MAS.
851 for (i = 0; i < 5; i++) {
854 /* If we have link, just jump out */
855 status = ixgbe_check_link(hw, &link_speed, &link_up,
857 if (status != IXGBE_SUCCESS)
866 * We didn't get link. If we advertised KR plus one of KX4/KX
867 * (or BX4/BX), then disable KR and try again.
869 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
870 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
873 /* Turn SmartSpeed on to disable KR support */
874 hw->phy.smart_speed_active = true;
875 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
876 autoneg_wait_to_complete);
877 if (status != IXGBE_SUCCESS)
881 * Wait for the controller to acquire link. 600ms will allow for
882 * the AN link_fail_inhibit_timer as well for multiple cycles of
883 * parallel detect, both 10g and 1g. This allows for the maximum
884 * connect attempts as defined in the AN MAS table 73-7.
886 for (i = 0; i < 6; i++) {
889 /* If we have link, just jump out */
890 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
891 if (status != IXGBE_SUCCESS)
898 /* We didn't get link. Turn SmartSpeed back off. */
899 hw->phy.smart_speed_active = false;
900 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
901 autoneg_wait_to_complete);
904 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
905 DEBUGOUT("Smartspeed has downgraded the link speed "
906 "from the maximum advertised\n");
911 * ixgbe_setup_mac_link_82599 - Set MAC link speed
912 * @hw: pointer to hardware structure
913 * @speed: new link speed
914 * @autoneg: true if autonegotiation enabled
915 * @autoneg_wait_to_complete: true when waiting for completion is needed
917 * Set the link speed in the AUTOC register and restarts link.
919 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
920 ixgbe_link_speed speed, bool autoneg,
921 bool autoneg_wait_to_complete)
923 s32 status = IXGBE_SUCCESS;
924 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
925 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
926 u32 start_autoc = autoc;
928 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
929 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
930 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
933 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
934 bool got_lock = false;
936 DEBUGFUNC("ixgbe_setup_mac_link_82599");
938 /* Check to see if speed passed in is supported. */
939 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
943 speed &= link_capabilities;
945 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
946 status = IXGBE_ERR_LINK_SETUP;
950 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
951 if (hw->mac.orig_link_settings_stored)
952 orig_autoc = hw->mac.orig_autoc;
956 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
957 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
958 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
959 /* Set KX4/KX/KR support according to speed requested */
960 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
961 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
962 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
963 autoc |= IXGBE_AUTOC_KX4_SUPP;
964 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
965 (hw->phy.smart_speed_active == false))
966 autoc |= IXGBE_AUTOC_KR_SUPP;
968 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
969 autoc |= IXGBE_AUTOC_KX_SUPP;
970 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
971 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
972 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
973 /* Switch from 1G SFI to 10G SFI if requested */
974 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
975 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
976 autoc &= ~IXGBE_AUTOC_LMS_MASK;
977 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
979 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
980 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
981 /* Switch from 10G SFI to 1G SFI if requested */
982 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
983 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
984 autoc &= ~IXGBE_AUTOC_LMS_MASK;
986 autoc |= IXGBE_AUTOC_LMS_1G_AN;
988 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
992 if (autoc != start_autoc) {
993 /* Need SW/FW semaphore around AUTOC writes if LESM is on,
994 * likewise reset_pipeline requires us to hold this lock as
995 * it also writes to AUTOC.
997 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
998 status = hw->mac.ops.acquire_swfw_sync(hw,
999 IXGBE_GSSR_MAC_CSR_SM);
1000 if (status != IXGBE_SUCCESS) {
1001 status = IXGBE_ERR_SWFW_SYNC;
1009 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
1010 ixgbe_reset_pipeline_82599(hw);
1013 hw->mac.ops.release_swfw_sync(hw,
1014 IXGBE_GSSR_MAC_CSR_SM);
1018 /* Only poll for autoneg to complete if specified to do so */
1019 if (autoneg_wait_to_complete) {
1020 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1021 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1022 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1023 links_reg = 0; /*Just in case Autoneg time=0*/
1024 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1026 IXGBE_READ_REG(hw, IXGBE_LINKS);
1027 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
1031 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
1033 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
1034 DEBUGOUT("Autoneg did not complete.\n");
1039 /* Add delay to filter out noises during initial link setup */
1048 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
1049 * @hw: pointer to hardware structure
1050 * @speed: new link speed
1051 * @autoneg: true if autonegotiation enabled
1052 * @autoneg_wait_to_complete: true if waiting is needed to complete
1054 * Restarts link on PHY and MAC based on settings passed in.
1056 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1057 ixgbe_link_speed speed,
1059 bool autoneg_wait_to_complete)
1063 DEBUGFUNC("ixgbe_setup_copper_link_82599");
1065 /* Setup the PHY according to input speed */
1066 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
1067 autoneg_wait_to_complete);
1069 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1075 * ixgbe_reset_hw_82599 - Perform hardware reset
1076 * @hw: pointer to hardware structure
1078 * Resets the hardware by resetting the transmit and receive units, masks
1079 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1082 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1084 ixgbe_link_speed link_speed;
1086 u32 ctrl, i, autoc, autoc2;
1087 bool link_up = false;
1089 DEBUGFUNC("ixgbe_reset_hw_82599");
1091 /* Call adapter stop to disable tx/rx and clear interrupts */
1092 status = hw->mac.ops.stop_adapter(hw);
1093 if (status != IXGBE_SUCCESS)
1096 /* flush pending Tx transactions */
1097 ixgbe_clear_tx_pending(hw);
1099 /* PHY ops must be identified and initialized prior to reset */
1101 /* Identify PHY and related function pointers */
1102 status = hw->phy.ops.init(hw);
1104 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1107 /* Setup SFP module if there is one present. */
1108 if (hw->phy.sfp_setup_needed) {
1109 status = hw->mac.ops.setup_sfp(hw);
1110 hw->phy.sfp_setup_needed = false;
1113 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1117 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1118 hw->phy.ops.reset(hw);
1122 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1123 * If link reset is used when link is up, it might reset the PHY when
1124 * mng is using it. If link is down or the flag to force full link
1125 * reset is set, then perform link reset.
1127 ctrl = IXGBE_CTRL_LNK_RST;
1128 if (!hw->force_full_reset) {
1129 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1131 ctrl = IXGBE_CTRL_RST;
1134 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1135 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1136 IXGBE_WRITE_FLUSH(hw);
1138 /* Poll for reset bit to self-clear meaning reset is complete */
1139 for (i = 0; i < 10; i++) {
1141 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1142 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1146 if (ctrl & IXGBE_CTRL_RST_MASK) {
1147 status = IXGBE_ERR_RESET_FAILED;
1148 DEBUGOUT("Reset polling failed to complete.\n");
1154 * Double resets are required for recovery from certain error
1155 * conditions. Between resets, it is necessary to stall to
1156 * allow time for any pending HW events to complete.
1158 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1159 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1164 * Store the original AUTOC/AUTOC2 values if they have not been
1165 * stored off yet. Otherwise restore the stored original
1166 * values since the reset operation sets back to defaults.
1168 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1169 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1171 /* Enable link if disabled in NVM */
1172 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1173 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1174 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1175 IXGBE_WRITE_FLUSH(hw);
1178 if (hw->mac.orig_link_settings_stored == false) {
1179 hw->mac.orig_autoc = autoc;
1180 hw->mac.orig_autoc2 = autoc2;
1181 hw->mac.orig_link_settings_stored = true;
1183 if (autoc != hw->mac.orig_autoc) {
1184 /* Need SW/FW semaphore around AUTOC writes if LESM is
1185 * on, likewise reset_pipeline requires us to hold
1186 * this lock as it also writes to AUTOC.
1188 bool got_lock = false;
1189 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1190 status = hw->mac.ops.acquire_swfw_sync(hw,
1191 IXGBE_GSSR_MAC_CSR_SM);
1192 if (status != IXGBE_SUCCESS) {
1193 status = IXGBE_ERR_SWFW_SYNC;
1200 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
1201 ixgbe_reset_pipeline_82599(hw);
1204 hw->mac.ops.release_swfw_sync(hw,
1205 IXGBE_GSSR_MAC_CSR_SM);
1208 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1209 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1210 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1211 autoc2 |= (hw->mac.orig_autoc2 &
1212 IXGBE_AUTOC2_UPPER_MASK);
1213 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1217 /* Store the permanent mac address */
1218 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1221 * Store MAC address from RAR0, clear receive address registers, and
1222 * clear the multicast table. Also reset num_rar_entries to 128,
1223 * since we modify this value when programming the SAN MAC address.
1225 hw->mac.num_rar_entries = 128;
1226 hw->mac.ops.init_rx_addrs(hw);
1228 /* Store the permanent SAN mac address */
1229 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1231 /* Add the SAN MAC address to the RAR only if it's a valid address */
1232 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1233 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1234 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1236 /* Save the SAN MAC RAR index */
1237 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1239 /* Reserve the last RAR for the SAN MAC address */
1240 hw->mac.num_rar_entries--;
1243 /* Store the alternative WWNN/WWPN prefix */
1244 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1245 &hw->mac.wwpn_prefix);
1252 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1253 * @hw: pointer to hardware structure
1255 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1258 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1259 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1261 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1264 * Before starting reinitialization process,
1265 * FDIRCMD.CMD must be zero.
1267 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1268 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1269 IXGBE_FDIRCMD_CMD_MASK))
1273 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1274 DEBUGOUT("Flow Director previous command isn't complete, "
1275 "aborting table re-initialization.\n");
1276 return IXGBE_ERR_FDIR_REINIT_FAILED;
1279 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1280 IXGBE_WRITE_FLUSH(hw);
1282 * 82599 adapters flow director init flow cannot be restarted,
1283 * Workaround 82599 silicon errata by performing the following steps
1284 * before re-writing the FDIRCTRL control register with the same value.
1285 * - write 1 to bit 8 of FDIRCMD register &
1286 * - write 0 to bit 8 of FDIRCMD register
1288 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1289 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1290 IXGBE_FDIRCMD_CLEARHT));
1291 IXGBE_WRITE_FLUSH(hw);
1292 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1293 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1294 ~IXGBE_FDIRCMD_CLEARHT));
1295 IXGBE_WRITE_FLUSH(hw);
1297 * Clear FDIR Hash register to clear any leftover hashes
1298 * waiting to be programmed.
1300 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1301 IXGBE_WRITE_FLUSH(hw);
1303 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1304 IXGBE_WRITE_FLUSH(hw);
1306 /* Poll init-done after we write FDIRCTRL register */
1307 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1308 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1309 IXGBE_FDIRCTRL_INIT_DONE)
1313 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1314 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1315 return IXGBE_ERR_FDIR_REINIT_FAILED;
1318 /* Clear FDIR statistics registers (read to clear) */
1319 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1320 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1321 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1322 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1323 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1325 return IXGBE_SUCCESS;
1329 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1330 * @hw: pointer to hardware structure
1331 * @fdirctrl: value to write to flow director control register
1333 STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1337 DEBUGFUNC("ixgbe_fdir_enable_82599");
1339 /* Prime the keys for hashing */
1340 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1341 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1344 * Poll init-done after we write the register. Estimated times:
1345 * 10G: PBALLOC = 11b, timing is 60us
1346 * 1G: PBALLOC = 11b, timing is 600us
1347 * 100M: PBALLOC = 11b, timing is 6ms
1349 * Multiple these timings by 4 if under full Rx load
1351 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1352 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1353 * this might not finish in our poll time, but we can live with that
1356 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1357 IXGBE_WRITE_FLUSH(hw);
1358 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1359 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1360 IXGBE_FDIRCTRL_INIT_DONE)
1365 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1366 DEBUGOUT("Flow Director poll time exceeded!\n");
1370 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1371 * @hw: pointer to hardware structure
1372 * @fdirctrl: value to write to flow director control register, initially
1373 * contains just the value of the Rx packet buffer allocation
1375 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1377 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1380 * Continue setup of fdirctrl register bits:
1381 * Move the flexible bytes to use the ethertype - shift 6 words
1382 * Set the maximum length per hash bucket to 0xA filters
1383 * Send interrupt when 64 filters are left
1385 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1386 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1387 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1389 /* write hashes and fdirctrl register, poll for completion */
1390 ixgbe_fdir_enable_82599(hw, fdirctrl);
1392 return IXGBE_SUCCESS;
1396 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1397 * @hw: pointer to hardware structure
1398 * @fdirctrl: value to write to flow director control register, initially
1399 * contains just the value of the Rx packet buffer allocation
1401 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1403 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1406 * Continue setup of fdirctrl register bits:
1407 * Turn perfect match filtering on
1408 * Report hash in RSS field of Rx wb descriptor
1409 * Initialize the drop queue
1410 * Move the flexible bytes to use the ethertype - shift 6 words
1411 * Set the maximum length per hash bucket to 0xA filters
1412 * Send interrupt when 64 (0x4 * 16) filters are left
1414 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1415 IXGBE_FDIRCTRL_REPORT_STATUS |
1416 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1417 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1418 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1419 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1422 /* write hashes and fdirctrl register, poll for completion */
1423 ixgbe_fdir_enable_82599(hw, fdirctrl);
1425 return IXGBE_SUCCESS;
1429 * These defines allow us to quickly generate all of the necessary instructions
1430 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1431 * for values 0 through 15
1433 #define IXGBE_ATR_COMMON_HASH_KEY \
1434 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1435 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1438 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1439 common_hash ^= lo_hash_dword >> n; \
1440 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1441 bucket_hash ^= lo_hash_dword >> n; \
1442 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1443 sig_hash ^= lo_hash_dword << (16 - n); \
1444 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1445 common_hash ^= hi_hash_dword >> n; \
1446 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1447 bucket_hash ^= hi_hash_dword >> n; \
1448 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1449 sig_hash ^= hi_hash_dword << (16 - n); \
1453 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1454 * @stream: input bitstream to compute the hash on
1456 * This function is almost identical to the function above but contains
1457 * several optomizations such as unwinding all of the loops, letting the
1458 * compiler work out all of the conditional ifs since the keys are static
1459 * defines, and computing two keys at once since the hashed dword stream
1460 * will be the same for both keys.
1462 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1463 union ixgbe_atr_hash_dword common)
1465 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1466 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1468 /* record the flow_vm_vlan bits as they are a key part to the hash */
1469 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1471 /* generate common hash dword */
1472 hi_hash_dword = IXGBE_NTOHL(common.dword);
1474 /* low dword is word swapped version of common */
1475 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1477 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1478 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1480 /* Process bits 0 and 16 */
1481 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1484 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1485 * delay this because bit 0 of the stream should not be processed
1486 * so we do not add the vlan until after bit 0 was processed
1488 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1490 /* Process remaining 30 bit of the key */
1491 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1492 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1493 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1494 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1495 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1496 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1497 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1498 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1499 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1500 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1501 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1502 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1503 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1504 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1505 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1507 /* combine common_hash result with signature and bucket hashes */
1508 bucket_hash ^= common_hash;
1509 bucket_hash &= IXGBE_ATR_HASH_MASK;
1511 sig_hash ^= common_hash << 16;
1512 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1514 /* return completed signature hash */
1515 return sig_hash ^ bucket_hash;
1519 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1520 * @hw: pointer to hardware structure
1521 * @input: unique input dword
1522 * @common: compressed common input dword
1523 * @queue: queue index to direct traffic to
1525 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1526 union ixgbe_atr_hash_dword input,
1527 union ixgbe_atr_hash_dword common,
1533 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1536 * Get the flow_type in order to program FDIRCMD properly
1537 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1538 * fifth is FDIRCMD.TUNNEL_FILTER
1540 switch (input.formatted.flow_type) {
1541 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1542 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1543 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1544 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1545 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1546 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1549 DEBUGOUT(" Error on flow type input\n");
1550 return IXGBE_ERR_CONFIG;
1553 /* configure FDIRCMD register */
1554 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1555 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1556 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1557 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1560 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1561 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1563 fdirhashcmd = (u64)fdircmd << 32;
1564 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1565 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1567 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1569 return IXGBE_SUCCESS;
1572 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1575 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1576 bucket_hash ^= lo_hash_dword >> n; \
1577 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1578 bucket_hash ^= hi_hash_dword >> n; \
1582 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1583 * @atr_input: input bitstream to compute the hash on
1584 * @input_mask: mask for the input bitstream
1586 * This function serves two main purposes. First it applys the input_mask
1587 * to the atr_input resulting in a cleaned up atr_input data stream.
1588 * Secondly it computes the hash and stores it in the bkt_hash field at
1589 * the end of the input byte stream. This way it will be available for
1590 * future use without needing to recompute the hash.
1592 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1593 union ixgbe_atr_input *input_mask)
1596 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1597 u32 bucket_hash = 0;
1599 /* Apply masks to input data */
1600 input->dword_stream[0] &= input_mask->dword_stream[0];
1601 input->dword_stream[1] &= input_mask->dword_stream[1];
1602 input->dword_stream[2] &= input_mask->dword_stream[2];
1603 input->dword_stream[3] &= input_mask->dword_stream[3];
1604 input->dword_stream[4] &= input_mask->dword_stream[4];
1605 input->dword_stream[5] &= input_mask->dword_stream[5];
1606 input->dword_stream[6] &= input_mask->dword_stream[6];
1607 input->dword_stream[7] &= input_mask->dword_stream[7];
1608 input->dword_stream[8] &= input_mask->dword_stream[8];
1609 input->dword_stream[9] &= input_mask->dword_stream[9];
1610 input->dword_stream[10] &= input_mask->dword_stream[10];
1612 /* record the flow_vm_vlan bits as they are a key part to the hash */
1613 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1615 /* generate common hash dword */
1616 hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
1617 input->dword_stream[2] ^
1618 input->dword_stream[3] ^
1619 input->dword_stream[4] ^
1620 input->dword_stream[5] ^
1621 input->dword_stream[6] ^
1622 input->dword_stream[7] ^
1623 input->dword_stream[8] ^
1624 input->dword_stream[9] ^
1625 input->dword_stream[10]);
1627 /* low dword is word swapped version of common */
1628 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1630 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1631 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1633 /* Process bits 0 and 16 */
1634 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1637 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1638 * delay this because bit 0 of the stream should not be processed
1639 * so we do not add the vlan until after bit 0 was processed
1641 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1643 /* Process remaining 30 bit of the key */
1644 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1645 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1646 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1647 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1648 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1649 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1650 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1651 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1652 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1653 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1654 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1655 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1656 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1657 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1658 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1661 * Limit hash to 13 bits since max bucket count is 8K.
1662 * Store result at the end of the input stream.
1664 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1668 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1669 * @input_mask: mask to be bit swapped
1671 * The source and destination port masks for flow director are bit swapped
1672 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1673 * generate a correctly swapped value we need to bit swap the mask and that
1674 * is what is accomplished by this function.
1676 STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1678 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1679 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1680 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1681 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1682 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1683 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1684 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1688 * These two macros are meant to address the fact that we have registers
1689 * that are either all or in part big-endian. As a result on big-endian
1690 * systems we will end up byte swapping the value to little-endian before
1691 * it is byte swapped again and written to the hardware in the original
1692 * big-endian format.
1694 #define IXGBE_STORE_AS_BE32(_value) \
1695 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1696 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1698 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1699 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1701 #define IXGBE_STORE_AS_BE16(_value) \
1702 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1704 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1705 union ixgbe_atr_input *input_mask)
1707 /* mask IPv6 since it is currently not supported */
1708 u32 fdirm = IXGBE_FDIRM_DIPv6;
1710 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1713 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1714 * are zero, then assume a full mask for that field. Also assume that
1715 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1716 * cannot be masked out in this implementation.
1718 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1722 /* verify bucket hash is cleared on hash generation */
1723 if (input_mask->formatted.bkt_hash)
1724 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1726 /* Program FDIRM and verify partial masks */
1727 switch (input_mask->formatted.vm_pool & 0x7F) {
1729 fdirm |= IXGBE_FDIRM_POOL;
1733 DEBUGOUT(" Error on vm pool mask\n");
1734 return IXGBE_ERR_CONFIG;
1737 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1739 fdirm |= IXGBE_FDIRM_L4P;
1740 if (input_mask->formatted.dst_port ||
1741 input_mask->formatted.src_port) {
1742 DEBUGOUT(" Error on src/dst port mask\n");
1743 return IXGBE_ERR_CONFIG;
1745 case IXGBE_ATR_L4TYPE_MASK:
1748 DEBUGOUT(" Error on flow type mask\n");
1749 return IXGBE_ERR_CONFIG;
1752 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1754 /* mask VLAN ID, fall through to mask VLAN priority */
1755 fdirm |= IXGBE_FDIRM_VLANID;
1757 /* mask VLAN priority */
1758 fdirm |= IXGBE_FDIRM_VLANP;
1761 /* mask VLAN ID only, fall through */
1762 fdirm |= IXGBE_FDIRM_VLANID;
1764 /* no VLAN fields masked */
1767 DEBUGOUT(" Error on VLAN mask\n");
1768 return IXGBE_ERR_CONFIG;
1771 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1773 /* Mask Flex Bytes, fall through */
1774 fdirm |= IXGBE_FDIRM_FLEX;
1778 DEBUGOUT(" Error on flexible byte mask\n");
1779 return IXGBE_ERR_CONFIG;
1783 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1784 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1786 /* store the TCP/UDP port masks, bit reversed from port layout */
1787 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1789 /* write both the same so that UDP and TCP use the same mask */
1790 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1791 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1793 /* store source and destination IP masks (big-enian) */
1794 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1795 ~input_mask->formatted.src_ip[0]);
1796 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1797 ~input_mask->formatted.dst_ip[0]);
1799 return IXGBE_SUCCESS;
1802 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1803 union ixgbe_atr_input *input,
1804 u16 soft_id, u8 queue)
1806 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1808 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1810 /* currently IPv6 is not supported, must be programmed with 0 */
1811 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1812 input->formatted.src_ip[0]);
1813 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1814 input->formatted.src_ip[1]);
1815 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1816 input->formatted.src_ip[2]);
1818 /* record the source address (big-endian) */
1819 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1821 /* record the first 32 bits of the destination address (big-endian) */
1822 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1824 /* record source and destination port (little-endian)*/
1825 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1826 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1827 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1828 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1830 /* record vlan (little-endian) and flex_bytes(big-endian) */
1831 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1832 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1833 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1834 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1837 /* configure FDIRHASH register */
1838 fdirhash = input->formatted.bkt_hash;
1839 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1840 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1843 * flush all previous writes to make certain registers are
1844 * programmed prior to issuing the command
1846 IXGBE_WRITE_FLUSH(hw);
1848 /* configure FDIRCMD register */
1849 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1850 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1851 if (queue == IXGBE_FDIR_DROP_QUEUE)
1852 fdircmd |= IXGBE_FDIRCMD_DROP;
1853 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1854 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1855 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1857 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1859 return IXGBE_SUCCESS;
1862 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1863 union ixgbe_atr_input *input,
1869 s32 err = IXGBE_SUCCESS;
1871 /* configure FDIRHASH register */
1872 fdirhash = input->formatted.bkt_hash;
1873 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1874 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1876 /* flush hash to HW */
1877 IXGBE_WRITE_FLUSH(hw);
1879 /* Query if filter is present */
1880 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1882 for (retry_count = 10; retry_count; retry_count--) {
1883 /* allow 10us for query to process */
1885 /* verify query completed successfully */
1886 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1887 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1892 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1894 /* if filter exists in hardware then remove it */
1895 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1896 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1897 IXGBE_WRITE_FLUSH(hw);
1898 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1899 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1906 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1907 * @hw: pointer to hardware structure
1908 * @input: input bitstream
1909 * @input_mask: mask for the input bitstream
1910 * @soft_id: software index for the filters
1911 * @queue: queue index to direct traffic to
1913 * Note that the caller to this function must lock before calling, since the
1914 * hardware writes must be protected from one another.
1916 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1917 union ixgbe_atr_input *input,
1918 union ixgbe_atr_input *input_mask,
1919 u16 soft_id, u8 queue)
1921 s32 err = IXGBE_ERR_CONFIG;
1923 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1926 * Check flow_type formatting, and bail out before we touch the hardware
1927 * if there's a configuration issue
1929 switch (input->formatted.flow_type) {
1930 case IXGBE_ATR_FLOW_TYPE_IPV4:
1931 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1932 if (input->formatted.dst_port || input->formatted.src_port) {
1933 DEBUGOUT(" Error on src/dst port\n");
1934 return IXGBE_ERR_CONFIG;
1937 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1938 if (input->formatted.dst_port || input->formatted.src_port) {
1939 DEBUGOUT(" Error on src/dst port\n");
1940 return IXGBE_ERR_CONFIG;
1942 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1943 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1944 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
1945 IXGBE_ATR_L4TYPE_MASK;
1948 DEBUGOUT(" Error on flow type input\n");
1952 /* program input mask into the HW */
1953 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
1957 /* apply mask and compute/store hash */
1958 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
1960 /* program filters to filter memory */
1961 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
1966 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1967 * @hw: pointer to hardware structure
1968 * @reg: analog register to read
1971 * Performs read operation to Omer analog register specified.
1973 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1977 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
1979 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1981 IXGBE_WRITE_FLUSH(hw);
1983 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1984 *val = (u8)core_ctl;
1986 return IXGBE_SUCCESS;
1990 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1991 * @hw: pointer to hardware structure
1992 * @reg: atlas register to write
1993 * @val: value to write
1995 * Performs write operation to Omer analog register specified.
1997 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2001 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
2003 core_ctl = (reg << 8) | val;
2004 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2005 IXGBE_WRITE_FLUSH(hw);
2008 return IXGBE_SUCCESS;
2012 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2013 * @hw: pointer to hardware structure
2015 * Starts the hardware using the generic start_hw function
2016 * and the generation start_hw function.
2017 * Then performs revision-specific operations, if any.
2019 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2021 s32 ret_val = IXGBE_SUCCESS;
2023 DEBUGFUNC("ixgbe_start_hw_82599");
2025 ret_val = ixgbe_start_hw_generic(hw);
2026 if (ret_val != IXGBE_SUCCESS)
2029 ret_val = ixgbe_start_hw_gen2(hw);
2030 if (ret_val != IXGBE_SUCCESS)
2033 /* We need to run link autotry after the driver loads */
2034 hw->mac.autotry_restart = true;
2036 if (ret_val == IXGBE_SUCCESS)
2037 ret_val = ixgbe_verify_fw_version_82599(hw);
2043 * ixgbe_identify_phy_82599 - Get physical layer module
2044 * @hw: pointer to hardware structure
2046 * Determines the physical layer module found on the current adapter.
2047 * If PHY already detected, maintains current PHY type in hw struct,
2048 * otherwise executes the PHY detection routine.
2050 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2054 DEBUGFUNC("ixgbe_identify_phy_82599");
2056 /* Detect PHY if not unknown - returns success if already detected. */
2057 status = ixgbe_identify_phy_generic(hw);
2058 if (status != IXGBE_SUCCESS) {
2059 /* 82599 10GBASE-T requires an external PHY */
2060 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2063 status = ixgbe_identify_module_generic(hw);
2066 /* Set PHY type none if no PHY detected */
2067 if (hw->phy.type == ixgbe_phy_unknown) {
2068 hw->phy.type = ixgbe_phy_none;
2069 status = IXGBE_SUCCESS;
2072 /* Return error if SFP module has been detected but is not supported */
2073 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2074 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
2081 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2082 * @hw: pointer to hardware structure
2084 * Determines physical layer capabilities of the current configuration.
2086 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2088 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2089 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2090 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2091 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2092 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2093 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2094 u16 ext_ability = 0;
2095 u8 comp_codes_10g = 0;
2096 u8 comp_codes_1g = 0;
2098 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2100 hw->phy.ops.identify(hw);
2102 switch (hw->phy.type) {
2104 case ixgbe_phy_cu_unknown:
2105 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2106 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2107 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2108 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2109 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2110 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2111 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
2112 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2118 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2119 case IXGBE_AUTOC_LMS_1G_AN:
2120 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2121 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2122 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2123 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2126 /* SFI mode so read SFP module */
2129 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2130 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2131 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2132 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2133 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2134 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2135 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2138 case IXGBE_AUTOC_LMS_10G_SERIAL:
2139 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2140 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2142 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2145 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2146 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2147 if (autoc & IXGBE_AUTOC_KX_SUPP)
2148 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2149 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2150 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2151 if (autoc & IXGBE_AUTOC_KR_SUPP)
2152 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2161 /* SFP check must be done last since DA modules are sometimes used to
2162 * test KR mode - we need to id KR mode correctly before SFP module.
2163 * Call identify_sfp because the pluggable module may have changed */
2164 hw->phy.ops.identify_sfp(hw);
2165 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2168 switch (hw->phy.type) {
2169 case ixgbe_phy_sfp_passive_tyco:
2170 case ixgbe_phy_sfp_passive_unknown:
2171 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2173 case ixgbe_phy_sfp_ftl_active:
2174 case ixgbe_phy_sfp_active_unknown:
2175 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2177 case ixgbe_phy_sfp_avago:
2178 case ixgbe_phy_sfp_ftl:
2179 case ixgbe_phy_sfp_intel:
2180 case ixgbe_phy_sfp_unknown:
2181 hw->phy.ops.read_i2c_eeprom(hw,
2182 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2183 hw->phy.ops.read_i2c_eeprom(hw,
2184 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2185 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2186 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2187 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2188 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2189 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2190 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2191 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
2192 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
2199 return physical_layer;
2203 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2204 * @hw: pointer to hardware structure
2205 * @regval: register value to write to RXCTRL
2207 * Enables the Rx DMA unit for 82599
2209 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2212 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2215 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2216 * If traffic is incoming before we enable the Rx unit, it could hang
2217 * the Rx DMA unit. Therefore, make sure the security engine is
2218 * completely disabled prior to enabling the Rx unit.
2221 hw->mac.ops.disable_sec_rx_path(hw);
2223 if (regval & IXGBE_RXCTRL_RXEN)
2224 ixgbe_enable_rx(hw);
2226 ixgbe_disable_rx(hw);
2228 hw->mac.ops.enable_sec_rx_path(hw);
2230 return IXGBE_SUCCESS;
2234 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2235 * @hw: pointer to hardware structure
2237 * Verifies that installed the firmware version is 0.6 or higher
2238 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2240 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2241 * if the FW version is not supported.
2243 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2245 s32 status = IXGBE_ERR_EEPROM_VERSION;
2246 u16 fw_offset, fw_ptp_cfg_offset;
2249 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2251 /* firmware check is only necessary for SFI devices */
2252 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2253 status = IXGBE_SUCCESS;
2254 goto fw_version_out;
2257 /* get the offset to the Firmware Module block */
2258 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
2259 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2260 "eeprom read at offset %d failed", IXGBE_FW_PTR);
2261 return IXGBE_ERR_EEPROM_VERSION;
2264 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2265 goto fw_version_out;
2267 /* get the offset to the Pass Through Patch Configuration block */
2268 if (hw->eeprom.ops.read(hw, (fw_offset +
2269 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2270 &fw_ptp_cfg_offset)) {
2271 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2272 "eeprom read at offset %d failed",
2274 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);
2275 return IXGBE_ERR_EEPROM_VERSION;
2278 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2279 goto fw_version_out;
2281 /* get the firmware version */
2282 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2283 IXGBE_FW_PATCH_VERSION_4), &fw_version)) {
2284 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2285 "eeprom read at offset %d failed",
2286 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);
2287 return IXGBE_ERR_EEPROM_VERSION;
2290 if (fw_version > 0x5)
2291 status = IXGBE_SUCCESS;
2298 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2299 * @hw: pointer to hardware structure
2301 * Returns true if the LESM FW module is present and enabled. Otherwise
2302 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2304 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2306 bool lesm_enabled = false;
2307 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2310 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2312 /* get the offset to the Firmware Module block */
2313 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2315 if ((status != IXGBE_SUCCESS) ||
2316 (fw_offset == 0) || (fw_offset == 0xFFFF))
2319 /* get the offset to the LESM Parameters block */
2320 status = hw->eeprom.ops.read(hw, (fw_offset +
2321 IXGBE_FW_LESM_PARAMETERS_PTR),
2322 &fw_lesm_param_offset);
2324 if ((status != IXGBE_SUCCESS) ||
2325 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2328 /* get the lesm state word */
2329 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2330 IXGBE_FW_LESM_STATE_1),
2333 if ((status == IXGBE_SUCCESS) &&
2334 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2335 lesm_enabled = true;
2338 return lesm_enabled;
2342 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2343 * fastest available method
2345 * @hw: pointer to hardware structure
2346 * @offset: offset of word in EEPROM to read
2347 * @words: number of words
2348 * @data: word(s) read from the EEPROM
2350 * Retrieves 16 bit word(s) read from EEPROM
2352 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2353 u16 words, u16 *data)
2355 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2356 s32 ret_val = IXGBE_ERR_CONFIG;
2358 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2361 * If EEPROM is detected and can be addressed using 14 bits,
2362 * use EERD otherwise use bit bang
2364 if ((eeprom->type == ixgbe_eeprom_spi) &&
2365 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2366 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2369 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2377 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2378 * fastest available method
2380 * @hw: pointer to hardware structure
2381 * @offset: offset of word in the EEPROM to read
2382 * @data: word read from the EEPROM
2384 * Reads a 16 bit word from the EEPROM
2386 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2387 u16 offset, u16 *data)
2389 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2390 s32 ret_val = IXGBE_ERR_CONFIG;
2392 DEBUGFUNC("ixgbe_read_eeprom_82599");
2395 * If EEPROM is detected and can be addressed using 14 bits,
2396 * use EERD otherwise use bit bang
2398 if ((eeprom->type == ixgbe_eeprom_spi) &&
2399 (offset <= IXGBE_EERD_MAX_ADDR))
2400 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2402 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2408 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2410 * @hw: pointer to hardware structure
2412 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2413 * full pipeline reset
2415 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2417 s32 i, autoc_reg, autoc2_reg, ret_val;
2420 /* Enable link if disabled in NVM */
2421 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2422 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2423 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2424 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2425 IXGBE_WRITE_FLUSH(hw);
2428 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2429 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2430 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2431 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
2432 /* Wait for AN to leave state 0 */
2433 for (i = 0; i < 10; i++) {
2435 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2436 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2440 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2441 DEBUGOUT("auto negotiation not completed\n");
2442 ret_val = IXGBE_ERR_RESET_FAILED;
2443 goto reset_pipeline_out;
2446 ret_val = IXGBE_SUCCESS;
2449 /* Write AUTOC register with original LMS field and Restart_AN */
2450 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2451 IXGBE_WRITE_FLUSH(hw);