1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82599.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
39 #ident "$Id: ixgbe_82599.c,v 1.301 2012/11/08 11:33:27 jtkirshe Exp $"
41 #define IXGBE_82599_MAX_TX_QUEUES 128
42 #define IXGBE_82599_MAX_RX_QUEUES 128
43 #define IXGBE_82599_RAR_ENTRIES 128
44 #define IXGBE_82599_MC_TBL_SIZE 128
45 #define IXGBE_82599_VFT_TBL_SIZE 128
46 #define IXGBE_82599_RX_PB_SIZE 512
48 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
49 ixgbe_link_speed speed,
50 bool autoneg_wait_to_complete);
51 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
53 u16 offset, u16 *data);
54 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
57 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
59 u32 fwsm, manc, factps;
61 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
62 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
65 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
66 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
69 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
70 if (factps & IXGBE_FACTPS_MNGCG)
76 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
78 struct ixgbe_mac_info *mac = &hw->mac;
80 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
83 * enable the laser control functions for SFP+ fiber
86 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
87 !ixgbe_mng_enabled(hw)) {
88 mac->ops.disable_tx_laser =
89 &ixgbe_disable_tx_laser_multispeed_fiber;
90 mac->ops.enable_tx_laser =
91 &ixgbe_enable_tx_laser_multispeed_fiber;
92 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
95 mac->ops.disable_tx_laser = NULL;
96 mac->ops.enable_tx_laser = NULL;
97 mac->ops.flap_tx_laser = NULL;
100 if (hw->phy.multispeed_fiber) {
101 /* Set up dual speed SFP+ support */
102 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
104 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
105 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
106 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
107 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
108 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
110 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
116 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
117 * @hw: pointer to hardware structure
119 * Initialize any function pointers that were not able to be
120 * set during init_shared_code because the PHY/SFP type was
121 * not known. Perform the SFP init if necessary.
124 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
126 struct ixgbe_mac_info *mac = &hw->mac;
127 struct ixgbe_phy_info *phy = &hw->phy;
128 s32 ret_val = IXGBE_SUCCESS;
130 DEBUGFUNC("ixgbe_init_phy_ops_82599");
132 /* Identify the PHY or SFP module */
133 ret_val = phy->ops.identify(hw);
134 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
135 goto init_phy_ops_out;
137 /* Setup function pointers based on detected SFP module and speeds */
138 ixgbe_init_mac_link_ops_82599(hw);
139 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
140 hw->phy.ops.reset = NULL;
142 /* If copper media, overwrite with copper function pointers */
143 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
144 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
145 mac->ops.get_link_capabilities =
146 &ixgbe_get_copper_link_capabilities_generic;
149 /* Set necessary function pointers based on phy type */
150 switch (hw->phy.type) {
152 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
153 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
154 phy->ops.get_firmware_version =
155 &ixgbe_get_phy_firmware_version_tnx;
164 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
166 s32 ret_val = IXGBE_SUCCESS;
167 u16 list_offset, data_offset, data_value;
169 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
171 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
172 ixgbe_init_mac_link_ops_82599(hw);
174 hw->phy.ops.reset = NULL;
176 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
178 if (ret_val != IXGBE_SUCCESS)
181 /* PHY config will finish before releasing the semaphore */
182 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
183 IXGBE_GSSR_MAC_CSR_SM);
184 if (ret_val != IXGBE_SUCCESS) {
185 ret_val = IXGBE_ERR_SWFW_SYNC;
189 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
191 while (data_value != 0xffff) {
192 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
193 IXGBE_WRITE_FLUSH(hw);
194 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
198 /* Release the semaphore */
199 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
200 /* Delay obtaining semaphore again to allow FW access
201 * prot_autoc_write uses the semaphore too.
203 msec_delay(hw->eeprom.semaphore_delay);
205 /* Restart DSP and set SFI mode */
206 ret_val = hw->mac.ops.prot_autoc_write(hw,
207 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
211 DEBUGOUT("sfp module setup not complete\n");
212 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
222 /* Release the semaphore */
223 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
224 /* Delay obtaining semaphore again to allow FW access */
225 msec_delay(hw->eeprom.semaphore_delay);
226 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
227 "eeprom read at offset %d failed", data_offset);
228 return IXGBE_ERR_PHY;
232 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
233 * @hw: pointer to hardware structure
234 * @locked: Return the if we locked for this read.
235 * @reg_val: Value we read from AUTOC
237 * For this part (82599) we need to wrap read-modify-writes with a possible
238 * FW/SW lock. It is assumed this lock will be freed with the next
239 * prot_autoc_write_82599().
241 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
246 /* If LESM is on then we need to hold the SW/FW semaphore. */
247 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
248 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
249 IXGBE_GSSR_MAC_CSR_SM);
250 if (ret_val != IXGBE_SUCCESS)
251 return IXGBE_ERR_SWFW_SYNC;
256 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
257 return IXGBE_SUCCESS;
261 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
262 * @hw: pointer to hardware structure
263 * @reg_val: value to write to AUTOC
264 * @locked: bool to indicate whether the SW/FW lock was already taken by
265 * previous proc_autoc_read_82599.
267 * This part (82599) may need to hold a the SW/FW lock around all writes to
268 * AUTOC. Likewise after a write we need to do a pipeline reset.
270 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
272 s32 ret_val = IXGBE_SUCCESS;
274 /* Blocked by MNG FW so bail */
275 if (ixgbe_check_reset_blocked(hw))
278 /* We only need to get the lock if:
279 * - We didn't do it already (in the read part of a read-modify-write)
282 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
283 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
284 IXGBE_GSSR_MAC_CSR_SM);
285 if (ret_val != IXGBE_SUCCESS)
286 return IXGBE_ERR_SWFW_SYNC;
291 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
292 ret_val = ixgbe_reset_pipeline_82599(hw);
295 /* Free the SW/FW semaphore as we either grabbed it here or
296 * already had it when this function was called.
299 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
305 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
306 * @hw: pointer to hardware structure
308 * Initialize the function pointers and assign the MAC type for 82599.
309 * Does not touch the hardware.
312 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
314 struct ixgbe_mac_info *mac = &hw->mac;
315 struct ixgbe_phy_info *phy = &hw->phy;
316 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
319 DEBUGFUNC("ixgbe_init_ops_82599");
321 ret_val = ixgbe_init_phy_ops_generic(hw);
322 ret_val = ixgbe_init_ops_generic(hw);
325 phy->ops.identify = &ixgbe_identify_phy_82599;
326 phy->ops.init = &ixgbe_init_phy_ops_82599;
329 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
330 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
331 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
332 mac->ops.get_supported_physical_layer =
333 &ixgbe_get_supported_physical_layer_82599;
334 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
335 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
336 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
337 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
338 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
339 mac->ops.start_hw = &ixgbe_start_hw_82599;
340 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
341 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
342 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
343 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
344 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
345 mac->ops.prot_autoc_read = &prot_autoc_read_82599;
346 mac->ops.prot_autoc_write = &prot_autoc_write_82599;
348 /* RAR, Multicast, VLAN */
349 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
350 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
351 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
352 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
353 mac->rar_highwater = 1;
354 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
355 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
356 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
357 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
358 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
359 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
360 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
363 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
364 mac->ops.check_link = &ixgbe_check_mac_link_generic;
365 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
366 ixgbe_init_mac_link_ops_82599(hw);
368 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
369 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
370 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
371 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
372 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
373 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
374 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
376 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
377 IXGBE_FWSM_MODE_MASK) ? true : false;
379 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
382 eeprom->ops.read = &ixgbe_read_eeprom_82599;
383 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
385 /* Manageability interface */
386 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
389 mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
395 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
396 * @hw: pointer to hardware structure
397 * @speed: pointer to link speed
398 * @autoneg: true when autoneg or autotry is enabled
400 * Determines the link capabilities by reading the AUTOC register.
402 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
403 ixgbe_link_speed *speed,
406 s32 status = IXGBE_SUCCESS;
409 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
412 /* Check if 1G SFP module. */
413 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
414 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
415 #ifdef SUPPORT_1000BASE_LX
416 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
417 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
419 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
420 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
421 *speed = IXGBE_LINK_SPEED_1GB_FULL;
427 * Determine link capabilities based on the stored value of AUTOC,
428 * which represents EEPROM defaults. If AUTOC value has not
429 * been stored, use the current register values.
431 if (hw->mac.orig_link_settings_stored)
432 autoc = hw->mac.orig_autoc;
434 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
436 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
437 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
438 *speed = IXGBE_LINK_SPEED_1GB_FULL;
442 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
443 *speed = IXGBE_LINK_SPEED_10GB_FULL;
447 case IXGBE_AUTOC_LMS_1G_AN:
448 *speed = IXGBE_LINK_SPEED_1GB_FULL;
452 case IXGBE_AUTOC_LMS_10G_SERIAL:
453 *speed = IXGBE_LINK_SPEED_10GB_FULL;
457 case IXGBE_AUTOC_LMS_KX4_KX_KR:
458 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
459 *speed = IXGBE_LINK_SPEED_UNKNOWN;
460 if (autoc & IXGBE_AUTOC_KR_SUPP)
461 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
462 if (autoc & IXGBE_AUTOC_KX4_SUPP)
463 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
464 if (autoc & IXGBE_AUTOC_KX_SUPP)
465 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
469 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
470 *speed = IXGBE_LINK_SPEED_100_FULL;
471 if (autoc & IXGBE_AUTOC_KR_SUPP)
472 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
473 if (autoc & IXGBE_AUTOC_KX4_SUPP)
474 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
475 if (autoc & IXGBE_AUTOC_KX_SUPP)
476 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
480 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
481 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
486 status = IXGBE_ERR_LINK_SETUP;
491 if (hw->phy.multispeed_fiber) {
492 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
493 IXGBE_LINK_SPEED_1GB_FULL;
503 * ixgbe_get_media_type_82599 - Get media type
504 * @hw: pointer to hardware structure
506 * Returns the media type (fiber, copper, backplane)
508 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
510 enum ixgbe_media_type media_type;
512 DEBUGFUNC("ixgbe_get_media_type_82599");
514 /* Detect if there is a copper PHY attached. */
515 switch (hw->phy.type) {
516 case ixgbe_phy_cu_unknown:
518 media_type = ixgbe_media_type_copper;
524 switch (hw->device_id) {
525 case IXGBE_DEV_ID_82599_KX4:
526 case IXGBE_DEV_ID_82599_KX4_MEZZ:
527 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
528 case IXGBE_DEV_ID_82599_KR:
529 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
530 case IXGBE_DEV_ID_82599_XAUI_LOM:
531 /* Default device ID is mezzanine card KX/KX4 */
532 media_type = ixgbe_media_type_backplane;
534 case IXGBE_DEV_ID_82599_SFP:
535 case IXGBE_DEV_ID_82599_SFP_FCOE:
536 case IXGBE_DEV_ID_82599_SFP_EM:
537 case IXGBE_DEV_ID_82599_SFP_SF2:
538 case IXGBE_DEV_ID_82599_SFP_SF_QP:
539 case IXGBE_DEV_ID_82599EN_SFP:
540 #ifdef RTE_NIC_BYPASS
541 case IXGBE_DEV_ID_82599_BYPASS:
543 media_type = ixgbe_media_type_fiber;
545 case IXGBE_DEV_ID_82599_CX4:
546 media_type = ixgbe_media_type_cx4;
548 case IXGBE_DEV_ID_82599_T3_LOM:
549 media_type = ixgbe_media_type_copper;
552 media_type = ixgbe_media_type_unknown;
560 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
561 * @hw: pointer to hardware structure
563 * Disables link during D3 power down sequence.
566 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
568 u32 autoc2_reg, fwsm;
571 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
572 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
574 /* Check to see if MNG FW could be enabled */
575 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
577 if (((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) &&
579 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
580 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
581 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
582 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
587 * ixgbe_start_mac_link_82599 - Setup MAC link settings
588 * @hw: pointer to hardware structure
589 * @autoneg_wait_to_complete: true when waiting for completion is needed
591 * Configures link settings based on values in the ixgbe_hw struct.
592 * Restarts the link. Performs autonegotiation if needed.
594 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
595 bool autoneg_wait_to_complete)
600 s32 status = IXGBE_SUCCESS;
601 bool got_lock = false;
603 DEBUGFUNC("ixgbe_start_mac_link_82599");
606 /* reset_pipeline requires us to hold this lock as it writes to
609 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
610 status = hw->mac.ops.acquire_swfw_sync(hw,
611 IXGBE_GSSR_MAC_CSR_SM);
612 if (status != IXGBE_SUCCESS)
619 ixgbe_reset_pipeline_82599(hw);
622 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
624 /* Only poll for autoneg to complete if specified to do so */
625 if (autoneg_wait_to_complete) {
626 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
627 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
628 IXGBE_AUTOC_LMS_KX4_KX_KR ||
629 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
630 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
631 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
632 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
633 links_reg = 0; /* Just in case Autoneg time = 0 */
634 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
635 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
636 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
640 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
641 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
642 DEBUGOUT("Autoneg did not complete.\n");
647 /* Add delay to filter out noises during initial link setup */
655 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
656 * @hw: pointer to hardware structure
658 * The base drivers may require better control over SFP+ module
659 * PHY states. This includes selectively shutting down the Tx
660 * laser on the PHY, effectively halting physical link.
662 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
664 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
666 /* Blocked by MNG FW so bail */
667 if (ixgbe_check_reset_blocked(hw))
670 /* Disable tx laser; allow 100us to go dark per spec */
671 esdp_reg |= IXGBE_ESDP_SDP3;
672 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
673 IXGBE_WRITE_FLUSH(hw);
678 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
679 * @hw: pointer to hardware structure
681 * The base drivers may require better control over SFP+ module
682 * PHY states. This includes selectively turning on the Tx
683 * laser on the PHY, effectively starting physical link.
685 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
687 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
689 /* Enable tx laser; allow 100ms to light up */
690 esdp_reg &= ~IXGBE_ESDP_SDP3;
691 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
692 IXGBE_WRITE_FLUSH(hw);
697 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
698 * @hw: pointer to hardware structure
700 * When the driver changes the link speeds that it can support,
701 * it sets autotry_restart to true to indicate that we need to
702 * initiate a new autotry session with the link partner. To do
703 * so, we set the speed then disable and re-enable the tx laser, to
704 * alert the link partner that it also needs to restart autotry on its
705 * end. This is consistent with true clause 37 autoneg, which also
706 * involves a loss of signal.
708 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
710 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
712 /* Blocked by MNG FW so bail */
713 if (ixgbe_check_reset_blocked(hw))
716 if (hw->mac.autotry_restart) {
717 ixgbe_disable_tx_laser_multispeed_fiber(hw);
718 ixgbe_enable_tx_laser_multispeed_fiber(hw);
719 hw->mac.autotry_restart = false;
725 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
726 * @hw: pointer to hardware structure
727 * @speed: new link speed
728 * @autoneg_wait_to_complete: true when waiting for completion is needed
730 * Set the link speed in the AUTOC register and restarts link.
732 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
733 ixgbe_link_speed speed,
734 bool autoneg_wait_to_complete)
736 s32 status = IXGBE_SUCCESS;
737 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
738 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
740 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
742 bool autoneg, link_up = false;
744 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
746 /* Mask off requested but non-supported speeds */
747 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
748 if (status != IXGBE_SUCCESS)
754 * Try each speed one by one, highest priority first. We do this in
755 * software because 10gb fiber doesn't support speed autonegotiation.
757 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
759 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
761 /* If we already have link at this speed, just jump out */
762 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
763 if (status != IXGBE_SUCCESS)
766 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
769 /* Set the module link speed */
770 switch (hw->phy.media_type) {
771 case ixgbe_media_type_fiber:
772 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
773 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
774 IXGBE_WRITE_FLUSH(hw);
777 DEBUGOUT("Unexpected media type.\n");
781 /* Allow module to change analog characteristics (1G->10G) */
784 status = ixgbe_setup_mac_link_82599(hw,
785 IXGBE_LINK_SPEED_10GB_FULL,
786 autoneg_wait_to_complete);
787 if (status != IXGBE_SUCCESS)
790 /* Flap the tx laser if it has not already been done */
791 ixgbe_flap_tx_laser(hw);
794 * Wait for the controller to acquire link. Per IEEE 802.3ap,
795 * Section 73.10.2, we may have to wait up to 500ms if KR is
796 * attempted. 82599 uses the same timing for 10g SFI.
798 for (i = 0; i < 5; i++) {
799 /* Wait for the link partner to also set speed */
802 /* If we have link, just jump out */
803 status = ixgbe_check_link(hw, &link_speed,
805 if (status != IXGBE_SUCCESS)
813 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
815 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
816 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
818 /* If we already have link at this speed, just jump out */
819 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
820 if (status != IXGBE_SUCCESS)
823 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
826 /* Set the module link speed */
827 switch (hw->phy.media_type) {
828 case ixgbe_media_type_fiber:
829 esdp_reg &= ~IXGBE_ESDP_SDP5;
830 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
831 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
832 IXGBE_WRITE_FLUSH(hw);
835 DEBUGOUT("Unexpected media type.\n");
839 /* Allow module to change analog characteristics (10G->1G) */
842 status = ixgbe_setup_mac_link_82599(hw,
843 IXGBE_LINK_SPEED_1GB_FULL,
844 autoneg_wait_to_complete);
845 if (status != IXGBE_SUCCESS)
848 /* Flap the tx laser if it has not already been done */
849 ixgbe_flap_tx_laser(hw);
851 /* Wait for the link partner to also set speed */
854 /* If we have link, just jump out */
855 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
856 if (status != IXGBE_SUCCESS)
864 * We didn't get link. Configure back to the highest speed we tried,
865 * (if there was more than one). We call ourselves back with just the
866 * single highest speed that the user requested.
869 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
870 highest_link_speed, autoneg_wait_to_complete);
873 /* Set autoneg_advertised value based on input link speed */
874 hw->phy.autoneg_advertised = 0;
876 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
877 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
879 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
880 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
886 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
887 * @hw: pointer to hardware structure
888 * @speed: new link speed
889 * @autoneg_wait_to_complete: true when waiting for completion is needed
891 * Implements the Intel SmartSpeed algorithm.
893 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
894 ixgbe_link_speed speed,
895 bool autoneg_wait_to_complete)
897 s32 status = IXGBE_SUCCESS;
898 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
900 bool link_up = false;
901 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
903 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
905 /* Set autoneg_advertised value based on input link speed */
906 hw->phy.autoneg_advertised = 0;
908 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
909 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
911 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
912 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
914 if (speed & IXGBE_LINK_SPEED_100_FULL)
915 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
918 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
919 * autoneg advertisement if link is unable to be established at the
920 * highest negotiated rate. This can sometimes happen due to integrity
921 * issues with the physical media connection.
924 /* First, try to get link with full advertisement */
925 hw->phy.smart_speed_active = false;
926 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
927 status = ixgbe_setup_mac_link_82599(hw, speed,
928 autoneg_wait_to_complete);
929 if (status != IXGBE_SUCCESS)
933 * Wait for the controller to acquire link. Per IEEE 802.3ap,
934 * Section 73.10.2, we may have to wait up to 500ms if KR is
935 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
936 * Table 9 in the AN MAS.
938 for (i = 0; i < 5; i++) {
941 /* If we have link, just jump out */
942 status = ixgbe_check_link(hw, &link_speed, &link_up,
944 if (status != IXGBE_SUCCESS)
953 * We didn't get link. If we advertised KR plus one of KX4/KX
954 * (or BX4/BX), then disable KR and try again.
956 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
957 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
960 /* Turn SmartSpeed on to disable KR support */
961 hw->phy.smart_speed_active = true;
962 status = ixgbe_setup_mac_link_82599(hw, speed,
963 autoneg_wait_to_complete);
964 if (status != IXGBE_SUCCESS)
968 * Wait for the controller to acquire link. 600ms will allow for
969 * the AN link_fail_inhibit_timer as well for multiple cycles of
970 * parallel detect, both 10g and 1g. This allows for the maximum
971 * connect attempts as defined in the AN MAS table 73-7.
973 for (i = 0; i < 6; i++) {
976 /* If we have link, just jump out */
977 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
978 if (status != IXGBE_SUCCESS)
985 /* We didn't get link. Turn SmartSpeed back off. */
986 hw->phy.smart_speed_active = false;
987 status = ixgbe_setup_mac_link_82599(hw, speed,
988 autoneg_wait_to_complete);
991 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
992 DEBUGOUT("Smartspeed has downgraded the link speed "
993 "from the maximum advertised\n");
998 * ixgbe_setup_mac_link_82599 - Set MAC link speed
999 * @hw: pointer to hardware structure
1000 * @speed: new link speed
1001 * @autoneg_wait_to_complete: true when waiting for completion is needed
1003 * Set the link speed in the AUTOC register and restarts link.
1005 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
1006 ixgbe_link_speed speed,
1007 bool autoneg_wait_to_complete)
1009 bool autoneg = false;
1010 s32 status = IXGBE_SUCCESS;
1011 u32 pma_pmd_1g, link_mode;
1012 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */
1013 u32 orig_autoc = 0; /* holds the cached value of AUTOC register */
1014 u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */
1015 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1016 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1019 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
1021 DEBUGFUNC("ixgbe_setup_mac_link_82599");
1023 /* Check to see if speed passed in is supported. */
1024 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
1028 speed &= link_capabilities;
1030 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
1031 status = IXGBE_ERR_LINK_SETUP;
1035 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
1036 if (hw->mac.orig_link_settings_stored)
1037 orig_autoc = hw->mac.orig_autoc;
1041 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
1042 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1044 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1045 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1046 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1047 /* Set KX4/KX/KR support according to speed requested */
1048 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
1049 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1050 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
1051 autoc |= IXGBE_AUTOC_KX4_SUPP;
1052 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
1053 (hw->phy.smart_speed_active == false))
1054 autoc |= IXGBE_AUTOC_KR_SUPP;
1056 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1057 autoc |= IXGBE_AUTOC_KX_SUPP;
1058 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
1059 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
1060 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
1061 /* Switch from 1G SFI to 10G SFI if requested */
1062 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
1063 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
1064 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1065 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
1067 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
1068 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
1069 /* Switch from 10G SFI to 1G SFI if requested */
1070 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1071 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
1072 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1074 autoc |= IXGBE_AUTOC_LMS_1G_AN;
1076 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
1080 if (autoc != current_autoc) {
1082 status = hw->mac.ops.prot_autoc_write(hw, autoc, false);
1083 if (status != IXGBE_SUCCESS)
1086 /* Only poll for autoneg to complete if specified to do so */
1087 if (autoneg_wait_to_complete) {
1088 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1089 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1090 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1091 links_reg = 0; /*Just in case Autoneg time=0*/
1092 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1094 IXGBE_READ_REG(hw, IXGBE_LINKS);
1095 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
1099 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
1101 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
1102 DEBUGOUT("Autoneg did not complete.\n");
1107 /* Add delay to filter out noises during initial link setup */
1116 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
1117 * @hw: pointer to hardware structure
1118 * @speed: new link speed
1119 * @autoneg_wait_to_complete: true if waiting is needed to complete
1121 * Restarts link on PHY and MAC based on settings passed in.
1123 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1124 ixgbe_link_speed speed,
1125 bool autoneg_wait_to_complete)
1129 DEBUGFUNC("ixgbe_setup_copper_link_82599");
1131 /* Setup the PHY according to input speed */
1132 status = hw->phy.ops.setup_link_speed(hw, speed,
1133 autoneg_wait_to_complete);
1135 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1141 * ixgbe_reset_hw_82599 - Perform hardware reset
1142 * @hw: pointer to hardware structure
1144 * Resets the hardware by resetting the transmit and receive units, masks
1145 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1148 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1150 ixgbe_link_speed link_speed;
1153 u32 i, autoc, autoc2;
1155 bool link_up = false;
1157 DEBUGFUNC("ixgbe_reset_hw_82599");
1159 /* Call adapter stop to disable tx/rx and clear interrupts */
1160 status = hw->mac.ops.stop_adapter(hw);
1161 if (status != IXGBE_SUCCESS)
1164 /* flush pending Tx transactions */
1165 ixgbe_clear_tx_pending(hw);
1167 /* PHY ops must be identified and initialized prior to reset */
1169 /* Identify PHY and related function pointers */
1170 status = hw->phy.ops.init(hw);
1172 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1175 /* Setup SFP module if there is one present. */
1176 if (hw->phy.sfp_setup_needed) {
1177 status = hw->mac.ops.setup_sfp(hw);
1178 hw->phy.sfp_setup_needed = false;
1181 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1185 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1186 hw->phy.ops.reset(hw);
1188 /* remember AUTOC from before we reset */
1189 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
1193 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1194 * If link reset is used when link is up, it might reset the PHY when
1195 * mng is using it. If link is down or the flag to force full link
1196 * reset is set, then perform link reset.
1198 ctrl = IXGBE_CTRL_LNK_RST;
1199 if (!hw->force_full_reset) {
1200 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1202 ctrl = IXGBE_CTRL_RST;
1205 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1206 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1207 IXGBE_WRITE_FLUSH(hw);
1209 /* Poll for reset bit to self-clear meaning reset is complete */
1210 for (i = 0; i < 10; i++) {
1212 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1213 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1217 if (ctrl & IXGBE_CTRL_RST_MASK) {
1218 status = IXGBE_ERR_RESET_FAILED;
1219 DEBUGOUT("Reset polling failed to complete.\n");
1225 * Double resets are required for recovery from certain error
1226 * conditions. Between resets, it is necessary to stall to
1227 * allow time for any pending HW events to complete.
1229 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1230 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1235 * Store the original AUTOC/AUTOC2 values if they have not been
1236 * stored off yet. Otherwise restore the stored original
1237 * values since the reset operation sets back to defaults.
1239 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1240 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1242 /* Enable link if disabled in NVM */
1243 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1244 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1245 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1246 IXGBE_WRITE_FLUSH(hw);
1249 if (hw->mac.orig_link_settings_stored == false) {
1250 hw->mac.orig_autoc = autoc;
1251 hw->mac.orig_autoc2 = autoc2;
1252 hw->mac.orig_link_settings_stored = true;
1255 /* If MNG FW is running on a multi-speed device that
1256 * doesn't autoneg with out driver support we need to
1257 * leave LMS in the state it was before we MAC reset.
1258 * Likewise if we support WoL we don't want change the
1261 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
1263 hw->mac.orig_autoc =
1264 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1267 if (autoc != hw->mac.orig_autoc) {
1268 status = hw->mac.ops.prot_autoc_write(hw,
1271 if (status != IXGBE_SUCCESS)
1275 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1276 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1277 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1278 autoc2 |= (hw->mac.orig_autoc2 &
1279 IXGBE_AUTOC2_UPPER_MASK);
1280 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1284 /* Store the permanent mac address */
1285 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1288 * Store MAC address from RAR0, clear receive address registers, and
1289 * clear the multicast table. Also reset num_rar_entries to 128,
1290 * since we modify this value when programming the SAN MAC address.
1292 hw->mac.num_rar_entries = 128;
1293 hw->mac.ops.init_rx_addrs(hw);
1295 /* Store the permanent SAN mac address */
1296 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1298 /* Add the SAN MAC address to the RAR only if it's a valid address */
1299 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1300 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1301 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1303 /* Save the SAN MAC RAR index */
1304 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1306 /* Reserve the last RAR for the SAN MAC address */
1307 hw->mac.num_rar_entries--;
1310 /* Store the alternative WWNN/WWPN prefix */
1311 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1312 &hw->mac.wwpn_prefix);
1319 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1320 * @hw: pointer to hardware structure
1322 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1325 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1326 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1328 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1331 * Before starting reinitialization process,
1332 * FDIRCMD.CMD must be zero.
1334 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1335 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1336 IXGBE_FDIRCMD_CMD_MASK))
1340 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1341 DEBUGOUT("Flow Director previous command isn't complete, "
1342 "aborting table re-initialization.\n");
1343 return IXGBE_ERR_FDIR_REINIT_FAILED;
1346 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1347 IXGBE_WRITE_FLUSH(hw);
1349 * 82599 adapters flow director init flow cannot be restarted,
1350 * Workaround 82599 silicon errata by performing the following steps
1351 * before re-writing the FDIRCTRL control register with the same value.
1352 * - write 1 to bit 8 of FDIRCMD register &
1353 * - write 0 to bit 8 of FDIRCMD register
1355 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1356 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1357 IXGBE_FDIRCMD_CLEARHT));
1358 IXGBE_WRITE_FLUSH(hw);
1359 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1360 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1361 ~IXGBE_FDIRCMD_CLEARHT));
1362 IXGBE_WRITE_FLUSH(hw);
1364 * Clear FDIR Hash register to clear any leftover hashes
1365 * waiting to be programmed.
1367 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1368 IXGBE_WRITE_FLUSH(hw);
1370 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1371 IXGBE_WRITE_FLUSH(hw);
1373 /* Poll init-done after we write FDIRCTRL register */
1374 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1375 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1376 IXGBE_FDIRCTRL_INIT_DONE)
1380 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1381 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1382 return IXGBE_ERR_FDIR_REINIT_FAILED;
1385 /* Clear FDIR statistics registers (read to clear) */
1386 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1387 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1388 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1389 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1390 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1392 return IXGBE_SUCCESS;
1396 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1397 * @hw: pointer to hardware structure
1398 * @fdirctrl: value to write to flow director control register
1400 STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1404 DEBUGFUNC("ixgbe_fdir_enable_82599");
1406 /* Prime the keys for hashing */
1407 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1408 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1411 * Poll init-done after we write the register. Estimated times:
1412 * 10G: PBALLOC = 11b, timing is 60us
1413 * 1G: PBALLOC = 11b, timing is 600us
1414 * 100M: PBALLOC = 11b, timing is 6ms
1416 * Multiple these timings by 4 if under full Rx load
1418 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1419 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1420 * this might not finish in our poll time, but we can live with that
1423 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1424 IXGBE_WRITE_FLUSH(hw);
1425 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1426 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1427 IXGBE_FDIRCTRL_INIT_DONE)
1432 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1433 DEBUGOUT("Flow Director poll time exceeded!\n");
1437 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1438 * @hw: pointer to hardware structure
1439 * @fdirctrl: value to write to flow director control register, initially
1440 * contains just the value of the Rx packet buffer allocation
1442 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1444 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1447 * Continue setup of fdirctrl register bits:
1448 * Move the flexible bytes to use the ethertype - shift 6 words
1449 * Set the maximum length per hash bucket to 0xA filters
1450 * Send interrupt when 64 filters are left
1452 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1453 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1454 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1456 /* write hashes and fdirctrl register, poll for completion */
1457 ixgbe_fdir_enable_82599(hw, fdirctrl);
1459 return IXGBE_SUCCESS;
1463 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1464 * @hw: pointer to hardware structure
1465 * @fdirctrl: value to write to flow director control register, initially
1466 * contains just the value of the Rx packet buffer allocation
1468 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1470 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1473 * Continue setup of fdirctrl register bits:
1474 * Turn perfect match filtering on
1475 * Report hash in RSS field of Rx wb descriptor
1476 * Initialize the drop queue
1477 * Move the flexible bytes to use the ethertype - shift 6 words
1478 * Set the maximum length per hash bucket to 0xA filters
1479 * Send interrupt when 64 (0x4 * 16) filters are left
1481 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1482 IXGBE_FDIRCTRL_REPORT_STATUS |
1483 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1484 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1485 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1486 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1489 /* write hashes and fdirctrl register, poll for completion */
1490 ixgbe_fdir_enable_82599(hw, fdirctrl);
1492 return IXGBE_SUCCESS;
1496 * These defines allow us to quickly generate all of the necessary instructions
1497 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1498 * for values 0 through 15
1500 #define IXGBE_ATR_COMMON_HASH_KEY \
1501 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1502 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1505 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1506 common_hash ^= lo_hash_dword >> n; \
1507 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1508 bucket_hash ^= lo_hash_dword >> n; \
1509 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1510 sig_hash ^= lo_hash_dword << (16 - n); \
1511 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1512 common_hash ^= hi_hash_dword >> n; \
1513 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1514 bucket_hash ^= hi_hash_dword >> n; \
1515 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1516 sig_hash ^= hi_hash_dword << (16 - n); \
1520 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1521 * @stream: input bitstream to compute the hash on
1523 * This function is almost identical to the function above but contains
1524 * several optomizations such as unwinding all of the loops, letting the
1525 * compiler work out all of the conditional ifs since the keys are static
1526 * defines, and computing two keys at once since the hashed dword stream
1527 * will be the same for both keys.
1529 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1530 union ixgbe_atr_hash_dword common)
1532 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1533 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1535 /* record the flow_vm_vlan bits as they are a key part to the hash */
1536 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1538 /* generate common hash dword */
1539 hi_hash_dword = IXGBE_NTOHL(common.dword);
1541 /* low dword is word swapped version of common */
1542 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1544 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1545 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1547 /* Process bits 0 and 16 */
1548 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1551 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1552 * delay this because bit 0 of the stream should not be processed
1553 * so we do not add the vlan until after bit 0 was processed
1555 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1557 /* Process remaining 30 bit of the key */
1558 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1559 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1560 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1561 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1562 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1563 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1564 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1565 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1566 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1567 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1568 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1569 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1570 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1571 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1572 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1574 /* combine common_hash result with signature and bucket hashes */
1575 bucket_hash ^= common_hash;
1576 bucket_hash &= IXGBE_ATR_HASH_MASK;
1578 sig_hash ^= common_hash << 16;
1579 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1581 /* return completed signature hash */
1582 return sig_hash ^ bucket_hash;
1586 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1587 * @hw: pointer to hardware structure
1588 * @input: unique input dword
1589 * @common: compressed common input dword
1590 * @queue: queue index to direct traffic to
1592 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1593 union ixgbe_atr_hash_dword input,
1594 union ixgbe_atr_hash_dword common,
1600 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1603 * Get the flow_type in order to program FDIRCMD properly
1604 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1605 * fifth is FDIRCMD.TUNNEL_FILTER
1607 switch (input.formatted.flow_type) {
1608 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1609 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1610 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1611 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1612 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1613 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1616 DEBUGOUT(" Error on flow type input\n");
1617 return IXGBE_ERR_CONFIG;
1620 /* configure FDIRCMD register */
1621 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1622 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1623 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1624 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1627 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1628 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1630 fdirhashcmd = (u64)fdircmd << 32;
1631 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1632 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1634 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1636 return IXGBE_SUCCESS;
1639 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1642 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1643 bucket_hash ^= lo_hash_dword >> n; \
1644 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1645 bucket_hash ^= hi_hash_dword >> n; \
1649 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1650 * @atr_input: input bitstream to compute the hash on
1651 * @input_mask: mask for the input bitstream
1653 * This function serves two main purposes. First it applys the input_mask
1654 * to the atr_input resulting in a cleaned up atr_input data stream.
1655 * Secondly it computes the hash and stores it in the bkt_hash field at
1656 * the end of the input byte stream. This way it will be available for
1657 * future use without needing to recompute the hash.
1659 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1660 union ixgbe_atr_input *input_mask)
1663 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1664 u32 bucket_hash = 0;
1666 /* Apply masks to input data */
1667 input->dword_stream[0] &= input_mask->dword_stream[0];
1668 input->dword_stream[1] &= input_mask->dword_stream[1];
1669 input->dword_stream[2] &= input_mask->dword_stream[2];
1670 input->dword_stream[3] &= input_mask->dword_stream[3];
1671 input->dword_stream[4] &= input_mask->dword_stream[4];
1672 input->dword_stream[5] &= input_mask->dword_stream[5];
1673 input->dword_stream[6] &= input_mask->dword_stream[6];
1674 input->dword_stream[7] &= input_mask->dword_stream[7];
1675 input->dword_stream[8] &= input_mask->dword_stream[8];
1676 input->dword_stream[9] &= input_mask->dword_stream[9];
1677 input->dword_stream[10] &= input_mask->dword_stream[10];
1679 /* record the flow_vm_vlan bits as they are a key part to the hash */
1680 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1682 /* generate common hash dword */
1683 hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
1684 input->dword_stream[2] ^
1685 input->dword_stream[3] ^
1686 input->dword_stream[4] ^
1687 input->dword_stream[5] ^
1688 input->dword_stream[6] ^
1689 input->dword_stream[7] ^
1690 input->dword_stream[8] ^
1691 input->dword_stream[9] ^
1692 input->dword_stream[10]);
1694 /* low dword is word swapped version of common */
1695 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1697 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1698 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1700 /* Process bits 0 and 16 */
1701 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1704 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1705 * delay this because bit 0 of the stream should not be processed
1706 * so we do not add the vlan until after bit 0 was processed
1708 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1710 /* Process remaining 30 bit of the key */
1711 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1712 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1713 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1714 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1715 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1716 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1717 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1718 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1719 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1720 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1721 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1722 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1723 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1724 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1725 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1728 * Limit hash to 13 bits since max bucket count is 8K.
1729 * Store result at the end of the input stream.
1731 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1735 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1736 * @input_mask: mask to be bit swapped
1738 * The source and destination port masks for flow director are bit swapped
1739 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1740 * generate a correctly swapped value we need to bit swap the mask and that
1741 * is what is accomplished by this function.
1743 STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1745 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1746 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1747 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1748 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1749 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1750 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1751 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1755 * These two macros are meant to address the fact that we have registers
1756 * that are either all or in part big-endian. As a result on big-endian
1757 * systems we will end up byte swapping the value to little-endian before
1758 * it is byte swapped again and written to the hardware in the original
1759 * big-endian format.
1761 #define IXGBE_STORE_AS_BE32(_value) \
1762 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1763 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1765 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1766 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1768 #define IXGBE_STORE_AS_BE16(_value) \
1769 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1771 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1772 union ixgbe_atr_input *input_mask)
1774 /* mask IPv6 since it is currently not supported */
1775 u32 fdirm = IXGBE_FDIRM_DIPv6;
1777 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1780 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1781 * are zero, then assume a full mask for that field. Also assume that
1782 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1783 * cannot be masked out in this implementation.
1785 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1789 /* verify bucket hash is cleared on hash generation */
1790 if (input_mask->formatted.bkt_hash)
1791 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1793 /* Program FDIRM and verify partial masks */
1794 switch (input_mask->formatted.vm_pool & 0x7F) {
1796 fdirm |= IXGBE_FDIRM_POOL;
1800 DEBUGOUT(" Error on vm pool mask\n");
1801 return IXGBE_ERR_CONFIG;
1804 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1806 fdirm |= IXGBE_FDIRM_L4P;
1807 if (input_mask->formatted.dst_port ||
1808 input_mask->formatted.src_port) {
1809 DEBUGOUT(" Error on src/dst port mask\n");
1810 return IXGBE_ERR_CONFIG;
1812 case IXGBE_ATR_L4TYPE_MASK:
1815 DEBUGOUT(" Error on flow type mask\n");
1816 return IXGBE_ERR_CONFIG;
1819 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1821 /* mask VLAN ID, fall through to mask VLAN priority */
1822 fdirm |= IXGBE_FDIRM_VLANID;
1824 /* mask VLAN priority */
1825 fdirm |= IXGBE_FDIRM_VLANP;
1828 /* mask VLAN ID only, fall through */
1829 fdirm |= IXGBE_FDIRM_VLANID;
1831 /* no VLAN fields masked */
1834 DEBUGOUT(" Error on VLAN mask\n");
1835 return IXGBE_ERR_CONFIG;
1838 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1840 /* Mask Flex Bytes, fall through */
1841 fdirm |= IXGBE_FDIRM_FLEX;
1845 DEBUGOUT(" Error on flexible byte mask\n");
1846 return IXGBE_ERR_CONFIG;
1850 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1851 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1853 /* store the TCP/UDP port masks, bit reversed from port layout */
1854 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1856 /* write both the same so that UDP and TCP use the same mask */
1857 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1858 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1860 /* store source and destination IP masks (big-enian) */
1861 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1862 ~input_mask->formatted.src_ip[0]);
1863 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1864 ~input_mask->formatted.dst_ip[0]);
1866 return IXGBE_SUCCESS;
1869 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1870 union ixgbe_atr_input *input,
1871 u16 soft_id, u8 queue)
1873 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1875 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1877 /* currently IPv6 is not supported, must be programmed with 0 */
1878 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1879 input->formatted.src_ip[0]);
1880 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1881 input->formatted.src_ip[1]);
1882 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1883 input->formatted.src_ip[2]);
1885 /* record the source address (big-endian) */
1886 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1888 /* record the first 32 bits of the destination address (big-endian) */
1889 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1891 /* record source and destination port (little-endian)*/
1892 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1893 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1894 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1895 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1897 /* record vlan (little-endian) and flex_bytes(big-endian) */
1898 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1899 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1900 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1901 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1904 /* configure FDIRHASH register */
1905 fdirhash = input->formatted.bkt_hash;
1906 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1907 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1910 * flush all previous writes to make certain registers are
1911 * programmed prior to issuing the command
1913 IXGBE_WRITE_FLUSH(hw);
1915 /* configure FDIRCMD register */
1916 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1917 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1918 if (queue == IXGBE_FDIR_DROP_QUEUE)
1919 fdircmd |= IXGBE_FDIRCMD_DROP;
1920 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1921 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1922 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1924 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1926 return IXGBE_SUCCESS;
1929 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1930 union ixgbe_atr_input *input,
1936 s32 err = IXGBE_SUCCESS;
1938 /* configure FDIRHASH register */
1939 fdirhash = input->formatted.bkt_hash;
1940 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1941 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1943 /* flush hash to HW */
1944 IXGBE_WRITE_FLUSH(hw);
1946 /* Query if filter is present */
1947 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1949 for (retry_count = 10; retry_count; retry_count--) {
1950 /* allow 10us for query to process */
1952 /* verify query completed successfully */
1953 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1954 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1959 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1961 /* if filter exists in hardware then remove it */
1962 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1963 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1964 IXGBE_WRITE_FLUSH(hw);
1965 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1966 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1973 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1974 * @hw: pointer to hardware structure
1975 * @input: input bitstream
1976 * @input_mask: mask for the input bitstream
1977 * @soft_id: software index for the filters
1978 * @queue: queue index to direct traffic to
1980 * Note that the caller to this function must lock before calling, since the
1981 * hardware writes must be protected from one another.
1983 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1984 union ixgbe_atr_input *input,
1985 union ixgbe_atr_input *input_mask,
1986 u16 soft_id, u8 queue)
1988 s32 err = IXGBE_ERR_CONFIG;
1990 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1993 * Check flow_type formatting, and bail out before we touch the hardware
1994 * if there's a configuration issue
1996 switch (input->formatted.flow_type) {
1997 case IXGBE_ATR_FLOW_TYPE_IPV4:
1998 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1999 if (input->formatted.dst_port || input->formatted.src_port) {
2000 DEBUGOUT(" Error on src/dst port\n");
2001 return IXGBE_ERR_CONFIG;
2004 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
2005 if (input->formatted.dst_port || input->formatted.src_port) {
2006 DEBUGOUT(" Error on src/dst port\n");
2007 return IXGBE_ERR_CONFIG;
2009 case IXGBE_ATR_FLOW_TYPE_TCPV4:
2010 case IXGBE_ATR_FLOW_TYPE_UDPV4:
2011 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
2012 IXGBE_ATR_L4TYPE_MASK;
2015 DEBUGOUT(" Error on flow type input\n");
2019 /* program input mask into the HW */
2020 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
2024 /* apply mask and compute/store hash */
2025 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
2027 /* program filters to filter memory */
2028 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
2033 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2034 * @hw: pointer to hardware structure
2035 * @reg: analog register to read
2038 * Performs read operation to Omer analog register specified.
2040 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
2044 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
2046 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2048 IXGBE_WRITE_FLUSH(hw);
2050 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2051 *val = (u8)core_ctl;
2053 return IXGBE_SUCCESS;
2057 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2058 * @hw: pointer to hardware structure
2059 * @reg: atlas register to write
2060 * @val: value to write
2062 * Performs write operation to Omer analog register specified.
2064 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2068 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
2070 core_ctl = (reg << 8) | val;
2071 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2072 IXGBE_WRITE_FLUSH(hw);
2075 return IXGBE_SUCCESS;
2079 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2080 * @hw: pointer to hardware structure
2082 * Starts the hardware using the generic start_hw function
2083 * and the generation start_hw function.
2084 * Then performs revision-specific operations, if any.
2086 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2088 s32 ret_val = IXGBE_SUCCESS;
2090 DEBUGFUNC("ixgbe_start_hw_82599");
2092 ret_val = ixgbe_start_hw_generic(hw);
2093 if (ret_val != IXGBE_SUCCESS)
2096 ret_val = ixgbe_start_hw_gen2(hw);
2097 if (ret_val != IXGBE_SUCCESS)
2100 /* We need to run link autotry after the driver loads */
2101 hw->mac.autotry_restart = true;
2103 if (ret_val == IXGBE_SUCCESS)
2104 ret_val = ixgbe_verify_fw_version_82599(hw);
2110 * ixgbe_identify_phy_82599 - Get physical layer module
2111 * @hw: pointer to hardware structure
2113 * Determines the physical layer module found on the current adapter.
2114 * If PHY already detected, maintains current PHY type in hw struct,
2115 * otherwise executes the PHY detection routine.
2117 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2121 DEBUGFUNC("ixgbe_identify_phy_82599");
2123 /* Detect PHY if not unknown - returns success if already detected. */
2124 status = ixgbe_identify_phy_generic(hw);
2125 if (status != IXGBE_SUCCESS) {
2126 /* 82599 10GBASE-T requires an external PHY */
2127 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2130 status = ixgbe_identify_module_generic(hw);
2133 /* Set PHY type none if no PHY detected */
2134 if (hw->phy.type == ixgbe_phy_unknown) {
2135 hw->phy.type = ixgbe_phy_none;
2136 status = IXGBE_SUCCESS;
2139 /* Return error if SFP module has been detected but is not supported */
2140 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2141 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
2148 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2149 * @hw: pointer to hardware structure
2151 * Determines physical layer capabilities of the current configuration.
2153 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2155 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2156 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2157 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2158 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2159 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2160 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2161 u16 ext_ability = 0;
2162 u8 comp_codes_10g = 0;
2163 u8 comp_codes_1g = 0;
2165 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2167 hw->phy.ops.identify(hw);
2169 switch (hw->phy.type) {
2171 case ixgbe_phy_cu_unknown:
2172 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2173 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2174 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2175 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2176 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2177 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2178 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
2179 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2185 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2186 case IXGBE_AUTOC_LMS_1G_AN:
2187 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2188 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2189 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2190 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2193 /* SFI mode so read SFP module */
2196 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2197 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2198 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2199 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2200 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2201 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2202 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2205 case IXGBE_AUTOC_LMS_10G_SERIAL:
2206 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2207 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2209 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2212 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2213 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2214 if (autoc & IXGBE_AUTOC_KX_SUPP)
2215 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2216 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2217 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2218 if (autoc & IXGBE_AUTOC_KR_SUPP)
2219 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2228 /* SFP check must be done last since DA modules are sometimes used to
2229 * test KR mode - we need to id KR mode correctly before SFP module.
2230 * Call identify_sfp because the pluggable module may have changed */
2231 hw->phy.ops.identify_sfp(hw);
2232 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2235 switch (hw->phy.type) {
2236 case ixgbe_phy_sfp_passive_tyco:
2237 case ixgbe_phy_sfp_passive_unknown:
2238 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2240 case ixgbe_phy_sfp_ftl_active:
2241 case ixgbe_phy_sfp_active_unknown:
2242 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2244 case ixgbe_phy_sfp_avago:
2245 case ixgbe_phy_sfp_ftl:
2246 case ixgbe_phy_sfp_intel:
2247 case ixgbe_phy_sfp_unknown:
2248 hw->phy.ops.read_i2c_eeprom(hw,
2249 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2250 hw->phy.ops.read_i2c_eeprom(hw,
2251 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2252 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2253 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2254 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2255 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2256 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2257 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2258 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
2259 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
2266 return physical_layer;
2270 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2271 * @hw: pointer to hardware structure
2272 * @regval: register value to write to RXCTRL
2274 * Enables the Rx DMA unit for 82599
2276 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2279 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2282 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2283 * If traffic is incoming before we enable the Rx unit, it could hang
2284 * the Rx DMA unit. Therefore, make sure the security engine is
2285 * completely disabled prior to enabling the Rx unit.
2288 hw->mac.ops.disable_sec_rx_path(hw);
2290 if (regval & IXGBE_RXCTRL_RXEN)
2291 ixgbe_enable_rx(hw);
2293 ixgbe_disable_rx(hw);
2295 hw->mac.ops.enable_sec_rx_path(hw);
2297 return IXGBE_SUCCESS;
2301 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2302 * @hw: pointer to hardware structure
2304 * Verifies that installed the firmware version is 0.6 or higher
2305 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2307 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2308 * if the FW version is not supported.
2310 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2312 s32 status = IXGBE_ERR_EEPROM_VERSION;
2313 u16 fw_offset, fw_ptp_cfg_offset;
2316 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2318 /* firmware check is only necessary for SFI devices */
2319 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2320 status = IXGBE_SUCCESS;
2321 goto fw_version_out;
2324 /* get the offset to the Firmware Module block */
2325 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
2326 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2327 "eeprom read at offset %d failed", IXGBE_FW_PTR);
2328 return IXGBE_ERR_EEPROM_VERSION;
2331 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2332 goto fw_version_out;
2334 /* get the offset to the Pass Through Patch Configuration block */
2335 if (hw->eeprom.ops.read(hw, (fw_offset +
2336 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2337 &fw_ptp_cfg_offset)) {
2338 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2339 "eeprom read at offset %d failed",
2341 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);
2342 return IXGBE_ERR_EEPROM_VERSION;
2345 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2346 goto fw_version_out;
2348 /* get the firmware version */
2349 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2350 IXGBE_FW_PATCH_VERSION_4), &fw_version)) {
2351 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2352 "eeprom read at offset %d failed",
2353 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);
2354 return IXGBE_ERR_EEPROM_VERSION;
2357 if (fw_version > 0x5)
2358 status = IXGBE_SUCCESS;
2365 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2366 * @hw: pointer to hardware structure
2368 * Returns true if the LESM FW module is present and enabled. Otherwise
2369 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2371 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2373 bool lesm_enabled = false;
2374 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2377 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2379 /* get the offset to the Firmware Module block */
2380 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2382 if ((status != IXGBE_SUCCESS) ||
2383 (fw_offset == 0) || (fw_offset == 0xFFFF))
2386 /* get the offset to the LESM Parameters block */
2387 status = hw->eeprom.ops.read(hw, (fw_offset +
2388 IXGBE_FW_LESM_PARAMETERS_PTR),
2389 &fw_lesm_param_offset);
2391 if ((status != IXGBE_SUCCESS) ||
2392 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2395 /* get the lesm state word */
2396 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2397 IXGBE_FW_LESM_STATE_1),
2400 if ((status == IXGBE_SUCCESS) &&
2401 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2402 lesm_enabled = true;
2405 return lesm_enabled;
2409 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2410 * fastest available method
2412 * @hw: pointer to hardware structure
2413 * @offset: offset of word in EEPROM to read
2414 * @words: number of words
2415 * @data: word(s) read from the EEPROM
2417 * Retrieves 16 bit word(s) read from EEPROM
2419 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2420 u16 words, u16 *data)
2422 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2423 s32 ret_val = IXGBE_ERR_CONFIG;
2425 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2428 * If EEPROM is detected and can be addressed using 14 bits,
2429 * use EERD otherwise use bit bang
2431 if ((eeprom->type == ixgbe_eeprom_spi) &&
2432 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2433 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2436 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2444 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2445 * fastest available method
2447 * @hw: pointer to hardware structure
2448 * @offset: offset of word in the EEPROM to read
2449 * @data: word read from the EEPROM
2451 * Reads a 16 bit word from the EEPROM
2453 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2454 u16 offset, u16 *data)
2456 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2457 s32 ret_val = IXGBE_ERR_CONFIG;
2459 DEBUGFUNC("ixgbe_read_eeprom_82599");
2462 * If EEPROM is detected and can be addressed using 14 bits,
2463 * use EERD otherwise use bit bang
2465 if ((eeprom->type == ixgbe_eeprom_spi) &&
2466 (offset <= IXGBE_EERD_MAX_ADDR))
2467 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2469 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2475 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2477 * @hw: pointer to hardware structure
2479 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2480 * full pipeline reset. This function assumes the SW/FW lock is held.
2482 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2486 u32 i, autoc_reg, autoc2_reg;
2488 /* Enable link if disabled in NVM */
2489 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2490 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2491 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2492 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2493 IXGBE_WRITE_FLUSH(hw);
2496 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2497 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2498 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2499 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
2500 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));
2501 /* Wait for AN to leave state 0 */
2502 for (i = 0; i < 10; i++) {
2504 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2505 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2509 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2510 DEBUGOUT("auto negotiation not completed\n");
2511 ret_val = IXGBE_ERR_RESET_FAILED;
2512 goto reset_pipeline_out;
2515 ret_val = IXGBE_SUCCESS;
2518 /* Write AUTOC register with original LMS field and Restart_AN */
2519 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2520 IXGBE_WRITE_FLUSH(hw);