1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82599.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
39 #ident "$Id: ixgbe_82599.c,v 1.301 2012/11/08 11:33:27 jtkirshe Exp $"
41 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed speed,
44 bool autoneg_wait_to_complete);
45 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
46 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
47 u16 offset, u16 *data);
48 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
49 u16 words, u16 *data);
51 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
53 struct ixgbe_mac_info *mac = &hw->mac;
55 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
57 /* enable the laser control functions for SFP+ fiber */
58 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
59 mac->ops.disable_tx_laser =
60 &ixgbe_disable_tx_laser_multispeed_fiber;
61 mac->ops.enable_tx_laser =
62 &ixgbe_enable_tx_laser_multispeed_fiber;
63 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
66 mac->ops.disable_tx_laser = NULL;
67 mac->ops.enable_tx_laser = NULL;
68 mac->ops.flap_tx_laser = NULL;
71 if (hw->phy.multispeed_fiber) {
72 /* Set up dual speed SFP+ support */
73 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
75 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
76 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
77 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
78 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
79 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
81 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
87 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
88 * @hw: pointer to hardware structure
90 * Initialize any function pointers that were not able to be
91 * set during init_shared_code because the PHY/SFP type was
92 * not known. Perform the SFP init if necessary.
95 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
97 struct ixgbe_mac_info *mac = &hw->mac;
98 struct ixgbe_phy_info *phy = &hw->phy;
99 s32 ret_val = IXGBE_SUCCESS;
101 DEBUGFUNC("ixgbe_init_phy_ops_82599");
103 /* Identify the PHY or SFP module */
104 ret_val = phy->ops.identify(hw);
105 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
106 goto init_phy_ops_out;
108 /* Setup function pointers based on detected SFP module and speeds */
109 ixgbe_init_mac_link_ops_82599(hw);
110 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
111 hw->phy.ops.reset = NULL;
113 /* If copper media, overwrite with copper function pointers */
114 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
115 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
116 mac->ops.get_link_capabilities =
117 &ixgbe_get_copper_link_capabilities_generic;
120 /* Set necessary function pointers based on phy type */
121 switch (hw->phy.type) {
123 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
124 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
125 phy->ops.get_firmware_version =
126 &ixgbe_get_phy_firmware_version_tnx;
135 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
137 s32 ret_val = IXGBE_SUCCESS;
138 u16 list_offset, data_offset, data_value;
139 bool got_lock = false;
141 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
143 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
144 ixgbe_init_mac_link_ops_82599(hw);
146 hw->phy.ops.reset = NULL;
148 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
150 if (ret_val != IXGBE_SUCCESS)
153 /* PHY config will finish before releasing the semaphore */
154 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
155 IXGBE_GSSR_MAC_CSR_SM);
156 if (ret_val != IXGBE_SUCCESS) {
157 ret_val = IXGBE_ERR_SWFW_SYNC;
161 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
162 while (data_value != 0xffff) {
163 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
164 IXGBE_WRITE_FLUSH(hw);
165 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
168 /* Release the semaphore */
169 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
170 /* Delay obtaining semaphore again to allow FW access */
171 msec_delay(hw->eeprom.semaphore_delay);
173 /* Need SW/FW semaphore around AUTOC writes if LESM on,
174 * likewise reset_pipeline requires lock as it also writes
177 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
178 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
179 IXGBE_GSSR_MAC_CSR_SM);
180 if (ret_val != IXGBE_SUCCESS) {
181 ret_val = IXGBE_ERR_SWFW_SYNC;
188 /* Restart DSP and set SFI mode */
189 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
190 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL));
192 ret_val = ixgbe_reset_pipeline_82599(hw);
195 hw->mac.ops.release_swfw_sync(hw,
196 IXGBE_GSSR_MAC_CSR_SM);
201 DEBUGOUT("sfp module setup not complete\n");
202 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
213 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
214 * @hw: pointer to hardware structure
216 * Initialize the function pointers and assign the MAC type for 82599.
217 * Does not touch the hardware.
220 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
222 struct ixgbe_mac_info *mac = &hw->mac;
223 struct ixgbe_phy_info *phy = &hw->phy;
224 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
227 DEBUGFUNC("ixgbe_init_ops_82599");
229 ret_val = ixgbe_init_phy_ops_generic(hw);
230 ret_val = ixgbe_init_ops_generic(hw);
233 phy->ops.identify = &ixgbe_identify_phy_82599;
234 phy->ops.init = &ixgbe_init_phy_ops_82599;
237 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
238 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
239 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
240 mac->ops.get_supported_physical_layer =
241 &ixgbe_get_supported_physical_layer_82599;
242 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
243 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
244 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
245 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
246 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
247 mac->ops.start_hw = &ixgbe_start_hw_82599;
248 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
249 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
250 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
251 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
252 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
254 /* RAR, Multicast, VLAN */
255 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
256 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
257 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
258 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
259 mac->rar_highwater = 1;
260 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
261 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
262 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
263 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
264 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
265 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
266 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
269 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
270 mac->ops.check_link = &ixgbe_check_mac_link_generic;
271 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
272 ixgbe_init_mac_link_ops_82599(hw);
274 mac->mcft_size = 128;
276 mac->num_rar_entries = 128;
277 mac->rx_pb_size = 512;
278 mac->max_tx_queues = 128;
279 mac->max_rx_queues = 128;
280 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
282 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
283 IXGBE_FWSM_MODE_MASK) ? true : false;
285 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
288 eeprom->ops.read = &ixgbe_read_eeprom_82599;
289 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
291 /* Manageability interface */
292 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
299 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
300 * @hw: pointer to hardware structure
301 * @speed: pointer to link speed
302 * @negotiation: true when autoneg or autotry is enabled
304 * Determines the link capabilities by reading the AUTOC register.
306 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
307 ixgbe_link_speed *speed,
310 s32 status = IXGBE_SUCCESS;
313 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
316 /* Check if 1G SFP module. */
317 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
318 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
319 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
320 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
321 *speed = IXGBE_LINK_SPEED_1GB_FULL;
327 * Determine link capabilities based on the stored value of AUTOC,
328 * which represents EEPROM defaults. If AUTOC value has not
329 * been stored, use the current register values.
331 if (hw->mac.orig_link_settings_stored)
332 autoc = hw->mac.orig_autoc;
334 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
336 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
337 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
338 *speed = IXGBE_LINK_SPEED_1GB_FULL;
339 *negotiation = false;
342 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
343 *speed = IXGBE_LINK_SPEED_10GB_FULL;
344 *negotiation = false;
347 case IXGBE_AUTOC_LMS_1G_AN:
348 *speed = IXGBE_LINK_SPEED_1GB_FULL;
352 case IXGBE_AUTOC_LMS_10G_SERIAL:
353 *speed = IXGBE_LINK_SPEED_10GB_FULL;
354 *negotiation = false;
357 case IXGBE_AUTOC_LMS_KX4_KX_KR:
358 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
359 *speed = IXGBE_LINK_SPEED_UNKNOWN;
360 if (autoc & IXGBE_AUTOC_KR_SUPP)
361 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
362 if (autoc & IXGBE_AUTOC_KX4_SUPP)
363 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
364 if (autoc & IXGBE_AUTOC_KX_SUPP)
365 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
369 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
370 *speed = IXGBE_LINK_SPEED_100_FULL;
371 if (autoc & IXGBE_AUTOC_KR_SUPP)
372 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
373 if (autoc & IXGBE_AUTOC_KX4_SUPP)
374 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
375 if (autoc & IXGBE_AUTOC_KX_SUPP)
376 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
380 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
381 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
382 *negotiation = false;
386 status = IXGBE_ERR_LINK_SETUP;
391 if (hw->phy.multispeed_fiber) {
392 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
393 IXGBE_LINK_SPEED_1GB_FULL;
402 * ixgbe_get_media_type_82599 - Get media type
403 * @hw: pointer to hardware structure
405 * Returns the media type (fiber, copper, backplane)
407 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
409 enum ixgbe_media_type media_type;
411 DEBUGFUNC("ixgbe_get_media_type_82599");
413 /* Detect if there is a copper PHY attached. */
414 switch (hw->phy.type) {
415 case ixgbe_phy_cu_unknown:
417 media_type = ixgbe_media_type_copper;
423 switch (hw->device_id) {
424 case IXGBE_DEV_ID_82599_KX4:
425 case IXGBE_DEV_ID_82599_KX4_MEZZ:
426 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
427 case IXGBE_DEV_ID_82599_KR:
428 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
429 case IXGBE_DEV_ID_82599_XAUI_LOM:
430 /* Default device ID is mezzanine card KX/KX4 */
431 media_type = ixgbe_media_type_backplane;
433 case IXGBE_DEV_ID_82599_SFP:
434 case IXGBE_DEV_ID_82599_SFP_FCOE:
435 case IXGBE_DEV_ID_82599_SFP_EM:
436 case IXGBE_DEV_ID_82599_SFP_SF2:
437 case IXGBE_DEV_ID_82599_SFP_SF_QP:
438 case IXGBE_DEV_ID_82599EN_SFP:
439 #ifdef RTE_NIC_BYPASS
440 case IXGBE_DEV_ID_82599_BYPASS:
442 media_type = ixgbe_media_type_fiber;
444 case IXGBE_DEV_ID_82599_CX4:
445 media_type = ixgbe_media_type_cx4;
447 case IXGBE_DEV_ID_82599_T3_LOM:
448 media_type = ixgbe_media_type_copper;
451 media_type = ixgbe_media_type_unknown;
459 * ixgbe_start_mac_link_82599 - Setup MAC link settings
460 * @hw: pointer to hardware structure
461 * @autoneg_wait_to_complete: true when waiting for completion is needed
463 * Configures link settings based on values in the ixgbe_hw struct.
464 * Restarts the link. Performs autonegotiation if needed.
466 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
467 bool autoneg_wait_to_complete)
472 s32 status = IXGBE_SUCCESS;
473 bool got_lock = false;
475 DEBUGFUNC("ixgbe_start_mac_link_82599");
478 /* reset_pipeline requires us to hold this lock as it writes to
481 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
482 status = hw->mac.ops.acquire_swfw_sync(hw,
483 IXGBE_GSSR_MAC_CSR_SM);
484 if (status != IXGBE_SUCCESS)
491 ixgbe_reset_pipeline_82599(hw);
494 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
496 /* Only poll for autoneg to complete if specified to do so */
497 if (autoneg_wait_to_complete) {
498 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
499 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
500 IXGBE_AUTOC_LMS_KX4_KX_KR ||
501 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
502 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
503 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
504 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
505 links_reg = 0; /* Just in case Autoneg time = 0 */
506 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
507 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
508 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
512 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
513 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
514 DEBUGOUT("Autoneg did not complete.\n");
519 /* Add delay to filter out noises during initial link setup */
527 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
528 * @hw: pointer to hardware structure
530 * The base drivers may require better control over SFP+ module
531 * PHY states. This includes selectively shutting down the Tx
532 * laser on the PHY, effectively halting physical link.
534 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
536 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
538 /* Disable tx laser; allow 100us to go dark per spec */
539 esdp_reg |= IXGBE_ESDP_SDP3;
540 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
541 IXGBE_WRITE_FLUSH(hw);
546 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
547 * @hw: pointer to hardware structure
549 * The base drivers may require better control over SFP+ module
550 * PHY states. This includes selectively turning on the Tx
551 * laser on the PHY, effectively starting physical link.
553 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
555 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
557 /* Enable tx laser; allow 100ms to light up */
558 esdp_reg &= ~IXGBE_ESDP_SDP3;
559 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
560 IXGBE_WRITE_FLUSH(hw);
565 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
566 * @hw: pointer to hardware structure
568 * When the driver changes the link speeds that it can support,
569 * it sets autotry_restart to true to indicate that we need to
570 * initiate a new autotry session with the link partner. To do
571 * so, we set the speed then disable and re-enable the tx laser, to
572 * alert the link partner that it also needs to restart autotry on its
573 * end. This is consistent with true clause 37 autoneg, which also
574 * involves a loss of signal.
576 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
578 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
580 if (hw->mac.autotry_restart) {
581 ixgbe_disable_tx_laser_multispeed_fiber(hw);
582 ixgbe_enable_tx_laser_multispeed_fiber(hw);
583 hw->mac.autotry_restart = false;
588 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
589 * @hw: pointer to hardware structure
590 * @speed: new link speed
591 * @autoneg: true if autonegotiation enabled
592 * @autoneg_wait_to_complete: true when waiting for completion is needed
594 * Set the link speed in the AUTOC register and restarts link.
596 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
597 ixgbe_link_speed speed, bool autoneg,
598 bool autoneg_wait_to_complete)
600 s32 status = IXGBE_SUCCESS;
601 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
602 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
604 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
606 bool link_up = false;
609 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
611 /* Mask off requested but non-supported speeds */
612 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);
613 if (status != IXGBE_SUCCESS)
619 * Try each speed one by one, highest priority first. We do this in
620 * software because 10gb fiber doesn't support speed autonegotiation.
622 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
624 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
626 /* If we already have link at this speed, just jump out */
627 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
628 if (status != IXGBE_SUCCESS)
631 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
634 /* Set the module link speed */
635 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
636 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
637 IXGBE_WRITE_FLUSH(hw);
639 /* Allow module to change analog characteristics (1G->10G) */
642 status = ixgbe_setup_mac_link_82599(hw,
643 IXGBE_LINK_SPEED_10GB_FULL,
645 autoneg_wait_to_complete);
646 if (status != IXGBE_SUCCESS)
649 /* Flap the tx laser if it has not already been done */
650 ixgbe_flap_tx_laser(hw);
653 * Wait for the controller to acquire link. Per IEEE 802.3ap,
654 * Section 73.10.2, we may have to wait up to 500ms if KR is
655 * attempted. 82599 uses the same timing for 10g SFI.
657 for (i = 0; i < 5; i++) {
658 /* Wait for the link partner to also set speed */
661 /* If we have link, just jump out */
662 status = ixgbe_check_link(hw, &link_speed,
664 if (status != IXGBE_SUCCESS)
672 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
674 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
675 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
677 /* If we already have link at this speed, just jump out */
678 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
679 if (status != IXGBE_SUCCESS)
682 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
685 /* Set the module link speed */
686 esdp_reg &= ~IXGBE_ESDP_SDP5;
687 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
688 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
689 IXGBE_WRITE_FLUSH(hw);
691 /* Allow module to change analog characteristics (10G->1G) */
694 status = ixgbe_setup_mac_link_82599(hw,
695 IXGBE_LINK_SPEED_1GB_FULL,
697 autoneg_wait_to_complete);
698 if (status != IXGBE_SUCCESS)
701 /* Flap the tx laser if it has not already been done */
702 ixgbe_flap_tx_laser(hw);
704 /* Wait for the link partner to also set speed */
707 /* If we have link, just jump out */
708 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
709 if (status != IXGBE_SUCCESS)
717 * We didn't get link. Configure back to the highest speed we tried,
718 * (if there was more than one). We call ourselves back with just the
719 * single highest speed that the user requested.
722 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
723 highest_link_speed, autoneg, autoneg_wait_to_complete);
726 /* Set autoneg_advertised value based on input link speed */
727 hw->phy.autoneg_advertised = 0;
729 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
730 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
732 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
733 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
739 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
740 * @hw: pointer to hardware structure
741 * @speed: new link speed
742 * @autoneg: true if autonegotiation enabled
743 * @autoneg_wait_to_complete: true when waiting for completion is needed
745 * Implements the Intel SmartSpeed algorithm.
747 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
748 ixgbe_link_speed speed, bool autoneg,
749 bool autoneg_wait_to_complete)
751 s32 status = IXGBE_SUCCESS;
752 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
754 bool link_up = false;
755 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
757 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
759 /* Set autoneg_advertised value based on input link speed */
760 hw->phy.autoneg_advertised = 0;
762 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
763 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
765 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
766 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
768 if (speed & IXGBE_LINK_SPEED_100_FULL)
769 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
772 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
773 * autoneg advertisement if link is unable to be established at the
774 * highest negotiated rate. This can sometimes happen due to integrity
775 * issues with the physical media connection.
778 /* First, try to get link with full advertisement */
779 hw->phy.smart_speed_active = false;
780 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
781 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
782 autoneg_wait_to_complete);
783 if (status != IXGBE_SUCCESS)
787 * Wait for the controller to acquire link. Per IEEE 802.3ap,
788 * Section 73.10.2, we may have to wait up to 500ms if KR is
789 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
790 * Table 9 in the AN MAS.
792 for (i = 0; i < 5; i++) {
795 /* If we have link, just jump out */
796 status = ixgbe_check_link(hw, &link_speed, &link_up,
798 if (status != IXGBE_SUCCESS)
807 * We didn't get link. If we advertised KR plus one of KX4/KX
808 * (or BX4/BX), then disable KR and try again.
810 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
811 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
814 /* Turn SmartSpeed on to disable KR support */
815 hw->phy.smart_speed_active = true;
816 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
817 autoneg_wait_to_complete);
818 if (status != IXGBE_SUCCESS)
822 * Wait for the controller to acquire link. 600ms will allow for
823 * the AN link_fail_inhibit_timer as well for multiple cycles of
824 * parallel detect, both 10g and 1g. This allows for the maximum
825 * connect attempts as defined in the AN MAS table 73-7.
827 for (i = 0; i < 6; i++) {
830 /* If we have link, just jump out */
831 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
832 if (status != IXGBE_SUCCESS)
839 /* We didn't get link. Turn SmartSpeed back off. */
840 hw->phy.smart_speed_active = false;
841 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
842 autoneg_wait_to_complete);
845 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
846 DEBUGOUT("Smartspeed has downgraded the link speed "
847 "from the maximum advertised\n");
852 * ixgbe_setup_mac_link_82599 - Set MAC link speed
853 * @hw: pointer to hardware structure
854 * @speed: new link speed
855 * @autoneg: true if autonegotiation enabled
856 * @autoneg_wait_to_complete: true when waiting for completion is needed
858 * Set the link speed in the AUTOC register and restarts link.
860 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
861 ixgbe_link_speed speed, bool autoneg,
862 bool autoneg_wait_to_complete)
864 s32 status = IXGBE_SUCCESS;
865 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
866 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
867 u32 start_autoc = autoc;
869 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
870 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
871 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
874 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
875 bool got_lock = false;
877 DEBUGFUNC("ixgbe_setup_mac_link_82599");
879 /* Check to see if speed passed in is supported. */
880 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
884 speed &= link_capabilities;
886 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
887 status = IXGBE_ERR_LINK_SETUP;
891 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
892 if (hw->mac.orig_link_settings_stored)
893 orig_autoc = hw->mac.orig_autoc;
897 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
898 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
899 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
900 /* Set KX4/KX/KR support according to speed requested */
901 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
902 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
903 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
904 autoc |= IXGBE_AUTOC_KX4_SUPP;
905 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
906 (hw->phy.smart_speed_active == false))
907 autoc |= IXGBE_AUTOC_KR_SUPP;
909 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
910 autoc |= IXGBE_AUTOC_KX_SUPP;
911 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
912 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
913 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
914 /* Switch from 1G SFI to 10G SFI if requested */
915 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
916 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
917 autoc &= ~IXGBE_AUTOC_LMS_MASK;
918 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
920 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
921 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
922 /* Switch from 10G SFI to 1G SFI if requested */
923 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
924 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
925 autoc &= ~IXGBE_AUTOC_LMS_MASK;
927 autoc |= IXGBE_AUTOC_LMS_1G_AN;
929 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
933 if (autoc != start_autoc) {
934 /* Need SW/FW semaphore around AUTOC writes if LESM is on,
935 * likewise reset_pipeline requires us to hold this lock as
936 * it also writes to AUTOC.
938 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
939 status = hw->mac.ops.acquire_swfw_sync(hw,
940 IXGBE_GSSR_MAC_CSR_SM);
941 if (status != IXGBE_SUCCESS) {
942 status = IXGBE_ERR_SWFW_SYNC;
950 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
951 ixgbe_reset_pipeline_82599(hw);
954 hw->mac.ops.release_swfw_sync(hw,
955 IXGBE_GSSR_MAC_CSR_SM);
959 /* Only poll for autoneg to complete if specified to do so */
960 if (autoneg_wait_to_complete) {
961 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
962 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
963 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
964 links_reg = 0; /*Just in case Autoneg time=0*/
965 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
967 IXGBE_READ_REG(hw, IXGBE_LINKS);
968 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
972 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
974 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
975 DEBUGOUT("Autoneg did not complete.\n");
980 /* Add delay to filter out noises during initial link setup */
989 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
990 * @hw: pointer to hardware structure
991 * @speed: new link speed
992 * @autoneg: true if autonegotiation enabled
993 * @autoneg_wait_to_complete: true if waiting is needed to complete
995 * Restarts link on PHY and MAC based on settings passed in.
997 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
998 ixgbe_link_speed speed,
1000 bool autoneg_wait_to_complete)
1004 DEBUGFUNC("ixgbe_setup_copper_link_82599");
1006 /* Setup the PHY according to input speed */
1007 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
1008 autoneg_wait_to_complete);
1010 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1016 * ixgbe_reset_hw_82599 - Perform hardware reset
1017 * @hw: pointer to hardware structure
1019 * Resets the hardware by resetting the transmit and receive units, masks
1020 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1023 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1025 ixgbe_link_speed link_speed;
1027 u32 ctrl, i, autoc, autoc2;
1028 bool link_up = false;
1030 DEBUGFUNC("ixgbe_reset_hw_82599");
1032 /* Call adapter stop to disable tx/rx and clear interrupts */
1033 status = hw->mac.ops.stop_adapter(hw);
1034 if (status != IXGBE_SUCCESS)
1037 /* flush pending Tx transactions */
1038 ixgbe_clear_tx_pending(hw);
1040 /* PHY ops must be identified and initialized prior to reset */
1042 /* Identify PHY and related function pointers */
1043 status = hw->phy.ops.init(hw);
1045 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1048 /* Setup SFP module if there is one present. */
1049 if (hw->phy.sfp_setup_needed) {
1050 status = hw->mac.ops.setup_sfp(hw);
1051 hw->phy.sfp_setup_needed = false;
1054 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1058 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1059 hw->phy.ops.reset(hw);
1063 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1064 * If link reset is used when link is up, it might reset the PHY when
1065 * mng is using it. If link is down or the flag to force full link
1066 * reset is set, then perform link reset.
1068 ctrl = IXGBE_CTRL_LNK_RST;
1069 if (!hw->force_full_reset) {
1070 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1072 ctrl = IXGBE_CTRL_RST;
1075 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1076 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1077 IXGBE_WRITE_FLUSH(hw);
1079 /* Poll for reset bit to self-clear indicating reset is complete */
1080 for (i = 0; i < 10; i++) {
1082 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1083 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1087 if (ctrl & IXGBE_CTRL_RST_MASK) {
1088 status = IXGBE_ERR_RESET_FAILED;
1089 DEBUGOUT("Reset polling failed to complete.\n");
1095 * Double resets are required for recovery from certain error
1096 * conditions. Between resets, it is necessary to stall to allow time
1097 * for any pending HW events to complete.
1099 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1100 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1105 * Store the original AUTOC/AUTOC2 values if they have not been
1106 * stored off yet. Otherwise restore the stored original
1107 * values since the reset operation sets back to defaults.
1109 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1110 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1112 /* Enable link if disabled in NVM */
1113 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1114 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1115 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1116 IXGBE_WRITE_FLUSH(hw);
1119 if (hw->mac.orig_link_settings_stored == false) {
1120 hw->mac.orig_autoc = autoc;
1121 hw->mac.orig_autoc2 = autoc2;
1122 hw->mac.orig_link_settings_stored = true;
1124 if (autoc != hw->mac.orig_autoc) {
1125 /* Need SW/FW semaphore around AUTOC writes if LESM is
1126 * on, likewise reset_pipeline requires us to hold
1127 * this lock as it also writes to AUTOC.
1129 bool got_lock = false;
1130 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1131 status = hw->mac.ops.acquire_swfw_sync(hw,
1132 IXGBE_GSSR_MAC_CSR_SM);
1133 if (status != IXGBE_SUCCESS) {
1134 status = IXGBE_ERR_SWFW_SYNC;
1141 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
1142 ixgbe_reset_pipeline_82599(hw);
1145 hw->mac.ops.release_swfw_sync(hw,
1146 IXGBE_GSSR_MAC_CSR_SM);
1149 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1150 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1151 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1152 autoc2 |= (hw->mac.orig_autoc2 &
1153 IXGBE_AUTOC2_UPPER_MASK);
1154 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1158 /* Store the permanent mac address */
1159 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1162 * Store MAC address from RAR0, clear receive address registers, and
1163 * clear the multicast table. Also reset num_rar_entries to 128,
1164 * since we modify this value when programming the SAN MAC address.
1166 hw->mac.num_rar_entries = 128;
1167 hw->mac.ops.init_rx_addrs(hw);
1169 /* Store the permanent SAN mac address */
1170 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1172 /* Add the SAN MAC address to the RAR only if it's a valid address */
1173 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1174 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1175 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1177 /* Save the SAN MAC RAR index */
1178 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1180 /* Reserve the last RAR for the SAN MAC address */
1181 hw->mac.num_rar_entries--;
1184 /* Store the alternative WWNN/WWPN prefix */
1185 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1186 &hw->mac.wwpn_prefix);
1193 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1194 * @hw: pointer to hardware structure
1196 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1199 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1200 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1202 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1205 * Before starting reinitialization process,
1206 * FDIRCMD.CMD must be zero.
1208 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1209 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1210 IXGBE_FDIRCMD_CMD_MASK))
1214 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1215 DEBUGOUT("Flow Director previous command isn't complete, "
1216 "aborting table re-initialization.\n");
1217 return IXGBE_ERR_FDIR_REINIT_FAILED;
1220 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1221 IXGBE_WRITE_FLUSH(hw);
1223 * 82599 adapters flow director init flow cannot be restarted,
1224 * Workaround 82599 silicon errata by performing the following steps
1225 * before re-writing the FDIRCTRL control register with the same value.
1226 * - write 1 to bit 8 of FDIRCMD register &
1227 * - write 0 to bit 8 of FDIRCMD register
1229 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1230 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1231 IXGBE_FDIRCMD_CLEARHT));
1232 IXGBE_WRITE_FLUSH(hw);
1233 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1234 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1235 ~IXGBE_FDIRCMD_CLEARHT));
1236 IXGBE_WRITE_FLUSH(hw);
1238 * Clear FDIR Hash register to clear any leftover hashes
1239 * waiting to be programmed.
1241 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1242 IXGBE_WRITE_FLUSH(hw);
1244 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1245 IXGBE_WRITE_FLUSH(hw);
1247 /* Poll init-done after we write FDIRCTRL register */
1248 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1249 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1250 IXGBE_FDIRCTRL_INIT_DONE)
1254 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1255 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1256 return IXGBE_ERR_FDIR_REINIT_FAILED;
1259 /* Clear FDIR statistics registers (read to clear) */
1260 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1261 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1262 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1263 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1264 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1266 return IXGBE_SUCCESS;
1270 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1271 * @hw: pointer to hardware structure
1272 * @fdirctrl: value to write to flow director control register
1274 STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1278 DEBUGFUNC("ixgbe_fdir_enable_82599");
1280 /* Prime the keys for hashing */
1281 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1282 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1285 * Poll init-done after we write the register. Estimated times:
1286 * 10G: PBALLOC = 11b, timing is 60us
1287 * 1G: PBALLOC = 11b, timing is 600us
1288 * 100M: PBALLOC = 11b, timing is 6ms
1290 * Multiple these timings by 4 if under full Rx load
1292 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1293 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1294 * this might not finish in our poll time, but we can live with that
1297 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1298 IXGBE_WRITE_FLUSH(hw);
1299 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1300 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1301 IXGBE_FDIRCTRL_INIT_DONE)
1306 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1307 DEBUGOUT("Flow Director poll time exceeded!\n");
1311 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1312 * @hw: pointer to hardware structure
1313 * @fdirctrl: value to write to flow director control register, initially
1314 * contains just the value of the Rx packet buffer allocation
1316 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1318 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1321 * Continue setup of fdirctrl register bits:
1322 * Move the flexible bytes to use the ethertype - shift 6 words
1323 * Set the maximum length per hash bucket to 0xA filters
1324 * Send interrupt when 64 filters are left
1326 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1327 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1328 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1330 /* write hashes and fdirctrl register, poll for completion */
1331 ixgbe_fdir_enable_82599(hw, fdirctrl);
1333 return IXGBE_SUCCESS;
1337 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1338 * @hw: pointer to hardware structure
1339 * @fdirctrl: value to write to flow director control register, initially
1340 * contains just the value of the Rx packet buffer allocation
1342 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1344 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1347 * Continue setup of fdirctrl register bits:
1348 * Turn perfect match filtering on
1349 * Report hash in RSS field of Rx wb descriptor
1350 * Initialize the drop queue
1351 * Move the flexible bytes to use the ethertype - shift 6 words
1352 * Set the maximum length per hash bucket to 0xA filters
1353 * Send interrupt when 64 (0x4 * 16) filters are left
1355 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1356 IXGBE_FDIRCTRL_REPORT_STATUS |
1357 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1358 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1359 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1360 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1362 /* write hashes and fdirctrl register, poll for completion */
1363 ixgbe_fdir_enable_82599(hw, fdirctrl);
1365 return IXGBE_SUCCESS;
1369 * These defines allow us to quickly generate all of the necessary instructions
1370 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1371 * for values 0 through 15
1373 #define IXGBE_ATR_COMMON_HASH_KEY \
1374 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1375 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1378 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1379 common_hash ^= lo_hash_dword >> n; \
1380 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1381 bucket_hash ^= lo_hash_dword >> n; \
1382 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1383 sig_hash ^= lo_hash_dword << (16 - n); \
1384 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1385 common_hash ^= hi_hash_dword >> n; \
1386 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1387 bucket_hash ^= hi_hash_dword >> n; \
1388 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1389 sig_hash ^= hi_hash_dword << (16 - n); \
1393 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1394 * @stream: input bitstream to compute the hash on
1396 * This function is almost identical to the function above but contains
1397 * several optomizations such as unwinding all of the loops, letting the
1398 * compiler work out all of the conditional ifs since the keys are static
1399 * defines, and computing two keys at once since the hashed dword stream
1400 * will be the same for both keys.
1402 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1403 union ixgbe_atr_hash_dword common)
1405 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1406 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1408 /* record the flow_vm_vlan bits as they are a key part to the hash */
1409 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1411 /* generate common hash dword */
1412 hi_hash_dword = IXGBE_NTOHL(common.dword);
1414 /* low dword is word swapped version of common */
1415 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1417 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1418 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1420 /* Process bits 0 and 16 */
1421 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1424 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1425 * delay this because bit 0 of the stream should not be processed
1426 * so we do not add the vlan until after bit 0 was processed
1428 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1430 /* Process remaining 30 bit of the key */
1431 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1432 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1433 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1434 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1435 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1436 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1437 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1438 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1439 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1440 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1441 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1442 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1443 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1444 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1445 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1447 /* combine common_hash result with signature and bucket hashes */
1448 bucket_hash ^= common_hash;
1449 bucket_hash &= IXGBE_ATR_HASH_MASK;
1451 sig_hash ^= common_hash << 16;
1452 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1454 /* return completed signature hash */
1455 return sig_hash ^ bucket_hash;
1459 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1460 * @hw: pointer to hardware structure
1461 * @input: unique input dword
1462 * @common: compressed common input dword
1463 * @queue: queue index to direct traffic to
1465 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1466 union ixgbe_atr_hash_dword input,
1467 union ixgbe_atr_hash_dword common,
1473 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1476 * Get the flow_type in order to program FDIRCMD properly
1477 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1479 switch (input.formatted.flow_type) {
1480 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1481 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1482 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1483 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1484 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1485 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1488 DEBUGOUT(" Error on flow type input\n");
1489 return IXGBE_ERR_CONFIG;
1492 /* configure FDIRCMD register */
1493 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1494 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1495 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1496 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1499 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1500 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1502 fdirhashcmd = (u64)fdircmd << 32;
1503 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1504 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1506 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1508 return IXGBE_SUCCESS;
1511 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1514 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1515 bucket_hash ^= lo_hash_dword >> n; \
1516 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1517 bucket_hash ^= hi_hash_dword >> n; \
1521 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1522 * @atr_input: input bitstream to compute the hash on
1523 * @input_mask: mask for the input bitstream
1525 * This function serves two main purposes. First it applys the input_mask
1526 * to the atr_input resulting in a cleaned up atr_input data stream.
1527 * Secondly it computes the hash and stores it in the bkt_hash field at
1528 * the end of the input byte stream. This way it will be available for
1529 * future use without needing to recompute the hash.
1531 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1532 union ixgbe_atr_input *input_mask)
1535 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1536 u32 bucket_hash = 0;
1538 /* Apply masks to input data */
1539 input->dword_stream[0] &= input_mask->dword_stream[0];
1540 input->dword_stream[1] &= input_mask->dword_stream[1];
1541 input->dword_stream[2] &= input_mask->dword_stream[2];
1542 input->dword_stream[3] &= input_mask->dword_stream[3];
1543 input->dword_stream[4] &= input_mask->dword_stream[4];
1544 input->dword_stream[5] &= input_mask->dword_stream[5];
1545 input->dword_stream[6] &= input_mask->dword_stream[6];
1546 input->dword_stream[7] &= input_mask->dword_stream[7];
1547 input->dword_stream[8] &= input_mask->dword_stream[8];
1548 input->dword_stream[9] &= input_mask->dword_stream[9];
1549 input->dword_stream[10] &= input_mask->dword_stream[10];
1551 /* record the flow_vm_vlan bits as they are a key part to the hash */
1552 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1554 /* generate common hash dword */
1555 hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
1556 input->dword_stream[2] ^
1557 input->dword_stream[3] ^
1558 input->dword_stream[4] ^
1559 input->dword_stream[5] ^
1560 input->dword_stream[6] ^
1561 input->dword_stream[7] ^
1562 input->dword_stream[8] ^
1563 input->dword_stream[9] ^
1564 input->dword_stream[10]);
1566 /* low dword is word swapped version of common */
1567 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1569 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1570 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1572 /* Process bits 0 and 16 */
1573 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1576 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1577 * delay this because bit 0 of the stream should not be processed
1578 * so we do not add the vlan until after bit 0 was processed
1580 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1582 /* Process remaining 30 bit of the key */
1583 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1584 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1585 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1586 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1587 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1588 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1589 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1590 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1591 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1592 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1593 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1594 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1595 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1596 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1597 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1600 * Limit hash to 13 bits since max bucket count is 8K.
1601 * Store result at the end of the input stream.
1603 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1607 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1608 * @input_mask: mask to be bit swapped
1610 * The source and destination port masks for flow director are bit swapped
1611 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1612 * generate a correctly swapped value we need to bit swap the mask and that
1613 * is what is accomplished by this function.
1615 STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1617 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1618 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1619 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1620 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1621 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1622 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1623 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1627 * These two macros are meant to address the fact that we have registers
1628 * that are either all or in part big-endian. As a result on big-endian
1629 * systems we will end up byte swapping the value to little-endian before
1630 * it is byte swapped again and written to the hardware in the original
1631 * big-endian format.
1633 #define IXGBE_STORE_AS_BE32(_value) \
1634 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1635 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1637 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1638 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1640 #define IXGBE_STORE_AS_BE16(_value) \
1641 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1643 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1644 union ixgbe_atr_input *input_mask)
1646 /* mask IPv6 since it is currently not supported */
1647 u32 fdirm = IXGBE_FDIRM_DIPv6;
1650 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1653 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1654 * are zero, then assume a full mask for that field. Also assume that
1655 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1656 * cannot be masked out in this implementation.
1658 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1662 /* verify bucket hash is cleared on hash generation */
1663 if (input_mask->formatted.bkt_hash)
1664 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1666 /* Program FDIRM and verify partial masks */
1667 switch (input_mask->formatted.vm_pool & 0x7F) {
1669 fdirm |= IXGBE_FDIRM_POOL;
1673 DEBUGOUT(" Error on vm pool mask\n");
1674 return IXGBE_ERR_CONFIG;
1677 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1679 fdirm |= IXGBE_FDIRM_L4P;
1680 if (input_mask->formatted.dst_port ||
1681 input_mask->formatted.src_port) {
1682 DEBUGOUT(" Error on src/dst port mask\n");
1683 return IXGBE_ERR_CONFIG;
1685 case IXGBE_ATR_L4TYPE_MASK:
1688 DEBUGOUT(" Error on flow type mask\n");
1689 return IXGBE_ERR_CONFIG;
1692 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1694 /* mask VLAN ID, fall through to mask VLAN priority */
1695 fdirm |= IXGBE_FDIRM_VLANID;
1697 /* mask VLAN priority */
1698 fdirm |= IXGBE_FDIRM_VLANP;
1701 /* mask VLAN ID only, fall through */
1702 fdirm |= IXGBE_FDIRM_VLANID;
1704 /* no VLAN fields masked */
1707 DEBUGOUT(" Error on VLAN mask\n");
1708 return IXGBE_ERR_CONFIG;
1711 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1713 /* Mask Flex Bytes, fall through */
1714 fdirm |= IXGBE_FDIRM_FLEX;
1718 DEBUGOUT(" Error on flexible byte mask\n");
1719 return IXGBE_ERR_CONFIG;
1722 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1723 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1725 /* store the TCP/UDP port masks, bit reversed from port layout */
1726 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1728 /* write both the same so that UDP and TCP use the same mask */
1729 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1730 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1732 /* store source and destination IP masks (big-enian) */
1733 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1734 ~input_mask->formatted.src_ip[0]);
1735 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1736 ~input_mask->formatted.dst_ip[0]);
1738 return IXGBE_SUCCESS;
1741 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1742 union ixgbe_atr_input *input,
1743 u16 soft_id, u8 queue)
1745 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1747 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1749 /* currently IPv6 is not supported, must be programmed with 0 */
1750 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1751 input->formatted.src_ip[0]);
1752 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1753 input->formatted.src_ip[1]);
1754 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1755 input->formatted.src_ip[2]);
1757 /* record the source address (big-endian) */
1758 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1760 /* record the first 32 bits of the destination address (big-endian) */
1761 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1763 /* record source and destination port (little-endian)*/
1764 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1765 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1766 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1767 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1769 /* record vlan (little-endian) and flex_bytes(big-endian) */
1770 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1771 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1772 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1773 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1775 /* configure FDIRHASH register */
1776 fdirhash = input->formatted.bkt_hash;
1777 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1778 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1781 * flush all previous writes to make certain registers are
1782 * programmed prior to issuing the command
1784 IXGBE_WRITE_FLUSH(hw);
1786 /* configure FDIRCMD register */
1787 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1788 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1789 if (queue == IXGBE_FDIR_DROP_QUEUE)
1790 fdircmd |= IXGBE_FDIRCMD_DROP;
1791 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1792 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1793 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1795 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1797 return IXGBE_SUCCESS;
1800 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1801 union ixgbe_atr_input *input,
1807 s32 err = IXGBE_SUCCESS;
1809 /* configure FDIRHASH register */
1810 fdirhash = input->formatted.bkt_hash;
1811 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1812 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1814 /* flush hash to HW */
1815 IXGBE_WRITE_FLUSH(hw);
1817 /* Query if filter is present */
1818 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1820 for (retry_count = 10; retry_count; retry_count--) {
1821 /* allow 10us for query to process */
1823 /* verify query completed successfully */
1824 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1825 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1830 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1832 /* if filter exists in hardware then remove it */
1833 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1834 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1835 IXGBE_WRITE_FLUSH(hw);
1836 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1837 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1844 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1845 * @hw: pointer to hardware structure
1846 * @input: input bitstream
1847 * @input_mask: mask for the input bitstream
1848 * @soft_id: software index for the filters
1849 * @queue: queue index to direct traffic to
1851 * Note that the caller to this function must lock before calling, since the
1852 * hardware writes must be protected from one another.
1854 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1855 union ixgbe_atr_input *input,
1856 union ixgbe_atr_input *input_mask,
1857 u16 soft_id, u8 queue)
1859 s32 err = IXGBE_ERR_CONFIG;
1861 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1864 * Check flow_type formatting, and bail out before we touch the hardware
1865 * if there's a configuration issue
1867 switch (input->formatted.flow_type) {
1868 case IXGBE_ATR_FLOW_TYPE_IPV4:
1869 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1870 if (input->formatted.dst_port || input->formatted.src_port) {
1871 DEBUGOUT(" Error on src/dst port\n");
1872 return IXGBE_ERR_CONFIG;
1875 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1876 if (input->formatted.dst_port || input->formatted.src_port) {
1877 DEBUGOUT(" Error on src/dst port\n");
1878 return IXGBE_ERR_CONFIG;
1880 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1881 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1882 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
1883 IXGBE_ATR_L4TYPE_MASK;
1886 DEBUGOUT(" Error on flow type input\n");
1890 /* program input mask into the HW */
1891 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
1895 /* apply mask and compute/store hash */
1896 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
1898 /* program filters to filter memory */
1899 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
1904 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1905 * @hw: pointer to hardware structure
1906 * @reg: analog register to read
1909 * Performs read operation to Omer analog register specified.
1911 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1915 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
1917 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1919 IXGBE_WRITE_FLUSH(hw);
1921 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1922 *val = (u8)core_ctl;
1924 return IXGBE_SUCCESS;
1928 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1929 * @hw: pointer to hardware structure
1930 * @reg: atlas register to write
1931 * @val: value to write
1933 * Performs write operation to Omer analog register specified.
1935 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1939 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
1941 core_ctl = (reg << 8) | val;
1942 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1943 IXGBE_WRITE_FLUSH(hw);
1946 return IXGBE_SUCCESS;
1950 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1951 * @hw: pointer to hardware structure
1953 * Starts the hardware using the generic start_hw function
1954 * and the generation start_hw function.
1955 * Then performs revision-specific operations, if any.
1957 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1959 s32 ret_val = IXGBE_SUCCESS;
1961 DEBUGFUNC("ixgbe_start_hw_82599");
1963 ret_val = ixgbe_start_hw_generic(hw);
1964 if (ret_val != IXGBE_SUCCESS)
1967 ret_val = ixgbe_start_hw_gen2(hw);
1968 if (ret_val != IXGBE_SUCCESS)
1971 /* We need to run link autotry after the driver loads */
1972 hw->mac.autotry_restart = true;
1974 if (ret_val == IXGBE_SUCCESS)
1975 ret_val = ixgbe_verify_fw_version_82599(hw);
1981 * ixgbe_identify_phy_82599 - Get physical layer module
1982 * @hw: pointer to hardware structure
1984 * Determines the physical layer module found on the current adapter.
1985 * If PHY already detected, maintains current PHY type in hw struct,
1986 * otherwise executes the PHY detection routine.
1988 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1990 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1992 DEBUGFUNC("ixgbe_identify_phy_82599");
1994 /* Detect PHY if not unknown - returns success if already detected. */
1995 status = ixgbe_identify_phy_generic(hw);
1996 if (status != IXGBE_SUCCESS) {
1997 /* 82599 10GBASE-T requires an external PHY */
1998 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2001 status = ixgbe_identify_module_generic(hw);
2004 /* Set PHY type none if no PHY detected */
2005 if (hw->phy.type == ixgbe_phy_unknown) {
2006 hw->phy.type = ixgbe_phy_none;
2007 status = IXGBE_SUCCESS;
2010 /* Return error if SFP module has been detected but is not supported */
2011 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2012 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
2019 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2020 * @hw: pointer to hardware structure
2022 * Determines physical layer capabilities of the current configuration.
2024 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2026 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2027 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2028 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2029 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2030 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2031 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2032 u16 ext_ability = 0;
2033 u8 comp_codes_10g = 0;
2034 u8 comp_codes_1g = 0;
2036 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2038 hw->phy.ops.identify(hw);
2040 switch (hw->phy.type) {
2042 case ixgbe_phy_cu_unknown:
2043 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2044 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2045 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2046 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2047 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2048 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2049 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
2050 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2056 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2057 case IXGBE_AUTOC_LMS_1G_AN:
2058 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2059 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2060 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2061 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2064 /* SFI mode so read SFP module */
2067 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2068 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2069 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2070 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2071 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2072 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2073 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2076 case IXGBE_AUTOC_LMS_10G_SERIAL:
2077 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2078 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2080 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2083 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2084 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2085 if (autoc & IXGBE_AUTOC_KX_SUPP)
2086 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2087 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2088 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2089 if (autoc & IXGBE_AUTOC_KR_SUPP)
2090 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2099 /* SFP check must be done last since DA modules are sometimes used to
2100 * test KR mode - we need to id KR mode correctly before SFP module.
2101 * Call identify_sfp because the pluggable module may have changed */
2102 hw->phy.ops.identify_sfp(hw);
2103 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2106 switch (hw->phy.type) {
2107 case ixgbe_phy_sfp_passive_tyco:
2108 case ixgbe_phy_sfp_passive_unknown:
2109 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2111 case ixgbe_phy_sfp_ftl_active:
2112 case ixgbe_phy_sfp_active_unknown:
2113 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2115 case ixgbe_phy_sfp_avago:
2116 case ixgbe_phy_sfp_ftl:
2117 case ixgbe_phy_sfp_intel:
2118 case ixgbe_phy_sfp_unknown:
2119 hw->phy.ops.read_i2c_eeprom(hw,
2120 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2121 hw->phy.ops.read_i2c_eeprom(hw,
2122 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2123 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2124 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2125 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2126 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2127 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2128 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2129 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
2130 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
2137 return physical_layer;
2141 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2142 * @hw: pointer to hardware structure
2143 * @regval: register value to write to RXCTRL
2145 * Enables the Rx DMA unit for 82599
2147 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2150 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2153 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2154 * If traffic is incoming before we enable the Rx unit, it could hang
2155 * the Rx DMA unit. Therefore, make sure the security engine is
2156 * completely disabled prior to enabling the Rx unit.
2159 hw->mac.ops.disable_sec_rx_path(hw);
2161 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2163 hw->mac.ops.enable_sec_rx_path(hw);
2165 return IXGBE_SUCCESS;
2169 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2170 * @hw: pointer to hardware structure
2172 * Verifies that installed the firmware version is 0.6 or higher
2173 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2175 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2176 * if the FW version is not supported.
2178 s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2180 s32 status = IXGBE_ERR_EEPROM_VERSION;
2181 u16 fw_offset, fw_ptp_cfg_offset;
2184 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2186 /* firmware check is only necessary for SFI devices */
2187 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2188 status = IXGBE_SUCCESS;
2189 goto fw_version_out;
2192 /* get the offset to the Firmware Module block */
2193 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2195 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2196 goto fw_version_out;
2198 /* get the offset to the Pass Through Patch Configuration block */
2199 hw->eeprom.ops.read(hw, (fw_offset +
2200 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2201 &fw_ptp_cfg_offset);
2203 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2204 goto fw_version_out;
2206 /* get the firmware version */
2207 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2208 IXGBE_FW_PATCH_VERSION_4), &fw_version);
2210 if (fw_version > 0x5)
2211 status = IXGBE_SUCCESS;
2218 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2219 * @hw: pointer to hardware structure
2221 * Returns true if the LESM FW module is present and enabled. Otherwise
2222 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2224 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2226 bool lesm_enabled = false;
2227 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2230 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2232 /* get the offset to the Firmware Module block */
2233 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2235 if ((status != IXGBE_SUCCESS) ||
2236 (fw_offset == 0) || (fw_offset == 0xFFFF))
2239 /* get the offset to the LESM Parameters block */
2240 status = hw->eeprom.ops.read(hw, (fw_offset +
2241 IXGBE_FW_LESM_PARAMETERS_PTR),
2242 &fw_lesm_param_offset);
2244 if ((status != IXGBE_SUCCESS) ||
2245 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2248 /* get the lesm state word */
2249 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2250 IXGBE_FW_LESM_STATE_1),
2253 if ((status == IXGBE_SUCCESS) &&
2254 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2255 lesm_enabled = true;
2258 return lesm_enabled;
2262 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2263 * fastest available method
2265 * @hw: pointer to hardware structure
2266 * @offset: offset of word in EEPROM to read
2267 * @words: number of words
2268 * @data: word(s) read from the EEPROM
2270 * Retrieves 16 bit word(s) read from EEPROM
2272 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2273 u16 words, u16 *data)
2275 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2276 s32 ret_val = IXGBE_ERR_CONFIG;
2278 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2281 * If EEPROM is detected and can be addressed using 14 bits,
2282 * use EERD otherwise use bit bang
2284 if ((eeprom->type == ixgbe_eeprom_spi) &&
2285 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2286 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2289 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2297 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2298 * fastest available method
2300 * @hw: pointer to hardware structure
2301 * @offset: offset of word in the EEPROM to read
2302 * @data: word read from the EEPROM
2304 * Reads a 16 bit word from the EEPROM
2306 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2307 u16 offset, u16 *data)
2309 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2310 s32 ret_val = IXGBE_ERR_CONFIG;
2312 DEBUGFUNC("ixgbe_read_eeprom_82599");
2315 * If EEPROM is detected and can be addressed using 14 bits,
2316 * use EERD otherwise use bit bang
2318 if ((eeprom->type == ixgbe_eeprom_spi) &&
2319 (offset <= IXGBE_EERD_MAX_ADDR))
2320 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2322 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2328 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2330 * @hw: pointer to hardware structure
2332 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2333 * full pipeline reset
2335 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2337 s32 i, autoc_reg, autoc2_reg, ret_val;
2340 /* Enable link if disabled in NVM */
2341 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2342 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2343 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2344 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2345 IXGBE_WRITE_FLUSH(hw);
2348 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2349 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2350 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2351 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
2352 /* Wait for AN to leave state 0 */
2353 for (i = 0; i < 10; i++) {
2355 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2356 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2360 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2361 DEBUGOUT("auto negotiation not completed\n");
2362 ret_val = IXGBE_ERR_RESET_FAILED;
2363 goto reset_pipeline_out;
2366 ret_val = IXGBE_SUCCESS;
2369 /* Write AUTOC register with original LMS field and Restart_AN */
2370 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2371 IXGBE_WRITE_FLUSH(hw);