1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82599.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
39 #ident "$Id: ixgbe_82599.c,v 1.334 2013/12/04 22:34:00 jtkirshe Exp $"
41 #define IXGBE_82599_MAX_TX_QUEUES 128
42 #define IXGBE_82599_MAX_RX_QUEUES 128
43 #define IXGBE_82599_RAR_ENTRIES 128
44 #define IXGBE_82599_MC_TBL_SIZE 128
45 #define IXGBE_82599_VFT_TBL_SIZE 128
46 #define IXGBE_82599_RX_PB_SIZE 512
48 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
49 ixgbe_link_speed speed,
50 bool autoneg_wait_to_complete);
51 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
53 u16 offset, u16 *data);
54 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
57 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
59 u32 fwsm, manc, factps;
61 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
62 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
65 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
66 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
69 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
70 if (factps & IXGBE_FACTPS_MNGCG)
76 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
78 struct ixgbe_mac_info *mac = &hw->mac;
80 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
83 * enable the laser control functions for SFP+ fiber
86 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
87 !ixgbe_mng_enabled(hw)) {
88 mac->ops.disable_tx_laser =
89 &ixgbe_disable_tx_laser_multispeed_fiber;
90 mac->ops.enable_tx_laser =
91 &ixgbe_enable_tx_laser_multispeed_fiber;
92 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
95 mac->ops.disable_tx_laser = NULL;
96 mac->ops.enable_tx_laser = NULL;
97 mac->ops.flap_tx_laser = NULL;
100 if (hw->phy.multispeed_fiber) {
101 /* Set up dual speed SFP+ support */
102 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
104 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
105 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
106 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
107 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
108 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
110 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
116 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
117 * @hw: pointer to hardware structure
119 * Initialize any function pointers that were not able to be
120 * set during init_shared_code because the PHY/SFP type was
121 * not known. Perform the SFP init if necessary.
124 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
126 struct ixgbe_mac_info *mac = &hw->mac;
127 struct ixgbe_phy_info *phy = &hw->phy;
128 s32 ret_val = IXGBE_SUCCESS;
130 DEBUGFUNC("ixgbe_init_phy_ops_82599");
132 /* Identify the PHY or SFP module */
133 ret_val = phy->ops.identify(hw);
134 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
135 goto init_phy_ops_out;
137 /* Setup function pointers based on detected SFP module and speeds */
138 ixgbe_init_mac_link_ops_82599(hw);
139 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
140 hw->phy.ops.reset = NULL;
142 /* If copper media, overwrite with copper function pointers */
143 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
144 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
145 mac->ops.get_link_capabilities =
146 &ixgbe_get_copper_link_capabilities_generic;
149 /* Set necessary function pointers based on PHY type */
150 switch (hw->phy.type) {
152 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
153 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
154 phy->ops.get_firmware_version =
155 &ixgbe_get_phy_firmware_version_tnx;
164 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
166 s32 ret_val = IXGBE_SUCCESS;
167 u16 list_offset, data_offset, data_value;
169 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
171 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
172 ixgbe_init_mac_link_ops_82599(hw);
174 hw->phy.ops.reset = NULL;
176 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
178 if (ret_val != IXGBE_SUCCESS)
181 /* PHY config will finish before releasing the semaphore */
182 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
183 IXGBE_GSSR_MAC_CSR_SM);
184 if (ret_val != IXGBE_SUCCESS) {
185 ret_val = IXGBE_ERR_SWFW_SYNC;
189 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
191 while (data_value != 0xffff) {
192 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
193 IXGBE_WRITE_FLUSH(hw);
194 if (hw->eeprom.ops.read(hw, ++data_offset, &data_value))
198 /* Release the semaphore */
199 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
200 /* Delay obtaining semaphore again to allow FW access
201 * prot_autoc_write uses the semaphore too.
203 msec_delay(hw->eeprom.semaphore_delay);
205 /* Restart DSP and set SFI mode */
206 ret_val = hw->mac.ops.prot_autoc_write(hw,
207 hw->mac.orig_autoc | IXGBE_AUTOC_LMS_10G_SERIAL,
211 DEBUGOUT("sfp module setup not complete\n");
212 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
222 /* Release the semaphore */
223 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
224 /* Delay obtaining semaphore again to allow FW access */
225 msec_delay(hw->eeprom.semaphore_delay);
226 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
227 "eeprom read at offset %d failed", data_offset);
228 return IXGBE_ERR_PHY;
232 * prot_autoc_read_82599 - Hides MAC differences needed for AUTOC read
233 * @hw: pointer to hardware structure
234 * @locked: Return the if we locked for this read.
235 * @reg_val: Value we read from AUTOC
237 * For this part (82599) we need to wrap read-modify-writes with a possible
238 * FW/SW lock. It is assumed this lock will be freed with the next
239 * prot_autoc_write_82599().
241 s32 prot_autoc_read_82599(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
246 /* If LESM is on then we need to hold the SW/FW semaphore. */
247 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
248 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
249 IXGBE_GSSR_MAC_CSR_SM);
250 if (ret_val != IXGBE_SUCCESS)
251 return IXGBE_ERR_SWFW_SYNC;
256 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
257 return IXGBE_SUCCESS;
261 * prot_autoc_write_82599 - Hides MAC differences needed for AUTOC write
262 * @hw: pointer to hardware structure
263 * @reg_val: value to write to AUTOC
264 * @locked: bool to indicate whether the SW/FW lock was already taken by
265 * previous proc_autoc_read_82599.
267 * This part (82599) may need to hold the SW/FW lock around all writes to
268 * AUTOC. Likewise after a write we need to do a pipeline reset.
270 s32 prot_autoc_write_82599(struct ixgbe_hw *hw, u32 autoc, bool locked)
272 s32 ret_val = IXGBE_SUCCESS;
274 /* Blocked by MNG FW so bail */
275 if (ixgbe_check_reset_blocked(hw))
278 /* We only need to get the lock if:
279 * - We didn't do it already (in the read part of a read-modify-write)
282 if (!locked && ixgbe_verify_lesm_fw_enabled_82599(hw)) {
283 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
284 IXGBE_GSSR_MAC_CSR_SM);
285 if (ret_val != IXGBE_SUCCESS)
286 return IXGBE_ERR_SWFW_SYNC;
291 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
292 ret_val = ixgbe_reset_pipeline_82599(hw);
295 /* Free the SW/FW semaphore as we either grabbed it here or
296 * already had it when this function was called.
299 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
305 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
306 * @hw: pointer to hardware structure
308 * Initialize the function pointers and assign the MAC type for 82599.
309 * Does not touch the hardware.
312 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
314 struct ixgbe_mac_info *mac = &hw->mac;
315 struct ixgbe_phy_info *phy = &hw->phy;
316 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
319 DEBUGFUNC("ixgbe_init_ops_82599");
321 ixgbe_init_phy_ops_generic(hw);
322 ret_val = ixgbe_init_ops_generic(hw);
325 phy->ops.identify = &ixgbe_identify_phy_82599;
326 phy->ops.init = &ixgbe_init_phy_ops_82599;
329 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
330 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
331 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
332 mac->ops.get_supported_physical_layer =
333 &ixgbe_get_supported_physical_layer_82599;
334 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
335 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
336 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
337 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
338 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
339 mac->ops.start_hw = &ixgbe_start_hw_82599;
340 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
341 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
342 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
343 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
344 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
345 mac->ops.prot_autoc_read = &prot_autoc_read_82599;
346 mac->ops.prot_autoc_write = &prot_autoc_write_82599;
348 /* RAR, Multicast, VLAN */
349 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
350 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
351 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
352 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
353 mac->rar_highwater = 1;
354 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
355 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
356 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
357 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
358 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
359 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
360 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
363 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
364 mac->ops.check_link = &ixgbe_check_mac_link_generic;
365 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
366 ixgbe_init_mac_link_ops_82599(hw);
368 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
369 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
370 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
371 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
372 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
373 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
374 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
376 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
377 IXGBE_FWSM_MODE_MASK) ? true : false;
379 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
382 eeprom->ops.read = &ixgbe_read_eeprom_82599;
383 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
385 /* Manageability interface */
386 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
389 mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
395 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
396 * @hw: pointer to hardware structure
397 * @speed: pointer to link speed
398 * @autoneg: true when autoneg or autotry is enabled
400 * Determines the link capabilities by reading the AUTOC register.
402 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
403 ixgbe_link_speed *speed,
406 s32 status = IXGBE_SUCCESS;
409 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
412 /* Check if 1G SFP module. */
413 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
414 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
415 #ifdef SUPPORT_1000BASE_LX
416 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
417 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
419 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
420 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
421 *speed = IXGBE_LINK_SPEED_1GB_FULL;
427 * Determine link capabilities based on the stored value of AUTOC,
428 * which represents EEPROM defaults. If AUTOC value has not
429 * been stored, use the current register values.
431 if (hw->mac.orig_link_settings_stored)
432 autoc = hw->mac.orig_autoc;
434 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
436 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
437 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
438 *speed = IXGBE_LINK_SPEED_1GB_FULL;
442 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
443 *speed = IXGBE_LINK_SPEED_10GB_FULL;
447 case IXGBE_AUTOC_LMS_1G_AN:
448 *speed = IXGBE_LINK_SPEED_1GB_FULL;
452 case IXGBE_AUTOC_LMS_10G_SERIAL:
453 *speed = IXGBE_LINK_SPEED_10GB_FULL;
457 case IXGBE_AUTOC_LMS_KX4_KX_KR:
458 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
459 *speed = IXGBE_LINK_SPEED_UNKNOWN;
460 if (autoc & IXGBE_AUTOC_KR_SUPP)
461 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
462 if (autoc & IXGBE_AUTOC_KX4_SUPP)
463 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
464 if (autoc & IXGBE_AUTOC_KX_SUPP)
465 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
469 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
470 *speed = IXGBE_LINK_SPEED_100_FULL;
471 if (autoc & IXGBE_AUTOC_KR_SUPP)
472 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
473 if (autoc & IXGBE_AUTOC_KX4_SUPP)
474 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
475 if (autoc & IXGBE_AUTOC_KX_SUPP)
476 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
480 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
481 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
486 status = IXGBE_ERR_LINK_SETUP;
491 if (hw->phy.multispeed_fiber) {
492 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
493 IXGBE_LINK_SPEED_1GB_FULL;
503 * ixgbe_get_media_type_82599 - Get media type
504 * @hw: pointer to hardware structure
506 * Returns the media type (fiber, copper, backplane)
508 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
510 enum ixgbe_media_type media_type;
512 DEBUGFUNC("ixgbe_get_media_type_82599");
514 /* Detect if there is a copper PHY attached. */
515 switch (hw->phy.type) {
516 case ixgbe_phy_cu_unknown:
518 media_type = ixgbe_media_type_copper;
524 switch (hw->device_id) {
525 case IXGBE_DEV_ID_82599_KX4:
526 case IXGBE_DEV_ID_82599_KX4_MEZZ:
527 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
528 case IXGBE_DEV_ID_82599_KR:
529 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
530 case IXGBE_DEV_ID_82599_XAUI_LOM:
531 /* Default device ID is mezzanine card KX/KX4 */
532 media_type = ixgbe_media_type_backplane;
534 case IXGBE_DEV_ID_82599_SFP:
535 case IXGBE_DEV_ID_82599_SFP_FCOE:
536 case IXGBE_DEV_ID_82599_SFP_EM:
537 case IXGBE_DEV_ID_82599_SFP_SF2:
538 case IXGBE_DEV_ID_82599_SFP_SF_QP:
539 case IXGBE_DEV_ID_82599EN_SFP:
540 media_type = ixgbe_media_type_fiber;
542 case IXGBE_DEV_ID_82599_CX4:
543 media_type = ixgbe_media_type_cx4;
545 case IXGBE_DEV_ID_82599_T3_LOM:
546 media_type = ixgbe_media_type_copper;
549 media_type = ixgbe_media_type_unknown;
557 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
558 * @hw: pointer to hardware structure
560 * Disables link during D3 power down sequence.
563 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
565 u32 autoc2_reg, fwsm;
568 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
569 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
571 /* Check to see if MNG FW could be enabled */
572 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
574 if (((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) &&
576 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
577 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
578 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
579 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
584 * ixgbe_start_mac_link_82599 - Setup MAC link settings
585 * @hw: pointer to hardware structure
586 * @autoneg_wait_to_complete: true when waiting for completion is needed
588 * Configures link settings based on values in the ixgbe_hw struct.
589 * Restarts the link. Performs autonegotiation if needed.
591 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
592 bool autoneg_wait_to_complete)
597 s32 status = IXGBE_SUCCESS;
598 bool got_lock = false;
600 DEBUGFUNC("ixgbe_start_mac_link_82599");
603 /* reset_pipeline requires us to hold this lock as it writes to
606 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
607 status = hw->mac.ops.acquire_swfw_sync(hw,
608 IXGBE_GSSR_MAC_CSR_SM);
609 if (status != IXGBE_SUCCESS)
616 ixgbe_reset_pipeline_82599(hw);
619 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
621 /* Only poll for autoneg to complete if specified to do so */
622 if (autoneg_wait_to_complete) {
623 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
624 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
625 IXGBE_AUTOC_LMS_KX4_KX_KR ||
626 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
627 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
628 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
629 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
630 links_reg = 0; /* Just in case Autoneg time = 0 */
631 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
632 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
633 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
637 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
638 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
639 DEBUGOUT("Autoneg did not complete.\n");
644 /* Add delay to filter out noises during initial link setup */
652 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
653 * @hw: pointer to hardware structure
655 * The base drivers may require better control over SFP+ module
656 * PHY states. This includes selectively shutting down the Tx
657 * laser on the PHY, effectively halting physical link.
659 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
661 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
663 /* Blocked by MNG FW so bail */
664 if (ixgbe_check_reset_blocked(hw))
667 /* Disable Tx laser; allow 100us to go dark per spec */
668 esdp_reg |= IXGBE_ESDP_SDP3;
669 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
670 IXGBE_WRITE_FLUSH(hw);
675 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
676 * @hw: pointer to hardware structure
678 * The base drivers may require better control over SFP+ module
679 * PHY states. This includes selectively turning on the Tx
680 * laser on the PHY, effectively starting physical link.
682 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
684 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
686 /* Enable Tx laser; allow 100ms to light up */
687 esdp_reg &= ~IXGBE_ESDP_SDP3;
688 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
689 IXGBE_WRITE_FLUSH(hw);
694 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
695 * @hw: pointer to hardware structure
697 * When the driver changes the link speeds that it can support,
698 * it sets autotry_restart to true to indicate that we need to
699 * initiate a new autotry session with the link partner. To do
700 * so, we set the speed then disable and re-enable the Tx laser, to
701 * alert the link partner that it also needs to restart autotry on its
702 * end. This is consistent with true clause 37 autoneg, which also
703 * involves a loss of signal.
705 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
707 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
709 /* Blocked by MNG FW so bail */
710 if (ixgbe_check_reset_blocked(hw))
713 if (hw->mac.autotry_restart) {
714 ixgbe_disable_tx_laser_multispeed_fiber(hw);
715 ixgbe_enable_tx_laser_multispeed_fiber(hw);
716 hw->mac.autotry_restart = false;
722 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
723 * @hw: pointer to hardware structure
724 * @speed: new link speed
725 * @autoneg_wait_to_complete: true when waiting for completion is needed
727 * Set the link speed in the AUTOC register and restarts link.
729 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
730 ixgbe_link_speed speed,
731 bool autoneg_wait_to_complete)
733 s32 status = IXGBE_SUCCESS;
734 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
735 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
737 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
739 bool autoneg, link_up = false;
741 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
743 /* Mask off requested but non-supported speeds */
744 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
745 if (status != IXGBE_SUCCESS)
751 * Try each speed one by one, highest priority first. We do this in
752 * software because 10gb fiber doesn't support speed autonegotiation.
754 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
756 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
758 /* If we already have link at this speed, just jump out */
759 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
760 if (status != IXGBE_SUCCESS)
763 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
766 /* Set the module link speed */
767 switch (hw->phy.media_type) {
768 case ixgbe_media_type_fiber:
769 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
770 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
771 IXGBE_WRITE_FLUSH(hw);
774 DEBUGOUT("Unexpected media type.\n");
778 /* Allow module to change analog characteristics (1G->10G) */
781 status = ixgbe_setup_mac_link_82599(hw,
782 IXGBE_LINK_SPEED_10GB_FULL,
783 autoneg_wait_to_complete);
784 if (status != IXGBE_SUCCESS)
787 /* Flap the tx laser if it has not already been done */
788 ixgbe_flap_tx_laser(hw);
791 * Wait for the controller to acquire link. Per IEEE 802.3ap,
792 * Section 73.10.2, we may have to wait up to 500ms if KR is
793 * attempted. 82599 uses the same timing for 10g SFI.
795 for (i = 0; i < 5; i++) {
796 /* Wait for the link partner to also set speed */
799 /* If we have link, just jump out */
800 status = ixgbe_check_link(hw, &link_speed,
802 if (status != IXGBE_SUCCESS)
810 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
812 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
813 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
815 /* If we already have link at this speed, just jump out */
816 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
817 if (status != IXGBE_SUCCESS)
820 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
823 /* Set the module link speed */
824 switch (hw->phy.media_type) {
825 case ixgbe_media_type_fiber:
826 esdp_reg &= ~IXGBE_ESDP_SDP5;
827 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
828 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
829 IXGBE_WRITE_FLUSH(hw);
832 DEBUGOUT("Unexpected media type.\n");
836 /* Allow module to change analog characteristics (10G->1G) */
839 status = ixgbe_setup_mac_link_82599(hw,
840 IXGBE_LINK_SPEED_1GB_FULL,
841 autoneg_wait_to_complete);
842 if (status != IXGBE_SUCCESS)
845 /* Flap the Tx laser if it has not already been done */
846 ixgbe_flap_tx_laser(hw);
848 /* Wait for the link partner to also set speed */
851 /* If we have link, just jump out */
852 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
853 if (status != IXGBE_SUCCESS)
861 * We didn't get link. Configure back to the highest speed we tried,
862 * (if there was more than one). We call ourselves back with just the
863 * single highest speed that the user requested.
866 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
867 highest_link_speed, autoneg_wait_to_complete);
870 /* Set autoneg_advertised value based on input link speed */
871 hw->phy.autoneg_advertised = 0;
873 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
874 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
876 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
877 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
883 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
884 * @hw: pointer to hardware structure
885 * @speed: new link speed
886 * @autoneg_wait_to_complete: true when waiting for completion is needed
888 * Implements the Intel SmartSpeed algorithm.
890 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
891 ixgbe_link_speed speed,
892 bool autoneg_wait_to_complete)
894 s32 status = IXGBE_SUCCESS;
895 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
897 bool link_up = false;
898 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
900 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
902 /* Set autoneg_advertised value based on input link speed */
903 hw->phy.autoneg_advertised = 0;
905 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
906 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
908 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
909 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
911 if (speed & IXGBE_LINK_SPEED_100_FULL)
912 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
915 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
916 * autoneg advertisement if link is unable to be established at the
917 * highest negotiated rate. This can sometimes happen due to integrity
918 * issues with the physical media connection.
921 /* First, try to get link with full advertisement */
922 hw->phy.smart_speed_active = false;
923 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
924 status = ixgbe_setup_mac_link_82599(hw, speed,
925 autoneg_wait_to_complete);
926 if (status != IXGBE_SUCCESS)
930 * Wait for the controller to acquire link. Per IEEE 802.3ap,
931 * Section 73.10.2, we may have to wait up to 500ms if KR is
932 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
933 * Table 9 in the AN MAS.
935 for (i = 0; i < 5; i++) {
938 /* If we have link, just jump out */
939 status = ixgbe_check_link(hw, &link_speed, &link_up,
941 if (status != IXGBE_SUCCESS)
950 * We didn't get link. If we advertised KR plus one of KX4/KX
951 * (or BX4/BX), then disable KR and try again.
953 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
954 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
957 /* Turn SmartSpeed on to disable KR support */
958 hw->phy.smart_speed_active = true;
959 status = ixgbe_setup_mac_link_82599(hw, speed,
960 autoneg_wait_to_complete);
961 if (status != IXGBE_SUCCESS)
965 * Wait for the controller to acquire link. 600ms will allow for
966 * the AN link_fail_inhibit_timer as well for multiple cycles of
967 * parallel detect, both 10g and 1g. This allows for the maximum
968 * connect attempts as defined in the AN MAS table 73-7.
970 for (i = 0; i < 6; i++) {
973 /* If we have link, just jump out */
974 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
975 if (status != IXGBE_SUCCESS)
982 /* We didn't get link. Turn SmartSpeed back off. */
983 hw->phy.smart_speed_active = false;
984 status = ixgbe_setup_mac_link_82599(hw, speed,
985 autoneg_wait_to_complete);
988 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
989 DEBUGOUT("Smartspeed has downgraded the link speed "
990 "from the maximum advertised\n");
995 * ixgbe_setup_mac_link_82599 - Set MAC link speed
996 * @hw: pointer to hardware structure
997 * @speed: new link speed
998 * @autoneg_wait_to_complete: true when waiting for completion is needed
1000 * Set the link speed in the AUTOC register and restarts link.
1002 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
1003 ixgbe_link_speed speed,
1004 bool autoneg_wait_to_complete)
1006 bool autoneg = false;
1007 s32 status = IXGBE_SUCCESS;
1008 u32 pma_pmd_1g, link_mode;
1009 u32 current_autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC); /* holds the value of AUTOC register at this current point in time */
1010 u32 orig_autoc = 0; /* holds the cached value of AUTOC register */
1011 u32 autoc = current_autoc; /* Temporary variable used for comparison purposes */
1012 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1013 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1016 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
1018 DEBUGFUNC("ixgbe_setup_mac_link_82599");
1020 /* Check to see if speed passed in is supported. */
1021 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
1025 speed &= link_capabilities;
1027 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
1028 status = IXGBE_ERR_LINK_SETUP;
1032 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
1033 if (hw->mac.orig_link_settings_stored)
1034 orig_autoc = hw->mac.orig_autoc;
1038 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
1039 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1041 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1042 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1043 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1044 /* Set KX4/KX/KR support according to speed requested */
1045 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
1046 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1047 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
1048 autoc |= IXGBE_AUTOC_KX4_SUPP;
1049 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
1050 (hw->phy.smart_speed_active == false))
1051 autoc |= IXGBE_AUTOC_KR_SUPP;
1053 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
1054 autoc |= IXGBE_AUTOC_KX_SUPP;
1055 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
1056 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
1057 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
1058 /* Switch from 1G SFI to 10G SFI if requested */
1059 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
1060 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
1061 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1062 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
1064 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
1065 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
1066 /* Switch from 10G SFI to 1G SFI if requested */
1067 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1068 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
1069 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1071 autoc |= IXGBE_AUTOC_LMS_1G_AN;
1073 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
1077 if (autoc != current_autoc) {
1079 status = hw->mac.ops.prot_autoc_write(hw, autoc, false);
1080 if (status != IXGBE_SUCCESS)
1083 /* Only poll for autoneg to complete if specified to do so */
1084 if (autoneg_wait_to_complete) {
1085 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1086 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1087 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1088 links_reg = 0; /*Just in case Autoneg time=0*/
1089 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1091 IXGBE_READ_REG(hw, IXGBE_LINKS);
1092 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
1096 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
1098 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
1099 DEBUGOUT("Autoneg did not complete.\n");
1104 /* Add delay to filter out noises during initial link setup */
1113 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
1114 * @hw: pointer to hardware structure
1115 * @speed: new link speed
1116 * @autoneg_wait_to_complete: true if waiting is needed to complete
1118 * Restarts link on PHY and MAC based on settings passed in.
1120 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1121 ixgbe_link_speed speed,
1122 bool autoneg_wait_to_complete)
1126 DEBUGFUNC("ixgbe_setup_copper_link_82599");
1128 /* Setup the PHY according to input speed */
1129 status = hw->phy.ops.setup_link_speed(hw, speed,
1130 autoneg_wait_to_complete);
1132 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1138 * ixgbe_reset_hw_82599 - Perform hardware reset
1139 * @hw: pointer to hardware structure
1141 * Resets the hardware by resetting the transmit and receive units, masks
1142 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1145 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1147 ixgbe_link_speed link_speed;
1150 u32 i, autoc, autoc2;
1152 bool link_up = false;
1154 DEBUGFUNC("ixgbe_reset_hw_82599");
1156 /* Call adapter stop to disable tx/rx and clear interrupts */
1157 status = hw->mac.ops.stop_adapter(hw);
1158 if (status != IXGBE_SUCCESS)
1161 /* flush pending Tx transactions */
1162 ixgbe_clear_tx_pending(hw);
1164 /* PHY ops must be identified and initialized prior to reset */
1166 /* Identify PHY and related function pointers */
1167 status = hw->phy.ops.init(hw);
1169 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1172 /* Setup SFP module if there is one present. */
1173 if (hw->phy.sfp_setup_needed) {
1174 status = hw->mac.ops.setup_sfp(hw);
1175 hw->phy.sfp_setup_needed = false;
1178 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1182 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1183 hw->phy.ops.reset(hw);
1185 /* remember AUTOC from before we reset */
1186 curr_lms = IXGBE_READ_REG(hw, IXGBE_AUTOC) & IXGBE_AUTOC_LMS_MASK;
1190 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1191 * If link reset is used when link is up, it might reset the PHY when
1192 * mng is using it. If link is down or the flag to force full link
1193 * reset is set, then perform link reset.
1195 ctrl = IXGBE_CTRL_LNK_RST;
1196 if (!hw->force_full_reset) {
1197 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1199 ctrl = IXGBE_CTRL_RST;
1202 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1203 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1204 IXGBE_WRITE_FLUSH(hw);
1206 /* Poll for reset bit to self-clear meaning reset is complete */
1207 for (i = 0; i < 10; i++) {
1209 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1210 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1214 if (ctrl & IXGBE_CTRL_RST_MASK) {
1215 status = IXGBE_ERR_RESET_FAILED;
1216 DEBUGOUT("Reset polling failed to complete.\n");
1222 * Double resets are required for recovery from certain error
1223 * conditions. Between resets, it is necessary to stall to
1224 * allow time for any pending HW events to complete.
1226 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1227 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1232 * Store the original AUTOC/AUTOC2 values if they have not been
1233 * stored off yet. Otherwise restore the stored original
1234 * values since the reset operation sets back to defaults.
1236 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1237 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1239 /* Enable link if disabled in NVM */
1240 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1241 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1242 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1243 IXGBE_WRITE_FLUSH(hw);
1246 if (hw->mac.orig_link_settings_stored == false) {
1247 hw->mac.orig_autoc = autoc;
1248 hw->mac.orig_autoc2 = autoc2;
1249 hw->mac.orig_link_settings_stored = true;
1252 /* If MNG FW is running on a multi-speed device that
1253 * doesn't autoneg with out driver support we need to
1254 * leave LMS in the state it was before we MAC reset.
1255 * Likewise if we support WoL we don't want change the
1258 if ((hw->phy.multispeed_fiber && ixgbe_mng_enabled(hw)) ||
1260 hw->mac.orig_autoc =
1261 (hw->mac.orig_autoc & ~IXGBE_AUTOC_LMS_MASK) |
1264 if (autoc != hw->mac.orig_autoc) {
1265 status = hw->mac.ops.prot_autoc_write(hw,
1268 if (status != IXGBE_SUCCESS)
1272 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1273 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1274 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1275 autoc2 |= (hw->mac.orig_autoc2 &
1276 IXGBE_AUTOC2_UPPER_MASK);
1277 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1281 /* Store the permanent mac address */
1282 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1285 * Store MAC address from RAR0, clear receive address registers, and
1286 * clear the multicast table. Also reset num_rar_entries to 128,
1287 * since we modify this value when programming the SAN MAC address.
1289 hw->mac.num_rar_entries = 128;
1290 hw->mac.ops.init_rx_addrs(hw);
1292 /* Store the permanent SAN mac address */
1293 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1295 /* Add the SAN MAC address to the RAR only if it's a valid address */
1296 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1297 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1298 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1300 /* Save the SAN MAC RAR index */
1301 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1303 /* Reserve the last RAR for the SAN MAC address */
1304 hw->mac.num_rar_entries--;
1307 /* Store the alternative WWNN/WWPN prefix */
1308 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1309 &hw->mac.wwpn_prefix);
1316 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1317 * @hw: pointer to hardware structure
1319 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1322 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1323 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1325 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1328 * Before starting reinitialization process,
1329 * FDIRCMD.CMD must be zero.
1331 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1332 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1333 IXGBE_FDIRCMD_CMD_MASK))
1337 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1338 DEBUGOUT("Flow Director previous command isn't complete, "
1339 "aborting table re-initialization.\n");
1340 return IXGBE_ERR_FDIR_REINIT_FAILED;
1343 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1344 IXGBE_WRITE_FLUSH(hw);
1346 * 82599 adapters flow director init flow cannot be restarted,
1347 * Workaround 82599 silicon errata by performing the following steps
1348 * before re-writing the FDIRCTRL control register with the same value.
1349 * - write 1 to bit 8 of FDIRCMD register &
1350 * - write 0 to bit 8 of FDIRCMD register
1352 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1353 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1354 IXGBE_FDIRCMD_CLEARHT));
1355 IXGBE_WRITE_FLUSH(hw);
1356 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1357 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1358 ~IXGBE_FDIRCMD_CLEARHT));
1359 IXGBE_WRITE_FLUSH(hw);
1361 * Clear FDIR Hash register to clear any leftover hashes
1362 * waiting to be programmed.
1364 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1365 IXGBE_WRITE_FLUSH(hw);
1367 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1368 IXGBE_WRITE_FLUSH(hw);
1370 /* Poll init-done after we write FDIRCTRL register */
1371 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1372 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1373 IXGBE_FDIRCTRL_INIT_DONE)
1377 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1378 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1379 return IXGBE_ERR_FDIR_REINIT_FAILED;
1382 /* Clear FDIR statistics registers (read to clear) */
1383 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1384 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1385 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1386 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1387 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1389 return IXGBE_SUCCESS;
1393 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1394 * @hw: pointer to hardware structure
1395 * @fdirctrl: value to write to flow director control register
1397 STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1401 DEBUGFUNC("ixgbe_fdir_enable_82599");
1403 /* Prime the keys for hashing */
1404 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1405 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1408 * Poll init-done after we write the register. Estimated times:
1409 * 10G: PBALLOC = 11b, timing is 60us
1410 * 1G: PBALLOC = 11b, timing is 600us
1411 * 100M: PBALLOC = 11b, timing is 6ms
1413 * Multiple these timings by 4 if under full Rx load
1415 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1416 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1417 * this might not finish in our poll time, but we can live with that
1420 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1421 IXGBE_WRITE_FLUSH(hw);
1422 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1423 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1424 IXGBE_FDIRCTRL_INIT_DONE)
1429 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1430 DEBUGOUT("Flow Director poll time exceeded!\n");
1434 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1435 * @hw: pointer to hardware structure
1436 * @fdirctrl: value to write to flow director control register, initially
1437 * contains just the value of the Rx packet buffer allocation
1439 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1441 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1444 * Continue setup of fdirctrl register bits:
1445 * Move the flexible bytes to use the ethertype - shift 6 words
1446 * Set the maximum length per hash bucket to 0xA filters
1447 * Send interrupt when 64 filters are left
1449 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1450 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1451 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1453 /* write hashes and fdirctrl register, poll for completion */
1454 ixgbe_fdir_enable_82599(hw, fdirctrl);
1456 return IXGBE_SUCCESS;
1460 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1461 * @hw: pointer to hardware structure
1462 * @fdirctrl: value to write to flow director control register, initially
1463 * contains just the value of the Rx packet buffer allocation
1464 * @cloud_mode: true - cloud mode, false - other mode
1466 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl,
1469 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1472 * Continue setup of fdirctrl register bits:
1473 * Turn perfect match filtering on
1474 * Report hash in RSS field of Rx wb descriptor
1475 * Initialize the drop queue
1476 * Move the flexible bytes to use the ethertype - shift 6 words
1477 * Set the maximum length per hash bucket to 0xA filters
1478 * Send interrupt when 64 (0x4 * 16) filters are left
1480 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1481 IXGBE_FDIRCTRL_REPORT_STATUS |
1482 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1483 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1484 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1485 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1488 /* write hashes and fdirctrl register, poll for completion */
1489 ixgbe_fdir_enable_82599(hw, fdirctrl);
1491 return IXGBE_SUCCESS;
1495 * These defines allow us to quickly generate all of the necessary instructions
1496 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1497 * for values 0 through 15
1499 #define IXGBE_ATR_COMMON_HASH_KEY \
1500 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1501 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1504 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1505 common_hash ^= lo_hash_dword >> n; \
1506 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1507 bucket_hash ^= lo_hash_dword >> n; \
1508 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1509 sig_hash ^= lo_hash_dword << (16 - n); \
1510 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1511 common_hash ^= hi_hash_dword >> n; \
1512 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1513 bucket_hash ^= hi_hash_dword >> n; \
1514 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1515 sig_hash ^= hi_hash_dword << (16 - n); \
1519 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1520 * @stream: input bitstream to compute the hash on
1522 * This function is almost identical to the function above but contains
1523 * several optimizations such as unwinding all of the loops, letting the
1524 * compiler work out all of the conditional ifs since the keys are static
1525 * defines, and computing two keys at once since the hashed dword stream
1526 * will be the same for both keys.
1528 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1529 union ixgbe_atr_hash_dword common)
1531 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1532 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1534 /* record the flow_vm_vlan bits as they are a key part to the hash */
1535 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1537 /* generate common hash dword */
1538 hi_hash_dword = IXGBE_NTOHL(common.dword);
1540 /* low dword is word swapped version of common */
1541 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1543 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1544 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1546 /* Process bits 0 and 16 */
1547 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1550 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1551 * delay this because bit 0 of the stream should not be processed
1552 * so we do not add the VLAN until after bit 0 was processed
1554 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1556 /* Process remaining 30 bit of the key */
1557 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1558 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1559 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1560 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1561 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1562 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1563 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1564 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1565 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1566 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1567 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1568 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1569 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1570 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1571 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1573 /* combine common_hash result with signature and bucket hashes */
1574 bucket_hash ^= common_hash;
1575 bucket_hash &= IXGBE_ATR_HASH_MASK;
1577 sig_hash ^= common_hash << 16;
1578 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1580 /* return completed signature hash */
1581 return sig_hash ^ bucket_hash;
1585 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1586 * @hw: pointer to hardware structure
1587 * @input: unique input dword
1588 * @common: compressed common input dword
1589 * @queue: queue index to direct traffic to
1591 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1592 union ixgbe_atr_hash_dword input,
1593 union ixgbe_atr_hash_dword common,
1599 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1602 * Get the flow_type in order to program FDIRCMD properly
1603 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1604 * fifth is FDIRCMD.TUNNEL_FILTER
1606 switch (input.formatted.flow_type) {
1607 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1608 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1609 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1610 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1611 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1612 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1615 DEBUGOUT(" Error on flow type input\n");
1616 return IXGBE_ERR_CONFIG;
1619 /* configure FDIRCMD register */
1620 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1621 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1622 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1623 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1626 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1627 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1629 fdirhashcmd = (u64)fdircmd << 32;
1630 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1631 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1633 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1635 return IXGBE_SUCCESS;
1638 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1641 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1642 bucket_hash ^= lo_hash_dword >> n; \
1643 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1644 bucket_hash ^= hi_hash_dword >> n; \
1648 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1649 * @atr_input: input bitstream to compute the hash on
1650 * @input_mask: mask for the input bitstream
1652 * This function serves two main purposes. First it applies the input_mask
1653 * to the atr_input resulting in a cleaned up atr_input data stream.
1654 * Secondly it computes the hash and stores it in the bkt_hash field at
1655 * the end of the input byte stream. This way it will be available for
1656 * future use without needing to recompute the hash.
1658 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1659 union ixgbe_atr_input *input_mask)
1662 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1663 u32 bucket_hash = 0;
1667 /* Apply masks to input data */
1668 for (i = 0; i < 14; i++)
1669 input->dword_stream[i] &= input_mask->dword_stream[i];
1671 /* record the flow_vm_vlan bits as they are a key part to the hash */
1672 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1674 /* generate common hash dword */
1675 for (i = 1; i <= 13; i++)
1676 hi_dword ^= input->dword_stream[i];
1677 hi_hash_dword = IXGBE_NTOHL(hi_dword);
1679 /* low dword is word swapped version of common */
1680 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1682 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1683 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1685 /* Process bits 0 and 16 */
1686 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1689 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1690 * delay this because bit 0 of the stream should not be processed
1691 * so we do not add the VLAN until after bit 0 was processed
1693 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1695 /* Process remaining 30 bit of the key */
1696 for (i = 1; i <= 15; i++)
1697 IXGBE_COMPUTE_BKT_HASH_ITERATION(i);
1700 * Limit hash to 13 bits since max bucket count is 8K.
1701 * Store result at the end of the input stream.
1703 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1707 * ixgbe_get_fdirtcpm_82599 - generate a TCP port from atr_input_masks
1708 * @input_mask: mask to be bit swapped
1710 * The source and destination port masks for flow director are bit swapped
1711 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1712 * generate a correctly swapped value we need to bit swap the mask and that
1713 * is what is accomplished by this function.
1715 STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1717 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1718 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1719 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1720 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1721 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1722 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1723 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1727 * These two macros are meant to address the fact that we have registers
1728 * that are either all or in part big-endian. As a result on big-endian
1729 * systems we will end up byte swapping the value to little-endian before
1730 * it is byte swapped again and written to the hardware in the original
1731 * big-endian format.
1733 #define IXGBE_STORE_AS_BE32(_value) \
1734 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1735 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1737 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1738 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1740 #define IXGBE_STORE_AS_BE16(_value) \
1741 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1743 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1744 union ixgbe_atr_input *input_mask, bool cloud_mode)
1746 /* mask IPv6 since it is currently not supported */
1747 u32 fdirm = IXGBE_FDIRM_DIPv6;
1749 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1752 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1753 * are zero, then assume a full mask for that field. Also assume that
1754 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1755 * cannot be masked out in this implementation.
1757 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1761 /* verify bucket hash is cleared on hash generation */
1762 if (input_mask->formatted.bkt_hash)
1763 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1765 /* Program FDIRM and verify partial masks */
1766 switch (input_mask->formatted.vm_pool & 0x7F) {
1768 fdirm |= IXGBE_FDIRM_POOL;
1772 DEBUGOUT(" Error on vm pool mask\n");
1773 return IXGBE_ERR_CONFIG;
1776 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1778 fdirm |= IXGBE_FDIRM_L4P;
1779 if (input_mask->formatted.dst_port ||
1780 input_mask->formatted.src_port) {
1781 DEBUGOUT(" Error on src/dst port mask\n");
1782 return IXGBE_ERR_CONFIG;
1784 case IXGBE_ATR_L4TYPE_MASK:
1787 DEBUGOUT(" Error on flow type mask\n");
1788 return IXGBE_ERR_CONFIG;
1791 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1793 /* mask VLAN ID, fall through to mask VLAN priority */
1794 fdirm |= IXGBE_FDIRM_VLANID;
1796 /* mask VLAN priority */
1797 fdirm |= IXGBE_FDIRM_VLANP;
1800 /* mask VLAN ID only, fall through */
1801 fdirm |= IXGBE_FDIRM_VLANID;
1803 /* no VLAN fields masked */
1806 DEBUGOUT(" Error on VLAN mask\n");
1807 return IXGBE_ERR_CONFIG;
1810 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1812 /* Mask Flex Bytes, fall through */
1813 fdirm |= IXGBE_FDIRM_FLEX;
1817 DEBUGOUT(" Error on flexible byte mask\n");
1818 return IXGBE_ERR_CONFIG;
1822 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1823 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1825 /* store the TCP/UDP port masks, bit reversed from port layout */
1826 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1828 /* write both the same so that UDP and TCP use the same mask */
1829 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1830 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1832 /* store source and destination IP masks (big-endian) */
1833 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1834 ~input_mask->formatted.src_ip[0]);
1835 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1836 ~input_mask->formatted.dst_ip[0]);
1838 return IXGBE_SUCCESS;
1841 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1842 union ixgbe_atr_input *input,
1843 u16 soft_id, u8 queue, bool cloud_mode)
1845 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1847 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1849 /* currently IPv6 is not supported, must be programmed with 0 */
1850 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1851 input->formatted.src_ip[0]);
1852 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1853 input->formatted.src_ip[1]);
1854 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1855 input->formatted.src_ip[2]);
1857 /* record the source address (big-endian) */
1858 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1860 /* record the first 32 bits of the destination address (big-endian) */
1861 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1863 /* record source and destination port (little-endian)*/
1864 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1865 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1866 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1867 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1869 /* record VLAN (little-endian) and flex_bytes(big-endian) */
1870 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1871 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1872 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1873 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1876 /* configure FDIRHASH register */
1877 fdirhash = input->formatted.bkt_hash;
1878 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1879 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1882 * flush all previous writes to make certain registers are
1883 * programmed prior to issuing the command
1885 IXGBE_WRITE_FLUSH(hw);
1887 /* configure FDIRCMD register */
1888 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1889 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1890 if (queue == IXGBE_FDIR_DROP_QUEUE)
1891 fdircmd |= IXGBE_FDIRCMD_DROP;
1892 if (input->formatted.flow_type & IXGBE_ATR_L4TYPE_TUNNEL_MASK)
1893 fdircmd |= IXGBE_FDIRCMD_TUNNEL_FILTER;
1894 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1895 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1896 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1898 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1900 return IXGBE_SUCCESS;
1903 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1904 union ixgbe_atr_input *input,
1910 s32 err = IXGBE_SUCCESS;
1912 /* configure FDIRHASH register */
1913 fdirhash = input->formatted.bkt_hash;
1914 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1915 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1917 /* flush hash to HW */
1918 IXGBE_WRITE_FLUSH(hw);
1920 /* Query if filter is present */
1921 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1923 for (retry_count = 10; retry_count; retry_count--) {
1924 /* allow 10us for query to process */
1926 /* verify query completed successfully */
1927 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1928 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1933 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1935 /* if filter exists in hardware then remove it */
1936 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1937 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1938 IXGBE_WRITE_FLUSH(hw);
1939 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1940 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1947 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1948 * @hw: pointer to hardware structure
1949 * @input: input bitstream
1950 * @input_mask: mask for the input bitstream
1951 * @soft_id: software index for the filters
1952 * @queue: queue index to direct traffic to
1954 * Note that the caller to this function must lock before calling, since the
1955 * hardware writes must be protected from one another.
1957 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1958 union ixgbe_atr_input *input,
1959 union ixgbe_atr_input *input_mask,
1960 u16 soft_id, u8 queue, bool cloud_mode)
1962 s32 err = IXGBE_ERR_CONFIG;
1964 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1967 * Check flow_type formatting, and bail out before we touch the hardware
1968 * if there's a configuration issue
1970 switch (input->formatted.flow_type) {
1971 case IXGBE_ATR_FLOW_TYPE_IPV4:
1972 case IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4:
1973 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1974 if (input->formatted.dst_port || input->formatted.src_port) {
1975 DEBUGOUT(" Error on src/dst port\n");
1976 return IXGBE_ERR_CONFIG;
1979 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1980 case IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4:
1981 if (input->formatted.dst_port || input->formatted.src_port) {
1982 DEBUGOUT(" Error on src/dst port\n");
1983 return IXGBE_ERR_CONFIG;
1985 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1986 case IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4:
1987 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1988 case IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4:
1989 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
1990 IXGBE_ATR_L4TYPE_MASK;
1993 DEBUGOUT(" Error on flow type input\n");
1997 /* program input mask into the HW */
1998 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask, cloud_mode);
2002 /* apply mask and compute/store hash */
2003 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
2005 /* program filters to filter memory */
2006 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
2007 soft_id, queue, cloud_mode);
2011 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
2012 * @hw: pointer to hardware structure
2013 * @reg: analog register to read
2016 * Performs read operation to Omer analog register specified.
2018 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
2022 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
2024 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2026 IXGBE_WRITE_FLUSH(hw);
2028 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2029 *val = (u8)core_ctl;
2031 return IXGBE_SUCCESS;
2035 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2036 * @hw: pointer to hardware structure
2037 * @reg: atlas register to write
2038 * @val: value to write
2040 * Performs write operation to Omer analog register specified.
2042 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2046 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
2048 core_ctl = (reg << 8) | val;
2049 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2050 IXGBE_WRITE_FLUSH(hw);
2053 return IXGBE_SUCCESS;
2057 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2058 * @hw: pointer to hardware structure
2060 * Starts the hardware using the generic start_hw function
2061 * and the generation start_hw function.
2062 * Then performs revision-specific operations, if any.
2064 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2066 s32 ret_val = IXGBE_SUCCESS;
2068 DEBUGFUNC("ixgbe_start_hw_82599");
2070 ret_val = ixgbe_start_hw_generic(hw);
2071 if (ret_val != IXGBE_SUCCESS)
2074 ret_val = ixgbe_start_hw_gen2(hw);
2075 if (ret_val != IXGBE_SUCCESS)
2078 /* We need to run link autotry after the driver loads */
2079 hw->mac.autotry_restart = true;
2081 if (ret_val == IXGBE_SUCCESS)
2082 ret_val = ixgbe_verify_fw_version_82599(hw);
2088 * ixgbe_identify_phy_82599 - Get physical layer module
2089 * @hw: pointer to hardware structure
2091 * Determines the physical layer module found on the current adapter.
2092 * If PHY already detected, maintains current PHY type in hw struct,
2093 * otherwise executes the PHY detection routine.
2095 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2099 DEBUGFUNC("ixgbe_identify_phy_82599");
2101 /* Detect PHY if not unknown - returns success if already detected. */
2102 status = ixgbe_identify_phy_generic(hw);
2103 if (status != IXGBE_SUCCESS) {
2104 /* 82599 10GBASE-T requires an external PHY */
2105 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2108 status = ixgbe_identify_module_generic(hw);
2111 /* Set PHY type none if no PHY detected */
2112 if (hw->phy.type == ixgbe_phy_unknown) {
2113 hw->phy.type = ixgbe_phy_none;
2114 return IXGBE_SUCCESS;
2117 /* Return error if SFP module has been detected but is not supported */
2118 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2119 return IXGBE_ERR_SFP_NOT_SUPPORTED;
2125 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2126 * @hw: pointer to hardware structure
2128 * Determines physical layer capabilities of the current configuration.
2130 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2132 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2133 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2134 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2135 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2136 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2137 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2138 u16 ext_ability = 0;
2139 u8 comp_codes_10g = 0;
2140 u8 comp_codes_1g = 0;
2142 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2144 hw->phy.ops.identify(hw);
2146 switch (hw->phy.type) {
2148 case ixgbe_phy_cu_unknown:
2149 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2150 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2151 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2152 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2153 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2154 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2155 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
2156 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2162 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2163 case IXGBE_AUTOC_LMS_1G_AN:
2164 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2165 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2166 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2167 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2170 /* SFI mode so read SFP module */
2173 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2174 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2175 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2176 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2177 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2178 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2179 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2182 case IXGBE_AUTOC_LMS_10G_SERIAL:
2183 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2184 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2186 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2189 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2190 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2191 if (autoc & IXGBE_AUTOC_KX_SUPP)
2192 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2193 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2194 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2195 if (autoc & IXGBE_AUTOC_KR_SUPP)
2196 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2205 /* SFP check must be done last since DA modules are sometimes used to
2206 * test KR mode - we need to id KR mode correctly before SFP module.
2207 * Call identify_sfp because the pluggable module may have changed */
2208 hw->phy.ops.identify_sfp(hw);
2209 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2212 switch (hw->phy.type) {
2213 case ixgbe_phy_sfp_passive_tyco:
2214 case ixgbe_phy_sfp_passive_unknown:
2215 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2217 case ixgbe_phy_sfp_ftl_active:
2218 case ixgbe_phy_sfp_active_unknown:
2219 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2221 case ixgbe_phy_sfp_avago:
2222 case ixgbe_phy_sfp_ftl:
2223 case ixgbe_phy_sfp_intel:
2224 case ixgbe_phy_sfp_unknown:
2225 hw->phy.ops.read_i2c_eeprom(hw,
2226 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2227 hw->phy.ops.read_i2c_eeprom(hw,
2228 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2229 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2230 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2231 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2232 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2233 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2234 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2235 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
2236 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
2243 return physical_layer;
2247 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2248 * @hw: pointer to hardware structure
2249 * @regval: register value to write to RXCTRL
2251 * Enables the Rx DMA unit for 82599
2253 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2256 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2259 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2260 * If traffic is incoming before we enable the Rx unit, it could hang
2261 * the Rx DMA unit. Therefore, make sure the security engine is
2262 * completely disabled prior to enabling the Rx unit.
2265 hw->mac.ops.disable_sec_rx_path(hw);
2267 if (regval & IXGBE_RXCTRL_RXEN)
2268 ixgbe_enable_rx(hw);
2270 ixgbe_disable_rx(hw);
2272 hw->mac.ops.enable_sec_rx_path(hw);
2274 return IXGBE_SUCCESS;
2278 * ixgbe_verify_fw_version_82599 - verify FW version for 82599
2279 * @hw: pointer to hardware structure
2281 * Verifies that installed the firmware version is 0.6 or higher
2282 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2284 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2285 * if the FW version is not supported.
2287 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2289 s32 status = IXGBE_ERR_EEPROM_VERSION;
2290 u16 fw_offset, fw_ptp_cfg_offset;
2293 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2295 /* firmware check is only necessary for SFI devices */
2296 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2297 status = IXGBE_SUCCESS;
2298 goto fw_version_out;
2301 /* get the offset to the Firmware Module block */
2302 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
2303 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2304 "eeprom read at offset %d failed", IXGBE_FW_PTR);
2305 return IXGBE_ERR_EEPROM_VERSION;
2308 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2309 goto fw_version_out;
2311 /* get the offset to the Pass Through Patch Configuration block */
2312 if (hw->eeprom.ops.read(hw, (fw_offset +
2313 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2314 &fw_ptp_cfg_offset)) {
2315 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2316 "eeprom read at offset %d failed",
2318 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);
2319 return IXGBE_ERR_EEPROM_VERSION;
2322 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2323 goto fw_version_out;
2325 /* get the firmware version */
2326 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2327 IXGBE_FW_PATCH_VERSION_4), &fw_version)) {
2328 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2329 "eeprom read at offset %d failed",
2330 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);
2331 return IXGBE_ERR_EEPROM_VERSION;
2334 if (fw_version > 0x5)
2335 status = IXGBE_SUCCESS;
2342 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2343 * @hw: pointer to hardware structure
2345 * Returns true if the LESM FW module is present and enabled. Otherwise
2346 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2348 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2350 bool lesm_enabled = false;
2351 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2354 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2356 /* get the offset to the Firmware Module block */
2357 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2359 if ((status != IXGBE_SUCCESS) ||
2360 (fw_offset == 0) || (fw_offset == 0xFFFF))
2363 /* get the offset to the LESM Parameters block */
2364 status = hw->eeprom.ops.read(hw, (fw_offset +
2365 IXGBE_FW_LESM_PARAMETERS_PTR),
2366 &fw_lesm_param_offset);
2368 if ((status != IXGBE_SUCCESS) ||
2369 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2372 /* get the LESM state word */
2373 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2374 IXGBE_FW_LESM_STATE_1),
2377 if ((status == IXGBE_SUCCESS) &&
2378 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2379 lesm_enabled = true;
2382 return lesm_enabled;
2386 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2387 * fastest available method
2389 * @hw: pointer to hardware structure
2390 * @offset: offset of word in EEPROM to read
2391 * @words: number of words
2392 * @data: word(s) read from the EEPROM
2394 * Retrieves 16 bit word(s) read from EEPROM
2396 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2397 u16 words, u16 *data)
2399 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2400 s32 ret_val = IXGBE_ERR_CONFIG;
2402 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2405 * If EEPROM is detected and can be addressed using 14 bits,
2406 * use EERD otherwise use bit bang
2408 if ((eeprom->type == ixgbe_eeprom_spi) &&
2409 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2410 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2413 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2421 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2422 * fastest available method
2424 * @hw: pointer to hardware structure
2425 * @offset: offset of word in the EEPROM to read
2426 * @data: word read from the EEPROM
2428 * Reads a 16 bit word from the EEPROM
2430 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2431 u16 offset, u16 *data)
2433 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2434 s32 ret_val = IXGBE_ERR_CONFIG;
2436 DEBUGFUNC("ixgbe_read_eeprom_82599");
2439 * If EEPROM is detected and can be addressed using 14 bits,
2440 * use EERD otherwise use bit bang
2442 if ((eeprom->type == ixgbe_eeprom_spi) &&
2443 (offset <= IXGBE_EERD_MAX_ADDR))
2444 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2446 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2452 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2454 * @hw: pointer to hardware structure
2456 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2457 * full pipeline reset. This function assumes the SW/FW lock is held.
2459 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2463 u32 i, autoc_reg, autoc2_reg;
2465 /* Enable link if disabled in NVM */
2466 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2467 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2468 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2469 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2470 IXGBE_WRITE_FLUSH(hw);
2473 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2474 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2475 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2476 IXGBE_WRITE_REG(hw, IXGBE_AUTOC,
2477 autoc_reg ^ (0x4 << IXGBE_AUTOC_LMS_SHIFT));
2478 /* Wait for AN to leave state 0 */
2479 for (i = 0; i < 10; i++) {
2481 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2482 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2486 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2487 DEBUGOUT("auto negotiation not completed\n");
2488 ret_val = IXGBE_ERR_RESET_FAILED;
2489 goto reset_pipeline_out;
2492 ret_val = IXGBE_SUCCESS;
2495 /* Write AUTOC register with original LMS field and Restart_AN */
2496 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2497 IXGBE_WRITE_FLUSH(hw);