1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82599.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
39 #ident "$Id: ixgbe_82599.c,v 1.301 2012/11/08 11:33:27 jtkirshe Exp $"
41 #define IXGBE_82599_MAX_TX_QUEUES 128
42 #define IXGBE_82599_MAX_RX_QUEUES 128
43 #define IXGBE_82599_RAR_ENTRIES 128
44 #define IXGBE_82599_MC_TBL_SIZE 128
45 #define IXGBE_82599_VFT_TBL_SIZE 128
46 #define IXGBE_82599_RX_PB_SIZE 512
48 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
49 ixgbe_link_speed speed,
50 bool autoneg_wait_to_complete);
51 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
53 u16 offset, u16 *data);
54 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
57 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
59 u32 fwsm, manc, factps;
61 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
62 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
65 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
66 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
69 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
70 if (factps & IXGBE_FACTPS_MNGCG)
76 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
78 struct ixgbe_mac_info *mac = &hw->mac;
80 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
83 * enable the laser control functions for SFP+ fiber
86 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
87 !ixgbe_mng_enabled(hw)) {
88 mac->ops.disable_tx_laser =
89 &ixgbe_disable_tx_laser_multispeed_fiber;
90 mac->ops.enable_tx_laser =
91 &ixgbe_enable_tx_laser_multispeed_fiber;
92 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
95 mac->ops.disable_tx_laser = NULL;
96 mac->ops.enable_tx_laser = NULL;
97 mac->ops.flap_tx_laser = NULL;
100 if (hw->phy.multispeed_fiber) {
101 /* Set up dual speed SFP+ support */
102 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
104 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
105 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
106 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
107 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
108 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
110 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
116 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
117 * @hw: pointer to hardware structure
119 * Initialize any function pointers that were not able to be
120 * set during init_shared_code because the PHY/SFP type was
121 * not known. Perform the SFP init if necessary.
124 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
126 struct ixgbe_mac_info *mac = &hw->mac;
127 struct ixgbe_phy_info *phy = &hw->phy;
128 s32 ret_val = IXGBE_SUCCESS;
130 DEBUGFUNC("ixgbe_init_phy_ops_82599");
132 /* Identify the PHY or SFP module */
133 ret_val = phy->ops.identify(hw);
134 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
135 goto init_phy_ops_out;
137 /* Setup function pointers based on detected SFP module and speeds */
138 ixgbe_init_mac_link_ops_82599(hw);
139 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
140 hw->phy.ops.reset = NULL;
142 /* If copper media, overwrite with copper function pointers */
143 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
144 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
145 mac->ops.get_link_capabilities =
146 &ixgbe_get_copper_link_capabilities_generic;
149 /* Set necessary function pointers based on phy type */
150 switch (hw->phy.type) {
152 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
153 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
154 phy->ops.get_firmware_version =
155 &ixgbe_get_phy_firmware_version_tnx;
164 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
166 s32 ret_val = IXGBE_SUCCESS;
167 u16 list_offset, data_offset, data_value;
168 bool got_lock = false;
170 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
172 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
173 ixgbe_init_mac_link_ops_82599(hw);
175 hw->phy.ops.reset = NULL;
177 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
179 if (ret_val != IXGBE_SUCCESS)
182 /* PHY config will finish before releasing the semaphore */
183 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
184 IXGBE_GSSR_MAC_CSR_SM);
185 if (ret_val != IXGBE_SUCCESS) {
186 ret_val = IXGBE_ERR_SWFW_SYNC;
190 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
191 while (data_value != 0xffff) {
192 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
193 IXGBE_WRITE_FLUSH(hw);
194 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
197 /* Release the semaphore */
198 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
199 /* Delay obtaining semaphore again to allow FW access */
200 msec_delay(hw->eeprom.semaphore_delay);
202 /* Need SW/FW semaphore around AUTOC writes if LESM on,
203 * likewise reset_pipeline requires lock as it also writes
206 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
207 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
208 IXGBE_GSSR_MAC_CSR_SM);
209 if (ret_val != IXGBE_SUCCESS) {
210 ret_val = IXGBE_ERR_SWFW_SYNC;
217 /* Restart DSP and set SFI mode */
218 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
219 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL));
221 ret_val = ixgbe_reset_pipeline_82599(hw);
224 hw->mac.ops.release_swfw_sync(hw,
225 IXGBE_GSSR_MAC_CSR_SM);
230 DEBUGOUT("sfp module setup not complete\n");
231 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
242 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
243 * @hw: pointer to hardware structure
245 * Initialize the function pointers and assign the MAC type for 82599.
246 * Does not touch the hardware.
249 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
251 struct ixgbe_mac_info *mac = &hw->mac;
252 struct ixgbe_phy_info *phy = &hw->phy;
253 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
256 DEBUGFUNC("ixgbe_init_ops_82599");
258 ret_val = ixgbe_init_phy_ops_generic(hw);
259 ret_val = ixgbe_init_ops_generic(hw);
262 phy->ops.identify = &ixgbe_identify_phy_82599;
263 phy->ops.init = &ixgbe_init_phy_ops_82599;
266 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
267 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
268 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
269 mac->ops.get_supported_physical_layer =
270 &ixgbe_get_supported_physical_layer_82599;
271 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
272 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
273 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
274 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
275 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
276 mac->ops.start_hw = &ixgbe_start_hw_82599;
277 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
278 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
279 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
280 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
281 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
283 /* RAR, Multicast, VLAN */
284 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
285 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
286 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
287 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
288 mac->rar_highwater = 1;
289 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
290 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
291 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
292 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
293 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
294 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
295 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
298 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
299 mac->ops.check_link = &ixgbe_check_mac_link_generic;
300 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
301 ixgbe_init_mac_link_ops_82599(hw);
303 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
304 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
305 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
306 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
307 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
308 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
309 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
311 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
312 IXGBE_FWSM_MODE_MASK) ? true : false;
314 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
317 eeprom->ops.read = &ixgbe_read_eeprom_82599;
318 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
320 /* Manageability interface */
321 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
324 mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
330 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
331 * @hw: pointer to hardware structure
332 * @speed: pointer to link speed
333 * @autoneg: true when autoneg or autotry is enabled
335 * Determines the link capabilities by reading the AUTOC register.
337 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
338 ixgbe_link_speed *speed,
341 s32 status = IXGBE_SUCCESS;
344 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
347 /* Check if 1G SFP module. */
348 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
349 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
350 #ifdef SUPPORT_1000BASE_LX
351 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
352 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
354 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
355 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
356 *speed = IXGBE_LINK_SPEED_1GB_FULL;
362 * Determine link capabilities based on the stored value of AUTOC,
363 * which represents EEPROM defaults. If AUTOC value has not
364 * been stored, use the current register values.
366 if (hw->mac.orig_link_settings_stored)
367 autoc = hw->mac.orig_autoc;
369 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
371 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
372 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
373 *speed = IXGBE_LINK_SPEED_1GB_FULL;
377 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
378 *speed = IXGBE_LINK_SPEED_10GB_FULL;
382 case IXGBE_AUTOC_LMS_1G_AN:
383 *speed = IXGBE_LINK_SPEED_1GB_FULL;
387 case IXGBE_AUTOC_LMS_10G_SERIAL:
388 *speed = IXGBE_LINK_SPEED_10GB_FULL;
392 case IXGBE_AUTOC_LMS_KX4_KX_KR:
393 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
394 *speed = IXGBE_LINK_SPEED_UNKNOWN;
395 if (autoc & IXGBE_AUTOC_KR_SUPP)
396 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
397 if (autoc & IXGBE_AUTOC_KX4_SUPP)
398 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
399 if (autoc & IXGBE_AUTOC_KX_SUPP)
400 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
404 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
405 *speed = IXGBE_LINK_SPEED_100_FULL;
406 if (autoc & IXGBE_AUTOC_KR_SUPP)
407 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
408 if (autoc & IXGBE_AUTOC_KX4_SUPP)
409 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
410 if (autoc & IXGBE_AUTOC_KX_SUPP)
411 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
415 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
416 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
421 status = IXGBE_ERR_LINK_SETUP;
426 if (hw->phy.multispeed_fiber) {
427 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
428 IXGBE_LINK_SPEED_1GB_FULL;
438 * ixgbe_get_media_type_82599 - Get media type
439 * @hw: pointer to hardware structure
441 * Returns the media type (fiber, copper, backplane)
443 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
445 enum ixgbe_media_type media_type;
447 DEBUGFUNC("ixgbe_get_media_type_82599");
449 /* Detect if there is a copper PHY attached. */
450 switch (hw->phy.type) {
451 case ixgbe_phy_cu_unknown:
453 media_type = ixgbe_media_type_copper;
459 switch (hw->device_id) {
460 case IXGBE_DEV_ID_82599_KX4:
461 case IXGBE_DEV_ID_82599_KX4_MEZZ:
462 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
463 case IXGBE_DEV_ID_82599_KR:
464 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
465 case IXGBE_DEV_ID_82599_XAUI_LOM:
466 /* Default device ID is mezzanine card KX/KX4 */
467 media_type = ixgbe_media_type_backplane;
469 case IXGBE_DEV_ID_82599_SFP:
470 case IXGBE_DEV_ID_82599_SFP_FCOE:
471 case IXGBE_DEV_ID_82599_SFP_EM:
472 case IXGBE_DEV_ID_82599_SFP_SF2:
473 case IXGBE_DEV_ID_82599_SFP_SF_QP:
474 case IXGBE_DEV_ID_82599EN_SFP:
475 #ifdef RTE_NIC_BYPASS
476 case IXGBE_DEV_ID_82599_BYPASS:
478 media_type = ixgbe_media_type_fiber;
480 case IXGBE_DEV_ID_82599_CX4:
481 media_type = ixgbe_media_type_cx4;
483 case IXGBE_DEV_ID_82599_T3_LOM:
484 media_type = ixgbe_media_type_copper;
487 media_type = ixgbe_media_type_unknown;
495 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
496 * @hw: pointer to hardware structure
498 * Disables link during D3 power down sequence.
501 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
503 u32 autoc2_reg, fwsm;
506 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
507 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
509 /* Check to see if MNG FW could be enabled */
510 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
512 if (((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) &&
514 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
515 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
516 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
517 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
522 * ixgbe_start_mac_link_82599 - Setup MAC link settings
523 * @hw: pointer to hardware structure
524 * @autoneg_wait_to_complete: true when waiting for completion is needed
526 * Configures link settings based on values in the ixgbe_hw struct.
527 * Restarts the link. Performs autonegotiation if needed.
529 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
530 bool autoneg_wait_to_complete)
535 s32 status = IXGBE_SUCCESS;
536 bool got_lock = false;
538 DEBUGFUNC("ixgbe_start_mac_link_82599");
541 /* reset_pipeline requires us to hold this lock as it writes to
544 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
545 status = hw->mac.ops.acquire_swfw_sync(hw,
546 IXGBE_GSSR_MAC_CSR_SM);
547 if (status != IXGBE_SUCCESS)
554 ixgbe_reset_pipeline_82599(hw);
557 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
559 /* Only poll for autoneg to complete if specified to do so */
560 if (autoneg_wait_to_complete) {
561 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
562 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
563 IXGBE_AUTOC_LMS_KX4_KX_KR ||
564 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
565 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
566 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
567 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
568 links_reg = 0; /* Just in case Autoneg time = 0 */
569 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
570 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
571 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
575 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
576 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
577 DEBUGOUT("Autoneg did not complete.\n");
582 /* Add delay to filter out noises during initial link setup */
590 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
591 * @hw: pointer to hardware structure
593 * The base drivers may require better control over SFP+ module
594 * PHY states. This includes selectively shutting down the Tx
595 * laser on the PHY, effectively halting physical link.
597 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
599 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
601 /* Blocked by MNG FW so bail */
602 if (ixgbe_check_reset_blocked(hw))
605 /* Disable tx laser; allow 100us to go dark per spec */
606 esdp_reg |= IXGBE_ESDP_SDP3;
607 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
608 IXGBE_WRITE_FLUSH(hw);
613 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
614 * @hw: pointer to hardware structure
616 * The base drivers may require better control over SFP+ module
617 * PHY states. This includes selectively turning on the Tx
618 * laser on the PHY, effectively starting physical link.
620 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
622 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
624 /* Enable tx laser; allow 100ms to light up */
625 esdp_reg &= ~IXGBE_ESDP_SDP3;
626 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
627 IXGBE_WRITE_FLUSH(hw);
632 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
633 * @hw: pointer to hardware structure
635 * When the driver changes the link speeds that it can support,
636 * it sets autotry_restart to true to indicate that we need to
637 * initiate a new autotry session with the link partner. To do
638 * so, we set the speed then disable and re-enable the tx laser, to
639 * alert the link partner that it also needs to restart autotry on its
640 * end. This is consistent with true clause 37 autoneg, which also
641 * involves a loss of signal.
643 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
645 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
647 /* Blocked by MNG FW so bail */
648 if (ixgbe_check_reset_blocked(hw))
651 if (hw->mac.autotry_restart) {
652 ixgbe_disable_tx_laser_multispeed_fiber(hw);
653 ixgbe_enable_tx_laser_multispeed_fiber(hw);
654 hw->mac.autotry_restart = false;
660 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
661 * @hw: pointer to hardware structure
662 * @speed: new link speed
663 * @autoneg_wait_to_complete: true when waiting for completion is needed
665 * Set the link speed in the AUTOC register and restarts link.
667 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
668 ixgbe_link_speed speed,
669 bool autoneg_wait_to_complete)
671 s32 status = IXGBE_SUCCESS;
672 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
673 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
675 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
677 bool autoneg, link_up = false;
679 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
681 /* Mask off requested but non-supported speeds */
682 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
683 if (status != IXGBE_SUCCESS)
689 * Try each speed one by one, highest priority first. We do this in
690 * software because 10gb fiber doesn't support speed autonegotiation.
692 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
694 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
696 /* If we already have link at this speed, just jump out */
697 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
698 if (status != IXGBE_SUCCESS)
701 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
704 /* Set the module link speed */
705 switch (hw->phy.media_type) {
706 case ixgbe_media_type_fiber:
707 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
708 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
709 IXGBE_WRITE_FLUSH(hw);
712 DEBUGOUT("Unexpected media type.\n");
716 /* Allow module to change analog characteristics (1G->10G) */
719 status = ixgbe_setup_mac_link_82599(hw,
720 IXGBE_LINK_SPEED_10GB_FULL,
721 autoneg_wait_to_complete);
722 if (status != IXGBE_SUCCESS)
725 /* Flap the tx laser if it has not already been done */
726 ixgbe_flap_tx_laser(hw);
729 * Wait for the controller to acquire link. Per IEEE 802.3ap,
730 * Section 73.10.2, we may have to wait up to 500ms if KR is
731 * attempted. 82599 uses the same timing for 10g SFI.
733 for (i = 0; i < 5; i++) {
734 /* Wait for the link partner to also set speed */
737 /* If we have link, just jump out */
738 status = ixgbe_check_link(hw, &link_speed,
740 if (status != IXGBE_SUCCESS)
748 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
750 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
751 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
753 /* If we already have link at this speed, just jump out */
754 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
755 if (status != IXGBE_SUCCESS)
758 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
761 /* Set the module link speed */
762 switch (hw->phy.media_type) {
763 case ixgbe_media_type_fiber:
764 esdp_reg &= ~IXGBE_ESDP_SDP5;
765 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
766 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
767 IXGBE_WRITE_FLUSH(hw);
770 DEBUGOUT("Unexpected media type.\n");
774 /* Allow module to change analog characteristics (10G->1G) */
777 status = ixgbe_setup_mac_link_82599(hw,
778 IXGBE_LINK_SPEED_1GB_FULL,
779 autoneg_wait_to_complete);
780 if (status != IXGBE_SUCCESS)
783 /* Flap the tx laser if it has not already been done */
784 ixgbe_flap_tx_laser(hw);
786 /* Wait for the link partner to also set speed */
789 /* If we have link, just jump out */
790 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
791 if (status != IXGBE_SUCCESS)
799 * We didn't get link. Configure back to the highest speed we tried,
800 * (if there was more than one). We call ourselves back with just the
801 * single highest speed that the user requested.
804 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
805 highest_link_speed, autoneg_wait_to_complete);
808 /* Set autoneg_advertised value based on input link speed */
809 hw->phy.autoneg_advertised = 0;
811 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
812 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
814 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
815 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
821 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
822 * @hw: pointer to hardware structure
823 * @speed: new link speed
824 * @autoneg_wait_to_complete: true when waiting for completion is needed
826 * Implements the Intel SmartSpeed algorithm.
828 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
829 ixgbe_link_speed speed,
830 bool autoneg_wait_to_complete)
832 s32 status = IXGBE_SUCCESS;
833 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
835 bool link_up = false;
836 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
838 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
840 /* Set autoneg_advertised value based on input link speed */
841 hw->phy.autoneg_advertised = 0;
843 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
844 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
846 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
847 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
849 if (speed & IXGBE_LINK_SPEED_100_FULL)
850 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
853 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
854 * autoneg advertisement if link is unable to be established at the
855 * highest negotiated rate. This can sometimes happen due to integrity
856 * issues with the physical media connection.
859 /* First, try to get link with full advertisement */
860 hw->phy.smart_speed_active = false;
861 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
862 status = ixgbe_setup_mac_link_82599(hw, speed,
863 autoneg_wait_to_complete);
864 if (status != IXGBE_SUCCESS)
868 * Wait for the controller to acquire link. Per IEEE 802.3ap,
869 * Section 73.10.2, we may have to wait up to 500ms if KR is
870 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
871 * Table 9 in the AN MAS.
873 for (i = 0; i < 5; i++) {
876 /* If we have link, just jump out */
877 status = ixgbe_check_link(hw, &link_speed, &link_up,
879 if (status != IXGBE_SUCCESS)
888 * We didn't get link. If we advertised KR plus one of KX4/KX
889 * (or BX4/BX), then disable KR and try again.
891 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
892 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
895 /* Turn SmartSpeed on to disable KR support */
896 hw->phy.smart_speed_active = true;
897 status = ixgbe_setup_mac_link_82599(hw, speed,
898 autoneg_wait_to_complete);
899 if (status != IXGBE_SUCCESS)
903 * Wait for the controller to acquire link. 600ms will allow for
904 * the AN link_fail_inhibit_timer as well for multiple cycles of
905 * parallel detect, both 10g and 1g. This allows for the maximum
906 * connect attempts as defined in the AN MAS table 73-7.
908 for (i = 0; i < 6; i++) {
911 /* If we have link, just jump out */
912 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
913 if (status != IXGBE_SUCCESS)
920 /* We didn't get link. Turn SmartSpeed back off. */
921 hw->phy.smart_speed_active = false;
922 status = ixgbe_setup_mac_link_82599(hw, speed,
923 autoneg_wait_to_complete);
926 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
927 DEBUGOUT("Smartspeed has downgraded the link speed "
928 "from the maximum advertised\n");
933 * ixgbe_setup_mac_link_82599 - Set MAC link speed
934 * @hw: pointer to hardware structure
935 * @speed: new link speed
936 * @autoneg_wait_to_complete: true when waiting for completion is needed
938 * Set the link speed in the AUTOC register and restarts link.
940 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
941 ixgbe_link_speed speed,
942 bool autoneg_wait_to_complete)
944 bool autoneg = false;
945 s32 status = IXGBE_SUCCESS;
946 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
947 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
948 u32 start_autoc = autoc;
950 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
951 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
952 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
955 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
956 bool got_lock = false;
958 DEBUGFUNC("ixgbe_setup_mac_link_82599");
960 /* Check to see if speed passed in is supported. */
961 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
965 speed &= link_capabilities;
967 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
968 status = IXGBE_ERR_LINK_SETUP;
972 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
973 if (hw->mac.orig_link_settings_stored)
974 orig_autoc = hw->mac.orig_autoc;
978 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
979 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
980 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
981 /* Set KX4/KX/KR support according to speed requested */
982 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
983 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
984 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
985 autoc |= IXGBE_AUTOC_KX4_SUPP;
986 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
987 (hw->phy.smart_speed_active == false))
988 autoc |= IXGBE_AUTOC_KR_SUPP;
990 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
991 autoc |= IXGBE_AUTOC_KX_SUPP;
992 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
993 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
994 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
995 /* Switch from 1G SFI to 10G SFI if requested */
996 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
997 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
998 autoc &= ~IXGBE_AUTOC_LMS_MASK;
999 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
1001 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
1002 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
1003 /* Switch from 10G SFI to 1G SFI if requested */
1004 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
1005 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
1006 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1008 autoc |= IXGBE_AUTOC_LMS_1G_AN;
1010 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
1014 if (autoc != start_autoc) {
1015 /* Need SW/FW semaphore around AUTOC writes if LESM is on,
1016 * likewise reset_pipeline requires us to hold this lock as
1017 * it also writes to AUTOC.
1019 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1020 status = hw->mac.ops.acquire_swfw_sync(hw,
1021 IXGBE_GSSR_MAC_CSR_SM);
1022 if (status != IXGBE_SUCCESS) {
1023 status = IXGBE_ERR_SWFW_SYNC;
1031 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
1032 ixgbe_reset_pipeline_82599(hw);
1035 hw->mac.ops.release_swfw_sync(hw,
1036 IXGBE_GSSR_MAC_CSR_SM);
1040 /* Only poll for autoneg to complete if specified to do so */
1041 if (autoneg_wait_to_complete) {
1042 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1043 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1044 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1045 links_reg = 0; /*Just in case Autoneg time=0*/
1046 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1048 IXGBE_READ_REG(hw, IXGBE_LINKS);
1049 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
1053 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
1055 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
1056 DEBUGOUT("Autoneg did not complete.\n");
1061 /* Add delay to filter out noises during initial link setup */
1070 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
1071 * @hw: pointer to hardware structure
1072 * @speed: new link speed
1073 * @autoneg_wait_to_complete: true if waiting is needed to complete
1075 * Restarts link on PHY and MAC based on settings passed in.
1077 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1078 ixgbe_link_speed speed,
1079 bool autoneg_wait_to_complete)
1083 DEBUGFUNC("ixgbe_setup_copper_link_82599");
1085 /* Setup the PHY according to input speed */
1086 status = hw->phy.ops.setup_link_speed(hw, speed,
1087 autoneg_wait_to_complete);
1089 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1095 * ixgbe_reset_hw_82599 - Perform hardware reset
1096 * @hw: pointer to hardware structure
1098 * Resets the hardware by resetting the transmit and receive units, masks
1099 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1102 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1104 ixgbe_link_speed link_speed;
1106 u32 ctrl, i, autoc, autoc2;
1107 bool link_up = false;
1109 DEBUGFUNC("ixgbe_reset_hw_82599");
1111 /* Call adapter stop to disable tx/rx and clear interrupts */
1112 status = hw->mac.ops.stop_adapter(hw);
1113 if (status != IXGBE_SUCCESS)
1116 /* flush pending Tx transactions */
1117 ixgbe_clear_tx_pending(hw);
1119 /* PHY ops must be identified and initialized prior to reset */
1121 /* Identify PHY and related function pointers */
1122 status = hw->phy.ops.init(hw);
1124 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1127 /* Setup SFP module if there is one present. */
1128 if (hw->phy.sfp_setup_needed) {
1129 status = hw->mac.ops.setup_sfp(hw);
1130 hw->phy.sfp_setup_needed = false;
1133 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1137 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1138 hw->phy.ops.reset(hw);
1142 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1143 * If link reset is used when link is up, it might reset the PHY when
1144 * mng is using it. If link is down or the flag to force full link
1145 * reset is set, then perform link reset.
1147 ctrl = IXGBE_CTRL_LNK_RST;
1148 if (!hw->force_full_reset) {
1149 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1151 ctrl = IXGBE_CTRL_RST;
1154 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1155 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1156 IXGBE_WRITE_FLUSH(hw);
1158 /* Poll for reset bit to self-clear meaning reset is complete */
1159 for (i = 0; i < 10; i++) {
1161 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1162 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1166 if (ctrl & IXGBE_CTRL_RST_MASK) {
1167 status = IXGBE_ERR_RESET_FAILED;
1168 DEBUGOUT("Reset polling failed to complete.\n");
1174 * Double resets are required for recovery from certain error
1175 * conditions. Between resets, it is necessary to stall to
1176 * allow time for any pending HW events to complete.
1178 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1179 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1184 * Store the original AUTOC/AUTOC2 values if they have not been
1185 * stored off yet. Otherwise restore the stored original
1186 * values since the reset operation sets back to defaults.
1188 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1189 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1191 /* Enable link if disabled in NVM */
1192 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1193 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1194 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1195 IXGBE_WRITE_FLUSH(hw);
1198 if (hw->mac.orig_link_settings_stored == false) {
1199 hw->mac.orig_autoc = autoc;
1200 hw->mac.orig_autoc2 = autoc2;
1201 hw->mac.orig_link_settings_stored = true;
1203 if (autoc != hw->mac.orig_autoc) {
1204 /* Need SW/FW semaphore around AUTOC writes if LESM is
1205 * on, likewise reset_pipeline requires us to hold
1206 * this lock as it also writes to AUTOC.
1208 bool got_lock = false;
1209 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1210 status = hw->mac.ops.acquire_swfw_sync(hw,
1211 IXGBE_GSSR_MAC_CSR_SM);
1212 if (status != IXGBE_SUCCESS) {
1213 status = IXGBE_ERR_SWFW_SYNC;
1220 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
1221 ixgbe_reset_pipeline_82599(hw);
1224 hw->mac.ops.release_swfw_sync(hw,
1225 IXGBE_GSSR_MAC_CSR_SM);
1228 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1229 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1230 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1231 autoc2 |= (hw->mac.orig_autoc2 &
1232 IXGBE_AUTOC2_UPPER_MASK);
1233 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1237 /* Store the permanent mac address */
1238 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1241 * Store MAC address from RAR0, clear receive address registers, and
1242 * clear the multicast table. Also reset num_rar_entries to 128,
1243 * since we modify this value when programming the SAN MAC address.
1245 hw->mac.num_rar_entries = 128;
1246 hw->mac.ops.init_rx_addrs(hw);
1248 /* Store the permanent SAN mac address */
1249 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1251 /* Add the SAN MAC address to the RAR only if it's a valid address */
1252 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1253 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1254 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1256 /* Save the SAN MAC RAR index */
1257 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1259 /* Reserve the last RAR for the SAN MAC address */
1260 hw->mac.num_rar_entries--;
1263 /* Store the alternative WWNN/WWPN prefix */
1264 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1265 &hw->mac.wwpn_prefix);
1272 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1273 * @hw: pointer to hardware structure
1275 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1278 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1279 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1281 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1284 * Before starting reinitialization process,
1285 * FDIRCMD.CMD must be zero.
1287 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1288 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1289 IXGBE_FDIRCMD_CMD_MASK))
1293 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1294 DEBUGOUT("Flow Director previous command isn't complete, "
1295 "aborting table re-initialization.\n");
1296 return IXGBE_ERR_FDIR_REINIT_FAILED;
1299 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1300 IXGBE_WRITE_FLUSH(hw);
1302 * 82599 adapters flow director init flow cannot be restarted,
1303 * Workaround 82599 silicon errata by performing the following steps
1304 * before re-writing the FDIRCTRL control register with the same value.
1305 * - write 1 to bit 8 of FDIRCMD register &
1306 * - write 0 to bit 8 of FDIRCMD register
1308 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1309 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1310 IXGBE_FDIRCMD_CLEARHT));
1311 IXGBE_WRITE_FLUSH(hw);
1312 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1313 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1314 ~IXGBE_FDIRCMD_CLEARHT));
1315 IXGBE_WRITE_FLUSH(hw);
1317 * Clear FDIR Hash register to clear any leftover hashes
1318 * waiting to be programmed.
1320 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1321 IXGBE_WRITE_FLUSH(hw);
1323 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1324 IXGBE_WRITE_FLUSH(hw);
1326 /* Poll init-done after we write FDIRCTRL register */
1327 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1328 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1329 IXGBE_FDIRCTRL_INIT_DONE)
1333 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1334 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1335 return IXGBE_ERR_FDIR_REINIT_FAILED;
1338 /* Clear FDIR statistics registers (read to clear) */
1339 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1340 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1341 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1342 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1343 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1345 return IXGBE_SUCCESS;
1349 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1350 * @hw: pointer to hardware structure
1351 * @fdirctrl: value to write to flow director control register
1353 STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1357 DEBUGFUNC("ixgbe_fdir_enable_82599");
1359 /* Prime the keys for hashing */
1360 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1361 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1364 * Poll init-done after we write the register. Estimated times:
1365 * 10G: PBALLOC = 11b, timing is 60us
1366 * 1G: PBALLOC = 11b, timing is 600us
1367 * 100M: PBALLOC = 11b, timing is 6ms
1369 * Multiple these timings by 4 if under full Rx load
1371 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1372 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1373 * this might not finish in our poll time, but we can live with that
1376 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1377 IXGBE_WRITE_FLUSH(hw);
1378 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1379 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1380 IXGBE_FDIRCTRL_INIT_DONE)
1385 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1386 DEBUGOUT("Flow Director poll time exceeded!\n");
1390 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1391 * @hw: pointer to hardware structure
1392 * @fdirctrl: value to write to flow director control register, initially
1393 * contains just the value of the Rx packet buffer allocation
1395 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1397 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1400 * Continue setup of fdirctrl register bits:
1401 * Move the flexible bytes to use the ethertype - shift 6 words
1402 * Set the maximum length per hash bucket to 0xA filters
1403 * Send interrupt when 64 filters are left
1405 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1406 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1407 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1409 /* write hashes and fdirctrl register, poll for completion */
1410 ixgbe_fdir_enable_82599(hw, fdirctrl);
1412 return IXGBE_SUCCESS;
1416 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1417 * @hw: pointer to hardware structure
1418 * @fdirctrl: value to write to flow director control register, initially
1419 * contains just the value of the Rx packet buffer allocation
1421 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1423 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1426 * Continue setup of fdirctrl register bits:
1427 * Turn perfect match filtering on
1428 * Report hash in RSS field of Rx wb descriptor
1429 * Initialize the drop queue
1430 * Move the flexible bytes to use the ethertype - shift 6 words
1431 * Set the maximum length per hash bucket to 0xA filters
1432 * Send interrupt when 64 (0x4 * 16) filters are left
1434 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1435 IXGBE_FDIRCTRL_REPORT_STATUS |
1436 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1437 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1438 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1439 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1442 /* write hashes and fdirctrl register, poll for completion */
1443 ixgbe_fdir_enable_82599(hw, fdirctrl);
1445 return IXGBE_SUCCESS;
1449 * These defines allow us to quickly generate all of the necessary instructions
1450 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1451 * for values 0 through 15
1453 #define IXGBE_ATR_COMMON_HASH_KEY \
1454 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1455 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1458 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1459 common_hash ^= lo_hash_dword >> n; \
1460 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1461 bucket_hash ^= lo_hash_dword >> n; \
1462 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1463 sig_hash ^= lo_hash_dword << (16 - n); \
1464 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1465 common_hash ^= hi_hash_dword >> n; \
1466 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1467 bucket_hash ^= hi_hash_dword >> n; \
1468 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1469 sig_hash ^= hi_hash_dword << (16 - n); \
1473 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1474 * @stream: input bitstream to compute the hash on
1476 * This function is almost identical to the function above but contains
1477 * several optomizations such as unwinding all of the loops, letting the
1478 * compiler work out all of the conditional ifs since the keys are static
1479 * defines, and computing two keys at once since the hashed dword stream
1480 * will be the same for both keys.
1482 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1483 union ixgbe_atr_hash_dword common)
1485 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1486 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1488 /* record the flow_vm_vlan bits as they are a key part to the hash */
1489 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1491 /* generate common hash dword */
1492 hi_hash_dword = IXGBE_NTOHL(common.dword);
1494 /* low dword is word swapped version of common */
1495 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1497 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1498 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1500 /* Process bits 0 and 16 */
1501 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1504 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1505 * delay this because bit 0 of the stream should not be processed
1506 * so we do not add the vlan until after bit 0 was processed
1508 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1510 /* Process remaining 30 bit of the key */
1511 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1512 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1513 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1514 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1515 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1516 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1517 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1518 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1519 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1520 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1521 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1522 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1523 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1524 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1525 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1527 /* combine common_hash result with signature and bucket hashes */
1528 bucket_hash ^= common_hash;
1529 bucket_hash &= IXGBE_ATR_HASH_MASK;
1531 sig_hash ^= common_hash << 16;
1532 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1534 /* return completed signature hash */
1535 return sig_hash ^ bucket_hash;
1539 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1540 * @hw: pointer to hardware structure
1541 * @input: unique input dword
1542 * @common: compressed common input dword
1543 * @queue: queue index to direct traffic to
1545 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1546 union ixgbe_atr_hash_dword input,
1547 union ixgbe_atr_hash_dword common,
1553 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1556 * Get the flow_type in order to program FDIRCMD properly
1557 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1558 * fifth is FDIRCMD.TUNNEL_FILTER
1560 switch (input.formatted.flow_type) {
1561 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1562 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1563 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1564 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1565 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1566 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1569 DEBUGOUT(" Error on flow type input\n");
1570 return IXGBE_ERR_CONFIG;
1573 /* configure FDIRCMD register */
1574 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1575 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1576 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1577 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1580 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1581 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1583 fdirhashcmd = (u64)fdircmd << 32;
1584 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1585 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1587 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1589 return IXGBE_SUCCESS;
1592 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1595 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1596 bucket_hash ^= lo_hash_dword >> n; \
1597 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1598 bucket_hash ^= hi_hash_dword >> n; \
1602 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1603 * @atr_input: input bitstream to compute the hash on
1604 * @input_mask: mask for the input bitstream
1606 * This function serves two main purposes. First it applys the input_mask
1607 * to the atr_input resulting in a cleaned up atr_input data stream.
1608 * Secondly it computes the hash and stores it in the bkt_hash field at
1609 * the end of the input byte stream. This way it will be available for
1610 * future use without needing to recompute the hash.
1612 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1613 union ixgbe_atr_input *input_mask)
1616 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1617 u32 bucket_hash = 0;
1619 /* Apply masks to input data */
1620 input->dword_stream[0] &= input_mask->dword_stream[0];
1621 input->dword_stream[1] &= input_mask->dword_stream[1];
1622 input->dword_stream[2] &= input_mask->dword_stream[2];
1623 input->dword_stream[3] &= input_mask->dword_stream[3];
1624 input->dword_stream[4] &= input_mask->dword_stream[4];
1625 input->dword_stream[5] &= input_mask->dword_stream[5];
1626 input->dword_stream[6] &= input_mask->dword_stream[6];
1627 input->dword_stream[7] &= input_mask->dword_stream[7];
1628 input->dword_stream[8] &= input_mask->dword_stream[8];
1629 input->dword_stream[9] &= input_mask->dword_stream[9];
1630 input->dword_stream[10] &= input_mask->dword_stream[10];
1632 /* record the flow_vm_vlan bits as they are a key part to the hash */
1633 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1635 /* generate common hash dword */
1636 hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
1637 input->dword_stream[2] ^
1638 input->dword_stream[3] ^
1639 input->dword_stream[4] ^
1640 input->dword_stream[5] ^
1641 input->dword_stream[6] ^
1642 input->dword_stream[7] ^
1643 input->dword_stream[8] ^
1644 input->dword_stream[9] ^
1645 input->dword_stream[10]);
1647 /* low dword is word swapped version of common */
1648 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1650 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1651 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1653 /* Process bits 0 and 16 */
1654 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1657 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1658 * delay this because bit 0 of the stream should not be processed
1659 * so we do not add the vlan until after bit 0 was processed
1661 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1663 /* Process remaining 30 bit of the key */
1664 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1665 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1666 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1667 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1668 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1669 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1670 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1671 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1672 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1673 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1674 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1675 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1676 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1677 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1678 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1681 * Limit hash to 13 bits since max bucket count is 8K.
1682 * Store result at the end of the input stream.
1684 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1688 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1689 * @input_mask: mask to be bit swapped
1691 * The source and destination port masks for flow director are bit swapped
1692 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1693 * generate a correctly swapped value we need to bit swap the mask and that
1694 * is what is accomplished by this function.
1696 STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1698 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1699 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1700 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1701 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1702 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1703 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1704 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1708 * These two macros are meant to address the fact that we have registers
1709 * that are either all or in part big-endian. As a result on big-endian
1710 * systems we will end up byte swapping the value to little-endian before
1711 * it is byte swapped again and written to the hardware in the original
1712 * big-endian format.
1714 #define IXGBE_STORE_AS_BE32(_value) \
1715 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1716 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1718 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1719 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1721 #define IXGBE_STORE_AS_BE16(_value) \
1722 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1724 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1725 union ixgbe_atr_input *input_mask)
1727 /* mask IPv6 since it is currently not supported */
1728 u32 fdirm = IXGBE_FDIRM_DIPv6;
1730 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1733 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1734 * are zero, then assume a full mask for that field. Also assume that
1735 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1736 * cannot be masked out in this implementation.
1738 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1742 /* verify bucket hash is cleared on hash generation */
1743 if (input_mask->formatted.bkt_hash)
1744 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1746 /* Program FDIRM and verify partial masks */
1747 switch (input_mask->formatted.vm_pool & 0x7F) {
1749 fdirm |= IXGBE_FDIRM_POOL;
1753 DEBUGOUT(" Error on vm pool mask\n");
1754 return IXGBE_ERR_CONFIG;
1757 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1759 fdirm |= IXGBE_FDIRM_L4P;
1760 if (input_mask->formatted.dst_port ||
1761 input_mask->formatted.src_port) {
1762 DEBUGOUT(" Error on src/dst port mask\n");
1763 return IXGBE_ERR_CONFIG;
1765 case IXGBE_ATR_L4TYPE_MASK:
1768 DEBUGOUT(" Error on flow type mask\n");
1769 return IXGBE_ERR_CONFIG;
1772 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1774 /* mask VLAN ID, fall through to mask VLAN priority */
1775 fdirm |= IXGBE_FDIRM_VLANID;
1777 /* mask VLAN priority */
1778 fdirm |= IXGBE_FDIRM_VLANP;
1781 /* mask VLAN ID only, fall through */
1782 fdirm |= IXGBE_FDIRM_VLANID;
1784 /* no VLAN fields masked */
1787 DEBUGOUT(" Error on VLAN mask\n");
1788 return IXGBE_ERR_CONFIG;
1791 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1793 /* Mask Flex Bytes, fall through */
1794 fdirm |= IXGBE_FDIRM_FLEX;
1798 DEBUGOUT(" Error on flexible byte mask\n");
1799 return IXGBE_ERR_CONFIG;
1803 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1804 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1806 /* store the TCP/UDP port masks, bit reversed from port layout */
1807 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1809 /* write both the same so that UDP and TCP use the same mask */
1810 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1811 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1813 /* store source and destination IP masks (big-enian) */
1814 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1815 ~input_mask->formatted.src_ip[0]);
1816 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1817 ~input_mask->formatted.dst_ip[0]);
1819 return IXGBE_SUCCESS;
1822 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1823 union ixgbe_atr_input *input,
1824 u16 soft_id, u8 queue)
1826 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1828 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1830 /* currently IPv6 is not supported, must be programmed with 0 */
1831 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1832 input->formatted.src_ip[0]);
1833 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1834 input->formatted.src_ip[1]);
1835 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1836 input->formatted.src_ip[2]);
1838 /* record the source address (big-endian) */
1839 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1841 /* record the first 32 bits of the destination address (big-endian) */
1842 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1844 /* record source and destination port (little-endian)*/
1845 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1846 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1847 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1848 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1850 /* record vlan (little-endian) and flex_bytes(big-endian) */
1851 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1852 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1853 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1854 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1857 /* configure FDIRHASH register */
1858 fdirhash = input->formatted.bkt_hash;
1859 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1860 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1863 * flush all previous writes to make certain registers are
1864 * programmed prior to issuing the command
1866 IXGBE_WRITE_FLUSH(hw);
1868 /* configure FDIRCMD register */
1869 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1870 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1871 if (queue == IXGBE_FDIR_DROP_QUEUE)
1872 fdircmd |= IXGBE_FDIRCMD_DROP;
1873 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1874 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1875 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1877 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1879 return IXGBE_SUCCESS;
1882 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1883 union ixgbe_atr_input *input,
1889 s32 err = IXGBE_SUCCESS;
1891 /* configure FDIRHASH register */
1892 fdirhash = input->formatted.bkt_hash;
1893 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1894 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1896 /* flush hash to HW */
1897 IXGBE_WRITE_FLUSH(hw);
1899 /* Query if filter is present */
1900 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1902 for (retry_count = 10; retry_count; retry_count--) {
1903 /* allow 10us for query to process */
1905 /* verify query completed successfully */
1906 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1907 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1912 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1914 /* if filter exists in hardware then remove it */
1915 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1916 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1917 IXGBE_WRITE_FLUSH(hw);
1918 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1919 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1926 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1927 * @hw: pointer to hardware structure
1928 * @input: input bitstream
1929 * @input_mask: mask for the input bitstream
1930 * @soft_id: software index for the filters
1931 * @queue: queue index to direct traffic to
1933 * Note that the caller to this function must lock before calling, since the
1934 * hardware writes must be protected from one another.
1936 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1937 union ixgbe_atr_input *input,
1938 union ixgbe_atr_input *input_mask,
1939 u16 soft_id, u8 queue)
1941 s32 err = IXGBE_ERR_CONFIG;
1943 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1946 * Check flow_type formatting, and bail out before we touch the hardware
1947 * if there's a configuration issue
1949 switch (input->formatted.flow_type) {
1950 case IXGBE_ATR_FLOW_TYPE_IPV4:
1951 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1952 if (input->formatted.dst_port || input->formatted.src_port) {
1953 DEBUGOUT(" Error on src/dst port\n");
1954 return IXGBE_ERR_CONFIG;
1957 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1958 if (input->formatted.dst_port || input->formatted.src_port) {
1959 DEBUGOUT(" Error on src/dst port\n");
1960 return IXGBE_ERR_CONFIG;
1962 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1963 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1964 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
1965 IXGBE_ATR_L4TYPE_MASK;
1968 DEBUGOUT(" Error on flow type input\n");
1972 /* program input mask into the HW */
1973 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
1977 /* apply mask and compute/store hash */
1978 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
1980 /* program filters to filter memory */
1981 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
1986 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1987 * @hw: pointer to hardware structure
1988 * @reg: analog register to read
1991 * Performs read operation to Omer analog register specified.
1993 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1997 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
1999 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
2001 IXGBE_WRITE_FLUSH(hw);
2003 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
2004 *val = (u8)core_ctl;
2006 return IXGBE_SUCCESS;
2010 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2011 * @hw: pointer to hardware structure
2012 * @reg: atlas register to write
2013 * @val: value to write
2015 * Performs write operation to Omer analog register specified.
2017 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2021 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
2023 core_ctl = (reg << 8) | val;
2024 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2025 IXGBE_WRITE_FLUSH(hw);
2028 return IXGBE_SUCCESS;
2032 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2033 * @hw: pointer to hardware structure
2035 * Starts the hardware using the generic start_hw function
2036 * and the generation start_hw function.
2037 * Then performs revision-specific operations, if any.
2039 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2041 s32 ret_val = IXGBE_SUCCESS;
2043 DEBUGFUNC("ixgbe_start_hw_82599");
2045 ret_val = ixgbe_start_hw_generic(hw);
2046 if (ret_val != IXGBE_SUCCESS)
2049 ret_val = ixgbe_start_hw_gen2(hw);
2050 if (ret_val != IXGBE_SUCCESS)
2053 /* We need to run link autotry after the driver loads */
2054 hw->mac.autotry_restart = true;
2056 if (ret_val == IXGBE_SUCCESS)
2057 ret_val = ixgbe_verify_fw_version_82599(hw);
2063 * ixgbe_identify_phy_82599 - Get physical layer module
2064 * @hw: pointer to hardware structure
2066 * Determines the physical layer module found on the current adapter.
2067 * If PHY already detected, maintains current PHY type in hw struct,
2068 * otherwise executes the PHY detection routine.
2070 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2074 DEBUGFUNC("ixgbe_identify_phy_82599");
2076 /* Detect PHY if not unknown - returns success if already detected. */
2077 status = ixgbe_identify_phy_generic(hw);
2078 if (status != IXGBE_SUCCESS) {
2079 /* 82599 10GBASE-T requires an external PHY */
2080 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2083 status = ixgbe_identify_module_generic(hw);
2086 /* Set PHY type none if no PHY detected */
2087 if (hw->phy.type == ixgbe_phy_unknown) {
2088 hw->phy.type = ixgbe_phy_none;
2089 status = IXGBE_SUCCESS;
2092 /* Return error if SFP module has been detected but is not supported */
2093 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2094 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
2101 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2102 * @hw: pointer to hardware structure
2104 * Determines physical layer capabilities of the current configuration.
2106 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2108 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2109 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2110 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2111 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2112 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2113 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2114 u16 ext_ability = 0;
2115 u8 comp_codes_10g = 0;
2116 u8 comp_codes_1g = 0;
2118 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2120 hw->phy.ops.identify(hw);
2122 switch (hw->phy.type) {
2124 case ixgbe_phy_cu_unknown:
2125 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2126 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2127 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2128 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2129 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2130 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2131 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
2132 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2138 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2139 case IXGBE_AUTOC_LMS_1G_AN:
2140 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2141 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2142 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2143 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2146 /* SFI mode so read SFP module */
2149 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2150 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2151 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2152 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2153 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2154 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2155 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2158 case IXGBE_AUTOC_LMS_10G_SERIAL:
2159 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2160 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2162 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2165 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2166 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2167 if (autoc & IXGBE_AUTOC_KX_SUPP)
2168 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2169 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2170 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2171 if (autoc & IXGBE_AUTOC_KR_SUPP)
2172 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2181 /* SFP check must be done last since DA modules are sometimes used to
2182 * test KR mode - we need to id KR mode correctly before SFP module.
2183 * Call identify_sfp because the pluggable module may have changed */
2184 hw->phy.ops.identify_sfp(hw);
2185 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2188 switch (hw->phy.type) {
2189 case ixgbe_phy_sfp_passive_tyco:
2190 case ixgbe_phy_sfp_passive_unknown:
2191 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2193 case ixgbe_phy_sfp_ftl_active:
2194 case ixgbe_phy_sfp_active_unknown:
2195 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2197 case ixgbe_phy_sfp_avago:
2198 case ixgbe_phy_sfp_ftl:
2199 case ixgbe_phy_sfp_intel:
2200 case ixgbe_phy_sfp_unknown:
2201 hw->phy.ops.read_i2c_eeprom(hw,
2202 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2203 hw->phy.ops.read_i2c_eeprom(hw,
2204 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2205 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2206 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2207 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2208 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2209 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2210 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2211 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
2212 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
2219 return physical_layer;
2223 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2224 * @hw: pointer to hardware structure
2225 * @regval: register value to write to RXCTRL
2227 * Enables the Rx DMA unit for 82599
2229 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2232 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2235 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2236 * If traffic is incoming before we enable the Rx unit, it could hang
2237 * the Rx DMA unit. Therefore, make sure the security engine is
2238 * completely disabled prior to enabling the Rx unit.
2241 hw->mac.ops.disable_sec_rx_path(hw);
2243 if (regval & IXGBE_RXCTRL_RXEN)
2244 ixgbe_enable_rx(hw);
2246 ixgbe_disable_rx(hw);
2248 hw->mac.ops.enable_sec_rx_path(hw);
2250 return IXGBE_SUCCESS;
2254 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2255 * @hw: pointer to hardware structure
2257 * Verifies that installed the firmware version is 0.6 or higher
2258 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2260 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2261 * if the FW version is not supported.
2263 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2265 s32 status = IXGBE_ERR_EEPROM_VERSION;
2266 u16 fw_offset, fw_ptp_cfg_offset;
2269 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2271 /* firmware check is only necessary for SFI devices */
2272 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2273 status = IXGBE_SUCCESS;
2274 goto fw_version_out;
2277 /* get the offset to the Firmware Module block */
2278 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
2279 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2280 "eeprom read at offset %d failed", IXGBE_FW_PTR);
2281 return IXGBE_ERR_EEPROM_VERSION;
2284 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2285 goto fw_version_out;
2287 /* get the offset to the Pass Through Patch Configuration block */
2288 if (hw->eeprom.ops.read(hw, (fw_offset +
2289 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2290 &fw_ptp_cfg_offset)) {
2291 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2292 "eeprom read at offset %d failed",
2294 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);
2295 return IXGBE_ERR_EEPROM_VERSION;
2298 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2299 goto fw_version_out;
2301 /* get the firmware version */
2302 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2303 IXGBE_FW_PATCH_VERSION_4), &fw_version)) {
2304 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2305 "eeprom read at offset %d failed",
2306 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);
2307 return IXGBE_ERR_EEPROM_VERSION;
2310 if (fw_version > 0x5)
2311 status = IXGBE_SUCCESS;
2318 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2319 * @hw: pointer to hardware structure
2321 * Returns true if the LESM FW module is present and enabled. Otherwise
2322 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2324 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2326 bool lesm_enabled = false;
2327 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2330 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2332 /* get the offset to the Firmware Module block */
2333 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2335 if ((status != IXGBE_SUCCESS) ||
2336 (fw_offset == 0) || (fw_offset == 0xFFFF))
2339 /* get the offset to the LESM Parameters block */
2340 status = hw->eeprom.ops.read(hw, (fw_offset +
2341 IXGBE_FW_LESM_PARAMETERS_PTR),
2342 &fw_lesm_param_offset);
2344 if ((status != IXGBE_SUCCESS) ||
2345 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2348 /* get the lesm state word */
2349 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2350 IXGBE_FW_LESM_STATE_1),
2353 if ((status == IXGBE_SUCCESS) &&
2354 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2355 lesm_enabled = true;
2358 return lesm_enabled;
2362 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2363 * fastest available method
2365 * @hw: pointer to hardware structure
2366 * @offset: offset of word in EEPROM to read
2367 * @words: number of words
2368 * @data: word(s) read from the EEPROM
2370 * Retrieves 16 bit word(s) read from EEPROM
2372 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2373 u16 words, u16 *data)
2375 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2376 s32 ret_val = IXGBE_ERR_CONFIG;
2378 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2381 * If EEPROM is detected and can be addressed using 14 bits,
2382 * use EERD otherwise use bit bang
2384 if ((eeprom->type == ixgbe_eeprom_spi) &&
2385 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2386 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2389 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2397 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2398 * fastest available method
2400 * @hw: pointer to hardware structure
2401 * @offset: offset of word in the EEPROM to read
2402 * @data: word read from the EEPROM
2404 * Reads a 16 bit word from the EEPROM
2406 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2407 u16 offset, u16 *data)
2409 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2410 s32 ret_val = IXGBE_ERR_CONFIG;
2412 DEBUGFUNC("ixgbe_read_eeprom_82599");
2415 * If EEPROM is detected and can be addressed using 14 bits,
2416 * use EERD otherwise use bit bang
2418 if ((eeprom->type == ixgbe_eeprom_spi) &&
2419 (offset <= IXGBE_EERD_MAX_ADDR))
2420 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2422 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2428 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2430 * @hw: pointer to hardware structure
2432 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2433 * full pipeline reset
2435 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2437 s32 i, autoc_reg, autoc2_reg, ret_val;
2440 /* Enable link if disabled in NVM */
2441 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2442 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2443 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2444 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2445 IXGBE_WRITE_FLUSH(hw);
2448 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2449 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2450 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2451 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
2452 /* Wait for AN to leave state 0 */
2453 for (i = 0; i < 10; i++) {
2455 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2456 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2460 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2461 DEBUGOUT("auto negotiation not completed\n");
2462 ret_val = IXGBE_ERR_RESET_FAILED;
2463 goto reset_pipeline_out;
2466 ret_val = IXGBE_SUCCESS;
2469 /* Write AUTOC register with original LMS field and Restart_AN */
2470 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2471 IXGBE_WRITE_FLUSH(hw);