1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82599.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
39 #ident "$Id: ixgbe_82599.c,v 1.301 2012/11/08 11:33:27 jtkirshe Exp $"
41 #define IXGBE_82599_MAX_TX_QUEUES 128
42 #define IXGBE_82599_MAX_RX_QUEUES 128
43 #define IXGBE_82599_RAR_ENTRIES 128
44 #define IXGBE_82599_MC_TBL_SIZE 128
45 #define IXGBE_82599_VFT_TBL_SIZE 128
46 #define IXGBE_82599_RX_PB_SIZE 512
48 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
49 ixgbe_link_speed speed,
50 bool autoneg_wait_to_complete);
51 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
53 u16 offset, u16 *data);
54 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
55 u16 words, u16 *data);
57 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
59 u32 fwsm, manc, factps;
61 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
62 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
65 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
66 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
69 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
70 if (factps & IXGBE_FACTPS_MNGCG)
76 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
78 struct ixgbe_mac_info *mac = &hw->mac;
80 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
83 * enable the laser control functions for SFP+ fiber
86 if ((mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
87 !ixgbe_mng_enabled(hw)) {
88 mac->ops.disable_tx_laser =
89 &ixgbe_disable_tx_laser_multispeed_fiber;
90 mac->ops.enable_tx_laser =
91 &ixgbe_enable_tx_laser_multispeed_fiber;
92 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
95 mac->ops.disable_tx_laser = NULL;
96 mac->ops.enable_tx_laser = NULL;
97 mac->ops.flap_tx_laser = NULL;
100 if (hw->phy.multispeed_fiber) {
101 /* Set up dual speed SFP+ support */
102 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
104 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
105 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
106 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
107 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
108 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
110 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
116 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
117 * @hw: pointer to hardware structure
119 * Initialize any function pointers that were not able to be
120 * set during init_shared_code because the PHY/SFP type was
121 * not known. Perform the SFP init if necessary.
124 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
126 struct ixgbe_mac_info *mac = &hw->mac;
127 struct ixgbe_phy_info *phy = &hw->phy;
128 s32 ret_val = IXGBE_SUCCESS;
130 DEBUGFUNC("ixgbe_init_phy_ops_82599");
132 /* Identify the PHY or SFP module */
133 ret_val = phy->ops.identify(hw);
134 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
135 goto init_phy_ops_out;
137 /* Setup function pointers based on detected SFP module and speeds */
138 ixgbe_init_mac_link_ops_82599(hw);
139 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
140 hw->phy.ops.reset = NULL;
142 /* If copper media, overwrite with copper function pointers */
143 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
144 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
145 mac->ops.get_link_capabilities =
146 &ixgbe_get_copper_link_capabilities_generic;
149 /* Set necessary function pointers based on phy type */
150 switch (hw->phy.type) {
152 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
153 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
154 phy->ops.get_firmware_version =
155 &ixgbe_get_phy_firmware_version_tnx;
164 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
166 s32 ret_val = IXGBE_SUCCESS;
167 u16 list_offset, data_offset, data_value;
168 bool got_lock = false;
170 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
172 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
173 ixgbe_init_mac_link_ops_82599(hw);
175 hw->phy.ops.reset = NULL;
177 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
179 if (ret_val != IXGBE_SUCCESS)
182 /* PHY config will finish before releasing the semaphore */
183 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
184 IXGBE_GSSR_MAC_CSR_SM);
185 if (ret_val != IXGBE_SUCCESS) {
186 ret_val = IXGBE_ERR_SWFW_SYNC;
190 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
191 while (data_value != 0xffff) {
192 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
193 IXGBE_WRITE_FLUSH(hw);
194 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
197 /* Release the semaphore */
198 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
199 /* Delay obtaining semaphore again to allow FW access */
200 msec_delay(hw->eeprom.semaphore_delay);
202 /* Need SW/FW semaphore around AUTOC writes if LESM on,
203 * likewise reset_pipeline requires lock as it also writes
206 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
207 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
208 IXGBE_GSSR_MAC_CSR_SM);
209 if (ret_val != IXGBE_SUCCESS) {
210 ret_val = IXGBE_ERR_SWFW_SYNC;
217 /* Restart DSP and set SFI mode */
218 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
219 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL));
221 ret_val = ixgbe_reset_pipeline_82599(hw);
224 hw->mac.ops.release_swfw_sync(hw,
225 IXGBE_GSSR_MAC_CSR_SM);
230 DEBUGOUT("sfp module setup not complete\n");
231 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
242 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
243 * @hw: pointer to hardware structure
245 * Initialize the function pointers and assign the MAC type for 82599.
246 * Does not touch the hardware.
249 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
251 struct ixgbe_mac_info *mac = &hw->mac;
252 struct ixgbe_phy_info *phy = &hw->phy;
253 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
256 DEBUGFUNC("ixgbe_init_ops_82599");
258 ret_val = ixgbe_init_phy_ops_generic(hw);
259 ret_val = ixgbe_init_ops_generic(hw);
262 phy->ops.identify = &ixgbe_identify_phy_82599;
263 phy->ops.init = &ixgbe_init_phy_ops_82599;
266 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
267 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
268 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
269 mac->ops.get_supported_physical_layer =
270 &ixgbe_get_supported_physical_layer_82599;
271 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
272 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
273 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
274 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
275 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
276 mac->ops.start_hw = &ixgbe_start_hw_82599;
277 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
278 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
279 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
280 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
281 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
283 /* RAR, Multicast, VLAN */
284 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
285 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
286 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
287 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
288 mac->rar_highwater = 1;
289 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
290 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
291 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
292 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
293 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
294 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
295 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
298 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
299 mac->ops.check_link = &ixgbe_check_mac_link_generic;
300 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
301 ixgbe_init_mac_link_ops_82599(hw);
303 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
304 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
305 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
306 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
307 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
308 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
309 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
311 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
312 IXGBE_FWSM_MODE_MASK) ? true : false;
314 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
317 eeprom->ops.read = &ixgbe_read_eeprom_82599;
318 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
320 /* Manageability interface */
321 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
324 mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
330 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
331 * @hw: pointer to hardware structure
332 * @speed: pointer to link speed
333 * @autoneg: true when autoneg or autotry is enabled
335 * Determines the link capabilities by reading the AUTOC register.
337 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
338 ixgbe_link_speed *speed,
341 s32 status = IXGBE_SUCCESS;
344 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
347 /* Check if 1G SFP module. */
348 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
349 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
350 #ifdef SUPPORT_1000BASE_LX
351 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
352 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
354 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
355 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
356 *speed = IXGBE_LINK_SPEED_1GB_FULL;
362 * Determine link capabilities based on the stored value of AUTOC,
363 * which represents EEPROM defaults. If AUTOC value has not
364 * been stored, use the current register values.
366 if (hw->mac.orig_link_settings_stored)
367 autoc = hw->mac.orig_autoc;
369 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
371 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
372 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
373 *speed = IXGBE_LINK_SPEED_1GB_FULL;
377 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
378 *speed = IXGBE_LINK_SPEED_10GB_FULL;
382 case IXGBE_AUTOC_LMS_1G_AN:
383 *speed = IXGBE_LINK_SPEED_1GB_FULL;
387 case IXGBE_AUTOC_LMS_10G_SERIAL:
388 *speed = IXGBE_LINK_SPEED_10GB_FULL;
392 case IXGBE_AUTOC_LMS_KX4_KX_KR:
393 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
394 *speed = IXGBE_LINK_SPEED_UNKNOWN;
395 if (autoc & IXGBE_AUTOC_KR_SUPP)
396 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
397 if (autoc & IXGBE_AUTOC_KX4_SUPP)
398 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
399 if (autoc & IXGBE_AUTOC_KX_SUPP)
400 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
404 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
405 *speed = IXGBE_LINK_SPEED_100_FULL;
406 if (autoc & IXGBE_AUTOC_KR_SUPP)
407 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
408 if (autoc & IXGBE_AUTOC_KX4_SUPP)
409 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
410 if (autoc & IXGBE_AUTOC_KX_SUPP)
411 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
415 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
416 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
421 status = IXGBE_ERR_LINK_SETUP;
426 if (hw->phy.multispeed_fiber) {
427 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
428 IXGBE_LINK_SPEED_1GB_FULL;
438 * ixgbe_get_media_type_82599 - Get media type
439 * @hw: pointer to hardware structure
441 * Returns the media type (fiber, copper, backplane)
443 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
445 enum ixgbe_media_type media_type;
447 DEBUGFUNC("ixgbe_get_media_type_82599");
449 /* Detect if there is a copper PHY attached. */
450 switch (hw->phy.type) {
451 case ixgbe_phy_cu_unknown:
453 media_type = ixgbe_media_type_copper;
459 switch (hw->device_id) {
460 case IXGBE_DEV_ID_82599_KX4:
461 case IXGBE_DEV_ID_82599_KX4_MEZZ:
462 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
463 case IXGBE_DEV_ID_82599_KR:
464 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
465 case IXGBE_DEV_ID_82599_XAUI_LOM:
466 /* Default device ID is mezzanine card KX/KX4 */
467 media_type = ixgbe_media_type_backplane;
469 case IXGBE_DEV_ID_82599_SFP:
470 case IXGBE_DEV_ID_82599_SFP_FCOE:
471 case IXGBE_DEV_ID_82599_SFP_EM:
472 case IXGBE_DEV_ID_82599_SFP_SF2:
473 case IXGBE_DEV_ID_82599_SFP_SF_QP:
474 case IXGBE_DEV_ID_82599EN_SFP:
475 #ifdef RTE_NIC_BYPASS
476 case IXGBE_DEV_ID_82599_BYPASS:
478 media_type = ixgbe_media_type_fiber;
480 case IXGBE_DEV_ID_82599_CX4:
481 media_type = ixgbe_media_type_cx4;
483 case IXGBE_DEV_ID_82599_T3_LOM:
484 media_type = ixgbe_media_type_copper;
487 media_type = ixgbe_media_type_unknown;
495 * ixgbe_stop_mac_link_on_d3_82599 - Disables link on D3
496 * @hw: pointer to hardware structure
498 * Disables link during D3 power down sequence.
501 void ixgbe_stop_mac_link_on_d3_82599(struct ixgbe_hw *hw)
503 u32 autoc2_reg, fwsm;
506 DEBUGFUNC("ixgbe_stop_mac_link_on_d3_82599");
507 ixgbe_read_eeprom(hw, IXGBE_EEPROM_CTRL_2, &ee_ctrl_2);
509 /* Check to see if MNG FW could be enabled */
510 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
512 if (((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT) &&
514 ee_ctrl_2 & IXGBE_EEPROM_CCD_BIT) {
515 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
516 autoc2_reg |= IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK;
517 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
522 * ixgbe_start_mac_link_82599 - Setup MAC link settings
523 * @hw: pointer to hardware structure
524 * @autoneg_wait_to_complete: true when waiting for completion is needed
526 * Configures link settings based on values in the ixgbe_hw struct.
527 * Restarts the link. Performs autonegotiation if needed.
529 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
530 bool autoneg_wait_to_complete)
535 s32 status = IXGBE_SUCCESS;
536 bool got_lock = false;
538 DEBUGFUNC("ixgbe_start_mac_link_82599");
541 /* reset_pipeline requires us to hold this lock as it writes to
544 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
545 status = hw->mac.ops.acquire_swfw_sync(hw,
546 IXGBE_GSSR_MAC_CSR_SM);
547 if (status != IXGBE_SUCCESS)
554 ixgbe_reset_pipeline_82599(hw);
557 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
559 /* Only poll for autoneg to complete if specified to do so */
560 if (autoneg_wait_to_complete) {
561 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
562 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
563 IXGBE_AUTOC_LMS_KX4_KX_KR ||
564 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
565 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
566 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
567 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
568 links_reg = 0; /* Just in case Autoneg time = 0 */
569 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
570 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
571 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
575 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
576 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
577 DEBUGOUT("Autoneg did not complete.\n");
582 /* Add delay to filter out noises during initial link setup */
590 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
591 * @hw: pointer to hardware structure
593 * The base drivers may require better control over SFP+ module
594 * PHY states. This includes selectively shutting down the Tx
595 * laser on the PHY, effectively halting physical link.
597 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
599 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
601 /* Disable tx laser; allow 100us to go dark per spec */
602 esdp_reg |= IXGBE_ESDP_SDP3;
603 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
604 IXGBE_WRITE_FLUSH(hw);
609 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
610 * @hw: pointer to hardware structure
612 * The base drivers may require better control over SFP+ module
613 * PHY states. This includes selectively turning on the Tx
614 * laser on the PHY, effectively starting physical link.
616 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
618 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
620 /* Enable tx laser; allow 100ms to light up */
621 esdp_reg &= ~IXGBE_ESDP_SDP3;
622 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
623 IXGBE_WRITE_FLUSH(hw);
628 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
629 * @hw: pointer to hardware structure
631 * When the driver changes the link speeds that it can support,
632 * it sets autotry_restart to true to indicate that we need to
633 * initiate a new autotry session with the link partner. To do
634 * so, we set the speed then disable and re-enable the tx laser, to
635 * alert the link partner that it also needs to restart autotry on its
636 * end. This is consistent with true clause 37 autoneg, which also
637 * involves a loss of signal.
639 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
641 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
643 if (hw->mac.autotry_restart) {
644 ixgbe_disable_tx_laser_multispeed_fiber(hw);
645 ixgbe_enable_tx_laser_multispeed_fiber(hw);
646 hw->mac.autotry_restart = false;
652 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
653 * @hw: pointer to hardware structure
654 * @speed: new link speed
655 * @autoneg_wait_to_complete: true when waiting for completion is needed
657 * Set the link speed in the AUTOC register and restarts link.
659 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
660 ixgbe_link_speed speed,
661 bool autoneg_wait_to_complete)
663 s32 status = IXGBE_SUCCESS;
664 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
665 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
667 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
669 bool autoneg, link_up = false;
671 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
673 /* Mask off requested but non-supported speeds */
674 status = ixgbe_get_link_capabilities(hw, &link_speed, &autoneg);
675 if (status != IXGBE_SUCCESS)
681 * Try each speed one by one, highest priority first. We do this in
682 * software because 10gb fiber doesn't support speed autonegotiation.
684 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
686 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
688 /* If we already have link at this speed, just jump out */
689 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
690 if (status != IXGBE_SUCCESS)
693 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
696 /* Set the module link speed */
697 switch (hw->phy.media_type) {
698 case ixgbe_media_type_fiber:
699 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
700 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
701 IXGBE_WRITE_FLUSH(hw);
704 DEBUGOUT("Unexpected media type.\n");
708 /* Allow module to change analog characteristics (1G->10G) */
711 status = ixgbe_setup_mac_link_82599(hw,
712 IXGBE_LINK_SPEED_10GB_FULL,
713 autoneg_wait_to_complete);
714 if (status != IXGBE_SUCCESS)
717 /* Flap the tx laser if it has not already been done */
718 ixgbe_flap_tx_laser(hw);
721 * Wait for the controller to acquire link. Per IEEE 802.3ap,
722 * Section 73.10.2, we may have to wait up to 500ms if KR is
723 * attempted. 82599 uses the same timing for 10g SFI.
725 for (i = 0; i < 5; i++) {
726 /* Wait for the link partner to also set speed */
729 /* If we have link, just jump out */
730 status = ixgbe_check_link(hw, &link_speed,
732 if (status != IXGBE_SUCCESS)
740 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
742 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
743 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
745 /* If we already have link at this speed, just jump out */
746 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
747 if (status != IXGBE_SUCCESS)
750 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
753 /* Set the module link speed */
754 switch (hw->phy.media_type) {
755 case ixgbe_media_type_fiber:
756 esdp_reg &= ~IXGBE_ESDP_SDP5;
757 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
758 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
759 IXGBE_WRITE_FLUSH(hw);
762 DEBUGOUT("Unexpected media type.\n");
766 /* Allow module to change analog characteristics (10G->1G) */
769 status = ixgbe_setup_mac_link_82599(hw,
770 IXGBE_LINK_SPEED_1GB_FULL,
771 autoneg_wait_to_complete);
772 if (status != IXGBE_SUCCESS)
775 /* Flap the tx laser if it has not already been done */
776 ixgbe_flap_tx_laser(hw);
778 /* Wait for the link partner to also set speed */
781 /* If we have link, just jump out */
782 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
783 if (status != IXGBE_SUCCESS)
791 * We didn't get link. Configure back to the highest speed we tried,
792 * (if there was more than one). We call ourselves back with just the
793 * single highest speed that the user requested.
796 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
797 highest_link_speed, autoneg_wait_to_complete);
800 /* Set autoneg_advertised value based on input link speed */
801 hw->phy.autoneg_advertised = 0;
803 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
804 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
806 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
807 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
813 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
814 * @hw: pointer to hardware structure
815 * @speed: new link speed
816 * @autoneg_wait_to_complete: true when waiting for completion is needed
818 * Implements the Intel SmartSpeed algorithm.
820 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
821 ixgbe_link_speed speed,
822 bool autoneg_wait_to_complete)
824 s32 status = IXGBE_SUCCESS;
825 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
827 bool link_up = false;
828 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
830 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
832 /* Set autoneg_advertised value based on input link speed */
833 hw->phy.autoneg_advertised = 0;
835 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
836 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
838 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
839 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
841 if (speed & IXGBE_LINK_SPEED_100_FULL)
842 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
845 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
846 * autoneg advertisement if link is unable to be established at the
847 * highest negotiated rate. This can sometimes happen due to integrity
848 * issues with the physical media connection.
851 /* First, try to get link with full advertisement */
852 hw->phy.smart_speed_active = false;
853 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
854 status = ixgbe_setup_mac_link_82599(hw, speed,
855 autoneg_wait_to_complete);
856 if (status != IXGBE_SUCCESS)
860 * Wait for the controller to acquire link. Per IEEE 802.3ap,
861 * Section 73.10.2, we may have to wait up to 500ms if KR is
862 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
863 * Table 9 in the AN MAS.
865 for (i = 0; i < 5; i++) {
868 /* If we have link, just jump out */
869 status = ixgbe_check_link(hw, &link_speed, &link_up,
871 if (status != IXGBE_SUCCESS)
880 * We didn't get link. If we advertised KR plus one of KX4/KX
881 * (or BX4/BX), then disable KR and try again.
883 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
884 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
887 /* Turn SmartSpeed on to disable KR support */
888 hw->phy.smart_speed_active = true;
889 status = ixgbe_setup_mac_link_82599(hw, speed,
890 autoneg_wait_to_complete);
891 if (status != IXGBE_SUCCESS)
895 * Wait for the controller to acquire link. 600ms will allow for
896 * the AN link_fail_inhibit_timer as well for multiple cycles of
897 * parallel detect, both 10g and 1g. This allows for the maximum
898 * connect attempts as defined in the AN MAS table 73-7.
900 for (i = 0; i < 6; i++) {
903 /* If we have link, just jump out */
904 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
905 if (status != IXGBE_SUCCESS)
912 /* We didn't get link. Turn SmartSpeed back off. */
913 hw->phy.smart_speed_active = false;
914 status = ixgbe_setup_mac_link_82599(hw, speed,
915 autoneg_wait_to_complete);
918 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
919 DEBUGOUT("Smartspeed has downgraded the link speed "
920 "from the maximum advertised\n");
925 * ixgbe_setup_mac_link_82599 - Set MAC link speed
926 * @hw: pointer to hardware structure
927 * @speed: new link speed
928 * @autoneg_wait_to_complete: true when waiting for completion is needed
930 * Set the link speed in the AUTOC register and restarts link.
932 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
933 ixgbe_link_speed speed,
934 bool autoneg_wait_to_complete)
936 bool autoneg = false;
937 s32 status = IXGBE_SUCCESS;
938 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
939 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
940 u32 start_autoc = autoc;
942 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
943 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
944 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
947 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
948 bool got_lock = false;
950 DEBUGFUNC("ixgbe_setup_mac_link_82599");
952 /* Check to see if speed passed in is supported. */
953 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
957 speed &= link_capabilities;
959 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
960 status = IXGBE_ERR_LINK_SETUP;
964 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
965 if (hw->mac.orig_link_settings_stored)
966 orig_autoc = hw->mac.orig_autoc;
970 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
971 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
972 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
973 /* Set KX4/KX/KR support according to speed requested */
974 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
975 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
976 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
977 autoc |= IXGBE_AUTOC_KX4_SUPP;
978 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
979 (hw->phy.smart_speed_active == false))
980 autoc |= IXGBE_AUTOC_KR_SUPP;
982 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
983 autoc |= IXGBE_AUTOC_KX_SUPP;
984 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
985 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
986 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
987 /* Switch from 1G SFI to 10G SFI if requested */
988 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
989 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
990 autoc &= ~IXGBE_AUTOC_LMS_MASK;
991 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
993 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
994 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
995 /* Switch from 10G SFI to 1G SFI if requested */
996 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
997 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
998 autoc &= ~IXGBE_AUTOC_LMS_MASK;
1000 autoc |= IXGBE_AUTOC_LMS_1G_AN;
1002 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
1006 if (autoc != start_autoc) {
1007 /* Need SW/FW semaphore around AUTOC writes if LESM is on,
1008 * likewise reset_pipeline requires us to hold this lock as
1009 * it also writes to AUTOC.
1011 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1012 status = hw->mac.ops.acquire_swfw_sync(hw,
1013 IXGBE_GSSR_MAC_CSR_SM);
1014 if (status != IXGBE_SUCCESS) {
1015 status = IXGBE_ERR_SWFW_SYNC;
1023 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
1024 ixgbe_reset_pipeline_82599(hw);
1027 hw->mac.ops.release_swfw_sync(hw,
1028 IXGBE_GSSR_MAC_CSR_SM);
1032 /* Only poll for autoneg to complete if specified to do so */
1033 if (autoneg_wait_to_complete) {
1034 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
1035 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
1036 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
1037 links_reg = 0; /*Just in case Autoneg time=0*/
1038 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
1040 IXGBE_READ_REG(hw, IXGBE_LINKS);
1041 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
1045 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
1047 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
1048 DEBUGOUT("Autoneg did not complete.\n");
1053 /* Add delay to filter out noises during initial link setup */
1062 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
1063 * @hw: pointer to hardware structure
1064 * @speed: new link speed
1065 * @autoneg_wait_to_complete: true if waiting is needed to complete
1067 * Restarts link on PHY and MAC based on settings passed in.
1069 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1070 ixgbe_link_speed speed,
1071 bool autoneg_wait_to_complete)
1075 DEBUGFUNC("ixgbe_setup_copper_link_82599");
1077 /* Setup the PHY according to input speed */
1078 status = hw->phy.ops.setup_link_speed(hw, speed,
1079 autoneg_wait_to_complete);
1081 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1087 * ixgbe_reset_hw_82599 - Perform hardware reset
1088 * @hw: pointer to hardware structure
1090 * Resets the hardware by resetting the transmit and receive units, masks
1091 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1094 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1096 ixgbe_link_speed link_speed;
1098 u32 ctrl, i, autoc, autoc2;
1099 bool link_up = false;
1101 DEBUGFUNC("ixgbe_reset_hw_82599");
1103 /* Call adapter stop to disable tx/rx and clear interrupts */
1104 status = hw->mac.ops.stop_adapter(hw);
1105 if (status != IXGBE_SUCCESS)
1108 /* flush pending Tx transactions */
1109 ixgbe_clear_tx_pending(hw);
1111 /* PHY ops must be identified and initialized prior to reset */
1113 /* Identify PHY and related function pointers */
1114 status = hw->phy.ops.init(hw);
1116 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1119 /* Setup SFP module if there is one present. */
1120 if (hw->phy.sfp_setup_needed) {
1121 status = hw->mac.ops.setup_sfp(hw);
1122 hw->phy.sfp_setup_needed = false;
1125 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1129 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1130 hw->phy.ops.reset(hw);
1134 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1135 * If link reset is used when link is up, it might reset the PHY when
1136 * mng is using it. If link is down or the flag to force full link
1137 * reset is set, then perform link reset.
1139 ctrl = IXGBE_CTRL_LNK_RST;
1140 if (!hw->force_full_reset) {
1141 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1143 ctrl = IXGBE_CTRL_RST;
1146 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1147 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1148 IXGBE_WRITE_FLUSH(hw);
1150 /* Poll for reset bit to self-clear meaning reset is complete */
1151 for (i = 0; i < 10; i++) {
1153 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1154 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1158 if (ctrl & IXGBE_CTRL_RST_MASK) {
1159 status = IXGBE_ERR_RESET_FAILED;
1160 DEBUGOUT("Reset polling failed to complete.\n");
1166 * Double resets are required for recovery from certain error
1167 * conditions. Between resets, it is necessary to stall to
1168 * allow time for any pending HW events to complete.
1170 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1171 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1176 * Store the original AUTOC/AUTOC2 values if they have not been
1177 * stored off yet. Otherwise restore the stored original
1178 * values since the reset operation sets back to defaults.
1180 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1181 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1183 /* Enable link if disabled in NVM */
1184 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1185 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1186 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1187 IXGBE_WRITE_FLUSH(hw);
1190 if (hw->mac.orig_link_settings_stored == false) {
1191 hw->mac.orig_autoc = autoc;
1192 hw->mac.orig_autoc2 = autoc2;
1193 hw->mac.orig_link_settings_stored = true;
1195 if (autoc != hw->mac.orig_autoc) {
1196 /* Need SW/FW semaphore around AUTOC writes if LESM is
1197 * on, likewise reset_pipeline requires us to hold
1198 * this lock as it also writes to AUTOC.
1200 bool got_lock = false;
1201 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1202 status = hw->mac.ops.acquire_swfw_sync(hw,
1203 IXGBE_GSSR_MAC_CSR_SM);
1204 if (status != IXGBE_SUCCESS) {
1205 status = IXGBE_ERR_SWFW_SYNC;
1212 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
1213 ixgbe_reset_pipeline_82599(hw);
1216 hw->mac.ops.release_swfw_sync(hw,
1217 IXGBE_GSSR_MAC_CSR_SM);
1220 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1221 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1222 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1223 autoc2 |= (hw->mac.orig_autoc2 &
1224 IXGBE_AUTOC2_UPPER_MASK);
1225 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1229 /* Store the permanent mac address */
1230 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1233 * Store MAC address from RAR0, clear receive address registers, and
1234 * clear the multicast table. Also reset num_rar_entries to 128,
1235 * since we modify this value when programming the SAN MAC address.
1237 hw->mac.num_rar_entries = 128;
1238 hw->mac.ops.init_rx_addrs(hw);
1240 /* Store the permanent SAN mac address */
1241 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1243 /* Add the SAN MAC address to the RAR only if it's a valid address */
1244 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1245 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1246 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1248 /* Save the SAN MAC RAR index */
1249 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1251 /* Reserve the last RAR for the SAN MAC address */
1252 hw->mac.num_rar_entries--;
1255 /* Store the alternative WWNN/WWPN prefix */
1256 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1257 &hw->mac.wwpn_prefix);
1264 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1265 * @hw: pointer to hardware structure
1267 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1270 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1271 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1273 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1276 * Before starting reinitialization process,
1277 * FDIRCMD.CMD must be zero.
1279 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1280 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1281 IXGBE_FDIRCMD_CMD_MASK))
1285 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1286 DEBUGOUT("Flow Director previous command isn't complete, "
1287 "aborting table re-initialization.\n");
1288 return IXGBE_ERR_FDIR_REINIT_FAILED;
1291 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1292 IXGBE_WRITE_FLUSH(hw);
1294 * 82599 adapters flow director init flow cannot be restarted,
1295 * Workaround 82599 silicon errata by performing the following steps
1296 * before re-writing the FDIRCTRL control register with the same value.
1297 * - write 1 to bit 8 of FDIRCMD register &
1298 * - write 0 to bit 8 of FDIRCMD register
1300 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1301 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1302 IXGBE_FDIRCMD_CLEARHT));
1303 IXGBE_WRITE_FLUSH(hw);
1304 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1305 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1306 ~IXGBE_FDIRCMD_CLEARHT));
1307 IXGBE_WRITE_FLUSH(hw);
1309 * Clear FDIR Hash register to clear any leftover hashes
1310 * waiting to be programmed.
1312 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1313 IXGBE_WRITE_FLUSH(hw);
1315 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1316 IXGBE_WRITE_FLUSH(hw);
1318 /* Poll init-done after we write FDIRCTRL register */
1319 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1320 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1321 IXGBE_FDIRCTRL_INIT_DONE)
1325 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1326 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1327 return IXGBE_ERR_FDIR_REINIT_FAILED;
1330 /* Clear FDIR statistics registers (read to clear) */
1331 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1332 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1333 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1334 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1335 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1337 return IXGBE_SUCCESS;
1341 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1342 * @hw: pointer to hardware structure
1343 * @fdirctrl: value to write to flow director control register
1345 STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1349 DEBUGFUNC("ixgbe_fdir_enable_82599");
1351 /* Prime the keys for hashing */
1352 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1353 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1356 * Poll init-done after we write the register. Estimated times:
1357 * 10G: PBALLOC = 11b, timing is 60us
1358 * 1G: PBALLOC = 11b, timing is 600us
1359 * 100M: PBALLOC = 11b, timing is 6ms
1361 * Multiple these timings by 4 if under full Rx load
1363 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1364 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1365 * this might not finish in our poll time, but we can live with that
1368 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1369 IXGBE_WRITE_FLUSH(hw);
1370 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1371 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1372 IXGBE_FDIRCTRL_INIT_DONE)
1377 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1378 DEBUGOUT("Flow Director poll time exceeded!\n");
1382 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1383 * @hw: pointer to hardware structure
1384 * @fdirctrl: value to write to flow director control register, initially
1385 * contains just the value of the Rx packet buffer allocation
1387 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1389 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1392 * Continue setup of fdirctrl register bits:
1393 * Move the flexible bytes to use the ethertype - shift 6 words
1394 * Set the maximum length per hash bucket to 0xA filters
1395 * Send interrupt when 64 filters are left
1397 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1398 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1399 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1401 /* write hashes and fdirctrl register, poll for completion */
1402 ixgbe_fdir_enable_82599(hw, fdirctrl);
1404 return IXGBE_SUCCESS;
1408 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1409 * @hw: pointer to hardware structure
1410 * @fdirctrl: value to write to flow director control register, initially
1411 * contains just the value of the Rx packet buffer allocation
1413 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1415 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1418 * Continue setup of fdirctrl register bits:
1419 * Turn perfect match filtering on
1420 * Report hash in RSS field of Rx wb descriptor
1421 * Initialize the drop queue
1422 * Move the flexible bytes to use the ethertype - shift 6 words
1423 * Set the maximum length per hash bucket to 0xA filters
1424 * Send interrupt when 64 (0x4 * 16) filters are left
1426 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1427 IXGBE_FDIRCTRL_REPORT_STATUS |
1428 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1429 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1430 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1431 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1434 /* write hashes and fdirctrl register, poll for completion */
1435 ixgbe_fdir_enable_82599(hw, fdirctrl);
1437 return IXGBE_SUCCESS;
1441 * These defines allow us to quickly generate all of the necessary instructions
1442 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1443 * for values 0 through 15
1445 #define IXGBE_ATR_COMMON_HASH_KEY \
1446 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1447 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1450 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1451 common_hash ^= lo_hash_dword >> n; \
1452 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1453 bucket_hash ^= lo_hash_dword >> n; \
1454 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1455 sig_hash ^= lo_hash_dword << (16 - n); \
1456 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1457 common_hash ^= hi_hash_dword >> n; \
1458 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1459 bucket_hash ^= hi_hash_dword >> n; \
1460 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1461 sig_hash ^= hi_hash_dword << (16 - n); \
1465 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1466 * @stream: input bitstream to compute the hash on
1468 * This function is almost identical to the function above but contains
1469 * several optomizations such as unwinding all of the loops, letting the
1470 * compiler work out all of the conditional ifs since the keys are static
1471 * defines, and computing two keys at once since the hashed dword stream
1472 * will be the same for both keys.
1474 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1475 union ixgbe_atr_hash_dword common)
1477 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1478 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1480 /* record the flow_vm_vlan bits as they are a key part to the hash */
1481 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1483 /* generate common hash dword */
1484 hi_hash_dword = IXGBE_NTOHL(common.dword);
1486 /* low dword is word swapped version of common */
1487 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1489 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1490 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1492 /* Process bits 0 and 16 */
1493 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1496 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1497 * delay this because bit 0 of the stream should not be processed
1498 * so we do not add the vlan until after bit 0 was processed
1500 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1502 /* Process remaining 30 bit of the key */
1503 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1504 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1505 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1506 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1507 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1508 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1509 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1510 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1511 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1512 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1513 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1514 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1515 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1516 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1517 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1519 /* combine common_hash result with signature and bucket hashes */
1520 bucket_hash ^= common_hash;
1521 bucket_hash &= IXGBE_ATR_HASH_MASK;
1523 sig_hash ^= common_hash << 16;
1524 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1526 /* return completed signature hash */
1527 return sig_hash ^ bucket_hash;
1531 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1532 * @hw: pointer to hardware structure
1533 * @input: unique input dword
1534 * @common: compressed common input dword
1535 * @queue: queue index to direct traffic to
1537 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1538 union ixgbe_atr_hash_dword input,
1539 union ixgbe_atr_hash_dword common,
1545 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1548 * Get the flow_type in order to program FDIRCMD properly
1549 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1550 * fifth is FDIRCMD.TUNNEL_FILTER
1552 switch (input.formatted.flow_type) {
1553 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1554 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1555 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1556 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1557 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1558 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1561 DEBUGOUT(" Error on flow type input\n");
1562 return IXGBE_ERR_CONFIG;
1565 /* configure FDIRCMD register */
1566 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1567 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1568 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1569 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1572 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1573 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1575 fdirhashcmd = (u64)fdircmd << 32;
1576 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1577 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1579 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1581 return IXGBE_SUCCESS;
1584 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1587 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1588 bucket_hash ^= lo_hash_dword >> n; \
1589 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1590 bucket_hash ^= hi_hash_dword >> n; \
1594 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1595 * @atr_input: input bitstream to compute the hash on
1596 * @input_mask: mask for the input bitstream
1598 * This function serves two main purposes. First it applys the input_mask
1599 * to the atr_input resulting in a cleaned up atr_input data stream.
1600 * Secondly it computes the hash and stores it in the bkt_hash field at
1601 * the end of the input byte stream. This way it will be available for
1602 * future use without needing to recompute the hash.
1604 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1605 union ixgbe_atr_input *input_mask)
1608 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1609 u32 bucket_hash = 0;
1611 /* Apply masks to input data */
1612 input->dword_stream[0] &= input_mask->dword_stream[0];
1613 input->dword_stream[1] &= input_mask->dword_stream[1];
1614 input->dword_stream[2] &= input_mask->dword_stream[2];
1615 input->dword_stream[3] &= input_mask->dword_stream[3];
1616 input->dword_stream[4] &= input_mask->dword_stream[4];
1617 input->dword_stream[5] &= input_mask->dword_stream[5];
1618 input->dword_stream[6] &= input_mask->dword_stream[6];
1619 input->dword_stream[7] &= input_mask->dword_stream[7];
1620 input->dword_stream[8] &= input_mask->dword_stream[8];
1621 input->dword_stream[9] &= input_mask->dword_stream[9];
1622 input->dword_stream[10] &= input_mask->dword_stream[10];
1624 /* record the flow_vm_vlan bits as they are a key part to the hash */
1625 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1627 /* generate common hash dword */
1628 hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
1629 input->dword_stream[2] ^
1630 input->dword_stream[3] ^
1631 input->dword_stream[4] ^
1632 input->dword_stream[5] ^
1633 input->dword_stream[6] ^
1634 input->dword_stream[7] ^
1635 input->dword_stream[8] ^
1636 input->dword_stream[9] ^
1637 input->dword_stream[10]);
1639 /* low dword is word swapped version of common */
1640 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1642 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1643 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1645 /* Process bits 0 and 16 */
1646 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1649 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1650 * delay this because bit 0 of the stream should not be processed
1651 * so we do not add the vlan until after bit 0 was processed
1653 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1655 /* Process remaining 30 bit of the key */
1656 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1657 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1658 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1659 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1660 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1661 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1662 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1663 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1664 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1665 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1666 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1667 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1668 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1669 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1670 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1673 * Limit hash to 13 bits since max bucket count is 8K.
1674 * Store result at the end of the input stream.
1676 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1680 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1681 * @input_mask: mask to be bit swapped
1683 * The source and destination port masks for flow director are bit swapped
1684 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1685 * generate a correctly swapped value we need to bit swap the mask and that
1686 * is what is accomplished by this function.
1688 STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1690 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1691 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1692 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1693 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1694 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1695 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1696 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1700 * These two macros are meant to address the fact that we have registers
1701 * that are either all or in part big-endian. As a result on big-endian
1702 * systems we will end up byte swapping the value to little-endian before
1703 * it is byte swapped again and written to the hardware in the original
1704 * big-endian format.
1706 #define IXGBE_STORE_AS_BE32(_value) \
1707 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1708 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1710 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1711 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1713 #define IXGBE_STORE_AS_BE16(_value) \
1714 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1716 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1717 union ixgbe_atr_input *input_mask)
1719 /* mask IPv6 since it is currently not supported */
1720 u32 fdirm = IXGBE_FDIRM_DIPv6;
1722 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1725 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1726 * are zero, then assume a full mask for that field. Also assume that
1727 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1728 * cannot be masked out in this implementation.
1730 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1734 /* verify bucket hash is cleared on hash generation */
1735 if (input_mask->formatted.bkt_hash)
1736 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1738 /* Program FDIRM and verify partial masks */
1739 switch (input_mask->formatted.vm_pool & 0x7F) {
1741 fdirm |= IXGBE_FDIRM_POOL;
1745 DEBUGOUT(" Error on vm pool mask\n");
1746 return IXGBE_ERR_CONFIG;
1749 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1751 fdirm |= IXGBE_FDIRM_L4P;
1752 if (input_mask->formatted.dst_port ||
1753 input_mask->formatted.src_port) {
1754 DEBUGOUT(" Error on src/dst port mask\n");
1755 return IXGBE_ERR_CONFIG;
1757 case IXGBE_ATR_L4TYPE_MASK:
1760 DEBUGOUT(" Error on flow type mask\n");
1761 return IXGBE_ERR_CONFIG;
1764 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1766 /* mask VLAN ID, fall through to mask VLAN priority */
1767 fdirm |= IXGBE_FDIRM_VLANID;
1769 /* mask VLAN priority */
1770 fdirm |= IXGBE_FDIRM_VLANP;
1773 /* mask VLAN ID only, fall through */
1774 fdirm |= IXGBE_FDIRM_VLANID;
1776 /* no VLAN fields masked */
1779 DEBUGOUT(" Error on VLAN mask\n");
1780 return IXGBE_ERR_CONFIG;
1783 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1785 /* Mask Flex Bytes, fall through */
1786 fdirm |= IXGBE_FDIRM_FLEX;
1790 DEBUGOUT(" Error on flexible byte mask\n");
1791 return IXGBE_ERR_CONFIG;
1795 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1796 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1798 /* store the TCP/UDP port masks, bit reversed from port layout */
1799 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1801 /* write both the same so that UDP and TCP use the same mask */
1802 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1803 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1805 /* store source and destination IP masks (big-enian) */
1806 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1807 ~input_mask->formatted.src_ip[0]);
1808 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1809 ~input_mask->formatted.dst_ip[0]);
1811 return IXGBE_SUCCESS;
1814 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1815 union ixgbe_atr_input *input,
1816 u16 soft_id, u8 queue)
1818 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1820 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1822 /* currently IPv6 is not supported, must be programmed with 0 */
1823 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1824 input->formatted.src_ip[0]);
1825 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1826 input->formatted.src_ip[1]);
1827 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1828 input->formatted.src_ip[2]);
1830 /* record the source address (big-endian) */
1831 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1833 /* record the first 32 bits of the destination address (big-endian) */
1834 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1836 /* record source and destination port (little-endian)*/
1837 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1838 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1839 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1840 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1842 /* record vlan (little-endian) and flex_bytes(big-endian) */
1843 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1844 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1845 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1846 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1849 /* configure FDIRHASH register */
1850 fdirhash = input->formatted.bkt_hash;
1851 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1852 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1855 * flush all previous writes to make certain registers are
1856 * programmed prior to issuing the command
1858 IXGBE_WRITE_FLUSH(hw);
1860 /* configure FDIRCMD register */
1861 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1862 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1863 if (queue == IXGBE_FDIR_DROP_QUEUE)
1864 fdircmd |= IXGBE_FDIRCMD_DROP;
1865 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1866 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1867 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1869 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1871 return IXGBE_SUCCESS;
1874 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1875 union ixgbe_atr_input *input,
1881 s32 err = IXGBE_SUCCESS;
1883 /* configure FDIRHASH register */
1884 fdirhash = input->formatted.bkt_hash;
1885 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1886 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1888 /* flush hash to HW */
1889 IXGBE_WRITE_FLUSH(hw);
1891 /* Query if filter is present */
1892 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1894 for (retry_count = 10; retry_count; retry_count--) {
1895 /* allow 10us for query to process */
1897 /* verify query completed successfully */
1898 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1899 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1904 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1906 /* if filter exists in hardware then remove it */
1907 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1908 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1909 IXGBE_WRITE_FLUSH(hw);
1910 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1911 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1918 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1919 * @hw: pointer to hardware structure
1920 * @input: input bitstream
1921 * @input_mask: mask for the input bitstream
1922 * @soft_id: software index for the filters
1923 * @queue: queue index to direct traffic to
1925 * Note that the caller to this function must lock before calling, since the
1926 * hardware writes must be protected from one another.
1928 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1929 union ixgbe_atr_input *input,
1930 union ixgbe_atr_input *input_mask,
1931 u16 soft_id, u8 queue)
1933 s32 err = IXGBE_ERR_CONFIG;
1935 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1938 * Check flow_type formatting, and bail out before we touch the hardware
1939 * if there's a configuration issue
1941 switch (input->formatted.flow_type) {
1942 case IXGBE_ATR_FLOW_TYPE_IPV4:
1943 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1944 if (input->formatted.dst_port || input->formatted.src_port) {
1945 DEBUGOUT(" Error on src/dst port\n");
1946 return IXGBE_ERR_CONFIG;
1949 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1950 if (input->formatted.dst_port || input->formatted.src_port) {
1951 DEBUGOUT(" Error on src/dst port\n");
1952 return IXGBE_ERR_CONFIG;
1954 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1955 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1956 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
1957 IXGBE_ATR_L4TYPE_MASK;
1960 DEBUGOUT(" Error on flow type input\n");
1964 /* program input mask into the HW */
1965 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
1969 /* apply mask and compute/store hash */
1970 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
1972 /* program filters to filter memory */
1973 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
1978 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1979 * @hw: pointer to hardware structure
1980 * @reg: analog register to read
1983 * Performs read operation to Omer analog register specified.
1985 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1989 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
1991 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1993 IXGBE_WRITE_FLUSH(hw);
1995 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1996 *val = (u8)core_ctl;
1998 return IXGBE_SUCCESS;
2002 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
2003 * @hw: pointer to hardware structure
2004 * @reg: atlas register to write
2005 * @val: value to write
2007 * Performs write operation to Omer analog register specified.
2009 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
2013 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
2015 core_ctl = (reg << 8) | val;
2016 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
2017 IXGBE_WRITE_FLUSH(hw);
2020 return IXGBE_SUCCESS;
2024 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
2025 * @hw: pointer to hardware structure
2027 * Starts the hardware using the generic start_hw function
2028 * and the generation start_hw function.
2029 * Then performs revision-specific operations, if any.
2031 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
2033 s32 ret_val = IXGBE_SUCCESS;
2035 DEBUGFUNC("ixgbe_start_hw_82599");
2037 ret_val = ixgbe_start_hw_generic(hw);
2038 if (ret_val != IXGBE_SUCCESS)
2041 ret_val = ixgbe_start_hw_gen2(hw);
2042 if (ret_val != IXGBE_SUCCESS)
2045 /* We need to run link autotry after the driver loads */
2046 hw->mac.autotry_restart = true;
2048 if (ret_val == IXGBE_SUCCESS)
2049 ret_val = ixgbe_verify_fw_version_82599(hw);
2055 * ixgbe_identify_phy_82599 - Get physical layer module
2056 * @hw: pointer to hardware structure
2058 * Determines the physical layer module found on the current adapter.
2059 * If PHY already detected, maintains current PHY type in hw struct,
2060 * otherwise executes the PHY detection routine.
2062 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2066 DEBUGFUNC("ixgbe_identify_phy_82599");
2068 /* Detect PHY if not unknown - returns success if already detected. */
2069 status = ixgbe_identify_phy_generic(hw);
2070 if (status != IXGBE_SUCCESS) {
2071 /* 82599 10GBASE-T requires an external PHY */
2072 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2075 status = ixgbe_identify_module_generic(hw);
2078 /* Set PHY type none if no PHY detected */
2079 if (hw->phy.type == ixgbe_phy_unknown) {
2080 hw->phy.type = ixgbe_phy_none;
2081 status = IXGBE_SUCCESS;
2084 /* Return error if SFP module has been detected but is not supported */
2085 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2086 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
2093 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2094 * @hw: pointer to hardware structure
2096 * Determines physical layer capabilities of the current configuration.
2098 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2100 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2101 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2102 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2103 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2104 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2105 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2106 u16 ext_ability = 0;
2107 u8 comp_codes_10g = 0;
2108 u8 comp_codes_1g = 0;
2110 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2112 hw->phy.ops.identify(hw);
2114 switch (hw->phy.type) {
2116 case ixgbe_phy_cu_unknown:
2117 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2118 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2119 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2120 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2121 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2122 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2123 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
2124 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2130 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2131 case IXGBE_AUTOC_LMS_1G_AN:
2132 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2133 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2134 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2135 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2138 /* SFI mode so read SFP module */
2141 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2142 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2143 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2144 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2145 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2146 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2147 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2150 case IXGBE_AUTOC_LMS_10G_SERIAL:
2151 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2152 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2154 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2157 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2158 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2159 if (autoc & IXGBE_AUTOC_KX_SUPP)
2160 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2161 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2162 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2163 if (autoc & IXGBE_AUTOC_KR_SUPP)
2164 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2173 /* SFP check must be done last since DA modules are sometimes used to
2174 * test KR mode - we need to id KR mode correctly before SFP module.
2175 * Call identify_sfp because the pluggable module may have changed */
2176 hw->phy.ops.identify_sfp(hw);
2177 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2180 switch (hw->phy.type) {
2181 case ixgbe_phy_sfp_passive_tyco:
2182 case ixgbe_phy_sfp_passive_unknown:
2183 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2185 case ixgbe_phy_sfp_ftl_active:
2186 case ixgbe_phy_sfp_active_unknown:
2187 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2189 case ixgbe_phy_sfp_avago:
2190 case ixgbe_phy_sfp_ftl:
2191 case ixgbe_phy_sfp_intel:
2192 case ixgbe_phy_sfp_unknown:
2193 hw->phy.ops.read_i2c_eeprom(hw,
2194 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2195 hw->phy.ops.read_i2c_eeprom(hw,
2196 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2197 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2198 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2199 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2200 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2201 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2202 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2203 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
2204 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
2211 return physical_layer;
2215 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2216 * @hw: pointer to hardware structure
2217 * @regval: register value to write to RXCTRL
2219 * Enables the Rx DMA unit for 82599
2221 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2224 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2227 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2228 * If traffic is incoming before we enable the Rx unit, it could hang
2229 * the Rx DMA unit. Therefore, make sure the security engine is
2230 * completely disabled prior to enabling the Rx unit.
2233 hw->mac.ops.disable_sec_rx_path(hw);
2235 if (regval & IXGBE_RXCTRL_RXEN)
2236 ixgbe_enable_rx(hw);
2238 ixgbe_disable_rx(hw);
2240 hw->mac.ops.enable_sec_rx_path(hw);
2242 return IXGBE_SUCCESS;
2246 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2247 * @hw: pointer to hardware structure
2249 * Verifies that installed the firmware version is 0.6 or higher
2250 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2252 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2253 * if the FW version is not supported.
2255 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2257 s32 status = IXGBE_ERR_EEPROM_VERSION;
2258 u16 fw_offset, fw_ptp_cfg_offset;
2261 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2263 /* firmware check is only necessary for SFI devices */
2264 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2265 status = IXGBE_SUCCESS;
2266 goto fw_version_out;
2269 /* get the offset to the Firmware Module block */
2270 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
2271 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2272 "eeprom read at offset %d failed", IXGBE_FW_PTR);
2273 return IXGBE_ERR_EEPROM_VERSION;
2276 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2277 goto fw_version_out;
2279 /* get the offset to the Pass Through Patch Configuration block */
2280 if (hw->eeprom.ops.read(hw, (fw_offset +
2281 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2282 &fw_ptp_cfg_offset)) {
2283 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2284 "eeprom read at offset %d failed",
2286 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);
2287 return IXGBE_ERR_EEPROM_VERSION;
2290 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2291 goto fw_version_out;
2293 /* get the firmware version */
2294 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2295 IXGBE_FW_PATCH_VERSION_4), &fw_version)) {
2296 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2297 "eeprom read at offset %d failed",
2298 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);
2299 return IXGBE_ERR_EEPROM_VERSION;
2302 if (fw_version > 0x5)
2303 status = IXGBE_SUCCESS;
2310 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2311 * @hw: pointer to hardware structure
2313 * Returns true if the LESM FW module is present and enabled. Otherwise
2314 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2316 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2318 bool lesm_enabled = false;
2319 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2322 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2324 /* get the offset to the Firmware Module block */
2325 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2327 if ((status != IXGBE_SUCCESS) ||
2328 (fw_offset == 0) || (fw_offset == 0xFFFF))
2331 /* get the offset to the LESM Parameters block */
2332 status = hw->eeprom.ops.read(hw, (fw_offset +
2333 IXGBE_FW_LESM_PARAMETERS_PTR),
2334 &fw_lesm_param_offset);
2336 if ((status != IXGBE_SUCCESS) ||
2337 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2340 /* get the lesm state word */
2341 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2342 IXGBE_FW_LESM_STATE_1),
2345 if ((status == IXGBE_SUCCESS) &&
2346 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2347 lesm_enabled = true;
2350 return lesm_enabled;
2354 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2355 * fastest available method
2357 * @hw: pointer to hardware structure
2358 * @offset: offset of word in EEPROM to read
2359 * @words: number of words
2360 * @data: word(s) read from the EEPROM
2362 * Retrieves 16 bit word(s) read from EEPROM
2364 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2365 u16 words, u16 *data)
2367 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2368 s32 ret_val = IXGBE_ERR_CONFIG;
2370 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2373 * If EEPROM is detected and can be addressed using 14 bits,
2374 * use EERD otherwise use bit bang
2376 if ((eeprom->type == ixgbe_eeprom_spi) &&
2377 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2378 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2381 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2389 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2390 * fastest available method
2392 * @hw: pointer to hardware structure
2393 * @offset: offset of word in the EEPROM to read
2394 * @data: word read from the EEPROM
2396 * Reads a 16 bit word from the EEPROM
2398 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2399 u16 offset, u16 *data)
2401 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2402 s32 ret_val = IXGBE_ERR_CONFIG;
2404 DEBUGFUNC("ixgbe_read_eeprom_82599");
2407 * If EEPROM is detected and can be addressed using 14 bits,
2408 * use EERD otherwise use bit bang
2410 if ((eeprom->type == ixgbe_eeprom_spi) &&
2411 (offset <= IXGBE_EERD_MAX_ADDR))
2412 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2414 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2420 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2422 * @hw: pointer to hardware structure
2424 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2425 * full pipeline reset
2427 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2429 s32 i, autoc_reg, autoc2_reg, ret_val;
2432 /* Enable link if disabled in NVM */
2433 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2434 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2435 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2436 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2437 IXGBE_WRITE_FLUSH(hw);
2440 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2441 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2442 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2443 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
2444 /* Wait for AN to leave state 0 */
2445 for (i = 0; i < 10; i++) {
2447 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2448 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2452 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2453 DEBUGOUT("auto negotiation not completed\n");
2454 ret_val = IXGBE_ERR_RESET_FAILED;
2455 goto reset_pipeline_out;
2458 ret_val = IXGBE_SUCCESS;
2461 /* Write AUTOC register with original LMS field and Restart_AN */
2462 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2463 IXGBE_WRITE_FLUSH(hw);