1 /******************************************************************************
3 Copyright (c) 2001-2010, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "ixgbe_type.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
40 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw);
41 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
42 ixgbe_link_speed *speed,
44 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw);
45 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
46 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
47 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw);
48 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
49 ixgbe_link_speed speed, bool autoneg,
50 bool autoneg_wait_to_complete);
51 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
52 ixgbe_link_speed speed, bool autoneg,
53 bool autoneg_wait_to_complete);
54 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
55 bool autoneg_wait_to_complete);
56 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
57 ixgbe_link_speed speed,
59 bool autoneg_wait_to_complete);
60 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
61 ixgbe_link_speed speed,
63 bool autoneg_wait_to_complete);
64 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw);
65 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw);
66 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw);
67 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val);
68 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val);
69 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw);
70 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw);
71 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw);
72 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw);
73 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval);
74 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
75 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw);
76 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
77 u16 offset, u16 *data);
78 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
79 u16 words, u16 *data);
81 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
83 struct ixgbe_mac_info *mac = &hw->mac;
85 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
87 /* enable the laser control functions for SFP+ fiber */
88 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
89 mac->ops.disable_tx_laser =
90 &ixgbe_disable_tx_laser_multispeed_fiber;
91 mac->ops.enable_tx_laser =
92 &ixgbe_enable_tx_laser_multispeed_fiber;
93 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
96 mac->ops.disable_tx_laser = NULL;
97 mac->ops.enable_tx_laser = NULL;
98 mac->ops.flap_tx_laser = NULL;
101 if (hw->phy.multispeed_fiber) {
102 /* Set up dual speed SFP+ support */
103 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
105 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
106 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
107 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
108 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
109 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
111 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
117 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
118 * @hw: pointer to hardware structure
120 * Initialize any function pointers that were not able to be
121 * set during init_shared_code because the PHY/SFP type was
122 * not known. Perform the SFP init if necessary.
125 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
127 struct ixgbe_mac_info *mac = &hw->mac;
128 struct ixgbe_phy_info *phy = &hw->phy;
129 s32 ret_val = IXGBE_SUCCESS;
131 DEBUGFUNC("ixgbe_init_phy_ops_82599");
133 /* Identify the PHY or SFP module */
134 ret_val = phy->ops.identify(hw);
135 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
136 goto init_phy_ops_out;
138 /* Setup function pointers based on detected SFP module and speeds */
139 ixgbe_init_mac_link_ops_82599(hw);
140 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
141 hw->phy.ops.reset = NULL;
143 /* If copper media, overwrite with copper function pointers */
144 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
145 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
146 mac->ops.get_link_capabilities =
147 &ixgbe_get_copper_link_capabilities_generic;
150 /* Set necessary function pointers based on phy type */
151 switch (hw->phy.type) {
153 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
154 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
155 phy->ops.get_firmware_version =
156 &ixgbe_get_phy_firmware_version_tnx;
165 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
167 s32 ret_val = IXGBE_SUCCESS;
170 u16 list_offset, data_offset, data_value;
172 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
174 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
175 ixgbe_init_mac_link_ops_82599(hw);
177 hw->phy.ops.reset = NULL;
179 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
181 if (ret_val != IXGBE_SUCCESS)
184 /* PHY config will finish before releasing the semaphore */
185 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
186 IXGBE_GSSR_MAC_CSR_SM);
187 if (ret_val != IXGBE_SUCCESS) {
188 ret_val = IXGBE_ERR_SWFW_SYNC;
192 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
193 while (data_value != 0xffff) {
194 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
195 IXGBE_WRITE_FLUSH(hw);
196 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
199 /* Release the semaphore */
200 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
201 /* Delay obtaining semaphore again to allow FW access */
202 msec_delay(hw->eeprom.semaphore_delay);
204 /* Now restart DSP by setting Restart_AN and clearing LMS */
205 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, ((IXGBE_READ_REG(hw,
206 IXGBE_AUTOC) & ~IXGBE_AUTOC_LMS_MASK) |
207 IXGBE_AUTOC_AN_RESTART));
209 /* Wait for AN to leave state 0 */
210 for (i = 0; i < 10; i++) {
212 reg_anlp1 = IXGBE_READ_REG(hw, IXGBE_ANLP1);
213 if (reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)
216 if (!(reg_anlp1 & IXGBE_ANLP1_AN_STATE_MASK)) {
217 DEBUGOUT("sfp module setup not complete\n");
218 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
222 /* Restart DSP by setting Restart_AN and return to SFI mode */
223 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
224 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL |
225 IXGBE_AUTOC_AN_RESTART));
233 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
234 * @hw: pointer to hardware structure
236 * Initialize the function pointers and assign the MAC type for 82599.
237 * Does not touch the hardware.
240 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
242 struct ixgbe_mac_info *mac = &hw->mac;
243 struct ixgbe_phy_info *phy = &hw->phy;
244 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
247 DEBUGFUNC("ixgbe_init_ops_82599");
249 ret_val = ixgbe_init_phy_ops_generic(hw);
250 ret_val = ixgbe_init_ops_generic(hw);
253 phy->ops.identify = &ixgbe_identify_phy_82599;
254 phy->ops.init = &ixgbe_init_phy_ops_82599;
257 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
258 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
259 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
260 mac->ops.get_supported_physical_layer =
261 &ixgbe_get_supported_physical_layer_82599;
262 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
263 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
264 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
265 mac->ops.start_hw = &ixgbe_start_hw_82599;
266 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
267 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
268 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
269 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
270 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
272 /* RAR, Multicast, VLAN */
273 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
274 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
275 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
276 mac->rar_highwater = 1;
277 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
278 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
279 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
280 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
281 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
282 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
285 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
286 mac->ops.check_link = &ixgbe_check_mac_link_generic;
287 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
288 ixgbe_init_mac_link_ops_82599(hw);
290 mac->mcft_size = 128;
292 mac->num_rar_entries = 128;
293 mac->rx_pb_size = 512;
294 mac->max_tx_queues = 128;
295 mac->max_rx_queues = 128;
296 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
298 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
299 IXGBE_FWSM_MODE_MASK) ? TRUE : FALSE;
301 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
304 eeprom->ops.read = &ixgbe_read_eeprom_82599;
305 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
307 /* Manageability interface */
308 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
314 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
315 * @hw: pointer to hardware structure
316 * @speed: pointer to link speed
317 * @negotiation: TRUE when autoneg or autotry is enabled
319 * Determines the link capabilities by reading the AUTOC register.
321 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
322 ixgbe_link_speed *speed,
325 s32 status = IXGBE_SUCCESS;
328 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
331 /* Check if 1G SFP module. */
332 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
333 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) {
334 *speed = IXGBE_LINK_SPEED_1GB_FULL;
340 * Determine link capabilities based on the stored value of AUTOC,
341 * which represents EEPROM defaults. If AUTOC value has not
342 * been stored, use the current register values.
344 if (hw->mac.orig_link_settings_stored)
345 autoc = hw->mac.orig_autoc;
347 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
349 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
350 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
351 *speed = IXGBE_LINK_SPEED_1GB_FULL;
352 *negotiation = FALSE;
355 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
356 *speed = IXGBE_LINK_SPEED_10GB_FULL;
357 *negotiation = FALSE;
360 case IXGBE_AUTOC_LMS_1G_AN:
361 *speed = IXGBE_LINK_SPEED_1GB_FULL;
365 case IXGBE_AUTOC_LMS_10G_SERIAL:
366 *speed = IXGBE_LINK_SPEED_10GB_FULL;
367 *negotiation = FALSE;
370 case IXGBE_AUTOC_LMS_KX4_KX_KR:
371 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
372 *speed = IXGBE_LINK_SPEED_UNKNOWN;
373 if (autoc & IXGBE_AUTOC_KR_SUPP)
374 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
375 if (autoc & IXGBE_AUTOC_KX4_SUPP)
376 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
377 if (autoc & IXGBE_AUTOC_KX_SUPP)
378 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
382 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
383 *speed = IXGBE_LINK_SPEED_100_FULL;
384 if (autoc & IXGBE_AUTOC_KR_SUPP)
385 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
386 if (autoc & IXGBE_AUTOC_KX4_SUPP)
387 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
388 if (autoc & IXGBE_AUTOC_KX_SUPP)
389 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
393 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
394 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
395 *negotiation = FALSE;
399 status = IXGBE_ERR_LINK_SETUP;
404 if (hw->phy.multispeed_fiber) {
405 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
406 IXGBE_LINK_SPEED_1GB_FULL;
415 * ixgbe_get_media_type_82599 - Get media type
416 * @hw: pointer to hardware structure
418 * Returns the media type (fiber, copper, backplane)
420 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
422 enum ixgbe_media_type media_type;
424 DEBUGFUNC("ixgbe_get_media_type_82599");
426 /* Detect if there is a copper PHY attached. */
427 switch (hw->phy.type) {
428 case ixgbe_phy_cu_unknown:
430 media_type = ixgbe_media_type_copper;
436 switch (hw->device_id) {
437 case IXGBE_DEV_ID_82599_KX4:
438 case IXGBE_DEV_ID_82599_KX4_MEZZ:
439 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
440 case IXGBE_DEV_ID_82599_KR:
441 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
442 case IXGBE_DEV_ID_82599_XAUI_LOM:
443 /* Default device ID is mezzanine card KX/KX4 */
444 media_type = ixgbe_media_type_backplane;
446 case IXGBE_DEV_ID_82599_SFP:
447 case IXGBE_DEV_ID_82599_SFP_FCOE:
448 case IXGBE_DEV_ID_82599_SFP_EM:
449 case IXGBE_DEV_ID_82599EN_SFP:
450 media_type = ixgbe_media_type_fiber;
452 case IXGBE_DEV_ID_82599_CX4:
453 media_type = ixgbe_media_type_cx4;
455 case IXGBE_DEV_ID_82599_T3_LOM:
456 media_type = ixgbe_media_type_copper;
459 media_type = ixgbe_media_type_unknown;
467 * ixgbe_start_mac_link_82599 - Setup MAC link settings
468 * @hw: pointer to hardware structure
469 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
471 * Configures link settings based on values in the ixgbe_hw struct.
472 * Restarts the link. Performs autonegotiation if needed.
474 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
475 bool autoneg_wait_to_complete)
480 s32 status = IXGBE_SUCCESS;
482 DEBUGFUNC("ixgbe_start_mac_link_82599");
486 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
487 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
488 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
490 /* Only poll for autoneg to complete if specified to do so */
491 if (autoneg_wait_to_complete) {
492 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
493 IXGBE_AUTOC_LMS_KX4_KX_KR ||
494 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
495 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
496 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
497 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
498 links_reg = 0; /* Just in case Autoneg time = 0 */
499 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
500 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
501 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
505 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
506 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
507 DEBUGOUT("Autoneg did not complete.\n");
512 /* Add delay to filter out noises during initial link setup */
519 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
520 * @hw: pointer to hardware structure
522 * The base drivers may require better control over SFP+ module
523 * PHY states. This includes selectively shutting down the Tx
524 * laser on the PHY, effectively halting physical link.
526 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
528 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
530 /* Disable tx laser; allow 100us to go dark per spec */
531 esdp_reg |= IXGBE_ESDP_SDP3;
532 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
533 IXGBE_WRITE_FLUSH(hw);
538 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
539 * @hw: pointer to hardware structure
541 * The base drivers may require better control over SFP+ module
542 * PHY states. This includes selectively turning on the Tx
543 * laser on the PHY, effectively starting physical link.
545 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
547 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
549 /* Enable tx laser; allow 100ms to light up */
550 esdp_reg &= ~IXGBE_ESDP_SDP3;
551 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
552 IXGBE_WRITE_FLUSH(hw);
557 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
558 * @hw: pointer to hardware structure
560 * When the driver changes the link speeds that it can support,
561 * it sets autotry_restart to TRUE to indicate that we need to
562 * initiate a new autotry session with the link partner. To do
563 * so, we set the speed then disable and re-enable the tx laser, to
564 * alert the link partner that it also needs to restart autotry on its
565 * end. This is consistent with TRUE clause 37 autoneg, which also
566 * involves a loss of signal.
568 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
570 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
572 if (hw->mac.autotry_restart) {
573 ixgbe_disable_tx_laser_multispeed_fiber(hw);
574 ixgbe_enable_tx_laser_multispeed_fiber(hw);
575 hw->mac.autotry_restart = FALSE;
580 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
581 * @hw: pointer to hardware structure
582 * @speed: new link speed
583 * @autoneg: TRUE if autonegotiation enabled
584 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
586 * Set the link speed in the AUTOC register and restarts link.
588 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
589 ixgbe_link_speed speed, bool autoneg,
590 bool autoneg_wait_to_complete)
592 s32 status = IXGBE_SUCCESS;
593 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
594 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
596 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
598 bool link_up = FALSE;
601 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
603 /* Mask off requested but non-supported speeds */
604 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);
605 if (status != IXGBE_SUCCESS)
611 * Try each speed one by one, highest priority first. We do this in
612 * software because 10gb fiber doesn't support speed autonegotiation.
614 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
616 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
618 /* If we already have link at this speed, just jump out */
619 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
620 if (status != IXGBE_SUCCESS)
623 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
626 /* Set the module link speed */
627 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
628 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
629 IXGBE_WRITE_FLUSH(hw);
631 /* Allow module to change analog characteristics (1G->10G) */
634 status = ixgbe_setup_mac_link_82599(hw,
635 IXGBE_LINK_SPEED_10GB_FULL,
637 autoneg_wait_to_complete);
638 if (status != IXGBE_SUCCESS)
641 /* Flap the tx laser if it has not already been done */
642 ixgbe_flap_tx_laser(hw);
645 * Wait for the controller to acquire link. Per IEEE 802.3ap,
646 * Section 73.10.2, we may have to wait up to 500ms if KR is
647 * attempted. 82599 uses the same timing for 10g SFI.
649 for (i = 0; i < 5; i++) {
650 /* Wait for the link partner to also set speed */
653 /* If we have link, just jump out */
654 status = ixgbe_check_link(hw, &link_speed,
656 if (status != IXGBE_SUCCESS)
664 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
666 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
667 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
669 /* If we already have link at this speed, just jump out */
670 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
671 if (status != IXGBE_SUCCESS)
674 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
677 /* Set the module link speed */
678 esdp_reg &= ~IXGBE_ESDP_SDP5;
679 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
680 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
681 IXGBE_WRITE_FLUSH(hw);
683 /* Allow module to change analog characteristics (10G->1G) */
686 status = ixgbe_setup_mac_link_82599(hw,
687 IXGBE_LINK_SPEED_1GB_FULL,
689 autoneg_wait_to_complete);
690 if (status != IXGBE_SUCCESS)
693 /* Flap the tx laser if it has not already been done */
694 ixgbe_flap_tx_laser(hw);
696 /* Wait for the link partner to also set speed */
699 /* If we have link, just jump out */
700 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
701 if (status != IXGBE_SUCCESS)
709 * We didn't get link. Configure back to the highest speed we tried,
710 * (if there was more than one). We call ourselves back with just the
711 * single highest speed that the user requested.
714 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
715 highest_link_speed, autoneg, autoneg_wait_to_complete);
718 /* Set autoneg_advertised value based on input link speed */
719 hw->phy.autoneg_advertised = 0;
721 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
722 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
724 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
725 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
731 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
732 * @hw: pointer to hardware structure
733 * @speed: new link speed
734 * @autoneg: TRUE if autonegotiation enabled
735 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
737 * Implements the Intel SmartSpeed algorithm.
739 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
740 ixgbe_link_speed speed, bool autoneg,
741 bool autoneg_wait_to_complete)
743 s32 status = IXGBE_SUCCESS;
744 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
746 bool link_up = FALSE;
747 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
749 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
751 /* Set autoneg_advertised value based on input link speed */
752 hw->phy.autoneg_advertised = 0;
754 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
755 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
757 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
758 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
760 if (speed & IXGBE_LINK_SPEED_100_FULL)
761 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
764 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
765 * autoneg advertisement if link is unable to be established at the
766 * highest negotiated rate. This can sometimes happen due to integrity
767 * issues with the physical media connection.
770 /* First, try to get link with full advertisement */
771 hw->phy.smart_speed_active = FALSE;
772 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
773 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
774 autoneg_wait_to_complete);
775 if (status != IXGBE_SUCCESS)
779 * Wait for the controller to acquire link. Per IEEE 802.3ap,
780 * Section 73.10.2, we may have to wait up to 500ms if KR is
781 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
782 * Table 9 in the AN MAS.
784 for (i = 0; i < 5; i++) {
787 /* If we have link, just jump out */
788 status = ixgbe_check_link(hw, &link_speed, &link_up,
790 if (status != IXGBE_SUCCESS)
799 * We didn't get link. If we advertised KR plus one of KX4/KX
800 * (or BX4/BX), then disable KR and try again.
802 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
803 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
806 /* Turn SmartSpeed on to disable KR support */
807 hw->phy.smart_speed_active = TRUE;
808 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
809 autoneg_wait_to_complete);
810 if (status != IXGBE_SUCCESS)
814 * Wait for the controller to acquire link. 600ms will allow for
815 * the AN link_fail_inhibit_timer as well for multiple cycles of
816 * parallel detect, both 10g and 1g. This allows for the maximum
817 * connect attempts as defined in the AN MAS table 73-7.
819 for (i = 0; i < 6; i++) {
822 /* If we have link, just jump out */
823 status = ixgbe_check_link(hw, &link_speed, &link_up, FALSE);
824 if (status != IXGBE_SUCCESS)
831 /* We didn't get link. Turn SmartSpeed back off. */
832 hw->phy.smart_speed_active = FALSE;
833 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
834 autoneg_wait_to_complete);
837 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
838 DEBUGOUT("Smartspeed has downgraded the link speed "
839 "from the maximum advertised\n");
844 * ixgbe_setup_mac_link_82599 - Set MAC link speed
845 * @hw: pointer to hardware structure
846 * @speed: new link speed
847 * @autoneg: TRUE if autonegotiation enabled
848 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed
850 * Set the link speed in the AUTOC register and restarts link.
852 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
853 ixgbe_link_speed speed, bool autoneg,
854 bool autoneg_wait_to_complete)
856 s32 status = IXGBE_SUCCESS;
857 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
858 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
859 u32 start_autoc = autoc;
861 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
862 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
863 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
866 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
868 DEBUGFUNC("ixgbe_setup_mac_link_82599");
870 /* Check to see if speed passed in is supported. */
871 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
872 if (status != IXGBE_SUCCESS)
875 speed &= link_capabilities;
877 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
878 status = IXGBE_ERR_LINK_SETUP;
882 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
883 if (hw->mac.orig_link_settings_stored)
884 orig_autoc = hw->mac.orig_autoc;
888 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
889 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
890 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
891 /* Set KX4/KX/KR support according to speed requested */
892 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
893 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
894 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
895 autoc |= IXGBE_AUTOC_KX4_SUPP;
896 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
897 (hw->phy.smart_speed_active == FALSE))
898 autoc |= IXGBE_AUTOC_KR_SUPP;
899 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
900 autoc |= IXGBE_AUTOC_KX_SUPP;
901 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
902 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
903 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
904 /* Switch from 1G SFI to 10G SFI if requested */
905 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
906 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
907 autoc &= ~IXGBE_AUTOC_LMS_MASK;
908 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
910 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
911 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
912 /* Switch from 10G SFI to 1G SFI if requested */
913 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
914 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
915 autoc &= ~IXGBE_AUTOC_LMS_MASK;
917 autoc |= IXGBE_AUTOC_LMS_1G_AN;
919 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
923 if (autoc != start_autoc) {
925 autoc |= IXGBE_AUTOC_AN_RESTART;
926 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
928 /* Only poll for autoneg to complete if specified to do so */
929 if (autoneg_wait_to_complete) {
930 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
931 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
932 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
933 links_reg = 0; /*Just in case Autoneg time=0*/
934 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
936 IXGBE_READ_REG(hw, IXGBE_LINKS);
937 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
941 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
943 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
944 DEBUGOUT("Autoneg did not complete.\n");
949 /* Add delay to filter out noises during initial link setup */
958 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
959 * @hw: pointer to hardware structure
960 * @speed: new link speed
961 * @autoneg: TRUE if autonegotiation enabled
962 * @autoneg_wait_to_complete: TRUE if waiting is needed to complete
964 * Restarts link on PHY and MAC based on settings passed in.
966 static s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
967 ixgbe_link_speed speed,
969 bool autoneg_wait_to_complete)
973 DEBUGFUNC("ixgbe_setup_copper_link_82599");
975 /* Setup the PHY according to input speed */
976 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
977 autoneg_wait_to_complete);
979 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
985 * ixgbe_reset_hw_82599 - Perform hardware reset
986 * @hw: pointer to hardware structure
988 * Resets the hardware by resetting the transmit and receive units, masks
989 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
992 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
994 ixgbe_link_speed link_speed;
996 u32 ctrl, i, autoc, autoc2;
997 bool link_up = FALSE;
999 DEBUGFUNC("ixgbe_reset_hw_82599");
1001 /* Call adapter stop to disable tx/rx and clear interrupts */
1002 status = hw->mac.ops.stop_adapter(hw);
1003 if (status != IXGBE_SUCCESS)
1006 /* flush pending Tx transactions */
1007 ixgbe_clear_tx_pending(hw);
1009 /* PHY ops must be identified and initialized prior to reset */
1011 /* Identify PHY and related function pointers */
1012 status = hw->phy.ops.init(hw);
1014 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1017 /* Setup SFP module if there is one present. */
1018 if (hw->phy.sfp_setup_needed) {
1019 status = hw->mac.ops.setup_sfp(hw);
1020 hw->phy.sfp_setup_needed = FALSE;
1023 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1027 if (hw->phy.reset_disable == FALSE && hw->phy.ops.reset != NULL)
1028 hw->phy.ops.reset(hw);
1032 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1033 * If link reset is used when link is up, it might reset the PHY when
1034 * mng is using it. If link is down or the flag to force full link
1035 * reset is set, then perform link reset.
1037 ctrl = IXGBE_CTRL_LNK_RST;
1038 if (!hw->force_full_reset) {
1039 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE);
1041 ctrl = IXGBE_CTRL_RST;
1044 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1045 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1046 IXGBE_WRITE_FLUSH(hw);
1048 /* Poll for reset bit to self-clear indicating reset is complete */
1049 for (i = 0; i < 10; i++) {
1051 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1052 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1056 if (ctrl & IXGBE_CTRL_RST_MASK) {
1057 status = IXGBE_ERR_RESET_FAILED;
1058 DEBUGOUT("Reset polling failed to complete.\n");
1064 * Double resets are required for recovery from certain error
1065 * conditions. Between resets, it is necessary to stall to allow time
1066 * for any pending HW events to complete.
1068 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1069 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1074 * Store the original AUTOC/AUTOC2 values if they have not been
1075 * stored off yet. Otherwise restore the stored original
1076 * values since the reset operation sets back to defaults.
1078 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1079 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1080 if (hw->mac.orig_link_settings_stored == FALSE) {
1081 hw->mac.orig_autoc = autoc;
1082 hw->mac.orig_autoc2 = autoc2;
1083 hw->mac.orig_link_settings_stored = TRUE;
1085 if (autoc != hw->mac.orig_autoc)
1086 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (hw->mac.orig_autoc |
1087 IXGBE_AUTOC_AN_RESTART));
1089 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1090 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1091 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1092 autoc2 |= (hw->mac.orig_autoc2 &
1093 IXGBE_AUTOC2_UPPER_MASK);
1094 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1098 /* Store the permanent mac address */
1099 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1102 * Store MAC address from RAR0, clear receive address registers, and
1103 * clear the multicast table. Also reset num_rar_entries to 128,
1104 * since we modify this value when programming the SAN MAC address.
1106 hw->mac.num_rar_entries = 128;
1107 hw->mac.ops.init_rx_addrs(hw);
1109 /* Store the permanent SAN mac address */
1110 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1112 /* Add the SAN MAC address to the RAR only if it's a valid address */
1113 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1114 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1115 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1117 /* Reserve the last RAR for the SAN MAC address */
1118 hw->mac.num_rar_entries--;
1121 /* Store the alternative WWNN/WWPN prefix */
1122 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1123 &hw->mac.wwpn_prefix);
1130 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1131 * @hw: pointer to hardware structure
1133 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1136 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1137 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1139 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1142 * Before starting reinitialization process,
1143 * FDIRCMD.CMD must be zero.
1145 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1146 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1147 IXGBE_FDIRCMD_CMD_MASK))
1151 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1152 DEBUGOUT("Flow Director previous command isn't complete, "
1153 "aborting table re-initialization. \n");
1154 return IXGBE_ERR_FDIR_REINIT_FAILED;
1157 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1158 IXGBE_WRITE_FLUSH(hw);
1160 * 82599 adapters flow director init flow cannot be restarted,
1161 * Workaround 82599 silicon errata by performing the following steps
1162 * before re-writing the FDIRCTRL control register with the same value.
1163 * - write 1 to bit 8 of FDIRCMD register &
1164 * - write 0 to bit 8 of FDIRCMD register
1166 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1167 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1168 IXGBE_FDIRCMD_CLEARHT));
1169 IXGBE_WRITE_FLUSH(hw);
1170 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1171 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1172 ~IXGBE_FDIRCMD_CLEARHT));
1173 IXGBE_WRITE_FLUSH(hw);
1175 * Clear FDIR Hash register to clear any leftover hashes
1176 * waiting to be programmed.
1178 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1179 IXGBE_WRITE_FLUSH(hw);
1181 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1182 IXGBE_WRITE_FLUSH(hw);
1184 /* Poll init-done after we write FDIRCTRL register */
1185 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1186 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1187 IXGBE_FDIRCTRL_INIT_DONE)
1191 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1192 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1193 return IXGBE_ERR_FDIR_REINIT_FAILED;
1196 /* Clear FDIR statistics registers (read to clear) */
1197 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1198 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1199 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1200 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1201 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1203 return IXGBE_SUCCESS;
1207 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1208 * @hw: pointer to hardware structure
1209 * @fdirctrl: value to write to flow director control register
1211 static void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1215 DEBUGFUNC("ixgbe_fdir_enable_82599");
1217 /* Prime the keys for hashing */
1218 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1219 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1222 * Poll init-done after we write the register. Estimated times:
1223 * 10G: PBALLOC = 11b, timing is 60us
1224 * 1G: PBALLOC = 11b, timing is 600us
1225 * 100M: PBALLOC = 11b, timing is 6ms
1227 * Multiple these timings by 4 if under full Rx load
1229 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1230 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1231 * this might not finish in our poll time, but we can live with that
1234 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1235 IXGBE_WRITE_FLUSH(hw);
1236 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1237 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1238 IXGBE_FDIRCTRL_INIT_DONE)
1243 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1244 DEBUGOUT("Flow Director poll time exceeded!\n");
1248 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1249 * @hw: pointer to hardware structure
1250 * @fdirctrl: value to write to flow director control register, initially
1251 * contains just the value of the Rx packet buffer allocation
1253 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1255 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1258 * Continue setup of fdirctrl register bits:
1259 * Move the flexible bytes to use the ethertype - shift 6 words
1260 * Set the maximum length per hash bucket to 0xA filters
1261 * Send interrupt when 64 filters are left
1263 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1264 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1265 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1267 /* write hashes and fdirctrl register, poll for completion */
1268 ixgbe_fdir_enable_82599(hw, fdirctrl);
1270 return IXGBE_SUCCESS;
1274 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1275 * @hw: pointer to hardware structure
1276 * @fdirctrl: value to write to flow director control register, initially
1277 * contains just the value of the Rx packet buffer allocation
1279 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1281 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1284 * Continue setup of fdirctrl register bits:
1285 * Turn perfect match filtering on
1286 * Report hash in RSS field of Rx wb descriptor
1287 * Initialize the drop queue
1288 * Move the flexible bytes to use the ethertype - shift 6 words
1289 * Set the maximum length per hash bucket to 0xA filters
1290 * Send interrupt when 64 (0x4 * 16) filters are left
1292 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1293 IXGBE_FDIRCTRL_REPORT_STATUS |
1294 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1295 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1296 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1297 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1299 /* write hashes and fdirctrl register, poll for completion */
1300 ixgbe_fdir_enable_82599(hw, fdirctrl);
1302 return IXGBE_SUCCESS;
1306 * These defines allow us to quickly generate all of the necessary instructions
1307 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1308 * for values 0 through 15
1310 #define IXGBE_ATR_COMMON_HASH_KEY \
1311 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1312 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1315 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1316 common_hash ^= lo_hash_dword >> n; \
1317 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1318 bucket_hash ^= lo_hash_dword >> n; \
1319 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1320 sig_hash ^= lo_hash_dword << (16 - n); \
1321 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1322 common_hash ^= hi_hash_dword >> n; \
1323 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1324 bucket_hash ^= hi_hash_dword >> n; \
1325 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1326 sig_hash ^= hi_hash_dword << (16 - n); \
1330 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1331 * @stream: input bitstream to compute the hash on
1333 * This function is almost identical to the function above but contains
1334 * several optomizations such as unwinding all of the loops, letting the
1335 * compiler work out all of the conditional ifs since the keys are static
1336 * defines, and computing two keys at once since the hashed dword stream
1337 * will be the same for both keys.
1339 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1340 union ixgbe_atr_hash_dword common)
1342 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1343 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1345 /* record the flow_vm_vlan bits as they are a key part to the hash */
1346 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1348 /* generate common hash dword */
1349 hi_hash_dword = IXGBE_NTOHL(common.dword);
1351 /* low dword is word swapped version of common */
1352 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1354 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1355 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1357 /* Process bits 0 and 16 */
1358 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1361 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1362 * delay this because bit 0 of the stream should not be processed
1363 * so we do not add the vlan until after bit 0 was processed
1365 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1367 /* Process remaining 30 bit of the key */
1368 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1369 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1370 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1371 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1372 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1373 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1374 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1375 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1376 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1377 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1378 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1379 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1380 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1381 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1382 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1384 /* combine common_hash result with signature and bucket hashes */
1385 bucket_hash ^= common_hash;
1386 bucket_hash &= IXGBE_ATR_HASH_MASK;
1388 sig_hash ^= common_hash << 16;
1389 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1391 /* return completed signature hash */
1392 return sig_hash ^ bucket_hash;
1396 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1397 * @hw: pointer to hardware structure
1398 * @input: unique input dword
1399 * @common: compressed common input dword
1400 * @queue: queue index to direct traffic to
1402 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1403 union ixgbe_atr_hash_dword input,
1404 union ixgbe_atr_hash_dword common,
1410 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1413 * Get the flow_type in order to program FDIRCMD properly
1414 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1416 switch (input.formatted.flow_type) {
1417 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1418 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1419 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1420 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1421 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1422 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1425 DEBUGOUT(" Error on flow type input\n");
1426 return IXGBE_ERR_CONFIG;
1429 /* configure FDIRCMD register */
1430 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1431 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1432 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1433 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1436 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1437 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1439 fdirhashcmd = (u64)fdircmd << 32;
1440 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1441 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1443 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1445 return IXGBE_SUCCESS;
1448 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1451 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1452 bucket_hash ^= lo_hash_dword >> n; \
1453 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1454 bucket_hash ^= hi_hash_dword >> n; \
1458 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1459 * @atr_input: input bitstream to compute the hash on
1460 * @input_mask: mask for the input bitstream
1462 * This function serves two main purposes. First it applys the input_mask
1463 * to the atr_input resulting in a cleaned up atr_input data stream.
1464 * Secondly it computes the hash and stores it in the bkt_hash field at
1465 * the end of the input byte stream. This way it will be available for
1466 * future use without needing to recompute the hash.
1468 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1469 union ixgbe_atr_input *input_mask)
1472 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1473 u32 bucket_hash = 0;
1475 /* Apply masks to input data */
1476 input->dword_stream[0] &= input_mask->dword_stream[0];
1477 input->dword_stream[1] &= input_mask->dword_stream[1];
1478 input->dword_stream[2] &= input_mask->dword_stream[2];
1479 input->dword_stream[3] &= input_mask->dword_stream[3];
1480 input->dword_stream[4] &= input_mask->dword_stream[4];
1481 input->dword_stream[5] &= input_mask->dword_stream[5];
1482 input->dword_stream[6] &= input_mask->dword_stream[6];
1483 input->dword_stream[7] &= input_mask->dword_stream[7];
1484 input->dword_stream[8] &= input_mask->dword_stream[8];
1485 input->dword_stream[9] &= input_mask->dword_stream[9];
1486 input->dword_stream[10] &= input_mask->dword_stream[10];
1488 /* record the flow_vm_vlan bits as they are a key part to the hash */
1489 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1491 /* generate common hash dword */
1492 hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
1493 input->dword_stream[2] ^
1494 input->dword_stream[3] ^
1495 input->dword_stream[4] ^
1496 input->dword_stream[5] ^
1497 input->dword_stream[6] ^
1498 input->dword_stream[7] ^
1499 input->dword_stream[8] ^
1500 input->dword_stream[9] ^
1501 input->dword_stream[10]);
1503 /* low dword is word swapped version of common */
1504 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1506 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1507 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1509 /* Process bits 0 and 16 */
1510 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1513 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1514 * delay this because bit 0 of the stream should not be processed
1515 * so we do not add the vlan until after bit 0 was processed
1517 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1519 /* Process remaining 30 bit of the key */
1520 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1521 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1522 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1523 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1524 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1525 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1526 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1527 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1528 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1529 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1530 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1531 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1532 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1533 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1534 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1537 * Limit hash to 13 bits since max bucket count is 8K.
1538 * Store result at the end of the input stream.
1540 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1544 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1545 * @input_mask: mask to be bit swapped
1547 * The source and destination port masks for flow director are bit swapped
1548 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1549 * generate a correctly swapped value we need to bit swap the mask and that
1550 * is what is accomplished by this function.
1552 static u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1554 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1555 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1556 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1557 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1558 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1559 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1560 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1564 * These two macros are meant to address the fact that we have registers
1565 * that are either all or in part big-endian. As a result on big-endian
1566 * systems we will end up byte swapping the value to little-endian before
1567 * it is byte swapped again and written to the hardware in the original
1568 * big-endian format.
1570 #define IXGBE_STORE_AS_BE32(_value) \
1571 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1572 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1574 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1575 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1577 #define IXGBE_STORE_AS_BE16(_value) \
1578 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1580 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1581 union ixgbe_atr_input *input_mask)
1583 /* mask IPv6 since it is currently not supported */
1584 u32 fdirm = IXGBE_FDIRM_DIPv6;
1587 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1590 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1591 * are zero, then assume a full mask for that field. Also assume that
1592 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1593 * cannot be masked out in this implementation.
1595 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1599 /* verify bucket hash is cleared on hash generation */
1600 if (input_mask->formatted.bkt_hash) {
1601 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1604 /* Program FDIRM and verify partial masks */
1605 switch (input_mask->formatted.vm_pool & 0x7F) {
1607 fdirm |= IXGBE_FDIRM_POOL;
1611 DEBUGOUT(" Error on vm pool mask\n");
1612 return IXGBE_ERR_CONFIG;
1615 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1617 fdirm |= IXGBE_FDIRM_L4P;
1618 if (input_mask->formatted.dst_port ||
1619 input_mask->formatted.src_port) {
1620 DEBUGOUT(" Error on src/dst port mask\n");
1621 return IXGBE_ERR_CONFIG;
1623 case IXGBE_ATR_L4TYPE_MASK:
1626 DEBUGOUT(" Error on flow type mask\n");
1627 return IXGBE_ERR_CONFIG;
1630 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1632 /* mask VLAN ID, fall through to mask VLAN priority */
1633 fdirm |= IXGBE_FDIRM_VLANID;
1635 /* mask VLAN priority */
1636 fdirm |= IXGBE_FDIRM_VLANP;
1639 /* mask VLAN ID only, fall through */
1640 fdirm |= IXGBE_FDIRM_VLANID;
1642 /* no VLAN fields masked */
1645 DEBUGOUT(" Error on VLAN mask\n");
1646 return IXGBE_ERR_CONFIG;
1649 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1651 /* Mask Flex Bytes, fall through */
1652 fdirm |= IXGBE_FDIRM_FLEX;
1656 DEBUGOUT(" Error on flexible byte mask\n");
1657 return IXGBE_ERR_CONFIG;
1660 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1661 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1663 /* store the TCP/UDP port masks, bit reversed from port layout */
1664 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1666 /* write both the same so that UDP and TCP use the same mask */
1667 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1668 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1670 /* store source and destination IP masks (big-enian) */
1671 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1672 ~input_mask->formatted.src_ip[0]);
1673 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1674 ~input_mask->formatted.dst_ip[0]);
1676 return IXGBE_SUCCESS;
1679 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1680 union ixgbe_atr_input *input,
1681 u16 soft_id, u8 queue)
1683 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1685 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1687 /* currently IPv6 is not supported, must be programmed with 0 */
1688 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1689 input->formatted.src_ip[0]);
1690 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1691 input->formatted.src_ip[1]);
1692 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1693 input->formatted.src_ip[2]);
1695 /* record the source address (big-endian) */
1696 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1698 /* record the first 32 bits of the destination address (big-endian) */
1699 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1701 /* record source and destination port (little-endian)*/
1702 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1703 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1704 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1705 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1707 /* record vlan (little-endian) and flex_bytes(big-endian) */
1708 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1709 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1710 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1711 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1713 /* configure FDIRHASH register */
1714 fdirhash = input->formatted.bkt_hash;
1715 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1716 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1719 * flush all previous writes to make certain registers are
1720 * programmed prior to issuing the command
1722 IXGBE_WRITE_FLUSH(hw);
1724 /* configure FDIRCMD register */
1725 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1726 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1727 if (queue == IXGBE_FDIR_DROP_QUEUE)
1728 fdircmd |= IXGBE_FDIRCMD_DROP;
1729 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1730 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1731 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1733 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1735 return IXGBE_SUCCESS;
1738 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1739 union ixgbe_atr_input *input,
1745 s32 err = IXGBE_SUCCESS;
1747 /* configure FDIRHASH register */
1748 fdirhash = input->formatted.bkt_hash;
1749 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1750 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1752 /* flush hash to HW */
1753 IXGBE_WRITE_FLUSH(hw);
1755 /* Query if filter is present */
1756 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1758 for (retry_count = 10; retry_count; retry_count--) {
1759 /* allow 10us for query to process */
1761 /* verify query completed successfully */
1762 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1763 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1768 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1770 /* if filter exists in hardware then remove it */
1771 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1772 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1773 IXGBE_WRITE_FLUSH(hw);
1774 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1775 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1782 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1783 * @hw: pointer to hardware structure
1784 * @input: input bitstream
1785 * @input_mask: mask for the input bitstream
1786 * @soft_id: software index for the filters
1787 * @queue: queue index to direct traffic to
1789 * Note that the caller to this function must lock before calling, since the
1790 * hardware writes must be protected from one another.
1792 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1793 union ixgbe_atr_input *input,
1794 union ixgbe_atr_input *input_mask,
1795 u16 soft_id, u8 queue)
1797 s32 err = IXGBE_ERR_CONFIG;
1799 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1802 * Check flow_type formatting, and bail out before we touch the hardware
1803 * if there's a configuration issue
1805 switch (input->formatted.flow_type) {
1806 case IXGBE_ATR_FLOW_TYPE_IPV4:
1807 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1808 if (input->formatted.dst_port || input->formatted.src_port) {
1809 DEBUGOUT(" Error on src/dst port\n");
1810 return IXGBE_ERR_CONFIG;
1813 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1814 if (input->formatted.dst_port || input->formatted.src_port) {
1815 DEBUGOUT(" Error on src/dst port\n");
1816 return IXGBE_ERR_CONFIG;
1818 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1819 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1820 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
1821 IXGBE_ATR_L4TYPE_MASK;
1824 DEBUGOUT(" Error on flow type input\n");
1828 /* program input mask into the HW */
1829 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
1833 /* apply mask and compute/store hash */
1834 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
1836 /* program filters to filter memory */
1837 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
1842 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1843 * @hw: pointer to hardware structure
1844 * @reg: analog register to read
1847 * Performs read operation to Omer analog register specified.
1849 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1853 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
1855 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1857 IXGBE_WRITE_FLUSH(hw);
1859 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1860 *val = (u8)core_ctl;
1862 return IXGBE_SUCCESS;
1866 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1867 * @hw: pointer to hardware structure
1868 * @reg: atlas register to write
1869 * @val: value to write
1871 * Performs write operation to Omer analog register specified.
1873 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1877 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
1879 core_ctl = (reg << 8) | val;
1880 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1881 IXGBE_WRITE_FLUSH(hw);
1884 return IXGBE_SUCCESS;
1888 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1889 * @hw: pointer to hardware structure
1891 * Starts the hardware using the generic start_hw function
1892 * and the generation start_hw function.
1893 * Then performs revision-specific operations, if any.
1895 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1897 s32 ret_val = IXGBE_SUCCESS;
1899 DEBUGFUNC("ixgbe_start_hw_82599");
1901 ret_val = ixgbe_start_hw_generic(hw);
1902 if (ret_val != IXGBE_SUCCESS)
1905 ret_val = ixgbe_start_hw_gen2(hw);
1906 if (ret_val != IXGBE_SUCCESS)
1909 /* We need to run link autotry after the driver loads */
1910 hw->mac.autotry_restart = TRUE;
1912 if (ret_val == IXGBE_SUCCESS)
1913 ret_val = ixgbe_verify_fw_version_82599(hw);
1919 * ixgbe_identify_phy_82599 - Get physical layer module
1920 * @hw: pointer to hardware structure
1922 * Determines the physical layer module found on the current adapter.
1923 * If PHY already detected, maintains current PHY type in hw struct,
1924 * otherwise executes the PHY detection routine.
1926 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
1928 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1930 DEBUGFUNC("ixgbe_identify_phy_82599");
1932 /* Detect PHY if not unknown - returns success if already detected. */
1933 status = ixgbe_identify_phy_generic(hw);
1934 if (status != IXGBE_SUCCESS) {
1935 /* 82599 10GBASE-T requires an external PHY */
1936 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
1939 status = ixgbe_identify_sfp_module_generic(hw);
1942 /* Set PHY type none if no PHY detected */
1943 if (hw->phy.type == ixgbe_phy_unknown) {
1944 hw->phy.type = ixgbe_phy_none;
1945 status = IXGBE_SUCCESS;
1948 /* Return error if SFP module has been detected but is not supported */
1949 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
1950 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1957 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
1958 * @hw: pointer to hardware structure
1960 * Determines physical layer capabilities of the current configuration.
1962 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
1964 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1965 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1966 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1967 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
1968 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
1969 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
1970 u16 ext_ability = 0;
1971 u8 comp_codes_10g = 0;
1972 u8 comp_codes_1g = 0;
1974 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
1976 hw->phy.ops.identify(hw);
1978 switch (hw->phy.type) {
1980 case ixgbe_phy_cu_unknown:
1981 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
1982 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
1983 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
1984 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
1985 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
1986 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
1987 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
1988 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
1994 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
1995 case IXGBE_AUTOC_LMS_1G_AN:
1996 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
1997 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
1998 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
1999 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2002 /* SFI mode so read SFP module */
2005 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2006 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2007 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2008 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2009 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2010 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2011 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2014 case IXGBE_AUTOC_LMS_10G_SERIAL:
2015 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2016 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2018 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2021 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2022 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2023 if (autoc & IXGBE_AUTOC_KX_SUPP)
2024 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2025 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2026 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2027 if (autoc & IXGBE_AUTOC_KR_SUPP)
2028 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2037 /* SFP check must be done last since DA modules are sometimes used to
2038 * test KR mode - we need to id KR mode correctly before SFP module.
2039 * Call identify_sfp because the pluggable module may have changed */
2040 hw->phy.ops.identify_sfp(hw);
2041 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2044 switch (hw->phy.type) {
2045 case ixgbe_phy_sfp_passive_tyco:
2046 case ixgbe_phy_sfp_passive_unknown:
2047 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2049 case ixgbe_phy_sfp_ftl_active:
2050 case ixgbe_phy_sfp_active_unknown:
2051 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2053 case ixgbe_phy_sfp_avago:
2054 case ixgbe_phy_sfp_ftl:
2055 case ixgbe_phy_sfp_intel:
2056 case ixgbe_phy_sfp_unknown:
2057 hw->phy.ops.read_i2c_eeprom(hw,
2058 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2059 hw->phy.ops.read_i2c_eeprom(hw,
2060 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2061 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2062 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2063 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2064 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2065 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2066 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2073 return physical_layer;
2077 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2078 * @hw: pointer to hardware structure
2079 * @regval: register value to write to RXCTRL
2081 * Enables the Rx DMA unit for 82599
2083 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2085 #define IXGBE_MAX_SECRX_POLL 30
2089 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2092 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2093 * If traffic is incoming before we enable the Rx unit, it could hang
2094 * the Rx DMA unit. Therefore, make sure the security engine is
2095 * completely disabled prior to enabling the Rx unit.
2097 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2098 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
2099 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2100 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
2101 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
2102 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
2105 /* Use interrupt-safe sleep just in case */
2109 /* For informational purposes only */
2110 if (i >= IXGBE_MAX_SECRX_POLL)
2111 DEBUGOUT("Rx unit being enabled before security "
2112 "path fully disabled. Continuing with init.\n");
2114 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2115 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
2116 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
2117 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
2118 IXGBE_WRITE_FLUSH(hw);
2120 return IXGBE_SUCCESS;
2124 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2125 * @hw: pointer to hardware structure
2127 * Verifies that installed the firmware version is 0.6 or higher
2128 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2130 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2131 * if the FW version is not supported.
2133 static s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2135 s32 status = IXGBE_ERR_EEPROM_VERSION;
2136 u16 fw_offset, fw_ptp_cfg_offset;
2139 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2141 /* firmware check is only necessary for SFI devices */
2142 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2143 status = IXGBE_SUCCESS;
2144 goto fw_version_out;
2147 /* get the offset to the Firmware Module block */
2148 hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2150 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2151 goto fw_version_out;
2153 /* get the offset to the Pass Through Patch Configuration block */
2154 hw->eeprom.ops.read(hw, (fw_offset +
2155 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2156 &fw_ptp_cfg_offset);
2158 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2159 goto fw_version_out;
2161 /* get the firmware version */
2162 hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2163 IXGBE_FW_PATCH_VERSION_4),
2166 if (fw_version > 0x5)
2167 status = IXGBE_SUCCESS;
2174 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2175 * @hw: pointer to hardware structure
2177 * Returns TRUE if the LESM FW module is present and enabled. Otherwise
2178 * returns FALSE. Smart Speed must be disabled if LESM FW module is enabled.
2180 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2182 bool lesm_enabled = FALSE;
2183 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2186 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2188 /* get the offset to the Firmware Module block */
2189 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2191 if ((status != IXGBE_SUCCESS) ||
2192 (fw_offset == 0) || (fw_offset == 0xFFFF))
2195 /* get the offset to the LESM Parameters block */
2196 status = hw->eeprom.ops.read(hw, (fw_offset +
2197 IXGBE_FW_LESM_PARAMETERS_PTR),
2198 &fw_lesm_param_offset);
2200 if ((status != IXGBE_SUCCESS) ||
2201 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2204 /* get the lesm state word */
2205 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2206 IXGBE_FW_LESM_STATE_1),
2209 if ((status == IXGBE_SUCCESS) &&
2210 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2211 lesm_enabled = TRUE;
2214 return lesm_enabled;
2218 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2219 * fastest available method
2221 * @hw: pointer to hardware structure
2222 * @offset: offset of word in EEPROM to read
2223 * @words: number of words
2224 * @data: word(s) read from the EEPROM
2226 * Retrieves 16 bit word(s) read from EEPROM
2228 static s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2229 u16 words, u16 *data)
2231 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2232 s32 ret_val = IXGBE_ERR_CONFIG;
2234 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2237 * If EEPROM is detected and can be addressed using 14 bits,
2238 * use EERD otherwise use bit bang
2240 if ((eeprom->type == ixgbe_eeprom_spi) &&
2241 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2242 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2245 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2253 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2254 * fastest available method
2256 * @hw: pointer to hardware structure
2257 * @offset: offset of word in the EEPROM to read
2258 * @data: word read from the EEPROM
2260 * Reads a 16 bit word from the EEPROM
2262 static s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2263 u16 offset, u16 *data)
2265 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2266 s32 ret_val = IXGBE_ERR_CONFIG;
2268 DEBUGFUNC("ixgbe_read_eeprom_82599");
2271 * If EEPROM is detected and can be addressed using 14 bits,
2272 * use EERD otherwise use bit bang
2274 if ((eeprom->type == ixgbe_eeprom_spi) &&
2275 (offset <= IXGBE_EERD_MAX_ADDR))
2276 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2278 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);