1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_type.h"
35 #include "ixgbe_82599.h"
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
39 #ident "$Id: ixgbe_82599.c,v 1.301 2012/11/08 11:33:27 jtkirshe Exp $"
41 #define IXGBE_82599_MAX_TX_QUEUES 128
42 #define IXGBE_82599_MAX_RX_QUEUES 128
43 #define IXGBE_82599_RAR_ENTRIES 128
44 #define IXGBE_82599_MC_TBL_SIZE 128
45 #define IXGBE_82599_VFT_TBL_SIZE 128
46 #define IXGBE_82599_RX_PB_SIZE 512
48 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
49 ixgbe_link_speed speed,
51 bool autoneg_wait_to_complete);
52 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw);
53 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
54 u16 offset, u16 *data);
55 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
56 u16 words, u16 *data);
58 void ixgbe_init_mac_link_ops_82599(struct ixgbe_hw *hw)
60 struct ixgbe_mac_info *mac = &hw->mac;
62 DEBUGFUNC("ixgbe_init_mac_link_ops_82599");
64 /* enable the laser control functions for SFP+ fiber */
65 if (mac->ops.get_media_type(hw) == ixgbe_media_type_fiber) {
66 mac->ops.disable_tx_laser =
67 &ixgbe_disable_tx_laser_multispeed_fiber;
68 mac->ops.enable_tx_laser =
69 &ixgbe_enable_tx_laser_multispeed_fiber;
70 mac->ops.flap_tx_laser = &ixgbe_flap_tx_laser_multispeed_fiber;
73 mac->ops.disable_tx_laser = NULL;
74 mac->ops.enable_tx_laser = NULL;
75 mac->ops.flap_tx_laser = NULL;
78 if (hw->phy.multispeed_fiber) {
79 /* Set up dual speed SFP+ support */
80 mac->ops.setup_link = &ixgbe_setup_mac_link_multispeed_fiber;
82 if ((ixgbe_get_media_type(hw) == ixgbe_media_type_backplane) &&
83 (hw->phy.smart_speed == ixgbe_smart_speed_auto ||
84 hw->phy.smart_speed == ixgbe_smart_speed_on) &&
85 !ixgbe_verify_lesm_fw_enabled_82599(hw)) {
86 mac->ops.setup_link = &ixgbe_setup_mac_link_smartspeed;
88 mac->ops.setup_link = &ixgbe_setup_mac_link_82599;
94 * ixgbe_init_phy_ops_82599 - PHY/SFP specific init
95 * @hw: pointer to hardware structure
97 * Initialize any function pointers that were not able to be
98 * set during init_shared_code because the PHY/SFP type was
99 * not known. Perform the SFP init if necessary.
102 s32 ixgbe_init_phy_ops_82599(struct ixgbe_hw *hw)
104 struct ixgbe_mac_info *mac = &hw->mac;
105 struct ixgbe_phy_info *phy = &hw->phy;
106 s32 ret_val = IXGBE_SUCCESS;
108 DEBUGFUNC("ixgbe_init_phy_ops_82599");
110 /* Identify the PHY or SFP module */
111 ret_val = phy->ops.identify(hw);
112 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED)
113 goto init_phy_ops_out;
115 /* Setup function pointers based on detected SFP module and speeds */
116 ixgbe_init_mac_link_ops_82599(hw);
117 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown)
118 hw->phy.ops.reset = NULL;
120 /* If copper media, overwrite with copper function pointers */
121 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) {
122 mac->ops.setup_link = &ixgbe_setup_copper_link_82599;
123 mac->ops.get_link_capabilities =
124 &ixgbe_get_copper_link_capabilities_generic;
127 /* Set necessary function pointers based on phy type */
128 switch (hw->phy.type) {
130 phy->ops.setup_link = &ixgbe_setup_phy_link_tnx;
131 phy->ops.check_link = &ixgbe_check_phy_link_tnx;
132 phy->ops.get_firmware_version =
133 &ixgbe_get_phy_firmware_version_tnx;
142 s32 ixgbe_setup_sfp_modules_82599(struct ixgbe_hw *hw)
144 s32 ret_val = IXGBE_SUCCESS;
145 u16 list_offset, data_offset, data_value;
146 bool got_lock = false;
148 DEBUGFUNC("ixgbe_setup_sfp_modules_82599");
150 if (hw->phy.sfp_type != ixgbe_sfp_type_unknown) {
151 ixgbe_init_mac_link_ops_82599(hw);
153 hw->phy.ops.reset = NULL;
155 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
157 if (ret_val != IXGBE_SUCCESS)
160 /* PHY config will finish before releasing the semaphore */
161 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
162 IXGBE_GSSR_MAC_CSR_SM);
163 if (ret_val != IXGBE_SUCCESS) {
164 ret_val = IXGBE_ERR_SWFW_SYNC;
168 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
169 while (data_value != 0xffff) {
170 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, data_value);
171 IXGBE_WRITE_FLUSH(hw);
172 hw->eeprom.ops.read(hw, ++data_offset, &data_value);
175 /* Release the semaphore */
176 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
177 /* Delay obtaining semaphore again to allow FW access */
178 msec_delay(hw->eeprom.semaphore_delay);
180 /* Need SW/FW semaphore around AUTOC writes if LESM on,
181 * likewise reset_pipeline requires lock as it also writes
184 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
185 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
186 IXGBE_GSSR_MAC_CSR_SM);
187 if (ret_val != IXGBE_SUCCESS) {
188 ret_val = IXGBE_ERR_SWFW_SYNC;
195 /* Restart DSP and set SFI mode */
196 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, (IXGBE_READ_REG(hw,
197 IXGBE_AUTOC) | IXGBE_AUTOC_LMS_10G_SERIAL));
199 ret_val = ixgbe_reset_pipeline_82599(hw);
202 hw->mac.ops.release_swfw_sync(hw,
203 IXGBE_GSSR_MAC_CSR_SM);
208 DEBUGOUT("sfp module setup not complete\n");
209 ret_val = IXGBE_ERR_SFP_SETUP_NOT_COMPLETE;
220 * ixgbe_init_ops_82599 - Inits func ptrs and MAC type
221 * @hw: pointer to hardware structure
223 * Initialize the function pointers and assign the MAC type for 82599.
224 * Does not touch the hardware.
227 s32 ixgbe_init_ops_82599(struct ixgbe_hw *hw)
229 struct ixgbe_mac_info *mac = &hw->mac;
230 struct ixgbe_phy_info *phy = &hw->phy;
231 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
234 DEBUGFUNC("ixgbe_init_ops_82599");
236 ret_val = ixgbe_init_phy_ops_generic(hw);
237 ret_val = ixgbe_init_ops_generic(hw);
240 phy->ops.identify = &ixgbe_identify_phy_82599;
241 phy->ops.init = &ixgbe_init_phy_ops_82599;
244 mac->ops.reset_hw = &ixgbe_reset_hw_82599;
245 mac->ops.enable_relaxed_ordering = &ixgbe_enable_relaxed_ordering_gen2;
246 mac->ops.get_media_type = &ixgbe_get_media_type_82599;
247 mac->ops.get_supported_physical_layer =
248 &ixgbe_get_supported_physical_layer_82599;
249 mac->ops.disable_sec_rx_path = &ixgbe_disable_sec_rx_path_generic;
250 mac->ops.enable_sec_rx_path = &ixgbe_enable_sec_rx_path_generic;
251 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_82599;
252 mac->ops.read_analog_reg8 = &ixgbe_read_analog_reg8_82599;
253 mac->ops.write_analog_reg8 = &ixgbe_write_analog_reg8_82599;
254 mac->ops.start_hw = &ixgbe_start_hw_82599;
255 mac->ops.get_san_mac_addr = &ixgbe_get_san_mac_addr_generic;
256 mac->ops.set_san_mac_addr = &ixgbe_set_san_mac_addr_generic;
257 mac->ops.get_device_caps = &ixgbe_get_device_caps_generic;
258 mac->ops.get_wwn_prefix = &ixgbe_get_wwn_prefix_generic;
259 mac->ops.get_fcoe_boot_status = &ixgbe_get_fcoe_boot_status_generic;
261 /* RAR, Multicast, VLAN */
262 mac->ops.set_vmdq = &ixgbe_set_vmdq_generic;
263 mac->ops.set_vmdq_san_mac = &ixgbe_set_vmdq_san_mac_generic;
264 mac->ops.clear_vmdq = &ixgbe_clear_vmdq_generic;
265 mac->ops.insert_mac_addr = &ixgbe_insert_mac_addr_generic;
266 mac->rar_highwater = 1;
267 mac->ops.set_vfta = &ixgbe_set_vfta_generic;
268 mac->ops.set_vlvf = &ixgbe_set_vlvf_generic;
269 mac->ops.clear_vfta = &ixgbe_clear_vfta_generic;
270 mac->ops.init_uta_tables = &ixgbe_init_uta_tables_generic;
271 mac->ops.setup_sfp = &ixgbe_setup_sfp_modules_82599;
272 mac->ops.set_mac_anti_spoofing = &ixgbe_set_mac_anti_spoofing;
273 mac->ops.set_vlan_anti_spoofing = &ixgbe_set_vlan_anti_spoofing;
276 mac->ops.get_link_capabilities = &ixgbe_get_link_capabilities_82599;
277 mac->ops.check_link = &ixgbe_check_mac_link_generic;
278 mac->ops.setup_rxpba = &ixgbe_set_rxpba_generic;
279 ixgbe_init_mac_link_ops_82599(hw);
281 mac->mcft_size = IXGBE_82599_MC_TBL_SIZE;
282 mac->vft_size = IXGBE_82599_VFT_TBL_SIZE;
283 mac->num_rar_entries = IXGBE_82599_RAR_ENTRIES;
284 mac->rx_pb_size = IXGBE_82599_RX_PB_SIZE;
285 mac->max_rx_queues = IXGBE_82599_MAX_RX_QUEUES;
286 mac->max_tx_queues = IXGBE_82599_MAX_TX_QUEUES;
287 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw);
289 mac->arc_subsystem_valid = (IXGBE_READ_REG(hw, IXGBE_FWSM) &
290 IXGBE_FWSM_MODE_MASK) ? true : false;
292 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf;
295 eeprom->ops.read = &ixgbe_read_eeprom_82599;
296 eeprom->ops.read_buffer = &ixgbe_read_eeprom_buffer_82599;
298 /* Manageability interface */
299 mac->ops.set_fw_drv_ver = &ixgbe_set_fw_drv_ver_generic;
302 mac->ops.get_rtrup2tc = &ixgbe_dcb_get_rtrup2tc_generic;
308 * ixgbe_get_link_capabilities_82599 - Determines link capabilities
309 * @hw: pointer to hardware structure
310 * @speed: pointer to link speed
311 * @negotiation: true when autoneg or autotry is enabled
313 * Determines the link capabilities by reading the AUTOC register.
315 s32 ixgbe_get_link_capabilities_82599(struct ixgbe_hw *hw,
316 ixgbe_link_speed *speed,
319 s32 status = IXGBE_SUCCESS;
322 DEBUGFUNC("ixgbe_get_link_capabilities_82599");
325 /* Check if 1G SFP module. */
326 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
327 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
328 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
329 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1) {
330 *speed = IXGBE_LINK_SPEED_1GB_FULL;
336 * Determine link capabilities based on the stored value of AUTOC,
337 * which represents EEPROM defaults. If AUTOC value has not
338 * been stored, use the current register values.
340 if (hw->mac.orig_link_settings_stored)
341 autoc = hw->mac.orig_autoc;
343 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
345 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
346 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
347 *speed = IXGBE_LINK_SPEED_1GB_FULL;
348 *negotiation = false;
351 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
352 *speed = IXGBE_LINK_SPEED_10GB_FULL;
353 *negotiation = false;
356 case IXGBE_AUTOC_LMS_1G_AN:
357 *speed = IXGBE_LINK_SPEED_1GB_FULL;
361 case IXGBE_AUTOC_LMS_10G_SERIAL:
362 *speed = IXGBE_LINK_SPEED_10GB_FULL;
363 *negotiation = false;
366 case IXGBE_AUTOC_LMS_KX4_KX_KR:
367 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
368 *speed = IXGBE_LINK_SPEED_UNKNOWN;
369 if (autoc & IXGBE_AUTOC_KR_SUPP)
370 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
371 if (autoc & IXGBE_AUTOC_KX4_SUPP)
372 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
373 if (autoc & IXGBE_AUTOC_KX_SUPP)
374 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
378 case IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII:
379 *speed = IXGBE_LINK_SPEED_100_FULL;
380 if (autoc & IXGBE_AUTOC_KR_SUPP)
381 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
382 if (autoc & IXGBE_AUTOC_KX4_SUPP)
383 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
384 if (autoc & IXGBE_AUTOC_KX_SUPP)
385 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
389 case IXGBE_AUTOC_LMS_SGMII_1G_100M:
390 *speed = IXGBE_LINK_SPEED_1GB_FULL | IXGBE_LINK_SPEED_100_FULL;
391 *negotiation = false;
395 status = IXGBE_ERR_LINK_SETUP;
400 if (hw->phy.multispeed_fiber) {
401 *speed |= IXGBE_LINK_SPEED_10GB_FULL |
402 IXGBE_LINK_SPEED_1GB_FULL;
411 * ixgbe_get_media_type_82599 - Get media type
412 * @hw: pointer to hardware structure
414 * Returns the media type (fiber, copper, backplane)
416 enum ixgbe_media_type ixgbe_get_media_type_82599(struct ixgbe_hw *hw)
418 enum ixgbe_media_type media_type;
420 DEBUGFUNC("ixgbe_get_media_type_82599");
422 /* Detect if there is a copper PHY attached. */
423 switch (hw->phy.type) {
424 case ixgbe_phy_cu_unknown:
426 media_type = ixgbe_media_type_copper;
432 switch (hw->device_id) {
433 case IXGBE_DEV_ID_82599_KX4:
434 case IXGBE_DEV_ID_82599_KX4_MEZZ:
435 case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
436 case IXGBE_DEV_ID_82599_KR:
437 case IXGBE_DEV_ID_82599_BACKPLANE_FCOE:
438 case IXGBE_DEV_ID_82599_XAUI_LOM:
439 /* Default device ID is mezzanine card KX/KX4 */
440 media_type = ixgbe_media_type_backplane;
442 case IXGBE_DEV_ID_82599_SFP:
443 case IXGBE_DEV_ID_82599_SFP_FCOE:
444 case IXGBE_DEV_ID_82599_SFP_EM:
445 case IXGBE_DEV_ID_82599_SFP_SF2:
446 case IXGBE_DEV_ID_82599_SFP_SF_QP:
447 case IXGBE_DEV_ID_82599EN_SFP:
448 #ifdef RTE_NIC_BYPASS
449 case IXGBE_DEV_ID_82599_BYPASS:
451 media_type = ixgbe_media_type_fiber;
453 case IXGBE_DEV_ID_82599_CX4:
454 media_type = ixgbe_media_type_cx4;
456 case IXGBE_DEV_ID_82599_T3_LOM:
457 media_type = ixgbe_media_type_copper;
460 media_type = ixgbe_media_type_unknown;
468 * ixgbe_start_mac_link_82599 - Setup MAC link settings
469 * @hw: pointer to hardware structure
470 * @autoneg_wait_to_complete: true when waiting for completion is needed
472 * Configures link settings based on values in the ixgbe_hw struct.
473 * Restarts the link. Performs autonegotiation if needed.
475 s32 ixgbe_start_mac_link_82599(struct ixgbe_hw *hw,
476 bool autoneg_wait_to_complete)
481 s32 status = IXGBE_SUCCESS;
482 bool got_lock = false;
484 DEBUGFUNC("ixgbe_start_mac_link_82599");
487 /* reset_pipeline requires us to hold this lock as it writes to
490 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
491 status = hw->mac.ops.acquire_swfw_sync(hw,
492 IXGBE_GSSR_MAC_CSR_SM);
493 if (status != IXGBE_SUCCESS)
500 ixgbe_reset_pipeline_82599(hw);
503 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
505 /* Only poll for autoneg to complete if specified to do so */
506 if (autoneg_wait_to_complete) {
507 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
508 if ((autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
509 IXGBE_AUTOC_LMS_KX4_KX_KR ||
510 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
511 IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
512 (autoc_reg & IXGBE_AUTOC_LMS_MASK) ==
513 IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
514 links_reg = 0; /* Just in case Autoneg time = 0 */
515 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
516 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
517 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
521 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
522 status = IXGBE_ERR_AUTONEG_NOT_COMPLETE;
523 DEBUGOUT("Autoneg did not complete.\n");
528 /* Add delay to filter out noises during initial link setup */
536 * ixgbe_disable_tx_laser_multispeed_fiber - Disable Tx laser
537 * @hw: pointer to hardware structure
539 * The base drivers may require better control over SFP+ module
540 * PHY states. This includes selectively shutting down the Tx
541 * laser on the PHY, effectively halting physical link.
543 void ixgbe_disable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
545 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
547 /* Disable tx laser; allow 100us to go dark per spec */
548 esdp_reg |= IXGBE_ESDP_SDP3;
549 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
550 IXGBE_WRITE_FLUSH(hw);
555 * ixgbe_enable_tx_laser_multispeed_fiber - Enable Tx laser
556 * @hw: pointer to hardware structure
558 * The base drivers may require better control over SFP+ module
559 * PHY states. This includes selectively turning on the Tx
560 * laser on the PHY, effectively starting physical link.
562 void ixgbe_enable_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
564 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
566 /* Enable tx laser; allow 100ms to light up */
567 esdp_reg &= ~IXGBE_ESDP_SDP3;
568 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
569 IXGBE_WRITE_FLUSH(hw);
574 * ixgbe_flap_tx_laser_multispeed_fiber - Flap Tx laser
575 * @hw: pointer to hardware structure
577 * When the driver changes the link speeds that it can support,
578 * it sets autotry_restart to true to indicate that we need to
579 * initiate a new autotry session with the link partner. To do
580 * so, we set the speed then disable and re-enable the tx laser, to
581 * alert the link partner that it also needs to restart autotry on its
582 * end. This is consistent with true clause 37 autoneg, which also
583 * involves a loss of signal.
585 void ixgbe_flap_tx_laser_multispeed_fiber(struct ixgbe_hw *hw)
587 DEBUGFUNC("ixgbe_flap_tx_laser_multispeed_fiber");
589 if (hw->mac.autotry_restart) {
590 ixgbe_disable_tx_laser_multispeed_fiber(hw);
591 ixgbe_enable_tx_laser_multispeed_fiber(hw);
592 hw->mac.autotry_restart = false;
597 * ixgbe_setup_mac_link_multispeed_fiber - Set MAC link speed
598 * @hw: pointer to hardware structure
599 * @speed: new link speed
600 * @autoneg: true if autonegotiation enabled
601 * @autoneg_wait_to_complete: true when waiting for completion is needed
603 * Set the link speed in the AUTOC register and restarts link.
605 s32 ixgbe_setup_mac_link_multispeed_fiber(struct ixgbe_hw *hw,
606 ixgbe_link_speed speed, bool autoneg,
607 bool autoneg_wait_to_complete)
609 s32 status = IXGBE_SUCCESS;
610 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
611 ixgbe_link_speed highest_link_speed = IXGBE_LINK_SPEED_UNKNOWN;
613 u32 esdp_reg = IXGBE_READ_REG(hw, IXGBE_ESDP);
615 bool link_up = false;
618 DEBUGFUNC("ixgbe_setup_mac_link_multispeed_fiber");
620 /* Mask off requested but non-supported speeds */
621 status = ixgbe_get_link_capabilities(hw, &link_speed, &negotiation);
622 if (status != IXGBE_SUCCESS)
628 * Try each speed one by one, highest priority first. We do this in
629 * software because 10gb fiber doesn't support speed autonegotiation.
631 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
633 highest_link_speed = IXGBE_LINK_SPEED_10GB_FULL;
635 /* If we already have link at this speed, just jump out */
636 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
637 if (status != IXGBE_SUCCESS)
640 if ((link_speed == IXGBE_LINK_SPEED_10GB_FULL) && link_up)
643 /* Set the module link speed */
644 esdp_reg |= (IXGBE_ESDP_SDP5_DIR | IXGBE_ESDP_SDP5);
645 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
646 IXGBE_WRITE_FLUSH(hw);
648 /* Allow module to change analog characteristics (1G->10G) */
651 status = ixgbe_setup_mac_link_82599(hw,
652 IXGBE_LINK_SPEED_10GB_FULL,
654 autoneg_wait_to_complete);
655 if (status != IXGBE_SUCCESS)
658 /* Flap the tx laser if it has not already been done */
659 ixgbe_flap_tx_laser(hw);
662 * Wait for the controller to acquire link. Per IEEE 802.3ap,
663 * Section 73.10.2, we may have to wait up to 500ms if KR is
664 * attempted. 82599 uses the same timing for 10g SFI.
666 for (i = 0; i < 5; i++) {
667 /* Wait for the link partner to also set speed */
670 /* If we have link, just jump out */
671 status = ixgbe_check_link(hw, &link_speed,
673 if (status != IXGBE_SUCCESS)
681 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
683 if (highest_link_speed == IXGBE_LINK_SPEED_UNKNOWN)
684 highest_link_speed = IXGBE_LINK_SPEED_1GB_FULL;
686 /* If we already have link at this speed, just jump out */
687 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
688 if (status != IXGBE_SUCCESS)
691 if ((link_speed == IXGBE_LINK_SPEED_1GB_FULL) && link_up)
694 /* Set the module link speed */
695 esdp_reg &= ~IXGBE_ESDP_SDP5;
696 esdp_reg |= IXGBE_ESDP_SDP5_DIR;
697 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp_reg);
698 IXGBE_WRITE_FLUSH(hw);
700 /* Allow module to change analog characteristics (10G->1G) */
703 status = ixgbe_setup_mac_link_82599(hw,
704 IXGBE_LINK_SPEED_1GB_FULL,
706 autoneg_wait_to_complete);
707 if (status != IXGBE_SUCCESS)
710 /* Flap the tx laser if it has not already been done */
711 ixgbe_flap_tx_laser(hw);
713 /* Wait for the link partner to also set speed */
716 /* If we have link, just jump out */
717 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
718 if (status != IXGBE_SUCCESS)
726 * We didn't get link. Configure back to the highest speed we tried,
727 * (if there was more than one). We call ourselves back with just the
728 * single highest speed that the user requested.
731 status = ixgbe_setup_mac_link_multispeed_fiber(hw,
732 highest_link_speed, autoneg, autoneg_wait_to_complete);
735 /* Set autoneg_advertised value based on input link speed */
736 hw->phy.autoneg_advertised = 0;
738 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
739 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
741 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
742 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
748 * ixgbe_setup_mac_link_smartspeed - Set MAC link speed using SmartSpeed
749 * @hw: pointer to hardware structure
750 * @speed: new link speed
751 * @autoneg: true if autonegotiation enabled
752 * @autoneg_wait_to_complete: true when waiting for completion is needed
754 * Implements the Intel SmartSpeed algorithm.
756 s32 ixgbe_setup_mac_link_smartspeed(struct ixgbe_hw *hw,
757 ixgbe_link_speed speed, bool autoneg,
758 bool autoneg_wait_to_complete)
760 s32 status = IXGBE_SUCCESS;
761 ixgbe_link_speed link_speed = IXGBE_LINK_SPEED_UNKNOWN;
763 bool link_up = false;
764 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
766 DEBUGFUNC("ixgbe_setup_mac_link_smartspeed");
768 /* Set autoneg_advertised value based on input link speed */
769 hw->phy.autoneg_advertised = 0;
771 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
772 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
774 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
775 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
777 if (speed & IXGBE_LINK_SPEED_100_FULL)
778 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
781 * Implement Intel SmartSpeed algorithm. SmartSpeed will reduce the
782 * autoneg advertisement if link is unable to be established at the
783 * highest negotiated rate. This can sometimes happen due to integrity
784 * issues with the physical media connection.
787 /* First, try to get link with full advertisement */
788 hw->phy.smart_speed_active = false;
789 for (j = 0; j < IXGBE_SMARTSPEED_MAX_RETRIES; j++) {
790 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
791 autoneg_wait_to_complete);
792 if (status != IXGBE_SUCCESS)
796 * Wait for the controller to acquire link. Per IEEE 802.3ap,
797 * Section 73.10.2, we may have to wait up to 500ms if KR is
798 * attempted, or 200ms if KX/KX4/BX/BX4 is attempted, per
799 * Table 9 in the AN MAS.
801 for (i = 0; i < 5; i++) {
804 /* If we have link, just jump out */
805 status = ixgbe_check_link(hw, &link_speed, &link_up,
807 if (status != IXGBE_SUCCESS)
816 * We didn't get link. If we advertised KR plus one of KX4/KX
817 * (or BX4/BX), then disable KR and try again.
819 if (((autoc_reg & IXGBE_AUTOC_KR_SUPP) == 0) ||
820 ((autoc_reg & IXGBE_AUTOC_KX4_KX_SUPP_MASK) == 0))
823 /* Turn SmartSpeed on to disable KR support */
824 hw->phy.smart_speed_active = true;
825 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
826 autoneg_wait_to_complete);
827 if (status != IXGBE_SUCCESS)
831 * Wait for the controller to acquire link. 600ms will allow for
832 * the AN link_fail_inhibit_timer as well for multiple cycles of
833 * parallel detect, both 10g and 1g. This allows for the maximum
834 * connect attempts as defined in the AN MAS table 73-7.
836 for (i = 0; i < 6; i++) {
839 /* If we have link, just jump out */
840 status = ixgbe_check_link(hw, &link_speed, &link_up, false);
841 if (status != IXGBE_SUCCESS)
848 /* We didn't get link. Turn SmartSpeed back off. */
849 hw->phy.smart_speed_active = false;
850 status = ixgbe_setup_mac_link_82599(hw, speed, autoneg,
851 autoneg_wait_to_complete);
854 if (link_up && (link_speed == IXGBE_LINK_SPEED_1GB_FULL))
855 DEBUGOUT("Smartspeed has downgraded the link speed "
856 "from the maximum advertised\n");
861 * ixgbe_setup_mac_link_82599 - Set MAC link speed
862 * @hw: pointer to hardware structure
863 * @speed: new link speed
864 * @autoneg: true if autonegotiation enabled
865 * @autoneg_wait_to_complete: true when waiting for completion is needed
867 * Set the link speed in the AUTOC register and restarts link.
869 s32 ixgbe_setup_mac_link_82599(struct ixgbe_hw *hw,
870 ixgbe_link_speed speed, bool autoneg,
871 bool autoneg_wait_to_complete)
873 s32 status = IXGBE_SUCCESS;
874 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
875 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
876 u32 start_autoc = autoc;
878 u32 link_mode = autoc & IXGBE_AUTOC_LMS_MASK;
879 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
880 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
883 ixgbe_link_speed link_capabilities = IXGBE_LINK_SPEED_UNKNOWN;
884 bool got_lock = false;
886 DEBUGFUNC("ixgbe_setup_mac_link_82599");
888 /* Check to see if speed passed in is supported. */
889 status = ixgbe_get_link_capabilities(hw, &link_capabilities, &autoneg);
893 speed &= link_capabilities;
895 if (speed == IXGBE_LINK_SPEED_UNKNOWN) {
896 status = IXGBE_ERR_LINK_SETUP;
900 /* Use stored value (EEPROM defaults) of AUTOC to find KR/KX4 support*/
901 if (hw->mac.orig_link_settings_stored)
902 orig_autoc = hw->mac.orig_autoc;
906 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
907 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
908 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
909 /* Set KX4/KX/KR support according to speed requested */
910 autoc &= ~(IXGBE_AUTOC_KX4_KX_SUPP_MASK | IXGBE_AUTOC_KR_SUPP);
911 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
912 if (orig_autoc & IXGBE_AUTOC_KX4_SUPP)
913 autoc |= IXGBE_AUTOC_KX4_SUPP;
914 if ((orig_autoc & IXGBE_AUTOC_KR_SUPP) &&
915 (hw->phy.smart_speed_active == false))
916 autoc |= IXGBE_AUTOC_KR_SUPP;
918 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
919 autoc |= IXGBE_AUTOC_KX_SUPP;
920 } else if ((pma_pmd_1g == IXGBE_AUTOC_1G_SFI) &&
921 (link_mode == IXGBE_AUTOC_LMS_1G_LINK_NO_AN ||
922 link_mode == IXGBE_AUTOC_LMS_1G_AN)) {
923 /* Switch from 1G SFI to 10G SFI if requested */
924 if ((speed == IXGBE_LINK_SPEED_10GB_FULL) &&
925 (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)) {
926 autoc &= ~IXGBE_AUTOC_LMS_MASK;
927 autoc |= IXGBE_AUTOC_LMS_10G_SERIAL;
929 } else if ((pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI) &&
930 (link_mode == IXGBE_AUTOC_LMS_10G_SERIAL)) {
931 /* Switch from 10G SFI to 1G SFI if requested */
932 if ((speed == IXGBE_LINK_SPEED_1GB_FULL) &&
933 (pma_pmd_1g == IXGBE_AUTOC_1G_SFI)) {
934 autoc &= ~IXGBE_AUTOC_LMS_MASK;
936 autoc |= IXGBE_AUTOC_LMS_1G_AN;
938 autoc |= IXGBE_AUTOC_LMS_1G_LINK_NO_AN;
942 if (autoc != start_autoc) {
943 /* Need SW/FW semaphore around AUTOC writes if LESM is on,
944 * likewise reset_pipeline requires us to hold this lock as
945 * it also writes to AUTOC.
947 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
948 status = hw->mac.ops.acquire_swfw_sync(hw,
949 IXGBE_GSSR_MAC_CSR_SM);
950 if (status != IXGBE_SUCCESS) {
951 status = IXGBE_ERR_SWFW_SYNC;
959 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc);
960 ixgbe_reset_pipeline_82599(hw);
963 hw->mac.ops.release_swfw_sync(hw,
964 IXGBE_GSSR_MAC_CSR_SM);
968 /* Only poll for autoneg to complete if specified to do so */
969 if (autoneg_wait_to_complete) {
970 if (link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR ||
971 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN ||
972 link_mode == IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII) {
973 links_reg = 0; /*Just in case Autoneg time=0*/
974 for (i = 0; i < IXGBE_AUTO_NEG_TIME; i++) {
976 IXGBE_READ_REG(hw, IXGBE_LINKS);
977 if (links_reg & IXGBE_LINKS_KX_AN_COMP)
981 if (!(links_reg & IXGBE_LINKS_KX_AN_COMP)) {
983 IXGBE_ERR_AUTONEG_NOT_COMPLETE;
984 DEBUGOUT("Autoneg did not complete.\n");
989 /* Add delay to filter out noises during initial link setup */
998 * ixgbe_setup_copper_link_82599 - Set the PHY autoneg advertised field
999 * @hw: pointer to hardware structure
1000 * @speed: new link speed
1001 * @autoneg: true if autonegotiation enabled
1002 * @autoneg_wait_to_complete: true if waiting is needed to complete
1004 * Restarts link on PHY and MAC based on settings passed in.
1006 STATIC s32 ixgbe_setup_copper_link_82599(struct ixgbe_hw *hw,
1007 ixgbe_link_speed speed,
1009 bool autoneg_wait_to_complete)
1013 DEBUGFUNC("ixgbe_setup_copper_link_82599");
1015 /* Setup the PHY according to input speed */
1016 status = hw->phy.ops.setup_link_speed(hw, speed, autoneg,
1017 autoneg_wait_to_complete);
1019 ixgbe_start_mac_link_82599(hw, autoneg_wait_to_complete);
1025 * ixgbe_reset_hw_82599 - Perform hardware reset
1026 * @hw: pointer to hardware structure
1028 * Resets the hardware by resetting the transmit and receive units, masks
1029 * and clears all interrupts, perform a PHY reset, and perform a link (MAC)
1032 s32 ixgbe_reset_hw_82599(struct ixgbe_hw *hw)
1034 ixgbe_link_speed link_speed;
1036 u32 ctrl, i, autoc, autoc2;
1037 bool link_up = false;
1039 DEBUGFUNC("ixgbe_reset_hw_82599");
1041 /* Call adapter stop to disable tx/rx and clear interrupts */
1042 status = hw->mac.ops.stop_adapter(hw);
1043 if (status != IXGBE_SUCCESS)
1046 /* flush pending Tx transactions */
1047 ixgbe_clear_tx_pending(hw);
1049 /* PHY ops must be identified and initialized prior to reset */
1051 /* Identify PHY and related function pointers */
1052 status = hw->phy.ops.init(hw);
1054 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1057 /* Setup SFP module if there is one present. */
1058 if (hw->phy.sfp_setup_needed) {
1059 status = hw->mac.ops.setup_sfp(hw);
1060 hw->phy.sfp_setup_needed = false;
1063 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED)
1067 if (hw->phy.reset_disable == false && hw->phy.ops.reset != NULL)
1068 hw->phy.ops.reset(hw);
1072 * Issue global reset to the MAC. Needs to be SW reset if link is up.
1073 * If link reset is used when link is up, it might reset the PHY when
1074 * mng is using it. If link is down or the flag to force full link
1075 * reset is set, then perform link reset.
1077 ctrl = IXGBE_CTRL_LNK_RST;
1078 if (!hw->force_full_reset) {
1079 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
1081 ctrl = IXGBE_CTRL_RST;
1084 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL);
1085 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
1086 IXGBE_WRITE_FLUSH(hw);
1088 /* Poll for reset bit to self-clear meaning reset is complete */
1089 for (i = 0; i < 10; i++) {
1091 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
1092 if (!(ctrl & IXGBE_CTRL_RST_MASK))
1096 if (ctrl & IXGBE_CTRL_RST_MASK) {
1097 status = IXGBE_ERR_RESET_FAILED;
1098 DEBUGOUT("Reset polling failed to complete.\n");
1104 * Double resets are required for recovery from certain error
1105 * conditions. Between resets, it is necessary to stall to
1106 * allow time for any pending HW events to complete.
1108 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) {
1109 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
1114 * Store the original AUTOC/AUTOC2 values if they have not been
1115 * stored off yet. Otherwise restore the stored original
1116 * values since the reset operation sets back to defaults.
1118 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
1119 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
1121 /* Enable link if disabled in NVM */
1122 if (autoc2 & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
1123 autoc2 &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
1124 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1125 IXGBE_WRITE_FLUSH(hw);
1128 if (hw->mac.orig_link_settings_stored == false) {
1129 hw->mac.orig_autoc = autoc;
1130 hw->mac.orig_autoc2 = autoc2;
1131 hw->mac.orig_link_settings_stored = true;
1133 if (autoc != hw->mac.orig_autoc) {
1134 /* Need SW/FW semaphore around AUTOC writes if LESM is
1135 * on, likewise reset_pipeline requires us to hold
1136 * this lock as it also writes to AUTOC.
1138 bool got_lock = false;
1139 if (ixgbe_verify_lesm_fw_enabled_82599(hw)) {
1140 status = hw->mac.ops.acquire_swfw_sync(hw,
1141 IXGBE_GSSR_MAC_CSR_SM);
1142 if (status != IXGBE_SUCCESS) {
1143 status = IXGBE_ERR_SWFW_SYNC;
1150 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, hw->mac.orig_autoc);
1151 ixgbe_reset_pipeline_82599(hw);
1154 hw->mac.ops.release_swfw_sync(hw,
1155 IXGBE_GSSR_MAC_CSR_SM);
1158 if ((autoc2 & IXGBE_AUTOC2_UPPER_MASK) !=
1159 (hw->mac.orig_autoc2 & IXGBE_AUTOC2_UPPER_MASK)) {
1160 autoc2 &= ~IXGBE_AUTOC2_UPPER_MASK;
1161 autoc2 |= (hw->mac.orig_autoc2 &
1162 IXGBE_AUTOC2_UPPER_MASK);
1163 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2);
1167 /* Store the permanent mac address */
1168 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr);
1171 * Store MAC address from RAR0, clear receive address registers, and
1172 * clear the multicast table. Also reset num_rar_entries to 128,
1173 * since we modify this value when programming the SAN MAC address.
1175 hw->mac.num_rar_entries = 128;
1176 hw->mac.ops.init_rx_addrs(hw);
1178 /* Store the permanent SAN mac address */
1179 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr);
1181 /* Add the SAN MAC address to the RAR only if it's a valid address */
1182 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) {
1183 hw->mac.ops.set_rar(hw, hw->mac.num_rar_entries - 1,
1184 hw->mac.san_addr, 0, IXGBE_RAH_AV);
1186 /* Save the SAN MAC RAR index */
1187 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1;
1189 /* Reserve the last RAR for the SAN MAC address */
1190 hw->mac.num_rar_entries--;
1193 /* Store the alternative WWNN/WWPN prefix */
1194 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix,
1195 &hw->mac.wwpn_prefix);
1202 * ixgbe_reinit_fdir_tables_82599 - Reinitialize Flow Director tables.
1203 * @hw: pointer to hardware structure
1205 s32 ixgbe_reinit_fdir_tables_82599(struct ixgbe_hw *hw)
1208 u32 fdirctrl = IXGBE_READ_REG(hw, IXGBE_FDIRCTRL);
1209 fdirctrl &= ~IXGBE_FDIRCTRL_INIT_DONE;
1211 DEBUGFUNC("ixgbe_reinit_fdir_tables_82599");
1214 * Before starting reinitialization process,
1215 * FDIRCMD.CMD must be zero.
1217 for (i = 0; i < IXGBE_FDIRCMD_CMD_POLL; i++) {
1218 if (!(IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1219 IXGBE_FDIRCMD_CMD_MASK))
1223 if (i >= IXGBE_FDIRCMD_CMD_POLL) {
1224 DEBUGOUT("Flow Director previous command isn't complete, "
1225 "aborting table re-initialization.\n");
1226 return IXGBE_ERR_FDIR_REINIT_FAILED;
1229 IXGBE_WRITE_REG(hw, IXGBE_FDIRFREE, 0);
1230 IXGBE_WRITE_FLUSH(hw);
1232 * 82599 adapters flow director init flow cannot be restarted,
1233 * Workaround 82599 silicon errata by performing the following steps
1234 * before re-writing the FDIRCTRL control register with the same value.
1235 * - write 1 to bit 8 of FDIRCMD register &
1236 * - write 0 to bit 8 of FDIRCMD register
1238 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1239 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) |
1240 IXGBE_FDIRCMD_CLEARHT));
1241 IXGBE_WRITE_FLUSH(hw);
1242 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1243 (IXGBE_READ_REG(hw, IXGBE_FDIRCMD) &
1244 ~IXGBE_FDIRCMD_CLEARHT));
1245 IXGBE_WRITE_FLUSH(hw);
1247 * Clear FDIR Hash register to clear any leftover hashes
1248 * waiting to be programmed.
1250 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, 0x00);
1251 IXGBE_WRITE_FLUSH(hw);
1253 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1254 IXGBE_WRITE_FLUSH(hw);
1256 /* Poll init-done after we write FDIRCTRL register */
1257 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1258 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1259 IXGBE_FDIRCTRL_INIT_DONE)
1263 if (i >= IXGBE_FDIR_INIT_DONE_POLL) {
1264 DEBUGOUT("Flow Director Signature poll time exceeded!\n");
1265 return IXGBE_ERR_FDIR_REINIT_FAILED;
1268 /* Clear FDIR statistics registers (read to clear) */
1269 IXGBE_READ_REG(hw, IXGBE_FDIRUSTAT);
1270 IXGBE_READ_REG(hw, IXGBE_FDIRFSTAT);
1271 IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
1272 IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
1273 IXGBE_READ_REG(hw, IXGBE_FDIRLEN);
1275 return IXGBE_SUCCESS;
1279 * ixgbe_fdir_enable_82599 - Initialize Flow Director control registers
1280 * @hw: pointer to hardware structure
1281 * @fdirctrl: value to write to flow director control register
1283 STATIC void ixgbe_fdir_enable_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1287 DEBUGFUNC("ixgbe_fdir_enable_82599");
1289 /* Prime the keys for hashing */
1290 IXGBE_WRITE_REG(hw, IXGBE_FDIRHKEY, IXGBE_ATR_BUCKET_HASH_KEY);
1291 IXGBE_WRITE_REG(hw, IXGBE_FDIRSKEY, IXGBE_ATR_SIGNATURE_HASH_KEY);
1294 * Poll init-done after we write the register. Estimated times:
1295 * 10G: PBALLOC = 11b, timing is 60us
1296 * 1G: PBALLOC = 11b, timing is 600us
1297 * 100M: PBALLOC = 11b, timing is 6ms
1299 * Multiple these timings by 4 if under full Rx load
1301 * So we'll poll for IXGBE_FDIR_INIT_DONE_POLL times, sleeping for
1302 * 1 msec per poll time. If we're at line rate and drop to 100M, then
1303 * this might not finish in our poll time, but we can live with that
1306 IXGBE_WRITE_REG(hw, IXGBE_FDIRCTRL, fdirctrl);
1307 IXGBE_WRITE_FLUSH(hw);
1308 for (i = 0; i < IXGBE_FDIR_INIT_DONE_POLL; i++) {
1309 if (IXGBE_READ_REG(hw, IXGBE_FDIRCTRL) &
1310 IXGBE_FDIRCTRL_INIT_DONE)
1315 if (i >= IXGBE_FDIR_INIT_DONE_POLL)
1316 DEBUGOUT("Flow Director poll time exceeded!\n");
1320 * ixgbe_init_fdir_signature_82599 - Initialize Flow Director signature filters
1321 * @hw: pointer to hardware structure
1322 * @fdirctrl: value to write to flow director control register, initially
1323 * contains just the value of the Rx packet buffer allocation
1325 s32 ixgbe_init_fdir_signature_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1327 DEBUGFUNC("ixgbe_init_fdir_signature_82599");
1330 * Continue setup of fdirctrl register bits:
1331 * Move the flexible bytes to use the ethertype - shift 6 words
1332 * Set the maximum length per hash bucket to 0xA filters
1333 * Send interrupt when 64 filters are left
1335 fdirctrl |= (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1336 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1337 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1339 /* write hashes and fdirctrl register, poll for completion */
1340 ixgbe_fdir_enable_82599(hw, fdirctrl);
1342 return IXGBE_SUCCESS;
1346 * ixgbe_init_fdir_perfect_82599 - Initialize Flow Director perfect filters
1347 * @hw: pointer to hardware structure
1348 * @fdirctrl: value to write to flow director control register, initially
1349 * contains just the value of the Rx packet buffer allocation
1351 s32 ixgbe_init_fdir_perfect_82599(struct ixgbe_hw *hw, u32 fdirctrl)
1353 DEBUGFUNC("ixgbe_init_fdir_perfect_82599");
1356 * Continue setup of fdirctrl register bits:
1357 * Turn perfect match filtering on
1358 * Report hash in RSS field of Rx wb descriptor
1359 * Initialize the drop queue
1360 * Move the flexible bytes to use the ethertype - shift 6 words
1361 * Set the maximum length per hash bucket to 0xA filters
1362 * Send interrupt when 64 (0x4 * 16) filters are left
1364 fdirctrl |= IXGBE_FDIRCTRL_PERFECT_MATCH |
1365 IXGBE_FDIRCTRL_REPORT_STATUS |
1366 (IXGBE_FDIR_DROP_QUEUE << IXGBE_FDIRCTRL_DROP_Q_SHIFT) |
1367 (0x6 << IXGBE_FDIRCTRL_FLEX_SHIFT) |
1368 (0xA << IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT) |
1369 (4 << IXGBE_FDIRCTRL_FULL_THRESH_SHIFT);
1372 /* write hashes and fdirctrl register, poll for completion */
1373 ixgbe_fdir_enable_82599(hw, fdirctrl);
1375 return IXGBE_SUCCESS;
1379 * These defines allow us to quickly generate all of the necessary instructions
1380 * in the function below by simply calling out IXGBE_COMPUTE_SIG_HASH_ITERATION
1381 * for values 0 through 15
1383 #define IXGBE_ATR_COMMON_HASH_KEY \
1384 (IXGBE_ATR_BUCKET_HASH_KEY & IXGBE_ATR_SIGNATURE_HASH_KEY)
1385 #define IXGBE_COMPUTE_SIG_HASH_ITERATION(_n) \
1388 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << n)) \
1389 common_hash ^= lo_hash_dword >> n; \
1390 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1391 bucket_hash ^= lo_hash_dword >> n; \
1392 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << n)) \
1393 sig_hash ^= lo_hash_dword << (16 - n); \
1394 if (IXGBE_ATR_COMMON_HASH_KEY & (0x01 << (n + 16))) \
1395 common_hash ^= hi_hash_dword >> n; \
1396 else if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1397 bucket_hash ^= hi_hash_dword >> n; \
1398 else if (IXGBE_ATR_SIGNATURE_HASH_KEY & (0x01 << (n + 16))) \
1399 sig_hash ^= hi_hash_dword << (16 - n); \
1403 * ixgbe_atr_compute_sig_hash_82599 - Compute the signature hash
1404 * @stream: input bitstream to compute the hash on
1406 * This function is almost identical to the function above but contains
1407 * several optomizations such as unwinding all of the loops, letting the
1408 * compiler work out all of the conditional ifs since the keys are static
1409 * defines, and computing two keys at once since the hashed dword stream
1410 * will be the same for both keys.
1412 u32 ixgbe_atr_compute_sig_hash_82599(union ixgbe_atr_hash_dword input,
1413 union ixgbe_atr_hash_dword common)
1415 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1416 u32 sig_hash = 0, bucket_hash = 0, common_hash = 0;
1418 /* record the flow_vm_vlan bits as they are a key part to the hash */
1419 flow_vm_vlan = IXGBE_NTOHL(input.dword);
1421 /* generate common hash dword */
1422 hi_hash_dword = IXGBE_NTOHL(common.dword);
1424 /* low dword is word swapped version of common */
1425 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1427 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1428 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1430 /* Process bits 0 and 16 */
1431 IXGBE_COMPUTE_SIG_HASH_ITERATION(0);
1434 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1435 * delay this because bit 0 of the stream should not be processed
1436 * so we do not add the vlan until after bit 0 was processed
1438 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1440 /* Process remaining 30 bit of the key */
1441 IXGBE_COMPUTE_SIG_HASH_ITERATION(1);
1442 IXGBE_COMPUTE_SIG_HASH_ITERATION(2);
1443 IXGBE_COMPUTE_SIG_HASH_ITERATION(3);
1444 IXGBE_COMPUTE_SIG_HASH_ITERATION(4);
1445 IXGBE_COMPUTE_SIG_HASH_ITERATION(5);
1446 IXGBE_COMPUTE_SIG_HASH_ITERATION(6);
1447 IXGBE_COMPUTE_SIG_HASH_ITERATION(7);
1448 IXGBE_COMPUTE_SIG_HASH_ITERATION(8);
1449 IXGBE_COMPUTE_SIG_HASH_ITERATION(9);
1450 IXGBE_COMPUTE_SIG_HASH_ITERATION(10);
1451 IXGBE_COMPUTE_SIG_HASH_ITERATION(11);
1452 IXGBE_COMPUTE_SIG_HASH_ITERATION(12);
1453 IXGBE_COMPUTE_SIG_HASH_ITERATION(13);
1454 IXGBE_COMPUTE_SIG_HASH_ITERATION(14);
1455 IXGBE_COMPUTE_SIG_HASH_ITERATION(15);
1457 /* combine common_hash result with signature and bucket hashes */
1458 bucket_hash ^= common_hash;
1459 bucket_hash &= IXGBE_ATR_HASH_MASK;
1461 sig_hash ^= common_hash << 16;
1462 sig_hash &= IXGBE_ATR_HASH_MASK << 16;
1464 /* return completed signature hash */
1465 return sig_hash ^ bucket_hash;
1469 * ixgbe_atr_add_signature_filter_82599 - Adds a signature hash filter
1470 * @hw: pointer to hardware structure
1471 * @input: unique input dword
1472 * @common: compressed common input dword
1473 * @queue: queue index to direct traffic to
1475 s32 ixgbe_fdir_add_signature_filter_82599(struct ixgbe_hw *hw,
1476 union ixgbe_atr_hash_dword input,
1477 union ixgbe_atr_hash_dword common,
1483 DEBUGFUNC("ixgbe_fdir_add_signature_filter_82599");
1486 * Get the flow_type in order to program FDIRCMD properly
1487 * lowest 2 bits are FDIRCMD.L4TYPE, third lowest bit is FDIRCMD.IPV6
1488 * fifth is FDIRCMD.TUNNEL_FILTER
1490 switch (input.formatted.flow_type) {
1491 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1492 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1493 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1494 case IXGBE_ATR_FLOW_TYPE_TCPV6:
1495 case IXGBE_ATR_FLOW_TYPE_UDPV6:
1496 case IXGBE_ATR_FLOW_TYPE_SCTPV6:
1499 DEBUGOUT(" Error on flow type input\n");
1500 return IXGBE_ERR_CONFIG;
1503 /* configure FDIRCMD register */
1504 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1505 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1506 fdircmd |= input.formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1507 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1510 * The lower 32-bits of fdirhashcmd is for FDIRHASH, the upper 32-bits
1511 * is for FDIRCMD. Then do a 64-bit register write from FDIRHASH.
1513 fdirhashcmd = (u64)fdircmd << 32;
1514 fdirhashcmd |= ixgbe_atr_compute_sig_hash_82599(input, common);
1515 IXGBE_WRITE_REG64(hw, IXGBE_FDIRHASH, fdirhashcmd);
1517 DEBUGOUT2("Tx Queue=%x hash=%x\n", queue, (u32)fdirhashcmd);
1519 return IXGBE_SUCCESS;
1522 #define IXGBE_COMPUTE_BKT_HASH_ITERATION(_n) \
1525 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << n)) \
1526 bucket_hash ^= lo_hash_dword >> n; \
1527 if (IXGBE_ATR_BUCKET_HASH_KEY & (0x01 << (n + 16))) \
1528 bucket_hash ^= hi_hash_dword >> n; \
1532 * ixgbe_atr_compute_perfect_hash_82599 - Compute the perfect filter hash
1533 * @atr_input: input bitstream to compute the hash on
1534 * @input_mask: mask for the input bitstream
1536 * This function serves two main purposes. First it applys the input_mask
1537 * to the atr_input resulting in a cleaned up atr_input data stream.
1538 * Secondly it computes the hash and stores it in the bkt_hash field at
1539 * the end of the input byte stream. This way it will be available for
1540 * future use without needing to recompute the hash.
1542 void ixgbe_atr_compute_perfect_hash_82599(union ixgbe_atr_input *input,
1543 union ixgbe_atr_input *input_mask)
1546 u32 hi_hash_dword, lo_hash_dword, flow_vm_vlan;
1547 u32 bucket_hash = 0;
1549 /* Apply masks to input data */
1550 input->dword_stream[0] &= input_mask->dword_stream[0];
1551 input->dword_stream[1] &= input_mask->dword_stream[1];
1552 input->dword_stream[2] &= input_mask->dword_stream[2];
1553 input->dword_stream[3] &= input_mask->dword_stream[3];
1554 input->dword_stream[4] &= input_mask->dword_stream[4];
1555 input->dword_stream[5] &= input_mask->dword_stream[5];
1556 input->dword_stream[6] &= input_mask->dword_stream[6];
1557 input->dword_stream[7] &= input_mask->dword_stream[7];
1558 input->dword_stream[8] &= input_mask->dword_stream[8];
1559 input->dword_stream[9] &= input_mask->dword_stream[9];
1560 input->dword_stream[10] &= input_mask->dword_stream[10];
1562 /* record the flow_vm_vlan bits as they are a key part to the hash */
1563 flow_vm_vlan = IXGBE_NTOHL(input->dword_stream[0]);
1565 /* generate common hash dword */
1566 hi_hash_dword = IXGBE_NTOHL(input->dword_stream[1] ^
1567 input->dword_stream[2] ^
1568 input->dword_stream[3] ^
1569 input->dword_stream[4] ^
1570 input->dword_stream[5] ^
1571 input->dword_stream[6] ^
1572 input->dword_stream[7] ^
1573 input->dword_stream[8] ^
1574 input->dword_stream[9] ^
1575 input->dword_stream[10]);
1577 /* low dword is word swapped version of common */
1578 lo_hash_dword = (hi_hash_dword >> 16) | (hi_hash_dword << 16);
1580 /* apply flow ID/VM pool/VLAN ID bits to hash words */
1581 hi_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan >> 16);
1583 /* Process bits 0 and 16 */
1584 IXGBE_COMPUTE_BKT_HASH_ITERATION(0);
1587 * apply flow ID/VM pool/VLAN ID bits to lo hash dword, we had to
1588 * delay this because bit 0 of the stream should not be processed
1589 * so we do not add the vlan until after bit 0 was processed
1591 lo_hash_dword ^= flow_vm_vlan ^ (flow_vm_vlan << 16);
1593 /* Process remaining 30 bit of the key */
1594 IXGBE_COMPUTE_BKT_HASH_ITERATION(1);
1595 IXGBE_COMPUTE_BKT_HASH_ITERATION(2);
1596 IXGBE_COMPUTE_BKT_HASH_ITERATION(3);
1597 IXGBE_COMPUTE_BKT_HASH_ITERATION(4);
1598 IXGBE_COMPUTE_BKT_HASH_ITERATION(5);
1599 IXGBE_COMPUTE_BKT_HASH_ITERATION(6);
1600 IXGBE_COMPUTE_BKT_HASH_ITERATION(7);
1601 IXGBE_COMPUTE_BKT_HASH_ITERATION(8);
1602 IXGBE_COMPUTE_BKT_HASH_ITERATION(9);
1603 IXGBE_COMPUTE_BKT_HASH_ITERATION(10);
1604 IXGBE_COMPUTE_BKT_HASH_ITERATION(11);
1605 IXGBE_COMPUTE_BKT_HASH_ITERATION(12);
1606 IXGBE_COMPUTE_BKT_HASH_ITERATION(13);
1607 IXGBE_COMPUTE_BKT_HASH_ITERATION(14);
1608 IXGBE_COMPUTE_BKT_HASH_ITERATION(15);
1611 * Limit hash to 13 bits since max bucket count is 8K.
1612 * Store result at the end of the input stream.
1614 input->formatted.bkt_hash = bucket_hash & 0x1FFF;
1618 * ixgbe_get_fdirtcpm_82599 - generate a tcp port from atr_input_masks
1619 * @input_mask: mask to be bit swapped
1621 * The source and destination port masks for flow director are bit swapped
1622 * in that bit 15 effects bit 0, 14 effects 1, 13, 2 etc. In order to
1623 * generate a correctly swapped value we need to bit swap the mask and that
1624 * is what is accomplished by this function.
1626 STATIC u32 ixgbe_get_fdirtcpm_82599(union ixgbe_atr_input *input_mask)
1628 u32 mask = IXGBE_NTOHS(input_mask->formatted.dst_port);
1629 mask <<= IXGBE_FDIRTCPM_DPORTM_SHIFT;
1630 mask |= IXGBE_NTOHS(input_mask->formatted.src_port);
1631 mask = ((mask & 0x55555555) << 1) | ((mask & 0xAAAAAAAA) >> 1);
1632 mask = ((mask & 0x33333333) << 2) | ((mask & 0xCCCCCCCC) >> 2);
1633 mask = ((mask & 0x0F0F0F0F) << 4) | ((mask & 0xF0F0F0F0) >> 4);
1634 return ((mask & 0x00FF00FF) << 8) | ((mask & 0xFF00FF00) >> 8);
1638 * These two macros are meant to address the fact that we have registers
1639 * that are either all or in part big-endian. As a result on big-endian
1640 * systems we will end up byte swapping the value to little-endian before
1641 * it is byte swapped again and written to the hardware in the original
1642 * big-endian format.
1644 #define IXGBE_STORE_AS_BE32(_value) \
1645 (((u32)(_value) >> 24) | (((u32)(_value) & 0x00FF0000) >> 8) | \
1646 (((u32)(_value) & 0x0000FF00) << 8) | ((u32)(_value) << 24))
1648 #define IXGBE_WRITE_REG_BE32(a, reg, value) \
1649 IXGBE_WRITE_REG((a), (reg), IXGBE_STORE_AS_BE32(IXGBE_NTOHL(value)))
1651 #define IXGBE_STORE_AS_BE16(_value) \
1652 IXGBE_NTOHS(((u16)(_value) >> 8) | ((u16)(_value) << 8))
1654 s32 ixgbe_fdir_set_input_mask_82599(struct ixgbe_hw *hw,
1655 union ixgbe_atr_input *input_mask)
1657 /* mask IPv6 since it is currently not supported */
1658 u32 fdirm = IXGBE_FDIRM_DIPv6;
1660 DEBUGFUNC("ixgbe_fdir_set_atr_input_mask_82599");
1663 * Program the relevant mask registers. If src/dst_port or src/dst_addr
1664 * are zero, then assume a full mask for that field. Also assume that
1665 * a VLAN of 0 is unspecified, so mask that out as well. L4type
1666 * cannot be masked out in this implementation.
1668 * This also assumes IPv4 only. IPv6 masking isn't supported at this
1672 /* verify bucket hash is cleared on hash generation */
1673 if (input_mask->formatted.bkt_hash)
1674 DEBUGOUT(" bucket hash should always be 0 in mask\n");
1676 /* Program FDIRM and verify partial masks */
1677 switch (input_mask->formatted.vm_pool & 0x7F) {
1679 fdirm |= IXGBE_FDIRM_POOL;
1683 DEBUGOUT(" Error on vm pool mask\n");
1684 return IXGBE_ERR_CONFIG;
1687 switch (input_mask->formatted.flow_type & IXGBE_ATR_L4TYPE_MASK) {
1689 fdirm |= IXGBE_FDIRM_L4P;
1690 if (input_mask->formatted.dst_port ||
1691 input_mask->formatted.src_port) {
1692 DEBUGOUT(" Error on src/dst port mask\n");
1693 return IXGBE_ERR_CONFIG;
1695 case IXGBE_ATR_L4TYPE_MASK:
1698 DEBUGOUT(" Error on flow type mask\n");
1699 return IXGBE_ERR_CONFIG;
1702 switch (IXGBE_NTOHS(input_mask->formatted.vlan_id) & 0xEFFF) {
1704 /* mask VLAN ID, fall through to mask VLAN priority */
1705 fdirm |= IXGBE_FDIRM_VLANID;
1707 /* mask VLAN priority */
1708 fdirm |= IXGBE_FDIRM_VLANP;
1711 /* mask VLAN ID only, fall through */
1712 fdirm |= IXGBE_FDIRM_VLANID;
1714 /* no VLAN fields masked */
1717 DEBUGOUT(" Error on VLAN mask\n");
1718 return IXGBE_ERR_CONFIG;
1721 switch (input_mask->formatted.flex_bytes & 0xFFFF) {
1723 /* Mask Flex Bytes, fall through */
1724 fdirm |= IXGBE_FDIRM_FLEX;
1728 DEBUGOUT(" Error on flexible byte mask\n");
1729 return IXGBE_ERR_CONFIG;
1733 /* Now mask VM pool and destination IPv6 - bits 5 and 2 */
1734 IXGBE_WRITE_REG(hw, IXGBE_FDIRM, fdirm);
1736 /* store the TCP/UDP port masks, bit reversed from port layout */
1737 fdirtcpm = ixgbe_get_fdirtcpm_82599(input_mask);
1739 /* write both the same so that UDP and TCP use the same mask */
1740 IXGBE_WRITE_REG(hw, IXGBE_FDIRTCPM, ~fdirtcpm);
1741 IXGBE_WRITE_REG(hw, IXGBE_FDIRUDPM, ~fdirtcpm);
1743 /* store source and destination IP masks (big-enian) */
1744 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIP4M,
1745 ~input_mask->formatted.src_ip[0]);
1746 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRDIP4M,
1747 ~input_mask->formatted.dst_ip[0]);
1749 return IXGBE_SUCCESS;
1752 s32 ixgbe_fdir_write_perfect_filter_82599(struct ixgbe_hw *hw,
1753 union ixgbe_atr_input *input,
1754 u16 soft_id, u8 queue)
1756 u32 fdirport, fdirvlan, fdirhash, fdircmd;
1758 DEBUGFUNC("ixgbe_fdir_write_perfect_filter_82599");
1760 /* currently IPv6 is not supported, must be programmed with 0 */
1761 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(0),
1762 input->formatted.src_ip[0]);
1763 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(1),
1764 input->formatted.src_ip[1]);
1765 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRSIPv6(2),
1766 input->formatted.src_ip[2]);
1768 /* record the source address (big-endian) */
1769 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPSA, input->formatted.src_ip[0]);
1771 /* record the first 32 bits of the destination address (big-endian) */
1772 IXGBE_WRITE_REG_BE32(hw, IXGBE_FDIRIPDA, input->formatted.dst_ip[0]);
1774 /* record source and destination port (little-endian)*/
1775 fdirport = IXGBE_NTOHS(input->formatted.dst_port);
1776 fdirport <<= IXGBE_FDIRPORT_DESTINATION_SHIFT;
1777 fdirport |= IXGBE_NTOHS(input->formatted.src_port);
1778 IXGBE_WRITE_REG(hw, IXGBE_FDIRPORT, fdirport);
1780 /* record vlan (little-endian) and flex_bytes(big-endian) */
1781 fdirvlan = IXGBE_STORE_AS_BE16(input->formatted.flex_bytes);
1782 fdirvlan <<= IXGBE_FDIRVLAN_FLEX_SHIFT;
1783 fdirvlan |= IXGBE_NTOHS(input->formatted.vlan_id);
1784 IXGBE_WRITE_REG(hw, IXGBE_FDIRVLAN, fdirvlan);
1787 /* configure FDIRHASH register */
1788 fdirhash = input->formatted.bkt_hash;
1789 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1790 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1793 * flush all previous writes to make certain registers are
1794 * programmed prior to issuing the command
1796 IXGBE_WRITE_FLUSH(hw);
1798 /* configure FDIRCMD register */
1799 fdircmd = IXGBE_FDIRCMD_CMD_ADD_FLOW | IXGBE_FDIRCMD_FILTER_UPDATE |
1800 IXGBE_FDIRCMD_LAST | IXGBE_FDIRCMD_QUEUE_EN;
1801 if (queue == IXGBE_FDIR_DROP_QUEUE)
1802 fdircmd |= IXGBE_FDIRCMD_DROP;
1803 fdircmd |= input->formatted.flow_type << IXGBE_FDIRCMD_FLOW_TYPE_SHIFT;
1804 fdircmd |= (u32)queue << IXGBE_FDIRCMD_RX_QUEUE_SHIFT;
1805 fdircmd |= (u32)input->formatted.vm_pool << IXGBE_FDIRCMD_VT_POOL_SHIFT;
1807 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, fdircmd);
1809 return IXGBE_SUCCESS;
1812 s32 ixgbe_fdir_erase_perfect_filter_82599(struct ixgbe_hw *hw,
1813 union ixgbe_atr_input *input,
1819 s32 err = IXGBE_SUCCESS;
1821 /* configure FDIRHASH register */
1822 fdirhash = input->formatted.bkt_hash;
1823 fdirhash |= soft_id << IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT;
1824 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1826 /* flush hash to HW */
1827 IXGBE_WRITE_FLUSH(hw);
1829 /* Query if filter is present */
1830 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD, IXGBE_FDIRCMD_CMD_QUERY_REM_FILT);
1832 for (retry_count = 10; retry_count; retry_count--) {
1833 /* allow 10us for query to process */
1835 /* verify query completed successfully */
1836 fdircmd = IXGBE_READ_REG(hw, IXGBE_FDIRCMD);
1837 if (!(fdircmd & IXGBE_FDIRCMD_CMD_MASK))
1842 err = IXGBE_ERR_FDIR_REINIT_FAILED;
1844 /* if filter exists in hardware then remove it */
1845 if (fdircmd & IXGBE_FDIRCMD_FILTER_VALID) {
1846 IXGBE_WRITE_REG(hw, IXGBE_FDIRHASH, fdirhash);
1847 IXGBE_WRITE_FLUSH(hw);
1848 IXGBE_WRITE_REG(hw, IXGBE_FDIRCMD,
1849 IXGBE_FDIRCMD_CMD_REMOVE_FLOW);
1856 * ixgbe_fdir_add_perfect_filter_82599 - Adds a perfect filter
1857 * @hw: pointer to hardware structure
1858 * @input: input bitstream
1859 * @input_mask: mask for the input bitstream
1860 * @soft_id: software index for the filters
1861 * @queue: queue index to direct traffic to
1863 * Note that the caller to this function must lock before calling, since the
1864 * hardware writes must be protected from one another.
1866 s32 ixgbe_fdir_add_perfect_filter_82599(struct ixgbe_hw *hw,
1867 union ixgbe_atr_input *input,
1868 union ixgbe_atr_input *input_mask,
1869 u16 soft_id, u8 queue)
1871 s32 err = IXGBE_ERR_CONFIG;
1873 DEBUGFUNC("ixgbe_fdir_add_perfect_filter_82599");
1876 * Check flow_type formatting, and bail out before we touch the hardware
1877 * if there's a configuration issue
1879 switch (input->formatted.flow_type) {
1880 case IXGBE_ATR_FLOW_TYPE_IPV4:
1881 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK;
1882 if (input->formatted.dst_port || input->formatted.src_port) {
1883 DEBUGOUT(" Error on src/dst port\n");
1884 return IXGBE_ERR_CONFIG;
1887 case IXGBE_ATR_FLOW_TYPE_SCTPV4:
1888 if (input->formatted.dst_port || input->formatted.src_port) {
1889 DEBUGOUT(" Error on src/dst port\n");
1890 return IXGBE_ERR_CONFIG;
1892 case IXGBE_ATR_FLOW_TYPE_TCPV4:
1893 case IXGBE_ATR_FLOW_TYPE_UDPV4:
1894 input_mask->formatted.flow_type = IXGBE_ATR_L4TYPE_IPV6_MASK |
1895 IXGBE_ATR_L4TYPE_MASK;
1898 DEBUGOUT(" Error on flow type input\n");
1902 /* program input mask into the HW */
1903 err = ixgbe_fdir_set_input_mask_82599(hw, input_mask);
1907 /* apply mask and compute/store hash */
1908 ixgbe_atr_compute_perfect_hash_82599(input, input_mask);
1910 /* program filters to filter memory */
1911 return ixgbe_fdir_write_perfect_filter_82599(hw, input,
1916 * ixgbe_read_analog_reg8_82599 - Reads 8 bit Omer analog register
1917 * @hw: pointer to hardware structure
1918 * @reg: analog register to read
1921 * Performs read operation to Omer analog register specified.
1923 s32 ixgbe_read_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 *val)
1927 DEBUGFUNC("ixgbe_read_analog_reg8_82599");
1929 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, IXGBE_CORECTL_WRITE_CMD |
1931 IXGBE_WRITE_FLUSH(hw);
1933 core_ctl = IXGBE_READ_REG(hw, IXGBE_CORECTL);
1934 *val = (u8)core_ctl;
1936 return IXGBE_SUCCESS;
1940 * ixgbe_write_analog_reg8_82599 - Writes 8 bit Omer analog register
1941 * @hw: pointer to hardware structure
1942 * @reg: atlas register to write
1943 * @val: value to write
1945 * Performs write operation to Omer analog register specified.
1947 s32 ixgbe_write_analog_reg8_82599(struct ixgbe_hw *hw, u32 reg, u8 val)
1951 DEBUGFUNC("ixgbe_write_analog_reg8_82599");
1953 core_ctl = (reg << 8) | val;
1954 IXGBE_WRITE_REG(hw, IXGBE_CORECTL, core_ctl);
1955 IXGBE_WRITE_FLUSH(hw);
1958 return IXGBE_SUCCESS;
1962 * ixgbe_start_hw_82599 - Prepare hardware for Tx/Rx
1963 * @hw: pointer to hardware structure
1965 * Starts the hardware using the generic start_hw function
1966 * and the generation start_hw function.
1967 * Then performs revision-specific operations, if any.
1969 s32 ixgbe_start_hw_82599(struct ixgbe_hw *hw)
1971 s32 ret_val = IXGBE_SUCCESS;
1973 DEBUGFUNC("ixgbe_start_hw_82599");
1975 ret_val = ixgbe_start_hw_generic(hw);
1976 if (ret_val != IXGBE_SUCCESS)
1979 ret_val = ixgbe_start_hw_gen2(hw);
1980 if (ret_val != IXGBE_SUCCESS)
1983 /* We need to run link autotry after the driver loads */
1984 hw->mac.autotry_restart = true;
1986 if (ret_val == IXGBE_SUCCESS)
1987 ret_val = ixgbe_verify_fw_version_82599(hw);
1993 * ixgbe_identify_phy_82599 - Get physical layer module
1994 * @hw: pointer to hardware structure
1996 * Determines the physical layer module found on the current adapter.
1997 * If PHY already detected, maintains current PHY type in hw struct,
1998 * otherwise executes the PHY detection routine.
2000 s32 ixgbe_identify_phy_82599(struct ixgbe_hw *hw)
2004 DEBUGFUNC("ixgbe_identify_phy_82599");
2006 /* Detect PHY if not unknown - returns success if already detected. */
2007 status = ixgbe_identify_phy_generic(hw);
2008 if (status != IXGBE_SUCCESS) {
2009 /* 82599 10GBASE-T requires an external PHY */
2010 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_copper)
2013 status = ixgbe_identify_module_generic(hw);
2016 /* Set PHY type none if no PHY detected */
2017 if (hw->phy.type == ixgbe_phy_unknown) {
2018 hw->phy.type = ixgbe_phy_none;
2019 status = IXGBE_SUCCESS;
2022 /* Return error if SFP module has been detected but is not supported */
2023 if (hw->phy.type == ixgbe_phy_sfp_unsupported)
2024 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
2031 * ixgbe_get_supported_physical_layer_82599 - Returns physical layer type
2032 * @hw: pointer to hardware structure
2034 * Determines physical layer capabilities of the current configuration.
2036 u32 ixgbe_get_supported_physical_layer_82599(struct ixgbe_hw *hw)
2038 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
2039 u32 autoc = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2040 u32 autoc2 = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2041 u32 pma_pmd_10g_serial = autoc2 & IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK;
2042 u32 pma_pmd_10g_parallel = autoc & IXGBE_AUTOC_10G_PMA_PMD_MASK;
2043 u32 pma_pmd_1g = autoc & IXGBE_AUTOC_1G_PMA_PMD_MASK;
2044 u16 ext_ability = 0;
2045 u8 comp_codes_10g = 0;
2046 u8 comp_codes_1g = 0;
2048 DEBUGFUNC("ixgbe_get_support_physical_layer_82599");
2050 hw->phy.ops.identify(hw);
2052 switch (hw->phy.type) {
2054 case ixgbe_phy_cu_unknown:
2055 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
2056 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
2057 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY)
2058 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T;
2059 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY)
2060 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T;
2061 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY)
2062 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX;
2068 switch (autoc & IXGBE_AUTOC_LMS_MASK) {
2069 case IXGBE_AUTOC_LMS_1G_AN:
2070 case IXGBE_AUTOC_LMS_1G_LINK_NO_AN:
2071 if (pma_pmd_1g == IXGBE_AUTOC_1G_KX_BX) {
2072 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_KX |
2073 IXGBE_PHYSICAL_LAYER_1000BASE_BX;
2076 /* SFI mode so read SFP module */
2079 case IXGBE_AUTOC_LMS_10G_LINK_NO_AN:
2080 if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_CX4)
2081 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_CX4;
2082 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_KX4)
2083 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2084 else if (pma_pmd_10g_parallel == IXGBE_AUTOC_10G_XAUI)
2085 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_XAUI;
2088 case IXGBE_AUTOC_LMS_10G_SERIAL:
2089 if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_KR) {
2090 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2092 } else if (pma_pmd_10g_serial == IXGBE_AUTOC2_10G_SFI)
2095 case IXGBE_AUTOC_LMS_KX4_KX_KR:
2096 case IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN:
2097 if (autoc & IXGBE_AUTOC_KX_SUPP)
2098 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_KX;
2099 if (autoc & IXGBE_AUTOC_KX4_SUPP)
2100 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KX4;
2101 if (autoc & IXGBE_AUTOC_KR_SUPP)
2102 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_KR;
2111 /* SFP check must be done last since DA modules are sometimes used to
2112 * test KR mode - we need to id KR mode correctly before SFP module.
2113 * Call identify_sfp because the pluggable module may have changed */
2114 hw->phy.ops.identify_sfp(hw);
2115 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
2118 switch (hw->phy.type) {
2119 case ixgbe_phy_sfp_passive_tyco:
2120 case ixgbe_phy_sfp_passive_unknown:
2121 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
2123 case ixgbe_phy_sfp_ftl_active:
2124 case ixgbe_phy_sfp_active_unknown:
2125 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
2127 case ixgbe_phy_sfp_avago:
2128 case ixgbe_phy_sfp_ftl:
2129 case ixgbe_phy_sfp_intel:
2130 case ixgbe_phy_sfp_unknown:
2131 hw->phy.ops.read_i2c_eeprom(hw,
2132 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
2133 hw->phy.ops.read_i2c_eeprom(hw,
2134 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
2135 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
2136 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
2137 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
2138 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
2139 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
2140 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
2141 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
2142 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
2149 return physical_layer;
2153 * ixgbe_enable_rx_dma_82599 - Enable the Rx DMA unit on 82599
2154 * @hw: pointer to hardware structure
2155 * @regval: register value to write to RXCTRL
2157 * Enables the Rx DMA unit for 82599
2159 s32 ixgbe_enable_rx_dma_82599(struct ixgbe_hw *hw, u32 regval)
2162 DEBUGFUNC("ixgbe_enable_rx_dma_82599");
2165 * Workaround for 82599 silicon errata when enabling the Rx datapath.
2166 * If traffic is incoming before we enable the Rx unit, it could hang
2167 * the Rx DMA unit. Therefore, make sure the security engine is
2168 * completely disabled prior to enabling the Rx unit.
2171 hw->mac.ops.disable_sec_rx_path(hw);
2173 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
2175 hw->mac.ops.enable_sec_rx_path(hw);
2177 return IXGBE_SUCCESS;
2181 * ixgbe_verify_fw_version_82599 - verify fw version for 82599
2182 * @hw: pointer to hardware structure
2184 * Verifies that installed the firmware version is 0.6 or higher
2185 * for SFI devices. All 82599 SFI devices should have version 0.6 or higher.
2187 * Returns IXGBE_ERR_EEPROM_VERSION if the FW is not present or
2188 * if the FW version is not supported.
2190 STATIC s32 ixgbe_verify_fw_version_82599(struct ixgbe_hw *hw)
2192 s32 status = IXGBE_ERR_EEPROM_VERSION;
2193 u16 fw_offset, fw_ptp_cfg_offset;
2196 DEBUGFUNC("ixgbe_verify_fw_version_82599");
2198 /* firmware check is only necessary for SFI devices */
2199 if (hw->phy.media_type != ixgbe_media_type_fiber) {
2200 status = IXGBE_SUCCESS;
2201 goto fw_version_out;
2204 /* get the offset to the Firmware Module block */
2205 if (hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset)) {
2206 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2207 "eeprom read at offset %d failed", IXGBE_FW_PTR);
2208 return IXGBE_ERR_EEPROM_VERSION;
2211 if ((fw_offset == 0) || (fw_offset == 0xFFFF))
2212 goto fw_version_out;
2214 /* get the offset to the Pass Through Patch Configuration block */
2215 if (hw->eeprom.ops.read(hw, (fw_offset +
2216 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR),
2217 &fw_ptp_cfg_offset)) {
2218 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2219 "eeprom read at offset %d failed",
2221 IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR);
2222 return IXGBE_ERR_EEPROM_VERSION;
2225 if ((fw_ptp_cfg_offset == 0) || (fw_ptp_cfg_offset == 0xFFFF))
2226 goto fw_version_out;
2228 /* get the firmware version */
2229 if (hw->eeprom.ops.read(hw, (fw_ptp_cfg_offset +
2230 IXGBE_FW_PATCH_VERSION_4), &fw_version)) {
2231 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2232 "eeprom read at offset %d failed",
2233 fw_ptp_cfg_offset + IXGBE_FW_PATCH_VERSION_4);
2234 return IXGBE_ERR_EEPROM_VERSION;
2237 if (fw_version > 0x5)
2238 status = IXGBE_SUCCESS;
2245 * ixgbe_verify_lesm_fw_enabled_82599 - Checks LESM FW module state.
2246 * @hw: pointer to hardware structure
2248 * Returns true if the LESM FW module is present and enabled. Otherwise
2249 * returns false. Smart Speed must be disabled if LESM FW module is enabled.
2251 bool ixgbe_verify_lesm_fw_enabled_82599(struct ixgbe_hw *hw)
2253 bool lesm_enabled = false;
2254 u16 fw_offset, fw_lesm_param_offset, fw_lesm_state;
2257 DEBUGFUNC("ixgbe_verify_lesm_fw_enabled_82599");
2259 /* get the offset to the Firmware Module block */
2260 status = hw->eeprom.ops.read(hw, IXGBE_FW_PTR, &fw_offset);
2262 if ((status != IXGBE_SUCCESS) ||
2263 (fw_offset == 0) || (fw_offset == 0xFFFF))
2266 /* get the offset to the LESM Parameters block */
2267 status = hw->eeprom.ops.read(hw, (fw_offset +
2268 IXGBE_FW_LESM_PARAMETERS_PTR),
2269 &fw_lesm_param_offset);
2271 if ((status != IXGBE_SUCCESS) ||
2272 (fw_lesm_param_offset == 0) || (fw_lesm_param_offset == 0xFFFF))
2275 /* get the lesm state word */
2276 status = hw->eeprom.ops.read(hw, (fw_lesm_param_offset +
2277 IXGBE_FW_LESM_STATE_1),
2280 if ((status == IXGBE_SUCCESS) &&
2281 (fw_lesm_state & IXGBE_FW_LESM_STATE_ENABLED))
2282 lesm_enabled = true;
2285 return lesm_enabled;
2289 * ixgbe_read_eeprom_buffer_82599 - Read EEPROM word(s) using
2290 * fastest available method
2292 * @hw: pointer to hardware structure
2293 * @offset: offset of word in EEPROM to read
2294 * @words: number of words
2295 * @data: word(s) read from the EEPROM
2297 * Retrieves 16 bit word(s) read from EEPROM
2299 STATIC s32 ixgbe_read_eeprom_buffer_82599(struct ixgbe_hw *hw, u16 offset,
2300 u16 words, u16 *data)
2302 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2303 s32 ret_val = IXGBE_ERR_CONFIG;
2305 DEBUGFUNC("ixgbe_read_eeprom_buffer_82599");
2308 * If EEPROM is detected and can be addressed using 14 bits,
2309 * use EERD otherwise use bit bang
2311 if ((eeprom->type == ixgbe_eeprom_spi) &&
2312 (offset + (words - 1) <= IXGBE_EERD_MAX_ADDR))
2313 ret_val = ixgbe_read_eerd_buffer_generic(hw, offset, words,
2316 ret_val = ixgbe_read_eeprom_buffer_bit_bang_generic(hw, offset,
2324 * ixgbe_read_eeprom_82599 - Read EEPROM word using
2325 * fastest available method
2327 * @hw: pointer to hardware structure
2328 * @offset: offset of word in the EEPROM to read
2329 * @data: word read from the EEPROM
2331 * Reads a 16 bit word from the EEPROM
2333 STATIC s32 ixgbe_read_eeprom_82599(struct ixgbe_hw *hw,
2334 u16 offset, u16 *data)
2336 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
2337 s32 ret_val = IXGBE_ERR_CONFIG;
2339 DEBUGFUNC("ixgbe_read_eeprom_82599");
2342 * If EEPROM is detected and can be addressed using 14 bits,
2343 * use EERD otherwise use bit bang
2345 if ((eeprom->type == ixgbe_eeprom_spi) &&
2346 (offset <= IXGBE_EERD_MAX_ADDR))
2347 ret_val = ixgbe_read_eerd_generic(hw, offset, data);
2349 ret_val = ixgbe_read_eeprom_bit_bang_generic(hw, offset, data);
2355 * ixgbe_reset_pipeline_82599 - perform pipeline reset
2357 * @hw: pointer to hardware structure
2359 * Reset pipeline by asserting Restart_AN together with LMS change to ensure
2360 * full pipeline reset
2362 s32 ixgbe_reset_pipeline_82599(struct ixgbe_hw *hw)
2364 s32 i, autoc_reg, autoc2_reg, ret_val;
2367 /* Enable link if disabled in NVM */
2368 autoc2_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC2);
2369 if (autoc2_reg & IXGBE_AUTOC2_LINK_DISABLE_MASK) {
2370 autoc2_reg &= ~IXGBE_AUTOC2_LINK_DISABLE_MASK;
2371 IXGBE_WRITE_REG(hw, IXGBE_AUTOC2, autoc2_reg);
2372 IXGBE_WRITE_FLUSH(hw);
2375 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2376 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
2377 /* Write AUTOC register with toggled LMS[2] bit and Restart_AN */
2378 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg ^ IXGBE_AUTOC_LMS_1G_AN);
2379 /* Wait for AN to leave state 0 */
2380 for (i = 0; i < 10; i++) {
2382 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2383 if (anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)
2387 if (!(anlp1_reg & IXGBE_ANLP1_AN_STATE_MASK)) {
2388 DEBUGOUT("auto negotiation not completed\n");
2389 ret_val = IXGBE_ERR_RESET_FAILED;
2390 goto reset_pipeline_out;
2393 ret_val = IXGBE_SUCCESS;
2396 /* Write AUTOC register with original LMS field and Restart_AN */
2397 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
2398 IXGBE_WRITE_FLUSH(hw);