1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
39 #ident "$Id: ixgbe_common.c,v 1.382 2013/11/22 01:02:01 jtkirshe Exp $"
41 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
42 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
44 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
46 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
48 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
49 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
51 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
53 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
54 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
56 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
57 u16 words, u16 *data);
58 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
64 * ixgbe_init_ops_generic - Inits function ptrs
65 * @hw: pointer to the hardware structure
67 * Initialize the function pointers.
69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
72 struct ixgbe_mac_info *mac = &hw->mac;
73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
75 DEBUGFUNC("ixgbe_init_ops_generic");
78 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
80 if (eec & IXGBE_EEC_PRES) {
81 eeprom->ops.read = &ixgbe_read_eerd_generic;
82 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
84 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
85 eeprom->ops.read_buffer =
86 &ixgbe_read_eeprom_buffer_bit_bang_generic;
88 eeprom->ops.write = &ixgbe_write_eeprom_generic;
89 eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
90 eeprom->ops.validate_checksum =
91 &ixgbe_validate_eeprom_checksum_generic;
92 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
93 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
96 mac->ops.init_hw = &ixgbe_init_hw_generic;
97 mac->ops.reset_hw = NULL;
98 mac->ops.start_hw = &ixgbe_start_hw_generic;
99 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
100 mac->ops.get_media_type = NULL;
101 mac->ops.get_supported_physical_layer = NULL;
102 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
103 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
104 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
105 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
106 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
107 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
108 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
109 mac->ops.prot_autoc_read = &prot_autoc_read_generic;
110 mac->ops.prot_autoc_write = &prot_autoc_write_generic;
113 mac->ops.led_on = &ixgbe_led_on_generic;
114 mac->ops.led_off = &ixgbe_led_off_generic;
115 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
116 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
118 /* RAR, Multicast, VLAN */
119 mac->ops.set_rar = &ixgbe_set_rar_generic;
120 mac->ops.clear_rar = &ixgbe_clear_rar_generic;
121 mac->ops.insert_mac_addr = NULL;
122 mac->ops.set_vmdq = NULL;
123 mac->ops.clear_vmdq = NULL;
124 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
125 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
126 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
127 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
128 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
129 mac->ops.clear_vfta = NULL;
130 mac->ops.set_vfta = NULL;
131 mac->ops.set_vlvf = NULL;
132 mac->ops.init_uta_tables = NULL;
133 mac->ops.enable_rx = &ixgbe_enable_rx_generic;
134 mac->ops.disable_rx = &ixgbe_disable_rx_generic;
137 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
140 mac->ops.get_link_capabilities = NULL;
141 mac->ops.setup_link = NULL;
142 mac->ops.check_link = NULL;
143 mac->ops.dmac_config = NULL;
144 mac->ops.dmac_update_tcs = NULL;
145 mac->ops.dmac_config_tcs = NULL;
147 return IXGBE_SUCCESS;
151 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
153 * @hw: pointer to hardware structure
155 * This function returns true if the device supports flow control
156 * autonegotiation, and false if it does not.
159 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
161 bool supported = false;
162 ixgbe_link_speed speed;
165 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
167 switch (hw->phy.media_type) {
168 case ixgbe_media_type_fiber_qsfp:
169 case ixgbe_media_type_fiber:
170 hw->mac.ops.check_link(hw, &speed, &link_up, false);
171 /* if link is down, assume supported */
173 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
178 case ixgbe_media_type_backplane:
181 case ixgbe_media_type_copper:
182 /* only some copper devices support flow control autoneg */
183 switch (hw->device_id) {
184 case IXGBE_DEV_ID_82599_T3_LOM:
185 case IXGBE_DEV_ID_X540T:
186 case IXGBE_DEV_ID_X540T1:
187 case IXGBE_DEV_ID_X550T:
197 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
198 "Device %x does not support flow control autoneg",
204 * ixgbe_setup_fc - Set up flow control
205 * @hw: pointer to hardware structure
207 * Called at init time to set up flow control.
209 STATIC s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
211 s32 ret_val = IXGBE_SUCCESS;
212 u32 reg = 0, reg_bp = 0;
216 DEBUGFUNC("ixgbe_setup_fc");
218 /* Validate the requested mode */
219 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
220 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
221 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
222 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
227 * 10gig parts do not have a word in the EEPROM to determine the
228 * default flow control setting, so we explicitly set it to full.
230 if (hw->fc.requested_mode == ixgbe_fc_default)
231 hw->fc.requested_mode = ixgbe_fc_full;
234 * Set up the 1G and 10G flow control advertisement registers so the
235 * HW will be able to do fc autoneg once the cable is plugged in. If
236 * we link at 10G, the 1G advertisement is harmless and vice versa.
238 switch (hw->phy.media_type) {
239 case ixgbe_media_type_backplane:
240 /* some MAC's need RMW protection on AUTOC */
241 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
242 if (ret_val != IXGBE_SUCCESS)
245 /* only backplane uses autoc so fall though */
246 case ixgbe_media_type_fiber_qsfp:
247 case ixgbe_media_type_fiber:
248 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
251 case ixgbe_media_type_copper:
252 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
253 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
260 * The possible values of fc.requested_mode are:
261 * 0: Flow control is completely disabled
262 * 1: Rx flow control is enabled (we can receive pause frames,
263 * but not send pause frames).
264 * 2: Tx flow control is enabled (we can send pause frames but
265 * we do not support receiving pause frames).
266 * 3: Both Rx and Tx flow control (symmetric) are enabled.
269 switch (hw->fc.requested_mode) {
271 /* Flow control completely disabled by software override. */
272 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
273 if (hw->phy.media_type == ixgbe_media_type_backplane)
274 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
275 IXGBE_AUTOC_ASM_PAUSE);
276 else if (hw->phy.media_type == ixgbe_media_type_copper)
277 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
279 case ixgbe_fc_tx_pause:
281 * Tx Flow control is enabled, and Rx Flow control is
282 * disabled by software override.
284 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
285 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
286 if (hw->phy.media_type == ixgbe_media_type_backplane) {
287 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
288 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
289 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
290 reg_cu |= IXGBE_TAF_ASM_PAUSE;
291 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
294 case ixgbe_fc_rx_pause:
296 * Rx Flow control is enabled and Tx Flow control is
297 * disabled by software override. Since there really
298 * isn't a way to advertise that we are capable of RX
299 * Pause ONLY, we will advertise that we support both
300 * symmetric and asymmetric Rx PAUSE, as such we fall
301 * through to the fc_full statement. Later, we will
302 * disable the adapter's ability to send PAUSE frames.
305 /* Flow control (both Rx and Tx) is enabled by SW override. */
306 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
307 if (hw->phy.media_type == ixgbe_media_type_backplane)
308 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
309 IXGBE_AUTOC_ASM_PAUSE;
310 else if (hw->phy.media_type == ixgbe_media_type_copper)
311 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
314 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
315 "Flow control param set incorrectly\n");
316 ret_val = IXGBE_ERR_CONFIG;
321 if (hw->mac.type < ixgbe_mac_X540) {
323 * Enable auto-negotiation between the MAC & PHY;
324 * the MAC will advertise clause 37 flow control.
326 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
327 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
329 /* Disable AN timeout */
330 if (hw->fc.strict_ieee)
331 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
333 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
334 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
338 * AUTOC restart handles negotiation of 1G and 10G on backplane
339 * and copper. There is no need to set the PCS1GCTL register.
342 if (hw->phy.media_type == ixgbe_media_type_backplane) {
343 reg_bp |= IXGBE_AUTOC_AN_RESTART;
344 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
347 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
348 (ixgbe_device_supports_autoneg_fc(hw))) {
349 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
350 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
353 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
359 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
360 * @hw: pointer to hardware structure
362 * Starts the hardware by filling the bus info structure and media type, clears
363 * all on chip counters, initializes receive address registers, multicast
364 * table, VLAN filter table, calls routine to set up link and flow control
365 * settings, and leaves transmit and receive units disabled and uninitialized
367 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
372 DEBUGFUNC("ixgbe_start_hw_generic");
374 /* Set the media type */
375 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
377 /* PHY ops initialization must be done in reset_hw() */
379 /* Clear the VLAN filter table */
380 hw->mac.ops.clear_vfta(hw);
382 /* Clear statistics registers */
383 hw->mac.ops.clear_hw_cntrs(hw);
385 /* Set No Snoop Disable */
386 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
387 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
388 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
389 IXGBE_WRITE_FLUSH(hw);
391 /* Setup flow control */
392 ret_val = ixgbe_setup_fc(hw);
393 if (ret_val != IXGBE_SUCCESS)
396 /* Clear adapter stopped flag */
397 hw->adapter_stopped = false;
404 * ixgbe_start_hw_gen2 - Init sequence for common device family
405 * @hw: pointer to hw structure
407 * Performs the init sequence common to the second generation
409 * Devices in the second generation:
413 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
418 /* Clear the rate limiters */
419 for (i = 0; i < hw->mac.max_tx_queues; i++) {
420 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
421 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
423 IXGBE_WRITE_FLUSH(hw);
425 /* Disable relaxed ordering */
426 for (i = 0; i < hw->mac.max_tx_queues; i++) {
427 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
428 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
429 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
432 for (i = 0; i < hw->mac.max_rx_queues; i++) {
433 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
434 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
435 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
436 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
439 return IXGBE_SUCCESS;
443 * ixgbe_init_hw_generic - Generic hardware initialization
444 * @hw: pointer to hardware structure
446 * Initialize the hardware by resetting the hardware, filling the bus info
447 * structure and media type, clears all on chip counters, initializes receive
448 * address registers, multicast table, VLAN filter table, calls routine to set
449 * up link and flow control settings, and leaves transmit and receive units
450 * disabled and uninitialized
452 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
456 DEBUGFUNC("ixgbe_init_hw_generic");
458 /* Reset the hardware */
459 status = hw->mac.ops.reset_hw(hw);
461 if (status == IXGBE_SUCCESS) {
463 status = hw->mac.ops.start_hw(hw);
470 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
471 * @hw: pointer to hardware structure
473 * Clears all hardware statistics counters by reading them from the hardware
474 * Statistics counters are clear on read.
476 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
480 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
482 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
483 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
484 IXGBE_READ_REG(hw, IXGBE_ERRBC);
485 IXGBE_READ_REG(hw, IXGBE_MSPDC);
486 for (i = 0; i < 8; i++)
487 IXGBE_READ_REG(hw, IXGBE_MPC(i));
489 IXGBE_READ_REG(hw, IXGBE_MLFC);
490 IXGBE_READ_REG(hw, IXGBE_MRFC);
491 IXGBE_READ_REG(hw, IXGBE_RLEC);
492 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
493 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
494 if (hw->mac.type >= ixgbe_mac_82599EB) {
495 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
496 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
498 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
499 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
502 for (i = 0; i < 8; i++) {
503 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
504 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
505 if (hw->mac.type >= ixgbe_mac_82599EB) {
506 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
507 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
509 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
510 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
513 if (hw->mac.type >= ixgbe_mac_82599EB)
514 for (i = 0; i < 8; i++)
515 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
516 IXGBE_READ_REG(hw, IXGBE_PRC64);
517 IXGBE_READ_REG(hw, IXGBE_PRC127);
518 IXGBE_READ_REG(hw, IXGBE_PRC255);
519 IXGBE_READ_REG(hw, IXGBE_PRC511);
520 IXGBE_READ_REG(hw, IXGBE_PRC1023);
521 IXGBE_READ_REG(hw, IXGBE_PRC1522);
522 IXGBE_READ_REG(hw, IXGBE_GPRC);
523 IXGBE_READ_REG(hw, IXGBE_BPRC);
524 IXGBE_READ_REG(hw, IXGBE_MPRC);
525 IXGBE_READ_REG(hw, IXGBE_GPTC);
526 IXGBE_READ_REG(hw, IXGBE_GORCL);
527 IXGBE_READ_REG(hw, IXGBE_GORCH);
528 IXGBE_READ_REG(hw, IXGBE_GOTCL);
529 IXGBE_READ_REG(hw, IXGBE_GOTCH);
530 if (hw->mac.type == ixgbe_mac_82598EB)
531 for (i = 0; i < 8; i++)
532 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
533 IXGBE_READ_REG(hw, IXGBE_RUC);
534 IXGBE_READ_REG(hw, IXGBE_RFC);
535 IXGBE_READ_REG(hw, IXGBE_ROC);
536 IXGBE_READ_REG(hw, IXGBE_RJC);
537 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
538 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
539 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
540 IXGBE_READ_REG(hw, IXGBE_TORL);
541 IXGBE_READ_REG(hw, IXGBE_TORH);
542 IXGBE_READ_REG(hw, IXGBE_TPR);
543 IXGBE_READ_REG(hw, IXGBE_TPT);
544 IXGBE_READ_REG(hw, IXGBE_PTC64);
545 IXGBE_READ_REG(hw, IXGBE_PTC127);
546 IXGBE_READ_REG(hw, IXGBE_PTC255);
547 IXGBE_READ_REG(hw, IXGBE_PTC511);
548 IXGBE_READ_REG(hw, IXGBE_PTC1023);
549 IXGBE_READ_REG(hw, IXGBE_PTC1522);
550 IXGBE_READ_REG(hw, IXGBE_MPTC);
551 IXGBE_READ_REG(hw, IXGBE_BPTC);
552 for (i = 0; i < 16; i++) {
553 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
554 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
555 if (hw->mac.type >= ixgbe_mac_82599EB) {
556 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
557 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
558 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
559 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
560 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
562 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
563 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
567 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
569 ixgbe_identify_phy(hw);
570 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
571 IXGBE_MDIO_PCS_DEV_TYPE, &i);
572 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
573 IXGBE_MDIO_PCS_DEV_TYPE, &i);
574 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
575 IXGBE_MDIO_PCS_DEV_TYPE, &i);
576 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
577 IXGBE_MDIO_PCS_DEV_TYPE, &i);
580 return IXGBE_SUCCESS;
584 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
585 * @hw: pointer to hardware structure
586 * @pba_num: stores the part number string from the EEPROM
587 * @pba_num_size: part number string buffer length
589 * Reads the part number string from the EEPROM.
591 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
600 DEBUGFUNC("ixgbe_read_pba_string_generic");
602 if (pba_num == NULL) {
603 DEBUGOUT("PBA string buffer was null\n");
604 return IXGBE_ERR_INVALID_ARGUMENT;
607 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
609 DEBUGOUT("NVM Read Error\n");
613 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
615 DEBUGOUT("NVM Read Error\n");
620 * if data is not ptr guard the PBA must be in legacy format which
621 * means pba_ptr is actually our second data word for the PBA number
622 * and we can decode it into an ascii string
624 if (data != IXGBE_PBANUM_PTR_GUARD) {
625 DEBUGOUT("NVM PBA number is not stored as string\n");
627 /* we will need 11 characters to store the PBA */
628 if (pba_num_size < 11) {
629 DEBUGOUT("PBA string buffer too small\n");
630 return IXGBE_ERR_NO_SPACE;
633 /* extract hex string from data and pba_ptr */
634 pba_num[0] = (data >> 12) & 0xF;
635 pba_num[1] = (data >> 8) & 0xF;
636 pba_num[2] = (data >> 4) & 0xF;
637 pba_num[3] = data & 0xF;
638 pba_num[4] = (pba_ptr >> 12) & 0xF;
639 pba_num[5] = (pba_ptr >> 8) & 0xF;
642 pba_num[8] = (pba_ptr >> 4) & 0xF;
643 pba_num[9] = pba_ptr & 0xF;
645 /* put a null character on the end of our string */
648 /* switch all the data but the '-' to hex char */
649 for (offset = 0; offset < 10; offset++) {
650 if (pba_num[offset] < 0xA)
651 pba_num[offset] += '0';
652 else if (pba_num[offset] < 0x10)
653 pba_num[offset] += 'A' - 0xA;
656 return IXGBE_SUCCESS;
659 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
661 DEBUGOUT("NVM Read Error\n");
665 if (length == 0xFFFF || length == 0) {
666 DEBUGOUT("NVM PBA number section invalid length\n");
667 return IXGBE_ERR_PBA_SECTION;
670 /* check if pba_num buffer is big enough */
671 if (pba_num_size < (((u32)length * 2) - 1)) {
672 DEBUGOUT("PBA string buffer too small\n");
673 return IXGBE_ERR_NO_SPACE;
676 /* trim pba length from start of string */
680 for (offset = 0; offset < length; offset++) {
681 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
683 DEBUGOUT("NVM Read Error\n");
686 pba_num[offset * 2] = (u8)(data >> 8);
687 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
689 pba_num[offset * 2] = '\0';
691 return IXGBE_SUCCESS;
695 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
696 * @hw: pointer to hardware structure
697 * @pba_num: stores the part number from the EEPROM
699 * Reads the part number from the EEPROM.
701 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
706 DEBUGFUNC("ixgbe_read_pba_num_generic");
708 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
710 DEBUGOUT("NVM Read Error\n");
712 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
713 DEBUGOUT("NVM Not supported\n");
714 return IXGBE_NOT_IMPLEMENTED;
716 *pba_num = (u32)(data << 16);
718 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
720 DEBUGOUT("NVM Read Error\n");
725 return IXGBE_SUCCESS;
730 * @hw: pointer to the HW structure
731 * @eeprom_buf: optional pointer to EEPROM image
732 * @eeprom_buf_size: size of EEPROM image in words
733 * @max_pba_block_size: PBA block size limit
734 * @pba: pointer to output PBA structure
736 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
737 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
740 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
741 u32 eeprom_buf_size, u16 max_pba_block_size,
742 struct ixgbe_pba *pba)
748 return IXGBE_ERR_PARAM;
750 if (eeprom_buf == NULL) {
751 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
756 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
757 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
758 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
760 return IXGBE_ERR_PARAM;
764 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
765 if (pba->pba_block == NULL)
766 return IXGBE_ERR_PARAM;
768 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
774 if (pba_block_size > max_pba_block_size)
775 return IXGBE_ERR_PARAM;
777 if (eeprom_buf == NULL) {
778 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
784 if (eeprom_buf_size > (u32)(pba->word[1] +
786 memcpy(pba->pba_block,
787 &eeprom_buf[pba->word[1]],
788 pba_block_size * sizeof(u16));
790 return IXGBE_ERR_PARAM;
795 return IXGBE_SUCCESS;
799 * ixgbe_write_pba_raw
800 * @hw: pointer to the HW structure
801 * @eeprom_buf: optional pointer to EEPROM image
802 * @eeprom_buf_size: size of EEPROM image in words
803 * @pba: pointer to PBA structure
805 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
806 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
809 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
810 u32 eeprom_buf_size, struct ixgbe_pba *pba)
815 return IXGBE_ERR_PARAM;
817 if (eeprom_buf == NULL) {
818 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
823 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
824 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
825 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
827 return IXGBE_ERR_PARAM;
831 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
832 if (pba->pba_block == NULL)
833 return IXGBE_ERR_PARAM;
835 if (eeprom_buf == NULL) {
836 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
842 if (eeprom_buf_size > (u32)(pba->word[1] +
843 pba->pba_block[0])) {
844 memcpy(&eeprom_buf[pba->word[1]],
846 pba->pba_block[0] * sizeof(u16));
848 return IXGBE_ERR_PARAM;
853 return IXGBE_SUCCESS;
857 * ixgbe_get_pba_block_size
858 * @hw: pointer to the HW structure
859 * @eeprom_buf: optional pointer to EEPROM image
860 * @eeprom_buf_size: size of EEPROM image in words
861 * @pba_data_size: pointer to output variable
863 * Returns the size of the PBA block in words. Function operates on EEPROM
864 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
868 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
869 u32 eeprom_buf_size, u16 *pba_block_size)
875 DEBUGFUNC("ixgbe_get_pba_block_size");
877 if (eeprom_buf == NULL) {
878 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
883 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
884 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
885 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
887 return IXGBE_ERR_PARAM;
891 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
892 if (eeprom_buf == NULL) {
893 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
898 if (eeprom_buf_size > pba_word[1])
899 length = eeprom_buf[pba_word[1] + 0];
901 return IXGBE_ERR_PARAM;
904 if (length == 0xFFFF || length == 0)
905 return IXGBE_ERR_PBA_SECTION;
907 /* PBA number in legacy format, there is no PBA Block. */
911 if (pba_block_size != NULL)
912 *pba_block_size = length;
914 return IXGBE_SUCCESS;
918 * ixgbe_get_mac_addr_generic - Generic get MAC address
919 * @hw: pointer to hardware structure
920 * @mac_addr: Adapter MAC address
922 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
923 * A reset of the adapter must be performed prior to calling this function
924 * in order for the MAC address to have been loaded from the EEPROM into RAR0
926 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
932 DEBUGFUNC("ixgbe_get_mac_addr_generic");
934 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
935 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
937 for (i = 0; i < 4; i++)
938 mac_addr[i] = (u8)(rar_low >> (i*8));
940 for (i = 0; i < 2; i++)
941 mac_addr[i+4] = (u8)(rar_high >> (i*8));
943 return IXGBE_SUCCESS;
947 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
948 * @hw: pointer to hardware structure
949 * @link_status: the link status returned by the PCI config space
951 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
953 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
955 struct ixgbe_mac_info *mac = &hw->mac;
957 hw->bus.type = ixgbe_bus_type_pci_express;
959 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
960 case IXGBE_PCI_LINK_WIDTH_1:
961 hw->bus.width = ixgbe_bus_width_pcie_x1;
963 case IXGBE_PCI_LINK_WIDTH_2:
964 hw->bus.width = ixgbe_bus_width_pcie_x2;
966 case IXGBE_PCI_LINK_WIDTH_4:
967 hw->bus.width = ixgbe_bus_width_pcie_x4;
969 case IXGBE_PCI_LINK_WIDTH_8:
970 hw->bus.width = ixgbe_bus_width_pcie_x8;
973 hw->bus.width = ixgbe_bus_width_unknown;
977 switch (link_status & IXGBE_PCI_LINK_SPEED) {
978 case IXGBE_PCI_LINK_SPEED_2500:
979 hw->bus.speed = ixgbe_bus_speed_2500;
981 case IXGBE_PCI_LINK_SPEED_5000:
982 hw->bus.speed = ixgbe_bus_speed_5000;
984 case IXGBE_PCI_LINK_SPEED_8000:
985 hw->bus.speed = ixgbe_bus_speed_8000;
988 hw->bus.speed = ixgbe_bus_speed_unknown;
992 mac->ops.set_lan_id(hw);
996 * ixgbe_get_bus_info_generic - Generic set PCI bus info
997 * @hw: pointer to hardware structure
999 * Gets the PCI bus info (speed, width, type) then calls helper function to
1000 * store this data within the ixgbe_hw structure.
1002 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1006 DEBUGFUNC("ixgbe_get_bus_info_generic");
1008 /* Get the negotiated link width and speed from PCI config space */
1009 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1011 ixgbe_set_pci_config_data_generic(hw, link_status);
1013 return IXGBE_SUCCESS;
1017 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1018 * @hw: pointer to the HW structure
1020 * Determines the LAN function id by reading memory-mapped registers
1021 * and swaps the port value if requested.
1023 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1025 struct ixgbe_bus_info *bus = &hw->bus;
1028 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1030 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1031 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1032 bus->lan_id = bus->func;
1034 /* check for a port swap */
1035 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
1036 if (reg & IXGBE_FACTPS_LFS)
1041 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1042 * @hw: pointer to hardware structure
1044 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1045 * disables transmit and receive units. The adapter_stopped flag is used by
1046 * the shared code and drivers to determine if the adapter is in a stopped
1047 * state and should not touch the hardware.
1049 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1054 DEBUGFUNC("ixgbe_stop_adapter_generic");
1057 * Set the adapter_stopped flag so other driver functions stop touching
1060 hw->adapter_stopped = true;
1062 /* Disable the receive unit */
1063 ixgbe_disable_rx(hw);
1065 /* Clear interrupt mask to stop interrupts from being generated */
1066 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1068 /* Clear any pending interrupts, flush previous writes */
1069 IXGBE_READ_REG(hw, IXGBE_EICR);
1071 /* Disable the transmit unit. Each queue must be disabled. */
1072 for (i = 0; i < hw->mac.max_tx_queues; i++)
1073 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1075 /* Disable the receive unit by stopping each queue */
1076 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1077 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1078 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1079 reg_val |= IXGBE_RXDCTL_SWFLSH;
1080 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1083 /* flush all queues disables */
1084 IXGBE_WRITE_FLUSH(hw);
1088 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
1089 * access and verify no pending requests
1091 return ixgbe_disable_pcie_master(hw);
1095 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1096 * @hw: pointer to hardware structure
1097 * @index: led number to turn on
1099 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1101 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1103 DEBUGFUNC("ixgbe_led_on_generic");
1105 /* To turn on the LED, set mode to ON. */
1106 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1107 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1108 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1109 IXGBE_WRITE_FLUSH(hw);
1111 return IXGBE_SUCCESS;
1115 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1116 * @hw: pointer to hardware structure
1117 * @index: led number to turn off
1119 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1121 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1123 DEBUGFUNC("ixgbe_led_off_generic");
1125 /* To turn off the LED, set mode to OFF. */
1126 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1127 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1128 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1129 IXGBE_WRITE_FLUSH(hw);
1131 return IXGBE_SUCCESS;
1135 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1136 * @hw: pointer to hardware structure
1138 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1139 * ixgbe_hw struct in order to set up EEPROM access.
1141 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1143 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1147 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1149 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1150 eeprom->type = ixgbe_eeprom_none;
1151 /* Set default semaphore delay to 10ms which is a well
1153 eeprom->semaphore_delay = 10;
1154 /* Clear EEPROM page size, it will be initialized as needed */
1155 eeprom->word_page_size = 0;
1158 * Check for EEPROM present first.
1159 * If not present leave as none
1161 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1162 if (eec & IXGBE_EEC_PRES) {
1163 eeprom->type = ixgbe_eeprom_spi;
1166 * SPI EEPROM is assumed here. This code would need to
1167 * change if a future EEPROM is not SPI.
1169 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1170 IXGBE_EEC_SIZE_SHIFT);
1171 eeprom->word_size = 1 << (eeprom_size +
1172 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1175 if (eec & IXGBE_EEC_ADDR_SIZE)
1176 eeprom->address_bits = 16;
1178 eeprom->address_bits = 8;
1179 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1180 "%d\n", eeprom->type, eeprom->word_size,
1181 eeprom->address_bits);
1184 return IXGBE_SUCCESS;
1188 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1189 * @hw: pointer to hardware structure
1190 * @offset: offset within the EEPROM to write
1191 * @words: number of word(s)
1192 * @data: 16 bit word(s) to write to EEPROM
1194 * Reads 16 bit word(s) from EEPROM through bit-bang method
1196 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1197 u16 words, u16 *data)
1199 s32 status = IXGBE_SUCCESS;
1202 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1204 hw->eeprom.ops.init_params(hw);
1207 status = IXGBE_ERR_INVALID_ARGUMENT;
1211 if (offset + words > hw->eeprom.word_size) {
1212 status = IXGBE_ERR_EEPROM;
1217 * The EEPROM page size cannot be queried from the chip. We do lazy
1218 * initialization. It is worth to do that when we write large buffer.
1220 if ((hw->eeprom.word_page_size == 0) &&
1221 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1222 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1225 * We cannot hold synchronization semaphores for too long
1226 * to avoid other entity starvation. However it is more efficient
1227 * to read in bursts than synchronizing access for each word.
1229 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1230 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1231 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1232 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1235 if (status != IXGBE_SUCCESS)
1244 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1245 * @hw: pointer to hardware structure
1246 * @offset: offset within the EEPROM to be written to
1247 * @words: number of word(s)
1248 * @data: 16 bit word(s) to be written to the EEPROM
1250 * If ixgbe_eeprom_update_checksum is not called after this function, the
1251 * EEPROM will most likely contain an invalid checksum.
1253 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1254 u16 words, u16 *data)
1260 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1262 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1264 /* Prepare the EEPROM for writing */
1265 status = ixgbe_acquire_eeprom(hw);
1267 if (status == IXGBE_SUCCESS) {
1268 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1269 ixgbe_release_eeprom(hw);
1270 status = IXGBE_ERR_EEPROM;
1274 if (status == IXGBE_SUCCESS) {
1275 for (i = 0; i < words; i++) {
1276 ixgbe_standby_eeprom(hw);
1278 /* Send the WRITE ENABLE command (8 bit opcode ) */
1279 ixgbe_shift_out_eeprom_bits(hw,
1280 IXGBE_EEPROM_WREN_OPCODE_SPI,
1281 IXGBE_EEPROM_OPCODE_BITS);
1283 ixgbe_standby_eeprom(hw);
1286 * Some SPI eeproms use the 8th address bit embedded
1289 if ((hw->eeprom.address_bits == 8) &&
1290 ((offset + i) >= 128))
1291 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1293 /* Send the Write command (8-bit opcode + addr) */
1294 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1295 IXGBE_EEPROM_OPCODE_BITS);
1296 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1297 hw->eeprom.address_bits);
1299 page_size = hw->eeprom.word_page_size;
1301 /* Send the data in burst via SPI*/
1304 word = (word >> 8) | (word << 8);
1305 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1310 /* do not wrap around page */
1311 if (((offset + i) & (page_size - 1)) ==
1314 } while (++i < words);
1316 ixgbe_standby_eeprom(hw);
1319 /* Done with writing - release the EEPROM */
1320 ixgbe_release_eeprom(hw);
1327 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1328 * @hw: pointer to hardware structure
1329 * @offset: offset within the EEPROM to be written to
1330 * @data: 16 bit word to be written to the EEPROM
1332 * If ixgbe_eeprom_update_checksum is not called after this function, the
1333 * EEPROM will most likely contain an invalid checksum.
1335 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1339 DEBUGFUNC("ixgbe_write_eeprom_generic");
1341 hw->eeprom.ops.init_params(hw);
1343 if (offset >= hw->eeprom.word_size) {
1344 status = IXGBE_ERR_EEPROM;
1348 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1355 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1356 * @hw: pointer to hardware structure
1357 * @offset: offset within the EEPROM to be read
1358 * @data: read 16 bit words(s) from EEPROM
1359 * @words: number of word(s)
1361 * Reads 16 bit word(s) from EEPROM through bit-bang method
1363 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1364 u16 words, u16 *data)
1366 s32 status = IXGBE_SUCCESS;
1369 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1371 hw->eeprom.ops.init_params(hw);
1374 status = IXGBE_ERR_INVALID_ARGUMENT;
1378 if (offset + words > hw->eeprom.word_size) {
1379 status = IXGBE_ERR_EEPROM;
1384 * We cannot hold synchronization semaphores for too long
1385 * to avoid other entity starvation. However it is more efficient
1386 * to read in bursts than synchronizing access for each word.
1388 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1389 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1390 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1392 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1395 if (status != IXGBE_SUCCESS)
1404 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1405 * @hw: pointer to hardware structure
1406 * @offset: offset within the EEPROM to be read
1407 * @words: number of word(s)
1408 * @data: read 16 bit word(s) from EEPROM
1410 * Reads 16 bit word(s) from EEPROM through bit-bang method
1412 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1413 u16 words, u16 *data)
1417 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1420 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1422 /* Prepare the EEPROM for reading */
1423 status = ixgbe_acquire_eeprom(hw);
1425 if (status == IXGBE_SUCCESS) {
1426 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1427 ixgbe_release_eeprom(hw);
1428 status = IXGBE_ERR_EEPROM;
1432 if (status == IXGBE_SUCCESS) {
1433 for (i = 0; i < words; i++) {
1434 ixgbe_standby_eeprom(hw);
1436 * Some SPI eeproms use the 8th address bit embedded
1439 if ((hw->eeprom.address_bits == 8) &&
1440 ((offset + i) >= 128))
1441 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1443 /* Send the READ command (opcode + addr) */
1444 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1445 IXGBE_EEPROM_OPCODE_BITS);
1446 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1447 hw->eeprom.address_bits);
1449 /* Read the data. */
1450 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1451 data[i] = (word_in >> 8) | (word_in << 8);
1454 /* End this read operation */
1455 ixgbe_release_eeprom(hw);
1462 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1463 * @hw: pointer to hardware structure
1464 * @offset: offset within the EEPROM to be read
1465 * @data: read 16 bit value from EEPROM
1467 * Reads 16 bit value from EEPROM through bit-bang method
1469 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1474 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1476 hw->eeprom.ops.init_params(hw);
1478 if (offset >= hw->eeprom.word_size) {
1479 status = IXGBE_ERR_EEPROM;
1483 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1490 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1491 * @hw: pointer to hardware structure
1492 * @offset: offset of word in the EEPROM to read
1493 * @words: number of word(s)
1494 * @data: 16 bit word(s) from the EEPROM
1496 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1498 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1499 u16 words, u16 *data)
1502 s32 status = IXGBE_SUCCESS;
1505 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1507 hw->eeprom.ops.init_params(hw);
1510 status = IXGBE_ERR_INVALID_ARGUMENT;
1511 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1515 if (offset >= hw->eeprom.word_size) {
1516 status = IXGBE_ERR_EEPROM;
1517 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1521 for (i = 0; i < words; i++) {
1522 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1523 IXGBE_EEPROM_RW_REG_START;
1525 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1526 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1528 if (status == IXGBE_SUCCESS) {
1529 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1530 IXGBE_EEPROM_RW_REG_DATA);
1532 DEBUGOUT("Eeprom read timed out\n");
1541 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1542 * @hw: pointer to hardware structure
1543 * @offset: offset within the EEPROM to be used as a scratch pad
1545 * Discover EEPROM page size by writing marching data at given offset.
1546 * This function is called only when we are writing a new large buffer
1547 * at given offset so the data would be overwritten anyway.
1549 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1552 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1553 s32 status = IXGBE_SUCCESS;
1556 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1558 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1561 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1562 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1563 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1564 hw->eeprom.word_page_size = 0;
1565 if (status != IXGBE_SUCCESS)
1568 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1569 if (status != IXGBE_SUCCESS)
1573 * When writing in burst more than the actual page size
1574 * EEPROM address wraps around current page.
1576 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1578 DEBUGOUT1("Detected EEPROM page size = %d words.",
1579 hw->eeprom.word_page_size);
1585 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1586 * @hw: pointer to hardware structure
1587 * @offset: offset of word in the EEPROM to read
1588 * @data: word read from the EEPROM
1590 * Reads a 16 bit word from the EEPROM using the EERD register.
1592 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1594 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1598 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1599 * @hw: pointer to hardware structure
1600 * @offset: offset of word in the EEPROM to write
1601 * @words: number of word(s)
1602 * @data: word(s) write to the EEPROM
1604 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1606 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1607 u16 words, u16 *data)
1610 s32 status = IXGBE_SUCCESS;
1613 DEBUGFUNC("ixgbe_write_eewr_generic");
1615 hw->eeprom.ops.init_params(hw);
1618 status = IXGBE_ERR_INVALID_ARGUMENT;
1619 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1623 if (offset >= hw->eeprom.word_size) {
1624 status = IXGBE_ERR_EEPROM;
1625 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1629 for (i = 0; i < words; i++) {
1630 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1631 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1632 IXGBE_EEPROM_RW_REG_START;
1634 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1635 if (status != IXGBE_SUCCESS) {
1636 DEBUGOUT("Eeprom write EEWR timed out\n");
1640 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1642 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1643 if (status != IXGBE_SUCCESS) {
1644 DEBUGOUT("Eeprom write EEWR timed out\n");
1654 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1655 * @hw: pointer to hardware structure
1656 * @offset: offset of word in the EEPROM to write
1657 * @data: word write to the EEPROM
1659 * Write a 16 bit word to the EEPROM using the EEWR register.
1661 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1663 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1667 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1668 * @hw: pointer to hardware structure
1669 * @ee_reg: EEPROM flag for polling
1671 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1672 * read or write is done respectively.
1674 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1678 s32 status = IXGBE_ERR_EEPROM;
1680 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1682 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1683 if (ee_reg == IXGBE_NVM_POLL_READ)
1684 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1686 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1688 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1689 status = IXGBE_SUCCESS;
1695 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1696 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1697 "EEPROM read/write done polling timed out");
1703 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1704 * @hw: pointer to hardware structure
1706 * Prepares EEPROM for access using bit-bang method. This function should
1707 * be called before issuing a command to the EEPROM.
1709 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1711 s32 status = IXGBE_SUCCESS;
1715 DEBUGFUNC("ixgbe_acquire_eeprom");
1717 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1719 status = IXGBE_ERR_SWFW_SYNC;
1721 if (status == IXGBE_SUCCESS) {
1722 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1724 /* Request EEPROM Access */
1725 eec |= IXGBE_EEC_REQ;
1726 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1728 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1729 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1730 if (eec & IXGBE_EEC_GNT)
1735 /* Release if grant not acquired */
1736 if (!(eec & IXGBE_EEC_GNT)) {
1737 eec &= ~IXGBE_EEC_REQ;
1738 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1739 DEBUGOUT("Could not acquire EEPROM grant\n");
1741 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1742 status = IXGBE_ERR_EEPROM;
1745 /* Setup EEPROM for Read/Write */
1746 if (status == IXGBE_SUCCESS) {
1747 /* Clear CS and SK */
1748 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1749 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1750 IXGBE_WRITE_FLUSH(hw);
1758 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1759 * @hw: pointer to hardware structure
1761 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1763 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1765 s32 status = IXGBE_ERR_EEPROM;
1770 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1773 /* Get SMBI software semaphore between device drivers first */
1774 for (i = 0; i < timeout; i++) {
1776 * If the SMBI bit is 0 when we read it, then the bit will be
1777 * set and we have the semaphore
1779 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1780 if (!(swsm & IXGBE_SWSM_SMBI)) {
1781 status = IXGBE_SUCCESS;
1788 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1791 * this release is particularly important because our attempts
1792 * above to get the semaphore may have succeeded, and if there
1793 * was a timeout, we should unconditionally clear the semaphore
1794 * bits to free the driver to make progress
1796 ixgbe_release_eeprom_semaphore(hw);
1801 * If the SMBI bit is 0 when we read it, then the bit will be
1802 * set and we have the semaphore
1804 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1805 if (!(swsm & IXGBE_SWSM_SMBI))
1806 status = IXGBE_SUCCESS;
1809 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1810 if (status == IXGBE_SUCCESS) {
1811 for (i = 0; i < timeout; i++) {
1812 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1814 /* Set the SW EEPROM semaphore bit to request access */
1815 swsm |= IXGBE_SWSM_SWESMBI;
1816 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1819 * If we set the bit successfully then we got the
1822 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1823 if (swsm & IXGBE_SWSM_SWESMBI)
1830 * Release semaphores and return error if SW EEPROM semaphore
1831 * was not granted because we don't have access to the EEPROM
1834 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1835 "SWESMBI Software EEPROM semaphore not granted.\n");
1836 ixgbe_release_eeprom_semaphore(hw);
1837 status = IXGBE_ERR_EEPROM;
1840 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1841 "Software semaphore SMBI between device drivers "
1849 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1850 * @hw: pointer to hardware structure
1852 * This function clears hardware semaphore bits.
1854 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1858 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1860 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1862 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1863 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1864 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1865 IXGBE_WRITE_FLUSH(hw);
1869 * ixgbe_ready_eeprom - Polls for EEPROM ready
1870 * @hw: pointer to hardware structure
1872 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1874 s32 status = IXGBE_SUCCESS;
1878 DEBUGFUNC("ixgbe_ready_eeprom");
1881 * Read "Status Register" repeatedly until the LSB is cleared. The
1882 * EEPROM will signal that the command has been completed by clearing
1883 * bit 0 of the internal status register. If it's not cleared within
1884 * 5 milliseconds, then error out.
1886 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1887 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1888 IXGBE_EEPROM_OPCODE_BITS);
1889 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1890 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1894 ixgbe_standby_eeprom(hw);
1898 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1899 * devices (and only 0-5mSec on 5V devices)
1901 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1902 DEBUGOUT("SPI EEPROM Status error\n");
1903 status = IXGBE_ERR_EEPROM;
1910 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1911 * @hw: pointer to hardware structure
1913 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1917 DEBUGFUNC("ixgbe_standby_eeprom");
1919 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1921 /* Toggle CS to flush commands */
1922 eec |= IXGBE_EEC_CS;
1923 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1924 IXGBE_WRITE_FLUSH(hw);
1926 eec &= ~IXGBE_EEC_CS;
1927 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1928 IXGBE_WRITE_FLUSH(hw);
1933 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1934 * @hw: pointer to hardware structure
1935 * @data: data to send to the EEPROM
1936 * @count: number of bits to shift out
1938 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1945 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1947 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1950 * Mask is used to shift "count" bits of "data" out to the EEPROM
1951 * one bit at a time. Determine the starting bit based on count
1953 mask = 0x01 << (count - 1);
1955 for (i = 0; i < count; i++) {
1957 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1958 * "1", and then raising and then lowering the clock (the SK
1959 * bit controls the clock input to the EEPROM). A "0" is
1960 * shifted out to the EEPROM by setting "DI" to "0" and then
1961 * raising and then lowering the clock.
1964 eec |= IXGBE_EEC_DI;
1966 eec &= ~IXGBE_EEC_DI;
1968 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1969 IXGBE_WRITE_FLUSH(hw);
1973 ixgbe_raise_eeprom_clk(hw, &eec);
1974 ixgbe_lower_eeprom_clk(hw, &eec);
1977 * Shift mask to signify next bit of data to shift in to the
1983 /* We leave the "DI" bit set to "0" when we leave this routine. */
1984 eec &= ~IXGBE_EEC_DI;
1985 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1986 IXGBE_WRITE_FLUSH(hw);
1990 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1991 * @hw: pointer to hardware structure
1993 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1999 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2002 * In order to read a register from the EEPROM, we need to shift
2003 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2004 * the clock input to the EEPROM (setting the SK bit), and then reading
2005 * the value of the "DO" bit. During this "shifting in" process the
2006 * "DI" bit should always be clear.
2008 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2010 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2012 for (i = 0; i < count; i++) {
2014 ixgbe_raise_eeprom_clk(hw, &eec);
2016 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2018 eec &= ~(IXGBE_EEC_DI);
2019 if (eec & IXGBE_EEC_DO)
2022 ixgbe_lower_eeprom_clk(hw, &eec);
2029 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2030 * @hw: pointer to hardware structure
2031 * @eec: EEC register's current value
2033 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2035 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2038 * Raise the clock input to the EEPROM
2039 * (setting the SK bit), then delay
2041 *eec = *eec | IXGBE_EEC_SK;
2042 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2043 IXGBE_WRITE_FLUSH(hw);
2048 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2049 * @hw: pointer to hardware structure
2050 * @eecd: EECD's current value
2052 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2054 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2057 * Lower the clock input to the EEPROM (clearing the SK bit), then
2060 *eec = *eec & ~IXGBE_EEC_SK;
2061 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2062 IXGBE_WRITE_FLUSH(hw);
2067 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2068 * @hw: pointer to hardware structure
2070 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2074 DEBUGFUNC("ixgbe_release_eeprom");
2076 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2078 eec |= IXGBE_EEC_CS; /* Pull CS high */
2079 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2081 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2082 IXGBE_WRITE_FLUSH(hw);
2086 /* Stop requesting EEPROM access */
2087 eec &= ~IXGBE_EEC_REQ;
2088 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2090 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2092 /* Delay before attempt to obtain semaphore again to allow FW access */
2093 msec_delay(hw->eeprom.semaphore_delay);
2097 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2098 * @hw: pointer to hardware structure
2100 * Returns a negative error code on error, or the 16-bit checksum
2102 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2111 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2113 /* Include 0x0-0x3F in the checksum */
2114 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2115 if (hw->eeprom.ops.read(hw, i, &word)) {
2116 DEBUGOUT("EEPROM read failed\n");
2117 return IXGBE_ERR_EEPROM;
2122 /* Include all data from pointers except for the fw pointer */
2123 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2124 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2125 DEBUGOUT("EEPROM read failed\n");
2126 return IXGBE_ERR_EEPROM;
2129 /* If the pointer seems invalid */
2130 if (pointer == 0xFFFF || pointer == 0)
2133 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2134 DEBUGOUT("EEPROM read failed\n");
2135 return IXGBE_ERR_EEPROM;
2138 if (length == 0xFFFF || length == 0)
2141 for (j = pointer + 1; j <= pointer + length; j++) {
2142 if (hw->eeprom.ops.read(hw, j, &word)) {
2143 DEBUGOUT("EEPROM read failed\n");
2144 return IXGBE_ERR_EEPROM;
2150 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2152 return (s32)checksum;
2156 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2157 * @hw: pointer to hardware structure
2158 * @checksum_val: calculated checksum
2160 * Performs checksum calculation and validates the EEPROM checksum. If the
2161 * caller does not need checksum_val, the value can be NULL.
2163 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2168 u16 read_checksum = 0;
2170 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2172 /* Read the first word from the EEPROM. If this times out or fails, do
2173 * not continue or we could be in for a very long wait while every
2176 status = hw->eeprom.ops.read(hw, 0, &checksum);
2178 DEBUGOUT("EEPROM read failed\n");
2182 status = hw->eeprom.ops.calc_checksum(hw);
2186 checksum = (u16)(status & 0xffff);
2188 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2190 DEBUGOUT("EEPROM read failed\n");
2194 /* Verify read checksum from EEPROM is the same as
2195 * calculated checksum
2197 if (read_checksum != checksum)
2198 status = IXGBE_ERR_EEPROM_CHECKSUM;
2200 /* If the user cares, return the calculated checksum */
2202 *checksum_val = checksum;
2208 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2209 * @hw: pointer to hardware structure
2211 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2216 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2218 /* Read the first word from the EEPROM. If this times out or fails, do
2219 * not continue or we could be in for a very long wait while every
2222 status = hw->eeprom.ops.read(hw, 0, &checksum);
2224 DEBUGOUT("EEPROM read failed\n");
2228 status = hw->eeprom.ops.calc_checksum(hw);
2232 checksum = (u16)(status & 0xffff);
2234 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2240 * ixgbe_validate_mac_addr - Validate MAC address
2241 * @mac_addr: pointer to MAC address.
2243 * Tests a MAC address to ensure it is a valid Individual Address
2245 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2247 s32 status = IXGBE_SUCCESS;
2249 DEBUGFUNC("ixgbe_validate_mac_addr");
2251 /* Make sure it is not a multicast address */
2252 if (IXGBE_IS_MULTICAST(mac_addr)) {
2253 DEBUGOUT("MAC address is multicast\n");
2254 status = IXGBE_ERR_INVALID_MAC_ADDR;
2255 /* Not a broadcast address */
2256 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2257 DEBUGOUT("MAC address is broadcast\n");
2258 status = IXGBE_ERR_INVALID_MAC_ADDR;
2259 /* Reject the zero address */
2260 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2261 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2262 DEBUGOUT("MAC address is all zeros\n");
2263 status = IXGBE_ERR_INVALID_MAC_ADDR;
2269 * ixgbe_set_rar_generic - Set Rx address register
2270 * @hw: pointer to hardware structure
2271 * @index: Receive address register to write
2272 * @addr: Address to put into receive address register
2273 * @vmdq: VMDq "set" or "pool" index
2274 * @enable_addr: set flag that address is active
2276 * Puts an ethernet address into a receive address register.
2278 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2281 u32 rar_low, rar_high;
2282 u32 rar_entries = hw->mac.num_rar_entries;
2284 DEBUGFUNC("ixgbe_set_rar_generic");
2286 /* Make sure we are using a valid rar index range */
2287 if (index >= rar_entries) {
2288 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2289 "RAR index %d is out of range.\n", index);
2290 return IXGBE_ERR_INVALID_ARGUMENT;
2293 /* setup VMDq pool selection before this RAR gets enabled */
2294 hw->mac.ops.set_vmdq(hw, index, vmdq);
2297 * HW expects these in little endian so we reverse the byte
2298 * order from network order (big endian) to little endian
2300 rar_low = ((u32)addr[0] |
2301 ((u32)addr[1] << 8) |
2302 ((u32)addr[2] << 16) |
2303 ((u32)addr[3] << 24));
2305 * Some parts put the VMDq setting in the extra RAH bits,
2306 * so save everything except the lower 16 bits that hold part
2307 * of the address and the address valid bit.
2309 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2310 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2311 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2313 if (enable_addr != 0)
2314 rar_high |= IXGBE_RAH_AV;
2316 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2317 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2319 return IXGBE_SUCCESS;
2323 * ixgbe_clear_rar_generic - Remove Rx address register
2324 * @hw: pointer to hardware structure
2325 * @index: Receive address register to write
2327 * Clears an ethernet address from a receive address register.
2329 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2332 u32 rar_entries = hw->mac.num_rar_entries;
2334 DEBUGFUNC("ixgbe_clear_rar_generic");
2336 /* Make sure we are using a valid rar index range */
2337 if (index >= rar_entries) {
2338 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2339 "RAR index %d is out of range.\n", index);
2340 return IXGBE_ERR_INVALID_ARGUMENT;
2344 * Some parts put the VMDq setting in the extra RAH bits,
2345 * so save everything except the lower 16 bits that hold part
2346 * of the address and the address valid bit.
2348 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2349 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2351 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2352 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2354 /* clear VMDq pool/queue selection for this RAR */
2355 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2357 return IXGBE_SUCCESS;
2361 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2362 * @hw: pointer to hardware structure
2364 * Places the MAC address in receive address register 0 and clears the rest
2365 * of the receive address registers. Clears the multicast table. Assumes
2366 * the receiver is in reset when the routine is called.
2368 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2371 u32 rar_entries = hw->mac.num_rar_entries;
2373 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2376 * If the current mac address is valid, assume it is a software override
2377 * to the permanent address.
2378 * Otherwise, use the permanent address from the eeprom.
2380 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2381 IXGBE_ERR_INVALID_MAC_ADDR) {
2382 /* Get the MAC address from the RAR0 for later reference */
2383 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2385 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2386 hw->mac.addr[0], hw->mac.addr[1],
2388 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2389 hw->mac.addr[4], hw->mac.addr[5]);
2391 /* Setup the receive address. */
2392 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2393 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2394 hw->mac.addr[0], hw->mac.addr[1],
2396 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2397 hw->mac.addr[4], hw->mac.addr[5]);
2399 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2401 /* clear VMDq pool/queue selection for RAR 0 */
2402 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2404 hw->addr_ctrl.overflow_promisc = 0;
2406 hw->addr_ctrl.rar_used_count = 1;
2408 /* Zero out the other receive addresses. */
2409 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2410 for (i = 1; i < rar_entries; i++) {
2411 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2412 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2416 hw->addr_ctrl.mta_in_use = 0;
2417 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2419 DEBUGOUT(" Clearing MTA\n");
2420 for (i = 0; i < hw->mac.mcft_size; i++)
2421 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2423 ixgbe_init_uta_tables(hw);
2425 return IXGBE_SUCCESS;
2429 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2430 * @hw: pointer to hardware structure
2431 * @addr: new address
2433 * Adds it to unused receive address register or goes into promiscuous mode.
2435 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2437 u32 rar_entries = hw->mac.num_rar_entries;
2440 DEBUGFUNC("ixgbe_add_uc_addr");
2442 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2443 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2446 * Place this address in the RAR if there is room,
2447 * else put the controller into promiscuous mode
2449 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2450 rar = hw->addr_ctrl.rar_used_count;
2451 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2452 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2453 hw->addr_ctrl.rar_used_count++;
2455 hw->addr_ctrl.overflow_promisc++;
2458 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2462 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2463 * @hw: pointer to hardware structure
2464 * @addr_list: the list of new addresses
2465 * @addr_count: number of addresses
2466 * @next: iterator function to walk the address list
2468 * The given list replaces any existing list. Clears the secondary addrs from
2469 * receive address registers. Uses unused receive address registers for the
2470 * first secondary addresses, and falls back to promiscuous mode as needed.
2472 * Drivers using secondary unicast addresses must set user_set_promisc when
2473 * manually putting the device into promiscuous mode.
2475 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2476 u32 addr_count, ixgbe_mc_addr_itr next)
2480 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2485 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2488 * Clear accounting of old secondary address list,
2489 * don't count RAR[0]
2491 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2492 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2493 hw->addr_ctrl.overflow_promisc = 0;
2495 /* Zero out the other receive addresses */
2496 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2497 for (i = 0; i < uc_addr_in_use; i++) {
2498 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2499 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2502 /* Add the new addresses */
2503 for (i = 0; i < addr_count; i++) {
2504 DEBUGOUT(" Adding the secondary addresses:\n");
2505 addr = next(hw, &addr_list, &vmdq);
2506 ixgbe_add_uc_addr(hw, addr, vmdq);
2509 if (hw->addr_ctrl.overflow_promisc) {
2510 /* enable promisc if not already in overflow or set by user */
2511 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2512 DEBUGOUT(" Entering address overflow promisc mode\n");
2513 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2514 fctrl |= IXGBE_FCTRL_UPE;
2515 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2518 /* only disable if set by overflow, not by user */
2519 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2520 DEBUGOUT(" Leaving address overflow promisc mode\n");
2521 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2522 fctrl &= ~IXGBE_FCTRL_UPE;
2523 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2527 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2528 return IXGBE_SUCCESS;
2532 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2533 * @hw: pointer to hardware structure
2534 * @mc_addr: the multicast address
2536 * Extracts the 12 bits, from a multicast address, to determine which
2537 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2538 * incoming rx multicast addresses, to determine the bit-vector to check in
2539 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2540 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2541 * to mc_filter_type.
2543 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2547 DEBUGFUNC("ixgbe_mta_vector");
2549 switch (hw->mac.mc_filter_type) {
2550 case 0: /* use bits [47:36] of the address */
2551 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2553 case 1: /* use bits [46:35] of the address */
2554 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2556 case 2: /* use bits [45:34] of the address */
2557 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2559 case 3: /* use bits [43:32] of the address */
2560 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2562 default: /* Invalid mc_filter_type */
2563 DEBUGOUT("MC filter type param set incorrectly\n");
2568 /* vector can only be 12-bits or boundary will be exceeded */
2574 * ixgbe_set_mta - Set bit-vector in multicast table
2575 * @hw: pointer to hardware structure
2576 * @hash_value: Multicast address hash value
2578 * Sets the bit-vector in the multicast table.
2580 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2586 DEBUGFUNC("ixgbe_set_mta");
2588 hw->addr_ctrl.mta_in_use++;
2590 vector = ixgbe_mta_vector(hw, mc_addr);
2591 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2594 * The MTA is a register array of 128 32-bit registers. It is treated
2595 * like an array of 4096 bits. We want to set bit
2596 * BitArray[vector_value]. So we figure out what register the bit is
2597 * in, read it, OR in the new bit, then write back the new value. The
2598 * register is determined by the upper 7 bits of the vector value and
2599 * the bit within that register are determined by the lower 5 bits of
2602 vector_reg = (vector >> 5) & 0x7F;
2603 vector_bit = vector & 0x1F;
2604 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2608 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2609 * @hw: pointer to hardware structure
2610 * @mc_addr_list: the list of new multicast addresses
2611 * @mc_addr_count: number of addresses
2612 * @next: iterator function to walk the multicast address list
2613 * @clear: flag, when set clears the table beforehand
2615 * When the clear flag is set, the given list replaces any existing list.
2616 * Hashes the given addresses into the multicast table.
2618 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2619 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2625 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2628 * Set the new number of MC addresses that we are being requested to
2631 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2632 hw->addr_ctrl.mta_in_use = 0;
2634 /* Clear mta_shadow */
2636 DEBUGOUT(" Clearing MTA\n");
2637 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2640 /* Update mta_shadow */
2641 for (i = 0; i < mc_addr_count; i++) {
2642 DEBUGOUT(" Adding the multicast addresses:\n");
2643 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2647 for (i = 0; i < hw->mac.mcft_size; i++)
2648 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2649 hw->mac.mta_shadow[i]);
2651 if (hw->addr_ctrl.mta_in_use > 0)
2652 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2653 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2655 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2656 return IXGBE_SUCCESS;
2660 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2661 * @hw: pointer to hardware structure
2663 * Enables multicast address in RAR and the use of the multicast hash table.
2665 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2667 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2669 DEBUGFUNC("ixgbe_enable_mc_generic");
2671 if (a->mta_in_use > 0)
2672 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2673 hw->mac.mc_filter_type);
2675 return IXGBE_SUCCESS;
2679 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2680 * @hw: pointer to hardware structure
2682 * Disables multicast address in RAR and the use of the multicast hash table.
2684 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2686 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2688 DEBUGFUNC("ixgbe_disable_mc_generic");
2690 if (a->mta_in_use > 0)
2691 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2693 return IXGBE_SUCCESS;
2697 * ixgbe_fc_enable_generic - Enable flow control
2698 * @hw: pointer to hardware structure
2700 * Enable flow control according to the current settings.
2702 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2704 s32 ret_val = IXGBE_SUCCESS;
2705 u32 mflcn_reg, fccfg_reg;
2710 DEBUGFUNC("ixgbe_fc_enable_generic");
2712 /* Validate the water mark configuration */
2713 if (!hw->fc.pause_time) {
2714 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2718 /* Low water mark of zero causes XOFF floods */
2719 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2720 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2721 hw->fc.high_water[i]) {
2722 if (!hw->fc.low_water[i] ||
2723 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2724 DEBUGOUT("Invalid water mark configuration\n");
2725 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2731 /* Negotiate the fc mode to use */
2732 ixgbe_fc_autoneg(hw);
2734 /* Disable any previous flow control settings */
2735 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2736 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2738 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2739 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2742 * The possible values of fc.current_mode are:
2743 * 0: Flow control is completely disabled
2744 * 1: Rx flow control is enabled (we can receive pause frames,
2745 * but not send pause frames).
2746 * 2: Tx flow control is enabled (we can send pause frames but
2747 * we do not support receiving pause frames).
2748 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2751 switch (hw->fc.current_mode) {
2754 * Flow control is disabled by software override or autoneg.
2755 * The code below will actually disable it in the HW.
2758 case ixgbe_fc_rx_pause:
2760 * Rx Flow control is enabled and Tx Flow control is
2761 * disabled by software override. Since there really
2762 * isn't a way to advertise that we are capable of RX
2763 * Pause ONLY, we will advertise that we support both
2764 * symmetric and asymmetric Rx PAUSE. Later, we will
2765 * disable the adapter's ability to send PAUSE frames.
2767 mflcn_reg |= IXGBE_MFLCN_RFCE;
2769 case ixgbe_fc_tx_pause:
2771 * Tx Flow control is enabled, and Rx Flow control is
2772 * disabled by software override.
2774 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2777 /* Flow control (both Rx and Tx) is enabled by SW override. */
2778 mflcn_reg |= IXGBE_MFLCN_RFCE;
2779 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2782 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2783 "Flow control param set incorrectly\n");
2784 ret_val = IXGBE_ERR_CONFIG;
2789 /* Set 802.3x based flow control settings. */
2790 mflcn_reg |= IXGBE_MFLCN_DPF;
2791 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2792 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2795 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2796 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2797 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2798 hw->fc.high_water[i]) {
2799 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2800 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2801 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2803 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2805 * In order to prevent Tx hangs when the internal Tx
2806 * switch is enabled we must set the high water mark
2807 * to the Rx packet buffer size - 24KB. This allows
2808 * the Tx switch to function even under heavy Rx
2811 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2814 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2817 /* Configure pause time (2 TCs per register) */
2818 reg = hw->fc.pause_time * 0x00010001;
2819 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2820 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2822 /* Configure flow control refresh threshold value */
2823 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2830 * ixgbe_negotiate_fc - Negotiate flow control
2831 * @hw: pointer to hardware structure
2832 * @adv_reg: flow control advertised settings
2833 * @lp_reg: link partner's flow control settings
2834 * @adv_sym: symmetric pause bit in advertisement
2835 * @adv_asm: asymmetric pause bit in advertisement
2836 * @lp_sym: symmetric pause bit in link partner advertisement
2837 * @lp_asm: asymmetric pause bit in link partner advertisement
2839 * Find the intersection between advertised settings and link partner's
2840 * advertised settings
2842 STATIC s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2843 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2845 if ((!(adv_reg)) || (!(lp_reg))) {
2846 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2847 "Local or link partner's advertised flow control "
2848 "settings are NULL. Local: %x, link partner: %x\n",
2850 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2853 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2855 * Now we need to check if the user selected Rx ONLY
2856 * of pause frames. In this case, we had to advertise
2857 * FULL flow control because we could not advertise RX
2858 * ONLY. Hence, we must now check to see if we need to
2859 * turn OFF the TRANSMISSION of PAUSE frames.
2861 if (hw->fc.requested_mode == ixgbe_fc_full) {
2862 hw->fc.current_mode = ixgbe_fc_full;
2863 DEBUGOUT("Flow Control = FULL.\n");
2865 hw->fc.current_mode = ixgbe_fc_rx_pause;
2866 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2868 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2869 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2870 hw->fc.current_mode = ixgbe_fc_tx_pause;
2871 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2872 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2873 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2874 hw->fc.current_mode = ixgbe_fc_rx_pause;
2875 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2877 hw->fc.current_mode = ixgbe_fc_none;
2878 DEBUGOUT("Flow Control = NONE.\n");
2880 return IXGBE_SUCCESS;
2884 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2885 * @hw: pointer to hardware structure
2887 * Enable flow control according on 1 gig fiber.
2889 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2891 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2892 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2895 * On multispeed fiber at 1g, bail out if
2896 * - link is up but AN did not complete, or if
2897 * - link is up and AN completed but timed out
2900 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2901 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2902 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2903 ERROR_REPORT1(IXGBE_ERROR_POLLING,
2904 "Auto-Negotiation did not complete or timed out");
2908 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2909 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2911 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2912 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2913 IXGBE_PCS1GANA_ASM_PAUSE,
2914 IXGBE_PCS1GANA_SYM_PAUSE,
2915 IXGBE_PCS1GANA_ASM_PAUSE);
2922 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2923 * @hw: pointer to hardware structure
2925 * Enable flow control according to IEEE clause 37.
2927 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2929 u32 links2, anlp1_reg, autoc_reg, links;
2930 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2933 * On backplane, bail out if
2934 * - backplane autoneg was not completed, or if
2935 * - we are 82599 and link partner is not AN enabled
2937 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2938 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2939 ERROR_REPORT1(IXGBE_ERROR_POLLING,
2940 "Auto-Negotiation did not complete");
2944 if (hw->mac.type == ixgbe_mac_82599EB) {
2945 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2946 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2947 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2948 "Link partner is not AN enabled");
2953 * Read the 10g AN autoc and LP ability registers and resolve
2954 * local flow control settings accordingly
2956 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2957 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2959 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2960 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2961 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2968 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2969 * @hw: pointer to hardware structure
2971 * Enable flow control according to IEEE clause 37.
2973 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2975 u16 technology_ability_reg = 0;
2976 u16 lp_technology_ability_reg = 0;
2978 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2979 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2980 &technology_ability_reg);
2981 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2982 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2983 &lp_technology_ability_reg);
2985 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2986 (u32)lp_technology_ability_reg,
2987 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2988 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2992 * ixgbe_fc_autoneg - Configure flow control
2993 * @hw: pointer to hardware structure
2995 * Compares our advertised flow control capabilities to those advertised by
2996 * our link partner, and determines the proper flow control mode to use.
2998 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
3000 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3001 ixgbe_link_speed speed;
3004 DEBUGFUNC("ixgbe_fc_autoneg");
3007 * AN should have completed when the cable was plugged in.
3008 * Look for reasons to bail out. Bail out if:
3009 * - FC autoneg is disabled, or if
3012 if (hw->fc.disable_fc_autoneg) {
3013 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3014 "Flow control autoneg is disabled");
3018 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3020 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3024 switch (hw->phy.media_type) {
3025 /* Autoneg flow control on fiber adapters */
3026 case ixgbe_media_type_fiber_qsfp:
3027 case ixgbe_media_type_fiber:
3028 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3029 ret_val = ixgbe_fc_autoneg_fiber(hw);
3032 /* Autoneg flow control on backplane adapters */
3033 case ixgbe_media_type_backplane:
3034 ret_val = ixgbe_fc_autoneg_backplane(hw);
3037 /* Autoneg flow control on copper adapters */
3038 case ixgbe_media_type_copper:
3039 if (ixgbe_device_supports_autoneg_fc(hw))
3040 ret_val = ixgbe_fc_autoneg_copper(hw);
3048 if (ret_val == IXGBE_SUCCESS) {
3049 hw->fc.fc_was_autonegged = true;
3051 hw->fc.fc_was_autonegged = false;
3052 hw->fc.current_mode = hw->fc.requested_mode;
3057 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3058 * @hw: pointer to hardware structure
3060 * System-wide timeout range is encoded in PCIe Device Control2 register.
3062 * Add 10% to specified maximum and return the number of times to poll for
3063 * completion timeout, in units of 100 microsec. Never return less than
3064 * 800 = 80 millisec.
3066 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3071 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3072 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3075 case IXGBE_PCIDEVCTRL2_65_130ms:
3076 pollcnt = 1300; /* 130 millisec */
3078 case IXGBE_PCIDEVCTRL2_260_520ms:
3079 pollcnt = 5200; /* 520 millisec */
3081 case IXGBE_PCIDEVCTRL2_1_2s:
3082 pollcnt = 20000; /* 2 sec */
3084 case IXGBE_PCIDEVCTRL2_4_8s:
3085 pollcnt = 80000; /* 8 sec */
3087 case IXGBE_PCIDEVCTRL2_17_34s:
3088 pollcnt = 34000; /* 34 sec */
3090 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3091 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3092 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3093 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3095 pollcnt = 800; /* 80 millisec minimum */
3099 /* add 10% to spec maximum */
3100 return (pollcnt * 11) / 10;
3104 * ixgbe_disable_pcie_master - Disable PCI-express master access
3105 * @hw: pointer to hardware structure
3107 * Disables PCI-Express master access and verifies there are no pending
3108 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3109 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3110 * is returned signifying master requests disabled.
3112 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3114 s32 status = IXGBE_SUCCESS;
3118 DEBUGFUNC("ixgbe_disable_pcie_master");
3120 /* Always set this bit to ensure any future transactions are blocked */
3121 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3123 /* Exit if master requests are blocked */
3124 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3125 IXGBE_REMOVED(hw->hw_addr))
3128 /* Poll for master request bit to clear */
3129 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3131 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3136 * Two consecutive resets are required via CTRL.RST per datasheet
3137 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3138 * of this need. The first reset prevents new master requests from
3139 * being issued by our device. We then must wait 1usec or more for any
3140 * remaining completions from the PCIe bus to trickle in, and then reset
3141 * again to clear out any effects they may have had on our device.
3143 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3144 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3147 * Before proceeding, make sure that the PCIe block does not have
3148 * transactions pending.
3150 poll = ixgbe_pcie_timeout_poll(hw);
3151 for (i = 0; i < poll; i++) {
3153 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3154 if (IXGBE_REMOVED(hw->hw_addr))
3156 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3160 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3161 "PCIe transaction pending bit also did not clear.\n");
3162 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3169 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3170 * @hw: pointer to hardware structure
3171 * @mask: Mask to specify which semaphore to acquire
3173 * Acquires the SWFW semaphore through the GSSR register for the specified
3174 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3176 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3180 u32 fwmask = mask << 5;
3184 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3186 for (i = 0; i < timeout; i++) {
3188 * SW NVM semaphore bit is used for access to all
3189 * SW_FW_SYNC bits (not just NVM)
3191 if (ixgbe_get_eeprom_semaphore(hw))
3192 return IXGBE_ERR_SWFW_SYNC;
3194 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3195 if (!(gssr & (fwmask | swmask))) {
3197 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3198 ixgbe_release_eeprom_semaphore(hw);
3199 return IXGBE_SUCCESS;
3201 /* Resource is currently in use by FW or SW */
3202 ixgbe_release_eeprom_semaphore(hw);
3207 /* If time expired clear the bits holding the lock and retry */
3208 if (gssr & (fwmask | swmask))
3209 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3212 return IXGBE_ERR_SWFW_SYNC;
3216 * ixgbe_release_swfw_sync - Release SWFW semaphore
3217 * @hw: pointer to hardware structure
3218 * @mask: Mask to specify which semaphore to release
3220 * Releases the SWFW semaphore through the GSSR register for the specified
3221 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3223 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3228 DEBUGFUNC("ixgbe_release_swfw_sync");
3230 ixgbe_get_eeprom_semaphore(hw);
3232 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3234 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3236 ixgbe_release_eeprom_semaphore(hw);
3240 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3241 * @hw: pointer to hardware structure
3243 * Stops the receive data path and waits for the HW to internally empty
3244 * the Rx security block
3246 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3248 #define IXGBE_MAX_SECRX_POLL 40
3253 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3256 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3257 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3258 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3259 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3260 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3261 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3264 /* Use interrupt-safe sleep just in case */
3268 /* For informational purposes only */
3269 if (i >= IXGBE_MAX_SECRX_POLL)
3270 DEBUGOUT("Rx unit being enabled before security "
3271 "path fully disabled. Continuing with init.\n");
3273 return IXGBE_SUCCESS;
3277 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3278 * @hw: pointer to hardware structure
3279 * @reg_val: Value we read from AUTOC
3281 * The default case requires no protection so just to the register read.
3283 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3286 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3287 return IXGBE_SUCCESS;
3291 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3292 * @hw: pointer to hardware structure
3293 * @reg_val: value to write to AUTOC
3294 * @locked: bool to indicate whether the SW/FW lock was already taken by
3297 * The default case requires no protection so just to the register write.
3299 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3301 UNREFERENCED_1PARAMETER(locked);
3303 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3304 return IXGBE_SUCCESS;
3308 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3309 * @hw: pointer to hardware structure
3311 * Enables the receive data path.
3313 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3317 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3319 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3320 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3321 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3322 IXGBE_WRITE_FLUSH(hw);
3324 return IXGBE_SUCCESS;
3328 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3329 * @hw: pointer to hardware structure
3330 * @regval: register value to write to RXCTRL
3332 * Enables the Rx DMA unit
3334 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3336 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3338 if (regval & IXGBE_RXCTRL_RXEN)
3339 ixgbe_enable_rx(hw);
3341 ixgbe_disable_rx(hw);
3343 return IXGBE_SUCCESS;
3347 * ixgbe_blink_led_start_generic - Blink LED based on index.
3348 * @hw: pointer to hardware structure
3349 * @index: led number to blink
3351 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3353 ixgbe_link_speed speed = 0;
3356 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3357 s32 ret_val = IXGBE_SUCCESS;
3358 bool locked = false;
3360 DEBUGFUNC("ixgbe_blink_led_start_generic");
3363 * Link must be up to auto-blink the LEDs;
3364 * Force it if link is down.
3366 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3369 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3370 if (ret_val != IXGBE_SUCCESS)
3373 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3374 autoc_reg |= IXGBE_AUTOC_FLU;
3376 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3377 if (ret_val != IXGBE_SUCCESS)
3380 IXGBE_WRITE_FLUSH(hw);
3384 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3385 led_reg |= IXGBE_LED_BLINK(index);
3386 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3387 IXGBE_WRITE_FLUSH(hw);
3394 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3395 * @hw: pointer to hardware structure
3396 * @index: led number to stop blinking
3398 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3401 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3402 s32 ret_val = IXGBE_SUCCESS;
3403 bool locked = false;
3405 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3407 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3408 if (ret_val != IXGBE_SUCCESS)
3411 autoc_reg &= ~IXGBE_AUTOC_FLU;
3412 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3414 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3415 if (ret_val != IXGBE_SUCCESS)
3418 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3419 led_reg &= ~IXGBE_LED_BLINK(index);
3420 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3421 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3422 IXGBE_WRITE_FLUSH(hw);
3429 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3430 * @hw: pointer to hardware structure
3431 * @san_mac_offset: SAN MAC address offset
3433 * This function will read the EEPROM location for the SAN MAC address
3434 * pointer, and returns the value at that location. This is used in both
3435 * get and set mac_addr routines.
3437 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3438 u16 *san_mac_offset)
3442 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3445 * First read the EEPROM pointer to see if the MAC addresses are
3448 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3451 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3452 "eeprom at offset %d failed",
3453 IXGBE_SAN_MAC_ADDR_PTR);
3460 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3461 * @hw: pointer to hardware structure
3462 * @san_mac_addr: SAN MAC address
3464 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3465 * per-port, so set_lan_id() must be called before reading the addresses.
3466 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3467 * upon for non-SFP connections, so we must call it here.
3469 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3471 u16 san_mac_data, san_mac_offset;
3475 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3478 * First read the EEPROM pointer to see if the MAC addresses are
3479 * available. If they're not, no point in calling set_lan_id() here.
3481 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3482 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3483 goto san_mac_addr_out;
3485 /* make sure we know which port we need to program */
3486 hw->mac.ops.set_lan_id(hw);
3487 /* apply the port offset to the address offset */
3488 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3489 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3490 for (i = 0; i < 3; i++) {
3491 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3494 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3495 "eeprom read at offset %d failed",
3497 goto san_mac_addr_out;
3499 san_mac_addr[i * 2] = (u8)(san_mac_data);
3500 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3503 return IXGBE_SUCCESS;
3507 * No addresses available in this EEPROM. It's not an
3508 * error though, so just wipe the local address and return.
3510 for (i = 0; i < 6; i++)
3511 san_mac_addr[i] = 0xFF;
3512 return IXGBE_SUCCESS;
3516 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3517 * @hw: pointer to hardware structure
3518 * @san_mac_addr: SAN MAC address
3520 * Write a SAN MAC address to the EEPROM.
3522 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3525 u16 san_mac_data, san_mac_offset;
3528 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3530 /* Look for SAN mac address pointer. If not defined, return */
3531 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3532 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3533 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3535 /* Make sure we know which port we need to write */
3536 hw->mac.ops.set_lan_id(hw);
3537 /* Apply the port offset to the address offset */
3538 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3539 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3541 for (i = 0; i < 3; i++) {
3542 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3543 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3544 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3548 return IXGBE_SUCCESS;
3552 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3553 * @hw: pointer to hardware structure
3555 * Read PCIe configuration space, and get the MSI-X vector count from
3556 * the capabilities table.
3558 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3564 switch (hw->mac.type) {
3565 case ixgbe_mac_82598EB:
3566 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3567 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3569 case ixgbe_mac_82599EB:
3570 case ixgbe_mac_X540:
3571 case ixgbe_mac_X550:
3572 case ixgbe_mac_X550EM_x:
3573 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3574 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3580 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3581 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3582 if (IXGBE_REMOVED(hw->hw_addr))
3584 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3586 /* MSI-X count is zero-based in HW */
3589 if (msix_count > max_msix_count)
3590 msix_count = max_msix_count;
3596 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3597 * @hw: pointer to hardware structure
3598 * @addr: Address to put into receive address register
3599 * @vmdq: VMDq pool to assign
3601 * Puts an ethernet address into a receive address register, or
3602 * finds the rar that it is aleady in; adds to the pool list
3604 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3606 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3607 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3609 u32 rar_low, rar_high;
3610 u32 addr_low, addr_high;
3612 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3614 /* swap bytes for HW little endian */
3615 addr_low = addr[0] | (addr[1] << 8)
3618 addr_high = addr[4] | (addr[5] << 8);
3621 * Either find the mac_id in rar or find the first empty space.
3622 * rar_highwater points to just after the highest currently used
3623 * rar in order to shorten the search. It grows when we add a new
3626 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3627 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3629 if (((IXGBE_RAH_AV & rar_high) == 0)
3630 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3631 first_empty_rar = rar;
3632 } else if ((rar_high & 0xFFFF) == addr_high) {
3633 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3634 if (rar_low == addr_low)
3635 break; /* found it already in the rars */
3639 if (rar < hw->mac.rar_highwater) {
3640 /* already there so just add to the pool bits */
3641 ixgbe_set_vmdq(hw, rar, vmdq);
3642 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3643 /* stick it into first empty RAR slot we found */
3644 rar = first_empty_rar;
3645 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3646 } else if (rar == hw->mac.rar_highwater) {
3647 /* add it to the top of the list and inc the highwater mark */
3648 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3649 hw->mac.rar_highwater++;
3650 } else if (rar >= hw->mac.num_rar_entries) {
3651 return IXGBE_ERR_INVALID_MAC_ADDR;
3655 * If we found rar[0], make sure the default pool bit (we use pool 0)
3656 * remains cleared to be sure default pool packets will get delivered
3659 ixgbe_clear_vmdq(hw, rar, 0);
3665 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3666 * @hw: pointer to hardware struct
3667 * @rar: receive address register index to disassociate
3668 * @vmdq: VMDq pool index to remove from the rar
3670 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3672 u32 mpsar_lo, mpsar_hi;
3673 u32 rar_entries = hw->mac.num_rar_entries;
3675 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3677 /* Make sure we are using a valid rar index range */
3678 if (rar >= rar_entries) {
3679 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3680 "RAR index %d is out of range.\n", rar);
3681 return IXGBE_ERR_INVALID_ARGUMENT;
3684 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3685 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3687 if (IXGBE_REMOVED(hw->hw_addr))
3690 if (!mpsar_lo && !mpsar_hi)
3693 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3695 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3699 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3702 } else if (vmdq < 32) {
3703 mpsar_lo &= ~(1 << vmdq);
3704 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3706 mpsar_hi &= ~(1 << (vmdq - 32));
3707 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3710 /* was that the last pool using this rar? */
3711 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3712 hw->mac.ops.clear_rar(hw, rar);
3714 return IXGBE_SUCCESS;
3718 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3719 * @hw: pointer to hardware struct
3720 * @rar: receive address register index to associate with a VMDq index
3721 * @vmdq: VMDq pool index
3723 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3726 u32 rar_entries = hw->mac.num_rar_entries;
3728 DEBUGFUNC("ixgbe_set_vmdq_generic");
3730 /* Make sure we are using a valid rar index range */
3731 if (rar >= rar_entries) {
3732 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3733 "RAR index %d is out of range.\n", rar);
3734 return IXGBE_ERR_INVALID_ARGUMENT;
3738 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3740 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3742 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3743 mpsar |= 1 << (vmdq - 32);
3744 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3746 return IXGBE_SUCCESS;
3750 * This function should only be involved in the IOV mode.
3751 * In IOV mode, Default pool is next pool after the number of
3752 * VFs advertized and not 0.
3753 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3755 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3756 * @hw: pointer to hardware struct
3757 * @vmdq: VMDq pool index
3759 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3761 u32 rar = hw->mac.san_mac_rar_index;
3763 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3766 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3767 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3769 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3770 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3773 return IXGBE_SUCCESS;
3777 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3778 * @hw: pointer to hardware structure
3780 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3784 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3785 DEBUGOUT(" Clearing UTA\n");
3787 for (i = 0; i < 128; i++)
3788 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3790 return IXGBE_SUCCESS;
3794 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3795 * @hw: pointer to hardware structure
3796 * @vlan: VLAN id to write to VLAN filter
3798 * return the VLVF index where this VLAN id should be placed
3801 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3804 u32 first_empty_slot = 0;
3807 /* short cut the special case */
3812 * Search for the vlan id in the VLVF entries. Save off the first empty
3813 * slot found along the way
3815 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3816 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3817 if (!bits && !(first_empty_slot))
3818 first_empty_slot = regindex;
3819 else if ((bits & 0x0FFF) == vlan)
3824 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3825 * in the VLVF. Else use the first empty VLVF register for this
3828 if (regindex >= IXGBE_VLVF_ENTRIES) {
3829 if (first_empty_slot)
3830 regindex = first_empty_slot;
3832 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
3833 "No space in VLVF.\n");
3834 regindex = IXGBE_ERR_NO_SPACE;
3842 * ixgbe_set_vfta_generic - Set VLAN filter table
3843 * @hw: pointer to hardware structure
3844 * @vlan: VLAN id to write to VLAN filter
3845 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3846 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3848 * Turn on/off specified VLAN in the VLAN filter table.
3850 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3857 s32 ret_val = IXGBE_SUCCESS;
3858 bool vfta_changed = false;
3860 DEBUGFUNC("ixgbe_set_vfta_generic");
3863 return IXGBE_ERR_PARAM;
3866 * this is a 2 part operation - first the VFTA, then the
3867 * VLVF and VLVFB if VT Mode is set
3868 * We don't write the VFTA until we know the VLVF part succeeded.
3872 * The VFTA is a bitstring made up of 128 32-bit registers
3873 * that enable the particular VLAN id, much like the MTA:
3874 * bits[11-5]: which register
3875 * bits[4-0]: which bit in the register
3877 regindex = (vlan >> 5) & 0x7F;
3878 bitindex = vlan & 0x1F;
3879 targetbit = (1 << bitindex);
3880 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3883 if (!(vfta & targetbit)) {
3885 vfta_changed = true;
3888 if ((vfta & targetbit)) {
3890 vfta_changed = true;
3895 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3897 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3899 if (ret_val != IXGBE_SUCCESS)
3903 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3905 return IXGBE_SUCCESS;
3909 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3910 * @hw: pointer to hardware structure
3911 * @vlan: VLAN id to write to VLAN filter
3912 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3913 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3914 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3917 * Turn on/off specified bit in VLVF table.
3919 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3920 bool vlan_on, bool *vfta_changed)
3924 DEBUGFUNC("ixgbe_set_vlvf_generic");
3927 return IXGBE_ERR_PARAM;
3929 /* If VT Mode is set
3931 * make sure the vlan is in VLVF
3932 * set the vind bit in the matching VLVFB
3934 * clear the pool bit and possibly the vind
3936 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3937 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3941 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3946 /* set the pool bit */
3948 bits = IXGBE_READ_REG(hw,
3949 IXGBE_VLVFB(vlvf_index * 2));
3950 bits |= (1 << vind);
3952 IXGBE_VLVFB(vlvf_index * 2),
3955 bits = IXGBE_READ_REG(hw,
3956 IXGBE_VLVFB((vlvf_index * 2) + 1));
3957 bits |= (1 << (vind - 32));
3959 IXGBE_VLVFB((vlvf_index * 2) + 1),
3963 /* clear the pool bit */
3965 bits = IXGBE_READ_REG(hw,
3966 IXGBE_VLVFB(vlvf_index * 2));
3967 bits &= ~(1 << vind);
3969 IXGBE_VLVFB(vlvf_index * 2),
3971 bits |= IXGBE_READ_REG(hw,
3972 IXGBE_VLVFB((vlvf_index * 2) + 1));
3974 bits = IXGBE_READ_REG(hw,
3975 IXGBE_VLVFB((vlvf_index * 2) + 1));
3976 bits &= ~(1 << (vind - 32));
3978 IXGBE_VLVFB((vlvf_index * 2) + 1),
3980 bits |= IXGBE_READ_REG(hw,
3981 IXGBE_VLVFB(vlvf_index * 2));
3986 * If there are still bits set in the VLVFB registers
3987 * for the VLAN ID indicated we need to see if the
3988 * caller is requesting that we clear the VFTA entry bit.
3989 * If the caller has requested that we clear the VFTA
3990 * entry bit but there are still pools/VFs using this VLAN
3991 * ID entry then ignore the request. We're not worried
3992 * about the case where we're turning the VFTA VLAN ID
3993 * entry bit on, only when requested to turn it off as
3994 * there may be multiple pools and/or VFs using the
3995 * VLAN ID entry. In that case we cannot clear the
3996 * VFTA bit until all pools/VFs using that VLAN ID have also
3997 * been cleared. This will be indicated by "bits" being
4001 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
4002 (IXGBE_VLVF_VIEN | vlan));
4003 if ((!vlan_on) && (vfta_changed != NULL)) {
4004 /* someone wants to clear the vfta entry
4005 * but some pools/VFs are still using it.
4007 *vfta_changed = false;
4010 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4013 return IXGBE_SUCCESS;
4017 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4018 * @hw: pointer to hardware structure
4020 * Clears the VLAN filer table, and the VMDq index associated with the filter
4022 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4026 DEBUGFUNC("ixgbe_clear_vfta_generic");
4028 for (offset = 0; offset < hw->mac.vft_size; offset++)
4029 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4031 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4032 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4033 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4034 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
4037 return IXGBE_SUCCESS;
4041 * ixgbe_check_mac_link_generic - Determine link and speed status
4042 * @hw: pointer to hardware structure
4043 * @speed: pointer to link speed
4044 * @link_up: true when link is up
4045 * @link_up_wait_to_complete: bool used to wait for link up or not
4047 * Reads the links register to determine if link is up and the current speed
4049 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4050 bool *link_up, bool link_up_wait_to_complete)
4052 u32 links_reg, links_orig;
4055 DEBUGFUNC("ixgbe_check_mac_link_generic");
4057 /* clear the old state */
4058 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4060 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4062 if (links_orig != links_reg) {
4063 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4064 links_orig, links_reg);
4067 if (link_up_wait_to_complete) {
4068 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
4069 if (links_reg & IXGBE_LINKS_UP) {
4076 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4079 if (links_reg & IXGBE_LINKS_UP)
4085 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4086 IXGBE_LINKS_SPEED_10G_82599) {
4087 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4088 if (hw->mac.type > ixgbe_mac_X550) {
4089 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4090 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4093 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4094 IXGBE_LINKS_SPEED_1G_82599)
4095 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4096 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4097 IXGBE_LINKS_SPEED_100_82599)
4098 *speed = IXGBE_LINK_SPEED_100_FULL;
4100 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4102 return IXGBE_SUCCESS;
4106 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4108 * @hw: pointer to hardware structure
4109 * @wwnn_prefix: the alternative WWNN prefix
4110 * @wwpn_prefix: the alternative WWPN prefix
4112 * This function will read the EEPROM from the alternative SAN MAC address
4113 * block to check the support for the alternative WWNN/WWPN prefix support.
4115 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4119 u16 alt_san_mac_blk_offset;
4121 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4123 /* clear output first */
4124 *wwnn_prefix = 0xFFFF;
4125 *wwpn_prefix = 0xFFFF;
4127 /* check if alternative SAN MAC is supported */
4128 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4129 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4130 goto wwn_prefix_err;
4132 if ((alt_san_mac_blk_offset == 0) ||
4133 (alt_san_mac_blk_offset == 0xFFFF))
4134 goto wwn_prefix_out;
4136 /* check capability in alternative san mac address block */
4137 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4138 if (hw->eeprom.ops.read(hw, offset, &caps))
4139 goto wwn_prefix_err;
4140 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4141 goto wwn_prefix_out;
4143 /* get the corresponding prefix for WWNN/WWPN */
4144 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4145 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4146 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4147 "eeprom read at offset %d failed", offset);
4150 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4151 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4152 goto wwn_prefix_err;
4155 return IXGBE_SUCCESS;
4158 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4159 "eeprom read at offset %d failed", offset);
4160 return IXGBE_SUCCESS;
4164 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4165 * @hw: pointer to hardware structure
4166 * @bs: the fcoe boot status
4168 * This function will read the FCOE boot status from the iSCSI FCOE block
4170 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4172 u16 offset, caps, flags;
4175 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4177 /* clear output first */
4178 *bs = ixgbe_fcoe_bootstatus_unavailable;
4180 /* check if FCOE IBA block is present */
4181 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4182 status = hw->eeprom.ops.read(hw, offset, &caps);
4183 if (status != IXGBE_SUCCESS)
4186 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4189 /* check if iSCSI FCOE block is populated */
4190 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4191 if (status != IXGBE_SUCCESS)
4194 if ((offset == 0) || (offset == 0xFFFF))
4197 /* read fcoe flags in iSCSI FCOE block */
4198 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4199 status = hw->eeprom.ops.read(hw, offset, &flags);
4200 if (status != IXGBE_SUCCESS)
4203 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4204 *bs = ixgbe_fcoe_bootstatus_enabled;
4206 *bs = ixgbe_fcoe_bootstatus_disabled;
4213 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4214 * @hw: pointer to hardware structure
4215 * @enable: enable or disable switch for anti-spoofing
4216 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
4219 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
4222 int pf_target_reg = pf >> 3;
4223 int pf_target_shift = pf % 8;
4226 if (hw->mac.type == ixgbe_mac_82598EB)
4230 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
4233 * PFVFSPOOF register array is size 8 with 8 bits assigned to
4234 * MAC anti-spoof enables in each register array element.
4236 for (j = 0; j < pf_target_reg; j++)
4237 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4240 * The PF should be allowed to spoof so that it can support
4241 * emulation mode NICs. Do not set the bits assigned to the PF
4243 pfvfspoof &= (1 << pf_target_shift) - 1;
4244 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4247 * Remaining pools belong to the PF so they do not need to have
4248 * anti-spoofing enabled.
4250 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
4251 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
4255 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4256 * @hw: pointer to hardware structure
4257 * @enable: enable or disable switch for VLAN anti-spoofing
4258 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4261 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4263 int vf_target_reg = vf >> 3;
4264 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4267 if (hw->mac.type == ixgbe_mac_82598EB)
4270 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4272 pfvfspoof |= (1 << vf_target_shift);
4274 pfvfspoof &= ~(1 << vf_target_shift);
4275 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4279 * ixgbe_get_device_caps_generic - Get additional device capabilities
4280 * @hw: pointer to hardware structure
4281 * @device_caps: the EEPROM word with the extra device capabilities
4283 * This function will read the EEPROM location for the device capabilities,
4284 * and return the word through device_caps.
4286 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4288 DEBUGFUNC("ixgbe_get_device_caps_generic");
4290 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4292 return IXGBE_SUCCESS;
4296 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4297 * @hw: pointer to hardware structure
4300 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4305 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4307 /* Enable relaxed ordering */
4308 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4309 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4310 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4311 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4314 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4315 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4316 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4317 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4318 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4324 * ixgbe_calculate_checksum - Calculate checksum for buffer
4325 * @buffer: pointer to EEPROM
4326 * @length: size of EEPROM to calculate a checksum for
4327 * Calculates the checksum for some buffer on a specified length. The
4328 * checksum calculated is returned.
4330 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4335 DEBUGFUNC("ixgbe_calculate_checksum");
4340 for (i = 0; i < length; i++)
4343 return (u8) (0 - sum);
4347 * ixgbe_host_interface_command - Issue command to manageability block
4348 * @hw: pointer to the HW structure
4349 * @buffer: contains the command to write and where the return status will
4351 * @length: length of buffer, must be multiple of 4 bytes
4352 * @return_data: read and return data from the buffer (true) or not (false)
4353 * Needed because FW structures are big endian and decoding of
4354 * these fields can be 8 bit or 16 bit based on command. Decoding
4355 * is not easily understood without making a table of commands.
4356 * So we will leave this up to the caller to read back the data
4359 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4360 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
4362 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4363 u32 length, bool return_data)
4365 u32 hicr, i, bi, fwsts;
4366 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4370 DEBUGFUNC("ixgbe_host_interface_command");
4372 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4373 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4374 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4376 /* Set bit 9 of FWSTS clearing FW reset indication */
4377 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4378 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4380 /* Check that the host interface is enabled. */
4381 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4382 if ((hicr & IXGBE_HICR_EN) == 0) {
4383 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4384 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4387 /* Calculate length in DWORDs. We must be DWORD aligned */
4388 if ((length % (sizeof(u32))) != 0) {
4389 DEBUGOUT("Buffer length failure, not aligned to dword");
4390 return IXGBE_ERR_INVALID_ARGUMENT;
4393 dword_len = length >> 2;
4395 /* The device driver writes the relevant command block
4396 * into the ram area.
4398 for (i = 0; i < dword_len; i++)
4399 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4400 i, IXGBE_CPU_TO_LE32(buffer[i]));
4402 /* Setting this bit tells the ARC that a new command is pending. */
4403 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4405 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
4406 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4407 if (!(hicr & IXGBE_HICR_C))
4412 /* Check command completion */
4413 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
4414 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4415 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4416 "Command has failed with no status valid.\n");
4417 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4423 /* Calculate length in DWORDs */
4424 dword_len = hdr_size >> 2;
4426 /* first pull in the header so we know the buffer length */
4427 for (bi = 0; bi < dword_len; bi++) {
4428 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4429 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4432 /* If there is any thing in data position pull it in */
4433 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4437 if (length < buf_len + hdr_size) {
4438 DEBUGOUT("Buffer not large enough for reply message.\n");
4439 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4442 /* Calculate length in DWORDs, add 3 for odd lengths */
4443 dword_len = (buf_len + 3) >> 2;
4445 /* Pull in the rest of the buffer (bi is where we left off) */
4446 for (; bi <= dword_len; bi++) {
4447 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4448 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4455 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4456 * @hw: pointer to the HW structure
4457 * @maj: driver version major number
4458 * @min: driver version minor number
4459 * @build: driver version build number
4460 * @sub: driver version sub build number
4462 * Sends driver version number to firmware through the manageability
4463 * block. On success return IXGBE_SUCCESS
4464 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4465 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4467 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4470 struct ixgbe_hic_drv_info fw_cmd;
4472 s32 ret_val = IXGBE_SUCCESS;
4474 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4476 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
4478 ret_val = IXGBE_ERR_SWFW_SYNC;
4482 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4483 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4484 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4485 fw_cmd.port_num = (u8)hw->bus.func;
4486 fw_cmd.ver_maj = maj;
4487 fw_cmd.ver_min = min;
4488 fw_cmd.ver_build = build;
4489 fw_cmd.ver_sub = sub;
4490 fw_cmd.hdr.checksum = 0;
4491 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4492 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4496 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4497 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4498 sizeof(fw_cmd), true);
4499 if (ret_val != IXGBE_SUCCESS)
4502 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4503 FW_CEM_RESP_STATUS_SUCCESS)
4504 ret_val = IXGBE_SUCCESS;
4506 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4511 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4517 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4518 * @hw: pointer to hardware structure
4519 * @num_pb: number of packet buffers to allocate
4520 * @headroom: reserve n KB of headroom
4521 * @strategy: packet buffer allocation strategy
4523 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4526 u32 pbsize = hw->mac.rx_pb_size;
4528 u32 rxpktsize, txpktsize, txpbthresh;
4530 /* Reserve headroom */
4536 /* Divide remaining packet buffer space amongst the number of packet
4537 * buffers requested using supplied strategy.
4540 case PBA_STRATEGY_WEIGHTED:
4541 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4542 * buffer with 5/8 of the packet buffer space.
4544 rxpktsize = (pbsize * 5) / (num_pb * 4);
4545 pbsize -= rxpktsize * (num_pb / 2);
4546 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4547 for (; i < (num_pb / 2); i++)
4548 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4549 /* Fall through to configure remaining packet buffers */
4550 case PBA_STRATEGY_EQUAL:
4551 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4552 for (; i < num_pb; i++)
4553 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4559 /* Only support an equally distributed Tx packet buffer strategy. */
4560 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4561 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4562 for (i = 0; i < num_pb; i++) {
4563 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4564 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4567 /* Clear unused TCs, if any, to zero buffer size*/
4568 for (; i < IXGBE_MAX_PB; i++) {
4569 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4570 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4571 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4576 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4577 * @hw: pointer to the hardware structure
4579 * The 82599 and x540 MACs can experience issues if TX work is still pending
4580 * when a reset occurs. This function prevents this by flushing the PCIe
4581 * buffers on the system.
4583 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4585 u32 gcr_ext, hlreg0;
4588 * If double reset is not requested then all transactions should
4589 * already be clear and as such there is no work to do
4591 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4595 * Set loopback enable to prevent any transmits from being sent
4596 * should the link come up. This assumes that the RXCTRL.RXEN bit
4597 * has already been cleared.
4599 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4600 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4602 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4603 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4604 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4605 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4607 /* Flush all writes and allow 20usec for all transactions to clear */
4608 IXGBE_WRITE_FLUSH(hw);
4611 /* restore previous register values */
4612 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4613 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4616 STATIC const u8 ixgbe_emc_temp_data[4] = {
4617 IXGBE_EMC_INTERNAL_DATA,
4618 IXGBE_EMC_DIODE1_DATA,
4619 IXGBE_EMC_DIODE2_DATA,
4620 IXGBE_EMC_DIODE3_DATA
4622 STATIC const u8 ixgbe_emc_therm_limit[4] = {
4623 IXGBE_EMC_INTERNAL_THERM_LIMIT,
4624 IXGBE_EMC_DIODE1_THERM_LIMIT,
4625 IXGBE_EMC_DIODE2_THERM_LIMIT,
4626 IXGBE_EMC_DIODE3_THERM_LIMIT
4630 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
4631 * @hw: pointer to hardware structure
4632 * @data: pointer to the thermal sensor data structure
4634 * Returns the thermal sensor data structure
4636 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
4638 s32 status = IXGBE_SUCCESS;
4646 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4648 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic");
4650 /* Only support thermal sensors attached to 82599 physical port 0 */
4651 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4652 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
4653 status = IXGBE_NOT_IMPLEMENTED;
4657 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4661 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
4662 status = IXGBE_NOT_IMPLEMENTED;
4666 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4670 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4671 != IXGBE_ETS_TYPE_EMC) {
4672 status = IXGBE_NOT_IMPLEMENTED;
4676 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4677 if (num_sensors > IXGBE_MAX_SENSORS)
4678 num_sensors = IXGBE_MAX_SENSORS;
4680 for (i = 0; i < num_sensors; i++) {
4681 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
4686 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4687 IXGBE_ETS_DATA_INDEX_SHIFT);
4688 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4689 IXGBE_ETS_DATA_LOC_SHIFT);
4691 if (sensor_location != 0) {
4692 status = hw->phy.ops.read_i2c_byte(hw,
4693 ixgbe_emc_temp_data[sensor_index],
4694 IXGBE_I2C_THERMAL_SENSOR_ADDR,
4695 &data->sensor[i].temp);
4705 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
4706 * @hw: pointer to hardware structure
4708 * Inits the thermal sensor thresholds according to the NVM map
4709 * and save off the threshold and location values into mac.thermal_sensor_data
4711 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4713 s32 status = IXGBE_SUCCESS;
4718 u8 low_thresh_delta;
4724 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4726 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic");
4728 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4730 /* Only support thermal sensors attached to 82599 physical port 0 */
4731 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4732 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4733 return IXGBE_NOT_IMPLEMENTED;
4735 offset = IXGBE_ETS_CFG;
4736 if (hw->eeprom.ops.read(hw, offset, &ets_offset))
4738 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4739 return IXGBE_NOT_IMPLEMENTED;
4741 offset = ets_offset;
4742 if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
4744 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4745 != IXGBE_ETS_TYPE_EMC)
4746 return IXGBE_NOT_IMPLEMENTED;
4748 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4749 IXGBE_ETS_LTHRES_DELTA_SHIFT);
4750 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4752 for (i = 0; i < num_sensors; i++) {
4753 offset = ets_offset + 1 + i;
4754 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
4755 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4756 "eeprom read at offset %d failed",
4760 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4761 IXGBE_ETS_DATA_INDEX_SHIFT);
4762 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4763 IXGBE_ETS_DATA_LOC_SHIFT);
4764 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4766 hw->phy.ops.write_i2c_byte(hw,
4767 ixgbe_emc_therm_limit[sensor_index],
4768 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
4770 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
4771 data->sensor[i].location = sensor_location;
4772 data->sensor[i].caution_thresh = therm_limit;
4773 data->sensor[i].max_op_thresh = therm_limit -
4780 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4781 "eeprom read at offset %d failed", offset);
4782 return IXGBE_NOT_IMPLEMENTED;
4787 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4788 * @hw: pointer to hardware structure
4789 * @map: pointer to u8 arr for returning map
4791 * Read the rtrup2tc HW register and resolve its content into map
4793 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4797 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4798 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4799 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4800 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4804 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4809 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4810 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4811 if (hw->mac.type != ixgbe_mac_82598EB) {
4812 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4813 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4814 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4815 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4816 hw->mac.set_lben = true;
4818 hw->mac.set_lben = false;
4821 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4822 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4826 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4831 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4832 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4834 if (hw->mac.type != ixgbe_mac_82598EB) {
4835 if (hw->mac.set_lben) {
4836 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4837 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4838 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4839 hw->mac.set_lben = false;
4845 * ixgbe_mng_enabled - Is the manageability engine enabled?
4846 * @hw: pointer to hardware structure
4848 * Returns true if the manageability engine is enabled.
4850 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
4852 u32 fwsm, manc, factps;
4854 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4855 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
4858 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
4859 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
4862 if (hw->mac.type <= ixgbe_mac_X540) {
4863 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
4864 if (factps & IXGBE_FACTPS_MNGCG)