1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
40 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
41 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
42 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
44 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
47 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
48 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
49 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
52 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
53 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
55 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
56 u16 words, u16 *data);
57 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
58 u16 words, u16 *data);
59 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
63 * ixgbe_init_ops_generic - Inits function ptrs
64 * @hw: pointer to the hardware structure
66 * Initialize the function pointers.
68 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
70 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
71 struct ixgbe_mac_info *mac = &hw->mac;
72 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
74 DEBUGFUNC("ixgbe_init_ops_generic");
77 eeprom->ops.init_params = ixgbe_init_eeprom_params_generic;
78 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
79 if (eec & IXGBE_EEC_PRES) {
80 eeprom->ops.read = ixgbe_read_eerd_generic;
81 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_generic;
83 eeprom->ops.read = ixgbe_read_eeprom_bit_bang_generic;
84 eeprom->ops.read_buffer =
85 ixgbe_read_eeprom_buffer_bit_bang_generic;
87 eeprom->ops.write = ixgbe_write_eeprom_generic;
88 eeprom->ops.write_buffer = ixgbe_write_eeprom_buffer_bit_bang_generic;
89 eeprom->ops.validate_checksum =
90 ixgbe_validate_eeprom_checksum_generic;
91 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_generic;
92 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_generic;
95 mac->ops.init_hw = ixgbe_init_hw_generic;
96 mac->ops.reset_hw = NULL;
97 mac->ops.start_hw = ixgbe_start_hw_generic;
98 mac->ops.clear_hw_cntrs = ixgbe_clear_hw_cntrs_generic;
99 mac->ops.get_media_type = NULL;
100 mac->ops.get_supported_physical_layer = NULL;
101 mac->ops.enable_rx_dma = ixgbe_enable_rx_dma_generic;
102 mac->ops.get_mac_addr = ixgbe_get_mac_addr_generic;
103 mac->ops.stop_adapter = ixgbe_stop_adapter_generic;
104 mac->ops.get_bus_info = ixgbe_get_bus_info_generic;
105 mac->ops.set_lan_id = ixgbe_set_lan_id_multi_port_pcie;
106 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync;
107 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync;
108 mac->ops.prot_autoc_read = prot_autoc_read_generic;
109 mac->ops.prot_autoc_write = prot_autoc_write_generic;
112 mac->ops.led_on = ixgbe_led_on_generic;
113 mac->ops.led_off = ixgbe_led_off_generic;
114 mac->ops.blink_led_start = ixgbe_blink_led_start_generic;
115 mac->ops.blink_led_stop = ixgbe_blink_led_stop_generic;
117 /* RAR, Multicast, VLAN */
118 mac->ops.set_rar = ixgbe_set_rar_generic;
119 mac->ops.clear_rar = ixgbe_clear_rar_generic;
120 mac->ops.insert_mac_addr = NULL;
121 mac->ops.set_vmdq = NULL;
122 mac->ops.clear_vmdq = NULL;
123 mac->ops.init_rx_addrs = ixgbe_init_rx_addrs_generic;
124 mac->ops.update_uc_addr_list = ixgbe_update_uc_addr_list_generic;
125 mac->ops.update_mc_addr_list = ixgbe_update_mc_addr_list_generic;
126 mac->ops.enable_mc = ixgbe_enable_mc_generic;
127 mac->ops.disable_mc = ixgbe_disable_mc_generic;
128 mac->ops.clear_vfta = NULL;
129 mac->ops.set_vfta = NULL;
130 mac->ops.set_vlvf = NULL;
131 mac->ops.init_uta_tables = NULL;
132 mac->ops.enable_rx = ixgbe_enable_rx_generic;
133 mac->ops.disable_rx = ixgbe_disable_rx_generic;
136 mac->ops.fc_enable = ixgbe_fc_enable_generic;
139 mac->ops.get_link_capabilities = NULL;
140 mac->ops.setup_link = NULL;
141 mac->ops.check_link = NULL;
142 mac->ops.dmac_config = NULL;
143 mac->ops.dmac_update_tcs = NULL;
144 mac->ops.dmac_config_tcs = NULL;
146 return IXGBE_SUCCESS;
150 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
152 * @hw: pointer to hardware structure
154 * This function returns true if the device supports flow control
155 * autonegotiation, and false if it does not.
158 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
160 bool supported = false;
161 ixgbe_link_speed speed;
164 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
166 switch (hw->phy.media_type) {
167 case ixgbe_media_type_fiber_qsfp:
168 case ixgbe_media_type_fiber:
169 hw->mac.ops.check_link(hw, &speed, &link_up, false);
170 /* if link is down, assume supported */
172 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
177 case ixgbe_media_type_backplane:
180 case ixgbe_media_type_copper:
181 /* only some copper devices support flow control autoneg */
182 switch (hw->device_id) {
183 case IXGBE_DEV_ID_82599_T3_LOM:
184 case IXGBE_DEV_ID_X540T:
185 case IXGBE_DEV_ID_X540T1:
186 case IXGBE_DEV_ID_X550T:
196 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
197 "Device %x does not support flow control autoneg",
203 * ixgbe_setup_fc - Set up flow control
204 * @hw: pointer to hardware structure
206 * Called at init time to set up flow control.
208 STATIC s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
210 s32 ret_val = IXGBE_SUCCESS;
211 u32 reg = 0, reg_bp = 0;
215 DEBUGFUNC("ixgbe_setup_fc");
217 /* Validate the requested mode */
218 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
219 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
220 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
221 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
226 * 10gig parts do not have a word in the EEPROM to determine the
227 * default flow control setting, so we explicitly set it to full.
229 if (hw->fc.requested_mode == ixgbe_fc_default)
230 hw->fc.requested_mode = ixgbe_fc_full;
233 * Set up the 1G and 10G flow control advertisement registers so the
234 * HW will be able to do fc autoneg once the cable is plugged in. If
235 * we link at 10G, the 1G advertisement is harmless and vice versa.
237 switch (hw->phy.media_type) {
238 case ixgbe_media_type_backplane:
239 /* some MAC's need RMW protection on AUTOC */
240 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
241 if (ret_val != IXGBE_SUCCESS)
244 /* only backplane uses autoc so fall though */
245 case ixgbe_media_type_fiber_qsfp:
246 case ixgbe_media_type_fiber:
247 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
250 case ixgbe_media_type_copper:
251 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
252 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
259 * The possible values of fc.requested_mode are:
260 * 0: Flow control is completely disabled
261 * 1: Rx flow control is enabled (we can receive pause frames,
262 * but not send pause frames).
263 * 2: Tx flow control is enabled (we can send pause frames but
264 * we do not support receiving pause frames).
265 * 3: Both Rx and Tx flow control (symmetric) are enabled.
268 switch (hw->fc.requested_mode) {
270 /* Flow control completely disabled by software override. */
271 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
272 if (hw->phy.media_type == ixgbe_media_type_backplane)
273 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
274 IXGBE_AUTOC_ASM_PAUSE);
275 else if (hw->phy.media_type == ixgbe_media_type_copper)
276 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
278 case ixgbe_fc_tx_pause:
280 * Tx Flow control is enabled, and Rx Flow control is
281 * disabled by software override.
283 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
284 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
285 if (hw->phy.media_type == ixgbe_media_type_backplane) {
286 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
287 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
288 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
289 reg_cu |= IXGBE_TAF_ASM_PAUSE;
290 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
293 case ixgbe_fc_rx_pause:
295 * Rx Flow control is enabled and Tx Flow control is
296 * disabled by software override. Since there really
297 * isn't a way to advertise that we are capable of RX
298 * Pause ONLY, we will advertise that we support both
299 * symmetric and asymmetric Rx PAUSE, as such we fall
300 * through to the fc_full statement. Later, we will
301 * disable the adapter's ability to send PAUSE frames.
304 /* Flow control (both Rx and Tx) is enabled by SW override. */
305 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
306 if (hw->phy.media_type == ixgbe_media_type_backplane)
307 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
308 IXGBE_AUTOC_ASM_PAUSE;
309 else if (hw->phy.media_type == ixgbe_media_type_copper)
310 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
313 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
314 "Flow control param set incorrectly\n");
315 ret_val = IXGBE_ERR_CONFIG;
320 if (hw->mac.type < ixgbe_mac_X540) {
322 * Enable auto-negotiation between the MAC & PHY;
323 * the MAC will advertise clause 37 flow control.
325 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
326 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
328 /* Disable AN timeout */
329 if (hw->fc.strict_ieee)
330 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
332 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
333 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
337 * AUTOC restart handles negotiation of 1G and 10G on backplane
338 * and copper. There is no need to set the PCS1GCTL register.
341 if (hw->phy.media_type == ixgbe_media_type_backplane) {
342 reg_bp |= IXGBE_AUTOC_AN_RESTART;
343 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
346 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
347 (ixgbe_device_supports_autoneg_fc(hw))) {
348 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
349 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
352 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
358 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
359 * @hw: pointer to hardware structure
361 * Starts the hardware by filling the bus info structure and media type, clears
362 * all on chip counters, initializes receive address registers, multicast
363 * table, VLAN filter table, calls routine to set up link and flow control
364 * settings, and leaves transmit and receive units disabled and uninitialized
366 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
371 DEBUGFUNC("ixgbe_start_hw_generic");
373 /* Set the media type */
374 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
376 /* PHY ops initialization must be done in reset_hw() */
378 /* Clear the VLAN filter table */
379 hw->mac.ops.clear_vfta(hw);
381 /* Clear statistics registers */
382 hw->mac.ops.clear_hw_cntrs(hw);
384 /* Set No Snoop Disable */
385 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
386 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
387 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
388 IXGBE_WRITE_FLUSH(hw);
390 /* Setup flow control */
391 ret_val = ixgbe_setup_fc(hw);
392 if (ret_val != IXGBE_SUCCESS)
395 /* Clear adapter stopped flag */
396 hw->adapter_stopped = false;
403 * ixgbe_start_hw_gen2 - Init sequence for common device family
404 * @hw: pointer to hw structure
406 * Performs the init sequence common to the second generation
408 * Devices in the second generation:
412 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
417 /* Clear the rate limiters */
418 for (i = 0; i < hw->mac.max_tx_queues; i++) {
419 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
420 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
422 IXGBE_WRITE_FLUSH(hw);
424 /* Disable relaxed ordering */
425 for (i = 0; i < hw->mac.max_tx_queues; i++) {
426 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
427 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
428 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
431 for (i = 0; i < hw->mac.max_rx_queues; i++) {
432 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
433 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
434 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
435 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
438 return IXGBE_SUCCESS;
442 * ixgbe_init_hw_generic - Generic hardware initialization
443 * @hw: pointer to hardware structure
445 * Initialize the hardware by resetting the hardware, filling the bus info
446 * structure and media type, clears all on chip counters, initializes receive
447 * address registers, multicast table, VLAN filter table, calls routine to set
448 * up link and flow control settings, and leaves transmit and receive units
449 * disabled and uninitialized
451 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
455 DEBUGFUNC("ixgbe_init_hw_generic");
457 /* Reset the hardware */
458 status = hw->mac.ops.reset_hw(hw);
460 if (status == IXGBE_SUCCESS) {
462 status = hw->mac.ops.start_hw(hw);
469 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
470 * @hw: pointer to hardware structure
472 * Clears all hardware statistics counters by reading them from the hardware
473 * Statistics counters are clear on read.
475 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
479 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
481 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
482 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
483 IXGBE_READ_REG(hw, IXGBE_ERRBC);
484 IXGBE_READ_REG(hw, IXGBE_MSPDC);
485 for (i = 0; i < 8; i++)
486 IXGBE_READ_REG(hw, IXGBE_MPC(i));
488 IXGBE_READ_REG(hw, IXGBE_MLFC);
489 IXGBE_READ_REG(hw, IXGBE_MRFC);
490 IXGBE_READ_REG(hw, IXGBE_RLEC);
491 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
492 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
493 if (hw->mac.type >= ixgbe_mac_82599EB) {
494 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
495 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
497 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
498 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
501 for (i = 0; i < 8; i++) {
502 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
503 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
504 if (hw->mac.type >= ixgbe_mac_82599EB) {
505 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
506 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
508 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
509 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
512 if (hw->mac.type >= ixgbe_mac_82599EB)
513 for (i = 0; i < 8; i++)
514 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
515 IXGBE_READ_REG(hw, IXGBE_PRC64);
516 IXGBE_READ_REG(hw, IXGBE_PRC127);
517 IXGBE_READ_REG(hw, IXGBE_PRC255);
518 IXGBE_READ_REG(hw, IXGBE_PRC511);
519 IXGBE_READ_REG(hw, IXGBE_PRC1023);
520 IXGBE_READ_REG(hw, IXGBE_PRC1522);
521 IXGBE_READ_REG(hw, IXGBE_GPRC);
522 IXGBE_READ_REG(hw, IXGBE_BPRC);
523 IXGBE_READ_REG(hw, IXGBE_MPRC);
524 IXGBE_READ_REG(hw, IXGBE_GPTC);
525 IXGBE_READ_REG(hw, IXGBE_GORCL);
526 IXGBE_READ_REG(hw, IXGBE_GORCH);
527 IXGBE_READ_REG(hw, IXGBE_GOTCL);
528 IXGBE_READ_REG(hw, IXGBE_GOTCH);
529 if (hw->mac.type == ixgbe_mac_82598EB)
530 for (i = 0; i < 8; i++)
531 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
532 IXGBE_READ_REG(hw, IXGBE_RUC);
533 IXGBE_READ_REG(hw, IXGBE_RFC);
534 IXGBE_READ_REG(hw, IXGBE_ROC);
535 IXGBE_READ_REG(hw, IXGBE_RJC);
536 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
537 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
538 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
539 IXGBE_READ_REG(hw, IXGBE_TORL);
540 IXGBE_READ_REG(hw, IXGBE_TORH);
541 IXGBE_READ_REG(hw, IXGBE_TPR);
542 IXGBE_READ_REG(hw, IXGBE_TPT);
543 IXGBE_READ_REG(hw, IXGBE_PTC64);
544 IXGBE_READ_REG(hw, IXGBE_PTC127);
545 IXGBE_READ_REG(hw, IXGBE_PTC255);
546 IXGBE_READ_REG(hw, IXGBE_PTC511);
547 IXGBE_READ_REG(hw, IXGBE_PTC1023);
548 IXGBE_READ_REG(hw, IXGBE_PTC1522);
549 IXGBE_READ_REG(hw, IXGBE_MPTC);
550 IXGBE_READ_REG(hw, IXGBE_BPTC);
551 for (i = 0; i < 16; i++) {
552 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
553 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
554 if (hw->mac.type >= ixgbe_mac_82599EB) {
555 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
556 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
557 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
558 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
559 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
561 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
562 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
566 if (hw->mac.type == ixgbe_mac_X550 || hw->mac.type == ixgbe_mac_X540) {
568 ixgbe_identify_phy(hw);
569 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
570 IXGBE_MDIO_PCS_DEV_TYPE, &i);
571 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
572 IXGBE_MDIO_PCS_DEV_TYPE, &i);
573 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
574 IXGBE_MDIO_PCS_DEV_TYPE, &i);
575 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
576 IXGBE_MDIO_PCS_DEV_TYPE, &i);
579 return IXGBE_SUCCESS;
583 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
584 * @hw: pointer to hardware structure
585 * @pba_num: stores the part number string from the EEPROM
586 * @pba_num_size: part number string buffer length
588 * Reads the part number string from the EEPROM.
590 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
599 DEBUGFUNC("ixgbe_read_pba_string_generic");
601 if (pba_num == NULL) {
602 DEBUGOUT("PBA string buffer was null\n");
603 return IXGBE_ERR_INVALID_ARGUMENT;
606 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
608 DEBUGOUT("NVM Read Error\n");
612 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
614 DEBUGOUT("NVM Read Error\n");
619 * if data is not ptr guard the PBA must be in legacy format which
620 * means pba_ptr is actually our second data word for the PBA number
621 * and we can decode it into an ascii string
623 if (data != IXGBE_PBANUM_PTR_GUARD) {
624 DEBUGOUT("NVM PBA number is not stored as string\n");
626 /* we will need 11 characters to store the PBA */
627 if (pba_num_size < 11) {
628 DEBUGOUT("PBA string buffer too small\n");
629 return IXGBE_ERR_NO_SPACE;
632 /* extract hex string from data and pba_ptr */
633 pba_num[0] = (data >> 12) & 0xF;
634 pba_num[1] = (data >> 8) & 0xF;
635 pba_num[2] = (data >> 4) & 0xF;
636 pba_num[3] = data & 0xF;
637 pba_num[4] = (pba_ptr >> 12) & 0xF;
638 pba_num[5] = (pba_ptr >> 8) & 0xF;
641 pba_num[8] = (pba_ptr >> 4) & 0xF;
642 pba_num[9] = pba_ptr & 0xF;
644 /* put a null character on the end of our string */
647 /* switch all the data but the '-' to hex char */
648 for (offset = 0; offset < 10; offset++) {
649 if (pba_num[offset] < 0xA)
650 pba_num[offset] += '0';
651 else if (pba_num[offset] < 0x10)
652 pba_num[offset] += 'A' - 0xA;
655 return IXGBE_SUCCESS;
658 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
660 DEBUGOUT("NVM Read Error\n");
664 if (length == 0xFFFF || length == 0) {
665 DEBUGOUT("NVM PBA number section invalid length\n");
666 return IXGBE_ERR_PBA_SECTION;
669 /* check if pba_num buffer is big enough */
670 if (pba_num_size < (((u32)length * 2) - 1)) {
671 DEBUGOUT("PBA string buffer too small\n");
672 return IXGBE_ERR_NO_SPACE;
675 /* trim pba length from start of string */
679 for (offset = 0; offset < length; offset++) {
680 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
682 DEBUGOUT("NVM Read Error\n");
685 pba_num[offset * 2] = (u8)(data >> 8);
686 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
688 pba_num[offset * 2] = '\0';
690 return IXGBE_SUCCESS;
694 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
695 * @hw: pointer to hardware structure
696 * @pba_num: stores the part number from the EEPROM
698 * Reads the part number from the EEPROM.
700 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
705 DEBUGFUNC("ixgbe_read_pba_num_generic");
707 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
709 DEBUGOUT("NVM Read Error\n");
711 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
712 DEBUGOUT("NVM Not supported\n");
713 return IXGBE_NOT_IMPLEMENTED;
715 *pba_num = (u32)(data << 16);
717 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
719 DEBUGOUT("NVM Read Error\n");
724 return IXGBE_SUCCESS;
729 * @hw: pointer to the HW structure
730 * @eeprom_buf: optional pointer to EEPROM image
731 * @eeprom_buf_size: size of EEPROM image in words
732 * @max_pba_block_size: PBA block size limit
733 * @pba: pointer to output PBA structure
735 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
736 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
739 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
740 u32 eeprom_buf_size, u16 max_pba_block_size,
741 struct ixgbe_pba *pba)
747 return IXGBE_ERR_PARAM;
749 if (eeprom_buf == NULL) {
750 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
755 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
756 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
757 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
759 return IXGBE_ERR_PARAM;
763 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
764 if (pba->pba_block == NULL)
765 return IXGBE_ERR_PARAM;
767 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
773 if (pba_block_size > max_pba_block_size)
774 return IXGBE_ERR_PARAM;
776 if (eeprom_buf == NULL) {
777 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
783 if (eeprom_buf_size > (u32)(pba->word[1] +
785 memcpy(pba->pba_block,
786 &eeprom_buf[pba->word[1]],
787 pba_block_size * sizeof(u16));
789 return IXGBE_ERR_PARAM;
794 return IXGBE_SUCCESS;
798 * ixgbe_write_pba_raw
799 * @hw: pointer to the HW structure
800 * @eeprom_buf: optional pointer to EEPROM image
801 * @eeprom_buf_size: size of EEPROM image in words
802 * @pba: pointer to PBA structure
804 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
805 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
808 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
809 u32 eeprom_buf_size, struct ixgbe_pba *pba)
814 return IXGBE_ERR_PARAM;
816 if (eeprom_buf == NULL) {
817 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
822 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
823 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
824 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
826 return IXGBE_ERR_PARAM;
830 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
831 if (pba->pba_block == NULL)
832 return IXGBE_ERR_PARAM;
834 if (eeprom_buf == NULL) {
835 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
841 if (eeprom_buf_size > (u32)(pba->word[1] +
842 pba->pba_block[0])) {
843 memcpy(&eeprom_buf[pba->word[1]],
845 pba->pba_block[0] * sizeof(u16));
847 return IXGBE_ERR_PARAM;
852 return IXGBE_SUCCESS;
856 * ixgbe_get_pba_block_size
857 * @hw: pointer to the HW structure
858 * @eeprom_buf: optional pointer to EEPROM image
859 * @eeprom_buf_size: size of EEPROM image in words
860 * @pba_data_size: pointer to output variable
862 * Returns the size of the PBA block in words. Function operates on EEPROM
863 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
867 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
868 u32 eeprom_buf_size, u16 *pba_block_size)
874 DEBUGFUNC("ixgbe_get_pba_block_size");
876 if (eeprom_buf == NULL) {
877 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
882 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
883 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
884 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
886 return IXGBE_ERR_PARAM;
890 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
891 if (eeprom_buf == NULL) {
892 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
897 if (eeprom_buf_size > pba_word[1])
898 length = eeprom_buf[pba_word[1] + 0];
900 return IXGBE_ERR_PARAM;
903 if (length == 0xFFFF || length == 0)
904 return IXGBE_ERR_PBA_SECTION;
906 /* PBA number in legacy format, there is no PBA Block. */
910 if (pba_block_size != NULL)
911 *pba_block_size = length;
913 return IXGBE_SUCCESS;
917 * ixgbe_get_mac_addr_generic - Generic get MAC address
918 * @hw: pointer to hardware structure
919 * @mac_addr: Adapter MAC address
921 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
922 * A reset of the adapter must be performed prior to calling this function
923 * in order for the MAC address to have been loaded from the EEPROM into RAR0
925 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
931 DEBUGFUNC("ixgbe_get_mac_addr_generic");
933 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
934 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
936 for (i = 0; i < 4; i++)
937 mac_addr[i] = (u8)(rar_low >> (i*8));
939 for (i = 0; i < 2; i++)
940 mac_addr[i+4] = (u8)(rar_high >> (i*8));
942 return IXGBE_SUCCESS;
946 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
947 * @hw: pointer to hardware structure
948 * @link_status: the link status returned by the PCI config space
950 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
952 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
954 struct ixgbe_mac_info *mac = &hw->mac;
956 if (hw->bus.type == ixgbe_bus_type_unknown)
957 hw->bus.type = ixgbe_bus_type_pci_express;
959 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
960 case IXGBE_PCI_LINK_WIDTH_1:
961 hw->bus.width = ixgbe_bus_width_pcie_x1;
963 case IXGBE_PCI_LINK_WIDTH_2:
964 hw->bus.width = ixgbe_bus_width_pcie_x2;
966 case IXGBE_PCI_LINK_WIDTH_4:
967 hw->bus.width = ixgbe_bus_width_pcie_x4;
969 case IXGBE_PCI_LINK_WIDTH_8:
970 hw->bus.width = ixgbe_bus_width_pcie_x8;
973 hw->bus.width = ixgbe_bus_width_unknown;
977 switch (link_status & IXGBE_PCI_LINK_SPEED) {
978 case IXGBE_PCI_LINK_SPEED_2500:
979 hw->bus.speed = ixgbe_bus_speed_2500;
981 case IXGBE_PCI_LINK_SPEED_5000:
982 hw->bus.speed = ixgbe_bus_speed_5000;
984 case IXGBE_PCI_LINK_SPEED_8000:
985 hw->bus.speed = ixgbe_bus_speed_8000;
988 hw->bus.speed = ixgbe_bus_speed_unknown;
992 mac->ops.set_lan_id(hw);
996 * ixgbe_get_bus_info_generic - Generic set PCI bus info
997 * @hw: pointer to hardware structure
999 * Gets the PCI bus info (speed, width, type) then calls helper function to
1000 * store this data within the ixgbe_hw structure.
1002 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1006 DEBUGFUNC("ixgbe_get_bus_info_generic");
1008 /* Get the negotiated link width and speed from PCI config space */
1009 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1011 ixgbe_set_pci_config_data_generic(hw, link_status);
1013 return IXGBE_SUCCESS;
1017 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1018 * @hw: pointer to the HW structure
1020 * Determines the LAN function id by reading memory-mapped registers
1021 * and swaps the port value if requested.
1023 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1025 struct ixgbe_bus_info *bus = &hw->bus;
1028 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1030 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1031 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1032 bus->lan_id = bus->func;
1034 /* check for a port swap */
1035 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
1036 if (reg & IXGBE_FACTPS_LFS)
1041 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1042 * @hw: pointer to hardware structure
1044 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1045 * disables transmit and receive units. The adapter_stopped flag is used by
1046 * the shared code and drivers to determine if the adapter is in a stopped
1047 * state and should not touch the hardware.
1049 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1054 DEBUGFUNC("ixgbe_stop_adapter_generic");
1057 * Set the adapter_stopped flag so other driver functions stop touching
1060 hw->adapter_stopped = true;
1062 /* Disable the receive unit */
1063 ixgbe_disable_rx(hw);
1065 /* Clear interrupt mask to stop interrupts from being generated */
1066 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1068 /* Clear any pending interrupts, flush previous writes */
1069 IXGBE_READ_REG(hw, IXGBE_EICR);
1071 /* Disable the transmit unit. Each queue must be disabled. */
1072 for (i = 0; i < hw->mac.max_tx_queues; i++)
1073 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1075 /* Disable the receive unit by stopping each queue */
1076 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1077 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1078 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1079 reg_val |= IXGBE_RXDCTL_SWFLSH;
1080 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1083 /* flush all queues disables */
1084 IXGBE_WRITE_FLUSH(hw);
1088 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
1089 * access and verify no pending requests
1091 return ixgbe_disable_pcie_master(hw);
1095 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1096 * @hw: pointer to hardware structure
1097 * @index: led number to turn on
1099 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1101 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1103 DEBUGFUNC("ixgbe_led_on_generic");
1105 /* To turn on the LED, set mode to ON. */
1106 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1107 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1108 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1109 IXGBE_WRITE_FLUSH(hw);
1111 return IXGBE_SUCCESS;
1115 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1116 * @hw: pointer to hardware structure
1117 * @index: led number to turn off
1119 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1121 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1123 DEBUGFUNC("ixgbe_led_off_generic");
1125 /* To turn off the LED, set mode to OFF. */
1126 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1127 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1128 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1129 IXGBE_WRITE_FLUSH(hw);
1131 return IXGBE_SUCCESS;
1135 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1136 * @hw: pointer to hardware structure
1138 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1139 * ixgbe_hw struct in order to set up EEPROM access.
1141 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1143 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1147 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1149 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1150 eeprom->type = ixgbe_eeprom_none;
1151 /* Set default semaphore delay to 10ms which is a well
1153 eeprom->semaphore_delay = 10;
1154 /* Clear EEPROM page size, it will be initialized as needed */
1155 eeprom->word_page_size = 0;
1158 * Check for EEPROM present first.
1159 * If not present leave as none
1161 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1162 if (eec & IXGBE_EEC_PRES) {
1163 eeprom->type = ixgbe_eeprom_spi;
1166 * SPI EEPROM is assumed here. This code would need to
1167 * change if a future EEPROM is not SPI.
1169 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1170 IXGBE_EEC_SIZE_SHIFT);
1171 eeprom->word_size = 1 << (eeprom_size +
1172 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1175 if (eec & IXGBE_EEC_ADDR_SIZE)
1176 eeprom->address_bits = 16;
1178 eeprom->address_bits = 8;
1179 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1180 "%d\n", eeprom->type, eeprom->word_size,
1181 eeprom->address_bits);
1184 return IXGBE_SUCCESS;
1188 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1189 * @hw: pointer to hardware structure
1190 * @offset: offset within the EEPROM to write
1191 * @words: number of word(s)
1192 * @data: 16 bit word(s) to write to EEPROM
1194 * Reads 16 bit word(s) from EEPROM through bit-bang method
1196 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1197 u16 words, u16 *data)
1199 s32 status = IXGBE_SUCCESS;
1202 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1204 hw->eeprom.ops.init_params(hw);
1207 status = IXGBE_ERR_INVALID_ARGUMENT;
1211 if (offset + words > hw->eeprom.word_size) {
1212 status = IXGBE_ERR_EEPROM;
1217 * The EEPROM page size cannot be queried from the chip. We do lazy
1218 * initialization. It is worth to do that when we write large buffer.
1220 if ((hw->eeprom.word_page_size == 0) &&
1221 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1222 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1225 * We cannot hold synchronization semaphores for too long
1226 * to avoid other entity starvation. However it is more efficient
1227 * to read in bursts than synchronizing access for each word.
1229 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1230 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1231 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1232 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1235 if (status != IXGBE_SUCCESS)
1244 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1245 * @hw: pointer to hardware structure
1246 * @offset: offset within the EEPROM to be written to
1247 * @words: number of word(s)
1248 * @data: 16 bit word(s) to be written to the EEPROM
1250 * If ixgbe_eeprom_update_checksum is not called after this function, the
1251 * EEPROM will most likely contain an invalid checksum.
1253 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1254 u16 words, u16 *data)
1260 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1262 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1264 /* Prepare the EEPROM for writing */
1265 status = ixgbe_acquire_eeprom(hw);
1267 if (status == IXGBE_SUCCESS) {
1268 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1269 ixgbe_release_eeprom(hw);
1270 status = IXGBE_ERR_EEPROM;
1274 if (status == IXGBE_SUCCESS) {
1275 for (i = 0; i < words; i++) {
1276 ixgbe_standby_eeprom(hw);
1278 /* Send the WRITE ENABLE command (8 bit opcode ) */
1279 ixgbe_shift_out_eeprom_bits(hw,
1280 IXGBE_EEPROM_WREN_OPCODE_SPI,
1281 IXGBE_EEPROM_OPCODE_BITS);
1283 ixgbe_standby_eeprom(hw);
1286 * Some SPI eeproms use the 8th address bit embedded
1289 if ((hw->eeprom.address_bits == 8) &&
1290 ((offset + i) >= 128))
1291 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1293 /* Send the Write command (8-bit opcode + addr) */
1294 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1295 IXGBE_EEPROM_OPCODE_BITS);
1296 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1297 hw->eeprom.address_bits);
1299 page_size = hw->eeprom.word_page_size;
1301 /* Send the data in burst via SPI*/
1304 word = (word >> 8) | (word << 8);
1305 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1310 /* do not wrap around page */
1311 if (((offset + i) & (page_size - 1)) ==
1314 } while (++i < words);
1316 ixgbe_standby_eeprom(hw);
1319 /* Done with writing - release the EEPROM */
1320 ixgbe_release_eeprom(hw);
1327 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1328 * @hw: pointer to hardware structure
1329 * @offset: offset within the EEPROM to be written to
1330 * @data: 16 bit word to be written to the EEPROM
1332 * If ixgbe_eeprom_update_checksum is not called after this function, the
1333 * EEPROM will most likely contain an invalid checksum.
1335 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1339 DEBUGFUNC("ixgbe_write_eeprom_generic");
1341 hw->eeprom.ops.init_params(hw);
1343 if (offset >= hw->eeprom.word_size) {
1344 status = IXGBE_ERR_EEPROM;
1348 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1355 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1356 * @hw: pointer to hardware structure
1357 * @offset: offset within the EEPROM to be read
1358 * @data: read 16 bit words(s) from EEPROM
1359 * @words: number of word(s)
1361 * Reads 16 bit word(s) from EEPROM through bit-bang method
1363 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1364 u16 words, u16 *data)
1366 s32 status = IXGBE_SUCCESS;
1369 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1371 hw->eeprom.ops.init_params(hw);
1374 status = IXGBE_ERR_INVALID_ARGUMENT;
1378 if (offset + words > hw->eeprom.word_size) {
1379 status = IXGBE_ERR_EEPROM;
1384 * We cannot hold synchronization semaphores for too long
1385 * to avoid other entity starvation. However it is more efficient
1386 * to read in bursts than synchronizing access for each word.
1388 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1389 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1390 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1392 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1395 if (status != IXGBE_SUCCESS)
1404 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1405 * @hw: pointer to hardware structure
1406 * @offset: offset within the EEPROM to be read
1407 * @words: number of word(s)
1408 * @data: read 16 bit word(s) from EEPROM
1410 * Reads 16 bit word(s) from EEPROM through bit-bang method
1412 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1413 u16 words, u16 *data)
1417 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1420 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1422 /* Prepare the EEPROM for reading */
1423 status = ixgbe_acquire_eeprom(hw);
1425 if (status == IXGBE_SUCCESS) {
1426 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1427 ixgbe_release_eeprom(hw);
1428 status = IXGBE_ERR_EEPROM;
1432 if (status == IXGBE_SUCCESS) {
1433 for (i = 0; i < words; i++) {
1434 ixgbe_standby_eeprom(hw);
1436 * Some SPI eeproms use the 8th address bit embedded
1439 if ((hw->eeprom.address_bits == 8) &&
1440 ((offset + i) >= 128))
1441 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1443 /* Send the READ command (opcode + addr) */
1444 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1445 IXGBE_EEPROM_OPCODE_BITS);
1446 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1447 hw->eeprom.address_bits);
1449 /* Read the data. */
1450 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1451 data[i] = (word_in >> 8) | (word_in << 8);
1454 /* End this read operation */
1455 ixgbe_release_eeprom(hw);
1462 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1463 * @hw: pointer to hardware structure
1464 * @offset: offset within the EEPROM to be read
1465 * @data: read 16 bit value from EEPROM
1467 * Reads 16 bit value from EEPROM through bit-bang method
1469 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1474 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1476 hw->eeprom.ops.init_params(hw);
1478 if (offset >= hw->eeprom.word_size) {
1479 status = IXGBE_ERR_EEPROM;
1483 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1490 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1491 * @hw: pointer to hardware structure
1492 * @offset: offset of word in the EEPROM to read
1493 * @words: number of word(s)
1494 * @data: 16 bit word(s) from the EEPROM
1496 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1498 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1499 u16 words, u16 *data)
1502 s32 status = IXGBE_SUCCESS;
1505 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1507 hw->eeprom.ops.init_params(hw);
1510 status = IXGBE_ERR_INVALID_ARGUMENT;
1511 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1515 if (offset >= hw->eeprom.word_size) {
1516 status = IXGBE_ERR_EEPROM;
1517 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1521 for (i = 0; i < words; i++) {
1522 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1523 IXGBE_EEPROM_RW_REG_START;
1525 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1526 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1528 if (status == IXGBE_SUCCESS) {
1529 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1530 IXGBE_EEPROM_RW_REG_DATA);
1532 DEBUGOUT("Eeprom read timed out\n");
1541 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1542 * @hw: pointer to hardware structure
1543 * @offset: offset within the EEPROM to be used as a scratch pad
1545 * Discover EEPROM page size by writing marching data at given offset.
1546 * This function is called only when we are writing a new large buffer
1547 * at given offset so the data would be overwritten anyway.
1549 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1552 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1553 s32 status = IXGBE_SUCCESS;
1556 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1558 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1561 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1562 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1563 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1564 hw->eeprom.word_page_size = 0;
1565 if (status != IXGBE_SUCCESS)
1568 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1569 if (status != IXGBE_SUCCESS)
1573 * When writing in burst more than the actual page size
1574 * EEPROM address wraps around current page.
1576 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1578 DEBUGOUT1("Detected EEPROM page size = %d words.",
1579 hw->eeprom.word_page_size);
1585 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1586 * @hw: pointer to hardware structure
1587 * @offset: offset of word in the EEPROM to read
1588 * @data: word read from the EEPROM
1590 * Reads a 16 bit word from the EEPROM using the EERD register.
1592 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1594 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1598 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1599 * @hw: pointer to hardware structure
1600 * @offset: offset of word in the EEPROM to write
1601 * @words: number of word(s)
1602 * @data: word(s) write to the EEPROM
1604 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1606 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1607 u16 words, u16 *data)
1610 s32 status = IXGBE_SUCCESS;
1613 DEBUGFUNC("ixgbe_write_eewr_generic");
1615 hw->eeprom.ops.init_params(hw);
1618 status = IXGBE_ERR_INVALID_ARGUMENT;
1619 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1623 if (offset >= hw->eeprom.word_size) {
1624 status = IXGBE_ERR_EEPROM;
1625 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1629 for (i = 0; i < words; i++) {
1630 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1631 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1632 IXGBE_EEPROM_RW_REG_START;
1634 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1635 if (status != IXGBE_SUCCESS) {
1636 DEBUGOUT("Eeprom write EEWR timed out\n");
1640 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1642 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1643 if (status != IXGBE_SUCCESS) {
1644 DEBUGOUT("Eeprom write EEWR timed out\n");
1654 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1655 * @hw: pointer to hardware structure
1656 * @offset: offset of word in the EEPROM to write
1657 * @data: word write to the EEPROM
1659 * Write a 16 bit word to the EEPROM using the EEWR register.
1661 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1663 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1667 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1668 * @hw: pointer to hardware structure
1669 * @ee_reg: EEPROM flag for polling
1671 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1672 * read or write is done respectively.
1674 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1678 s32 status = IXGBE_ERR_EEPROM;
1680 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1682 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1683 if (ee_reg == IXGBE_NVM_POLL_READ)
1684 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1686 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1688 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1689 status = IXGBE_SUCCESS;
1695 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1696 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1697 "EEPROM read/write done polling timed out");
1703 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1704 * @hw: pointer to hardware structure
1706 * Prepares EEPROM for access using bit-bang method. This function should
1707 * be called before issuing a command to the EEPROM.
1709 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1711 s32 status = IXGBE_SUCCESS;
1715 DEBUGFUNC("ixgbe_acquire_eeprom");
1717 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1719 status = IXGBE_ERR_SWFW_SYNC;
1721 if (status == IXGBE_SUCCESS) {
1722 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1724 /* Request EEPROM Access */
1725 eec |= IXGBE_EEC_REQ;
1726 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1728 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1729 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1730 if (eec & IXGBE_EEC_GNT)
1735 /* Release if grant not acquired */
1736 if (!(eec & IXGBE_EEC_GNT)) {
1737 eec &= ~IXGBE_EEC_REQ;
1738 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1739 DEBUGOUT("Could not acquire EEPROM grant\n");
1741 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1742 status = IXGBE_ERR_EEPROM;
1745 /* Setup EEPROM for Read/Write */
1746 if (status == IXGBE_SUCCESS) {
1747 /* Clear CS and SK */
1748 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1749 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1750 IXGBE_WRITE_FLUSH(hw);
1758 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1759 * @hw: pointer to hardware structure
1761 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1763 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1765 s32 status = IXGBE_ERR_EEPROM;
1770 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1773 /* Get SMBI software semaphore between device drivers first */
1774 for (i = 0; i < timeout; i++) {
1776 * If the SMBI bit is 0 when we read it, then the bit will be
1777 * set and we have the semaphore
1779 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1780 if (!(swsm & IXGBE_SWSM_SMBI)) {
1781 status = IXGBE_SUCCESS;
1788 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1791 * this release is particularly important because our attempts
1792 * above to get the semaphore may have succeeded, and if there
1793 * was a timeout, we should unconditionally clear the semaphore
1794 * bits to free the driver to make progress
1796 ixgbe_release_eeprom_semaphore(hw);
1801 * If the SMBI bit is 0 when we read it, then the bit will be
1802 * set and we have the semaphore
1804 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1805 if (!(swsm & IXGBE_SWSM_SMBI))
1806 status = IXGBE_SUCCESS;
1809 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1810 if (status == IXGBE_SUCCESS) {
1811 for (i = 0; i < timeout; i++) {
1812 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1814 /* Set the SW EEPROM semaphore bit to request access */
1815 swsm |= IXGBE_SWSM_SWESMBI;
1816 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1819 * If we set the bit successfully then we got the
1822 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1823 if (swsm & IXGBE_SWSM_SWESMBI)
1830 * Release semaphores and return error if SW EEPROM semaphore
1831 * was not granted because we don't have access to the EEPROM
1834 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1835 "SWESMBI Software EEPROM semaphore not granted.\n");
1836 ixgbe_release_eeprom_semaphore(hw);
1837 status = IXGBE_ERR_EEPROM;
1840 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1841 "Software semaphore SMBI between device drivers "
1849 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1850 * @hw: pointer to hardware structure
1852 * This function clears hardware semaphore bits.
1854 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1858 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1860 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1862 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1863 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1864 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1865 IXGBE_WRITE_FLUSH(hw);
1869 * ixgbe_ready_eeprom - Polls for EEPROM ready
1870 * @hw: pointer to hardware structure
1872 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1874 s32 status = IXGBE_SUCCESS;
1878 DEBUGFUNC("ixgbe_ready_eeprom");
1881 * Read "Status Register" repeatedly until the LSB is cleared. The
1882 * EEPROM will signal that the command has been completed by clearing
1883 * bit 0 of the internal status register. If it's not cleared within
1884 * 5 milliseconds, then error out.
1886 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1887 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1888 IXGBE_EEPROM_OPCODE_BITS);
1889 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1890 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1894 ixgbe_standby_eeprom(hw);
1898 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1899 * devices (and only 0-5mSec on 5V devices)
1901 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1902 DEBUGOUT("SPI EEPROM Status error\n");
1903 status = IXGBE_ERR_EEPROM;
1910 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1911 * @hw: pointer to hardware structure
1913 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1917 DEBUGFUNC("ixgbe_standby_eeprom");
1919 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1921 /* Toggle CS to flush commands */
1922 eec |= IXGBE_EEC_CS;
1923 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1924 IXGBE_WRITE_FLUSH(hw);
1926 eec &= ~IXGBE_EEC_CS;
1927 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1928 IXGBE_WRITE_FLUSH(hw);
1933 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1934 * @hw: pointer to hardware structure
1935 * @data: data to send to the EEPROM
1936 * @count: number of bits to shift out
1938 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1945 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1947 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1950 * Mask is used to shift "count" bits of "data" out to the EEPROM
1951 * one bit at a time. Determine the starting bit based on count
1953 mask = 0x01 << (count - 1);
1955 for (i = 0; i < count; i++) {
1957 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1958 * "1", and then raising and then lowering the clock (the SK
1959 * bit controls the clock input to the EEPROM). A "0" is
1960 * shifted out to the EEPROM by setting "DI" to "0" and then
1961 * raising and then lowering the clock.
1964 eec |= IXGBE_EEC_DI;
1966 eec &= ~IXGBE_EEC_DI;
1968 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1969 IXGBE_WRITE_FLUSH(hw);
1973 ixgbe_raise_eeprom_clk(hw, &eec);
1974 ixgbe_lower_eeprom_clk(hw, &eec);
1977 * Shift mask to signify next bit of data to shift in to the
1983 /* We leave the "DI" bit set to "0" when we leave this routine. */
1984 eec &= ~IXGBE_EEC_DI;
1985 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1986 IXGBE_WRITE_FLUSH(hw);
1990 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1991 * @hw: pointer to hardware structure
1993 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1999 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2002 * In order to read a register from the EEPROM, we need to shift
2003 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2004 * the clock input to the EEPROM (setting the SK bit), and then reading
2005 * the value of the "DO" bit. During this "shifting in" process the
2006 * "DI" bit should always be clear.
2008 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2010 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2012 for (i = 0; i < count; i++) {
2014 ixgbe_raise_eeprom_clk(hw, &eec);
2016 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2018 eec &= ~(IXGBE_EEC_DI);
2019 if (eec & IXGBE_EEC_DO)
2022 ixgbe_lower_eeprom_clk(hw, &eec);
2029 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2030 * @hw: pointer to hardware structure
2031 * @eec: EEC register's current value
2033 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2035 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2038 * Raise the clock input to the EEPROM
2039 * (setting the SK bit), then delay
2041 *eec = *eec | IXGBE_EEC_SK;
2042 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2043 IXGBE_WRITE_FLUSH(hw);
2048 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2049 * @hw: pointer to hardware structure
2050 * @eecd: EECD's current value
2052 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2054 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2057 * Lower the clock input to the EEPROM (clearing the SK bit), then
2060 *eec = *eec & ~IXGBE_EEC_SK;
2061 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2062 IXGBE_WRITE_FLUSH(hw);
2067 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2068 * @hw: pointer to hardware structure
2070 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2074 DEBUGFUNC("ixgbe_release_eeprom");
2076 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2078 eec |= IXGBE_EEC_CS; /* Pull CS high */
2079 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2081 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2082 IXGBE_WRITE_FLUSH(hw);
2086 /* Stop requesting EEPROM access */
2087 eec &= ~IXGBE_EEC_REQ;
2088 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2090 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2092 /* Delay before attempt to obtain semaphore again to allow FW access */
2093 msec_delay(hw->eeprom.semaphore_delay);
2097 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2098 * @hw: pointer to hardware structure
2100 * Returns a negative error code on error, or the 16-bit checksum
2102 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2111 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2113 /* Include 0x0-0x3F in the checksum */
2114 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2115 if (hw->eeprom.ops.read(hw, i, &word)) {
2116 DEBUGOUT("EEPROM read failed\n");
2117 return IXGBE_ERR_EEPROM;
2122 /* Include all data from pointers except for the fw pointer */
2123 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2124 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2125 DEBUGOUT("EEPROM read failed\n");
2126 return IXGBE_ERR_EEPROM;
2129 /* If the pointer seems invalid */
2130 if (pointer == 0xFFFF || pointer == 0)
2133 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2134 DEBUGOUT("EEPROM read failed\n");
2135 return IXGBE_ERR_EEPROM;
2138 if (length == 0xFFFF || length == 0)
2141 for (j = pointer + 1; j <= pointer + length; j++) {
2142 if (hw->eeprom.ops.read(hw, j, &word)) {
2143 DEBUGOUT("EEPROM read failed\n");
2144 return IXGBE_ERR_EEPROM;
2150 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2152 return (s32)checksum;
2156 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2157 * @hw: pointer to hardware structure
2158 * @checksum_val: calculated checksum
2160 * Performs checksum calculation and validates the EEPROM checksum. If the
2161 * caller does not need checksum_val, the value can be NULL.
2163 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2168 u16 read_checksum = 0;
2170 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2172 /* Read the first word from the EEPROM. If this times out or fails, do
2173 * not continue or we could be in for a very long wait while every
2176 status = hw->eeprom.ops.read(hw, 0, &checksum);
2178 DEBUGOUT("EEPROM read failed\n");
2182 status = hw->eeprom.ops.calc_checksum(hw);
2186 checksum = (u16)(status & 0xffff);
2188 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2190 DEBUGOUT("EEPROM read failed\n");
2194 /* Verify read checksum from EEPROM is the same as
2195 * calculated checksum
2197 if (read_checksum != checksum)
2198 status = IXGBE_ERR_EEPROM_CHECKSUM;
2200 /* If the user cares, return the calculated checksum */
2202 *checksum_val = checksum;
2208 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2209 * @hw: pointer to hardware structure
2211 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2216 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2218 /* Read the first word from the EEPROM. If this times out or fails, do
2219 * not continue or we could be in for a very long wait while every
2222 status = hw->eeprom.ops.read(hw, 0, &checksum);
2224 DEBUGOUT("EEPROM read failed\n");
2228 status = hw->eeprom.ops.calc_checksum(hw);
2232 checksum = (u16)(status & 0xffff);
2234 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2240 * ixgbe_validate_mac_addr - Validate MAC address
2241 * @mac_addr: pointer to MAC address.
2243 * Tests a MAC address to ensure it is a valid Individual Address
2245 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2247 s32 status = IXGBE_SUCCESS;
2249 DEBUGFUNC("ixgbe_validate_mac_addr");
2251 /* Make sure it is not a multicast address */
2252 if (IXGBE_IS_MULTICAST(mac_addr)) {
2253 DEBUGOUT("MAC address is multicast\n");
2254 status = IXGBE_ERR_INVALID_MAC_ADDR;
2255 /* Not a broadcast address */
2256 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2257 DEBUGOUT("MAC address is broadcast\n");
2258 status = IXGBE_ERR_INVALID_MAC_ADDR;
2259 /* Reject the zero address */
2260 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2261 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2262 DEBUGOUT("MAC address is all zeros\n");
2263 status = IXGBE_ERR_INVALID_MAC_ADDR;
2269 * ixgbe_set_rar_generic - Set Rx address register
2270 * @hw: pointer to hardware structure
2271 * @index: Receive address register to write
2272 * @addr: Address to put into receive address register
2273 * @vmdq: VMDq "set" or "pool" index
2274 * @enable_addr: set flag that address is active
2276 * Puts an ethernet address into a receive address register.
2278 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2281 u32 rar_low, rar_high;
2282 u32 rar_entries = hw->mac.num_rar_entries;
2284 DEBUGFUNC("ixgbe_set_rar_generic");
2286 /* Make sure we are using a valid rar index range */
2287 if (index >= rar_entries) {
2288 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2289 "RAR index %d is out of range.\n", index);
2290 return IXGBE_ERR_INVALID_ARGUMENT;
2293 /* setup VMDq pool selection before this RAR gets enabled */
2294 hw->mac.ops.set_vmdq(hw, index, vmdq);
2297 * HW expects these in little endian so we reverse the byte
2298 * order from network order (big endian) to little endian
2300 rar_low = ((u32)addr[0] |
2301 ((u32)addr[1] << 8) |
2302 ((u32)addr[2] << 16) |
2303 ((u32)addr[3] << 24));
2305 * Some parts put the VMDq setting in the extra RAH bits,
2306 * so save everything except the lower 16 bits that hold part
2307 * of the address and the address valid bit.
2309 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2310 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2311 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2313 if (enable_addr != 0)
2314 rar_high |= IXGBE_RAH_AV;
2316 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2317 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2319 return IXGBE_SUCCESS;
2323 * ixgbe_clear_rar_generic - Remove Rx address register
2324 * @hw: pointer to hardware structure
2325 * @index: Receive address register to write
2327 * Clears an ethernet address from a receive address register.
2329 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2332 u32 rar_entries = hw->mac.num_rar_entries;
2334 DEBUGFUNC("ixgbe_clear_rar_generic");
2336 /* Make sure we are using a valid rar index range */
2337 if (index >= rar_entries) {
2338 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2339 "RAR index %d is out of range.\n", index);
2340 return IXGBE_ERR_INVALID_ARGUMENT;
2344 * Some parts put the VMDq setting in the extra RAH bits,
2345 * so save everything except the lower 16 bits that hold part
2346 * of the address and the address valid bit.
2348 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2349 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2351 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2352 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2354 /* clear VMDq pool/queue selection for this RAR */
2355 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2357 return IXGBE_SUCCESS;
2361 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2362 * @hw: pointer to hardware structure
2364 * Places the MAC address in receive address register 0 and clears the rest
2365 * of the receive address registers. Clears the multicast table. Assumes
2366 * the receiver is in reset when the routine is called.
2368 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2371 u32 rar_entries = hw->mac.num_rar_entries;
2373 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2376 * If the current mac address is valid, assume it is a software override
2377 * to the permanent address.
2378 * Otherwise, use the permanent address from the eeprom.
2380 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2381 IXGBE_ERR_INVALID_MAC_ADDR) {
2382 /* Get the MAC address from the RAR0 for later reference */
2383 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2385 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2386 hw->mac.addr[0], hw->mac.addr[1],
2388 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2389 hw->mac.addr[4], hw->mac.addr[5]);
2391 /* Setup the receive address. */
2392 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2393 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2394 hw->mac.addr[0], hw->mac.addr[1],
2396 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2397 hw->mac.addr[4], hw->mac.addr[5]);
2399 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2401 /* clear VMDq pool/queue selection for RAR 0 */
2402 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2404 hw->addr_ctrl.overflow_promisc = 0;
2406 hw->addr_ctrl.rar_used_count = 1;
2408 /* Zero out the other receive addresses. */
2409 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2410 for (i = 1; i < rar_entries; i++) {
2411 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2412 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2416 hw->addr_ctrl.mta_in_use = 0;
2417 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2419 DEBUGOUT(" Clearing MTA\n");
2420 for (i = 0; i < hw->mac.mcft_size; i++)
2421 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2423 ixgbe_init_uta_tables(hw);
2425 return IXGBE_SUCCESS;
2429 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2430 * @hw: pointer to hardware structure
2431 * @addr: new address
2433 * Adds it to unused receive address register or goes into promiscuous mode.
2435 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2437 u32 rar_entries = hw->mac.num_rar_entries;
2440 DEBUGFUNC("ixgbe_add_uc_addr");
2442 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2443 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2446 * Place this address in the RAR if there is room,
2447 * else put the controller into promiscuous mode
2449 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2450 rar = hw->addr_ctrl.rar_used_count;
2451 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2452 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2453 hw->addr_ctrl.rar_used_count++;
2455 hw->addr_ctrl.overflow_promisc++;
2458 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2462 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2463 * @hw: pointer to hardware structure
2464 * @addr_list: the list of new addresses
2465 * @addr_count: number of addresses
2466 * @next: iterator function to walk the address list
2468 * The given list replaces any existing list. Clears the secondary addrs from
2469 * receive address registers. Uses unused receive address registers for the
2470 * first secondary addresses, and falls back to promiscuous mode as needed.
2472 * Drivers using secondary unicast addresses must set user_set_promisc when
2473 * manually putting the device into promiscuous mode.
2475 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2476 u32 addr_count, ixgbe_mc_addr_itr next)
2480 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2485 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2488 * Clear accounting of old secondary address list,
2489 * don't count RAR[0]
2491 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2492 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2493 hw->addr_ctrl.overflow_promisc = 0;
2495 /* Zero out the other receive addresses */
2496 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2497 for (i = 0; i < uc_addr_in_use; i++) {
2498 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2499 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2502 /* Add the new addresses */
2503 for (i = 0; i < addr_count; i++) {
2504 DEBUGOUT(" Adding the secondary addresses:\n");
2505 addr = next(hw, &addr_list, &vmdq);
2506 ixgbe_add_uc_addr(hw, addr, vmdq);
2509 if (hw->addr_ctrl.overflow_promisc) {
2510 /* enable promisc if not already in overflow or set by user */
2511 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2512 DEBUGOUT(" Entering address overflow promisc mode\n");
2513 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2514 fctrl |= IXGBE_FCTRL_UPE;
2515 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2518 /* only disable if set by overflow, not by user */
2519 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2520 DEBUGOUT(" Leaving address overflow promisc mode\n");
2521 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2522 fctrl &= ~IXGBE_FCTRL_UPE;
2523 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2527 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2528 return IXGBE_SUCCESS;
2532 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2533 * @hw: pointer to hardware structure
2534 * @mc_addr: the multicast address
2536 * Extracts the 12 bits, from a multicast address, to determine which
2537 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2538 * incoming rx multicast addresses, to determine the bit-vector to check in
2539 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2540 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2541 * to mc_filter_type.
2543 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2547 DEBUGFUNC("ixgbe_mta_vector");
2549 switch (hw->mac.mc_filter_type) {
2550 case 0: /* use bits [47:36] of the address */
2551 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2553 case 1: /* use bits [46:35] of the address */
2554 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2556 case 2: /* use bits [45:34] of the address */
2557 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2559 case 3: /* use bits [43:32] of the address */
2560 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2562 default: /* Invalid mc_filter_type */
2563 DEBUGOUT("MC filter type param set incorrectly\n");
2568 /* vector can only be 12-bits or boundary will be exceeded */
2574 * ixgbe_set_mta - Set bit-vector in multicast table
2575 * @hw: pointer to hardware structure
2576 * @hash_value: Multicast address hash value
2578 * Sets the bit-vector in the multicast table.
2580 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2586 DEBUGFUNC("ixgbe_set_mta");
2588 hw->addr_ctrl.mta_in_use++;
2590 vector = ixgbe_mta_vector(hw, mc_addr);
2591 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2594 * The MTA is a register array of 128 32-bit registers. It is treated
2595 * like an array of 4096 bits. We want to set bit
2596 * BitArray[vector_value]. So we figure out what register the bit is
2597 * in, read it, OR in the new bit, then write back the new value. The
2598 * register is determined by the upper 7 bits of the vector value and
2599 * the bit within that register are determined by the lower 5 bits of
2602 vector_reg = (vector >> 5) & 0x7F;
2603 vector_bit = vector & 0x1F;
2604 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2608 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2609 * @hw: pointer to hardware structure
2610 * @mc_addr_list: the list of new multicast addresses
2611 * @mc_addr_count: number of addresses
2612 * @next: iterator function to walk the multicast address list
2613 * @clear: flag, when set clears the table beforehand
2615 * When the clear flag is set, the given list replaces any existing list.
2616 * Hashes the given addresses into the multicast table.
2618 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2619 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2625 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2628 * Set the new number of MC addresses that we are being requested to
2631 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2632 hw->addr_ctrl.mta_in_use = 0;
2634 /* Clear mta_shadow */
2636 DEBUGOUT(" Clearing MTA\n");
2637 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2640 /* Update mta_shadow */
2641 for (i = 0; i < mc_addr_count; i++) {
2642 DEBUGOUT(" Adding the multicast addresses:\n");
2643 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2647 for (i = 0; i < hw->mac.mcft_size; i++)
2648 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2649 hw->mac.mta_shadow[i]);
2651 if (hw->addr_ctrl.mta_in_use > 0)
2652 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2653 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2655 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2656 return IXGBE_SUCCESS;
2660 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2661 * @hw: pointer to hardware structure
2663 * Enables multicast address in RAR and the use of the multicast hash table.
2665 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2667 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2669 DEBUGFUNC("ixgbe_enable_mc_generic");
2671 if (a->mta_in_use > 0)
2672 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2673 hw->mac.mc_filter_type);
2675 return IXGBE_SUCCESS;
2679 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2680 * @hw: pointer to hardware structure
2682 * Disables multicast address in RAR and the use of the multicast hash table.
2684 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2686 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2688 DEBUGFUNC("ixgbe_disable_mc_generic");
2690 if (a->mta_in_use > 0)
2691 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2693 return IXGBE_SUCCESS;
2697 * ixgbe_fc_enable_generic - Enable flow control
2698 * @hw: pointer to hardware structure
2700 * Enable flow control according to the current settings.
2702 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2704 s32 ret_val = IXGBE_SUCCESS;
2705 u32 mflcn_reg, fccfg_reg;
2710 DEBUGFUNC("ixgbe_fc_enable_generic");
2712 /* Validate the water mark configuration */
2713 if (!hw->fc.pause_time) {
2714 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2718 /* Low water mark of zero causes XOFF floods */
2719 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2720 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2721 hw->fc.high_water[i]) {
2722 if (!hw->fc.low_water[i] ||
2723 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2724 DEBUGOUT("Invalid water mark configuration\n");
2725 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2731 /* Negotiate the fc mode to use */
2732 ixgbe_fc_autoneg(hw);
2734 /* Disable any previous flow control settings */
2735 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2736 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2738 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2739 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2742 * The possible values of fc.current_mode are:
2743 * 0: Flow control is completely disabled
2744 * 1: Rx flow control is enabled (we can receive pause frames,
2745 * but not send pause frames).
2746 * 2: Tx flow control is enabled (we can send pause frames but
2747 * we do not support receiving pause frames).
2748 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2751 switch (hw->fc.current_mode) {
2754 * Flow control is disabled by software override or autoneg.
2755 * The code below will actually disable it in the HW.
2758 case ixgbe_fc_rx_pause:
2760 * Rx Flow control is enabled and Tx Flow control is
2761 * disabled by software override. Since there really
2762 * isn't a way to advertise that we are capable of RX
2763 * Pause ONLY, we will advertise that we support both
2764 * symmetric and asymmetric Rx PAUSE. Later, we will
2765 * disable the adapter's ability to send PAUSE frames.
2767 mflcn_reg |= IXGBE_MFLCN_RFCE;
2769 case ixgbe_fc_tx_pause:
2771 * Tx Flow control is enabled, and Rx Flow control is
2772 * disabled by software override.
2774 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2777 /* Flow control (both Rx and Tx) is enabled by SW override. */
2778 mflcn_reg |= IXGBE_MFLCN_RFCE;
2779 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2782 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2783 "Flow control param set incorrectly\n");
2784 ret_val = IXGBE_ERR_CONFIG;
2789 /* Set 802.3x based flow control settings. */
2790 mflcn_reg |= IXGBE_MFLCN_DPF;
2791 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2792 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2795 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2796 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2797 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2798 hw->fc.high_water[i]) {
2799 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2800 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2801 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2803 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2805 * In order to prevent Tx hangs when the internal Tx
2806 * switch is enabled we must set the high water mark
2807 * to the Rx packet buffer size - 24KB. This allows
2808 * the Tx switch to function even under heavy Rx
2811 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2814 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2817 /* Configure pause time (2 TCs per register) */
2818 reg = hw->fc.pause_time * 0x00010001;
2819 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2820 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2822 /* Configure flow control refresh threshold value */
2823 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2830 * ixgbe_negotiate_fc - Negotiate flow control
2831 * @hw: pointer to hardware structure
2832 * @adv_reg: flow control advertised settings
2833 * @lp_reg: link partner's flow control settings
2834 * @adv_sym: symmetric pause bit in advertisement
2835 * @adv_asm: asymmetric pause bit in advertisement
2836 * @lp_sym: symmetric pause bit in link partner advertisement
2837 * @lp_asm: asymmetric pause bit in link partner advertisement
2839 * Find the intersection between advertised settings and link partner's
2840 * advertised settings
2842 STATIC s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2843 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2845 if ((!(adv_reg)) || (!(lp_reg))) {
2846 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2847 "Local or link partner's advertised flow control "
2848 "settings are NULL. Local: %x, link partner: %x\n",
2850 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2853 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2855 * Now we need to check if the user selected Rx ONLY
2856 * of pause frames. In this case, we had to advertise
2857 * FULL flow control because we could not advertise RX
2858 * ONLY. Hence, we must now check to see if we need to
2859 * turn OFF the TRANSMISSION of PAUSE frames.
2861 if (hw->fc.requested_mode == ixgbe_fc_full) {
2862 hw->fc.current_mode = ixgbe_fc_full;
2863 DEBUGOUT("Flow Control = FULL.\n");
2865 hw->fc.current_mode = ixgbe_fc_rx_pause;
2866 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2868 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2869 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2870 hw->fc.current_mode = ixgbe_fc_tx_pause;
2871 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2872 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2873 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2874 hw->fc.current_mode = ixgbe_fc_rx_pause;
2875 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2877 hw->fc.current_mode = ixgbe_fc_none;
2878 DEBUGOUT("Flow Control = NONE.\n");
2880 return IXGBE_SUCCESS;
2884 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2885 * @hw: pointer to hardware structure
2887 * Enable flow control according on 1 gig fiber.
2889 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2891 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2892 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2895 * On multispeed fiber at 1g, bail out if
2896 * - link is up but AN did not complete, or if
2897 * - link is up and AN completed but timed out
2900 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2901 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2902 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2903 DEBUGOUT("Auto-Negotiation did not complete or timed out\n");
2907 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2908 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2910 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2911 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2912 IXGBE_PCS1GANA_ASM_PAUSE,
2913 IXGBE_PCS1GANA_SYM_PAUSE,
2914 IXGBE_PCS1GANA_ASM_PAUSE);
2921 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2922 * @hw: pointer to hardware structure
2924 * Enable flow control according to IEEE clause 37.
2926 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2928 u32 links2, anlp1_reg, autoc_reg, links;
2929 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2932 * On backplane, bail out if
2933 * - backplane autoneg was not completed, or if
2934 * - we are 82599 and link partner is not AN enabled
2936 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2937 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2938 DEBUGOUT("Auto-Negotiation did not complete\n");
2942 if (hw->mac.type == ixgbe_mac_82599EB) {
2943 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2944 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2945 DEBUGOUT("Link partner is not AN enabled\n");
2950 * Read the 10g AN autoc and LP ability registers and resolve
2951 * local flow control settings accordingly
2953 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2954 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2956 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2957 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2958 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2965 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2966 * @hw: pointer to hardware structure
2968 * Enable flow control according to IEEE clause 37.
2970 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2972 u16 technology_ability_reg = 0;
2973 u16 lp_technology_ability_reg = 0;
2975 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2976 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2977 &technology_ability_reg);
2978 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2979 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2980 &lp_technology_ability_reg);
2982 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2983 (u32)lp_technology_ability_reg,
2984 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2985 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2989 * ixgbe_fc_autoneg - Configure flow control
2990 * @hw: pointer to hardware structure
2992 * Compares our advertised flow control capabilities to those advertised by
2993 * our link partner, and determines the proper flow control mode to use.
2995 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2997 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2998 ixgbe_link_speed speed;
3001 DEBUGFUNC("ixgbe_fc_autoneg");
3004 * AN should have completed when the cable was plugged in.
3005 * Look for reasons to bail out. Bail out if:
3006 * - FC autoneg is disabled, or if
3009 if (hw->fc.disable_fc_autoneg) {
3010 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3011 "Flow control autoneg is disabled");
3015 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3017 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3021 switch (hw->phy.media_type) {
3022 /* Autoneg flow control on fiber adapters */
3023 case ixgbe_media_type_fiber_qsfp:
3024 case ixgbe_media_type_fiber:
3025 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3026 ret_val = ixgbe_fc_autoneg_fiber(hw);
3029 /* Autoneg flow control on backplane adapters */
3030 case ixgbe_media_type_backplane:
3031 ret_val = ixgbe_fc_autoneg_backplane(hw);
3034 /* Autoneg flow control on copper adapters */
3035 case ixgbe_media_type_copper:
3036 if (ixgbe_device_supports_autoneg_fc(hw))
3037 ret_val = ixgbe_fc_autoneg_copper(hw);
3045 if (ret_val == IXGBE_SUCCESS) {
3046 hw->fc.fc_was_autonegged = true;
3048 hw->fc.fc_was_autonegged = false;
3049 hw->fc.current_mode = hw->fc.requested_mode;
3054 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3055 * @hw: pointer to hardware structure
3057 * System-wide timeout range is encoded in PCIe Device Control2 register.
3059 * Add 10% to specified maximum and return the number of times to poll for
3060 * completion timeout, in units of 100 microsec. Never return less than
3061 * 800 = 80 millisec.
3063 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3068 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3069 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3072 case IXGBE_PCIDEVCTRL2_65_130ms:
3073 pollcnt = 1300; /* 130 millisec */
3075 case IXGBE_PCIDEVCTRL2_260_520ms:
3076 pollcnt = 5200; /* 520 millisec */
3078 case IXGBE_PCIDEVCTRL2_1_2s:
3079 pollcnt = 20000; /* 2 sec */
3081 case IXGBE_PCIDEVCTRL2_4_8s:
3082 pollcnt = 80000; /* 8 sec */
3084 case IXGBE_PCIDEVCTRL2_17_34s:
3085 pollcnt = 34000; /* 34 sec */
3087 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3088 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3089 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3090 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3092 pollcnt = 800; /* 80 millisec minimum */
3096 /* add 10% to spec maximum */
3097 return (pollcnt * 11) / 10;
3101 * ixgbe_disable_pcie_master - Disable PCI-express master access
3102 * @hw: pointer to hardware structure
3104 * Disables PCI-Express master access and verifies there are no pending
3105 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3106 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3107 * is returned signifying master requests disabled.
3109 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3111 s32 status = IXGBE_SUCCESS;
3115 DEBUGFUNC("ixgbe_disable_pcie_master");
3117 /* Always set this bit to ensure any future transactions are blocked */
3118 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3120 /* Exit if master requests are blocked */
3121 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3122 IXGBE_REMOVED(hw->hw_addr))
3125 /* Poll for master request bit to clear */
3126 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3128 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3133 * Two consecutive resets are required via CTRL.RST per datasheet
3134 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3135 * of this need. The first reset prevents new master requests from
3136 * being issued by our device. We then must wait 1usec or more for any
3137 * remaining completions from the PCIe bus to trickle in, and then reset
3138 * again to clear out any effects they may have had on our device.
3140 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3141 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3144 * Before proceeding, make sure that the PCIe block does not have
3145 * transactions pending.
3147 poll = ixgbe_pcie_timeout_poll(hw);
3148 for (i = 0; i < poll; i++) {
3150 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3151 if (IXGBE_REMOVED(hw->hw_addr))
3153 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3157 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3158 "PCIe transaction pending bit also did not clear.\n");
3159 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3166 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3167 * @hw: pointer to hardware structure
3168 * @mask: Mask to specify which semaphore to acquire
3170 * Acquires the SWFW semaphore through the GSSR register for the specified
3171 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3173 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3177 u32 fwmask = mask << 5;
3181 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3183 for (i = 0; i < timeout; i++) {
3185 * SW NVM semaphore bit is used for access to all
3186 * SW_FW_SYNC bits (not just NVM)
3188 if (ixgbe_get_eeprom_semaphore(hw))
3189 return IXGBE_ERR_SWFW_SYNC;
3191 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3192 if (!(gssr & (fwmask | swmask))) {
3194 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3195 ixgbe_release_eeprom_semaphore(hw);
3196 return IXGBE_SUCCESS;
3198 /* Resource is currently in use by FW or SW */
3199 ixgbe_release_eeprom_semaphore(hw);
3204 /* If time expired clear the bits holding the lock and retry */
3205 if (gssr & (fwmask | swmask))
3206 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3209 return IXGBE_ERR_SWFW_SYNC;
3213 * ixgbe_release_swfw_sync - Release SWFW semaphore
3214 * @hw: pointer to hardware structure
3215 * @mask: Mask to specify which semaphore to release
3217 * Releases the SWFW semaphore through the GSSR register for the specified
3218 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3220 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3225 DEBUGFUNC("ixgbe_release_swfw_sync");
3227 ixgbe_get_eeprom_semaphore(hw);
3229 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3231 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3233 ixgbe_release_eeprom_semaphore(hw);
3237 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3238 * @hw: pointer to hardware structure
3240 * Stops the receive data path and waits for the HW to internally empty
3241 * the Rx security block
3243 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3245 #define IXGBE_MAX_SECRX_POLL 40
3250 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3253 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3254 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3255 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3256 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3257 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3258 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3261 /* Use interrupt-safe sleep just in case */
3265 /* For informational purposes only */
3266 if (i >= IXGBE_MAX_SECRX_POLL)
3267 DEBUGOUT("Rx unit being enabled before security "
3268 "path fully disabled. Continuing with init.\n");
3270 return IXGBE_SUCCESS;
3274 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3275 * @hw: pointer to hardware structure
3276 * @reg_val: Value we read from AUTOC
3278 * The default case requires no protection so just to the register read.
3280 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3283 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3284 return IXGBE_SUCCESS;
3288 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3289 * @hw: pointer to hardware structure
3290 * @reg_val: value to write to AUTOC
3291 * @locked: bool to indicate whether the SW/FW lock was already taken by
3294 * The default case requires no protection so just to the register write.
3296 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3298 UNREFERENCED_1PARAMETER(locked);
3300 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3301 return IXGBE_SUCCESS;
3305 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3306 * @hw: pointer to hardware structure
3308 * Enables the receive data path.
3310 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3314 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3316 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3317 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3318 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3319 IXGBE_WRITE_FLUSH(hw);
3321 return IXGBE_SUCCESS;
3325 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3326 * @hw: pointer to hardware structure
3327 * @regval: register value to write to RXCTRL
3329 * Enables the Rx DMA unit
3331 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3333 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3335 if (regval & IXGBE_RXCTRL_RXEN)
3336 ixgbe_enable_rx(hw);
3338 ixgbe_disable_rx(hw);
3340 return IXGBE_SUCCESS;
3344 * ixgbe_blink_led_start_generic - Blink LED based on index.
3345 * @hw: pointer to hardware structure
3346 * @index: led number to blink
3348 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3350 ixgbe_link_speed speed = 0;
3353 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3354 s32 ret_val = IXGBE_SUCCESS;
3355 bool locked = false;
3357 DEBUGFUNC("ixgbe_blink_led_start_generic");
3360 * Link must be up to auto-blink the LEDs;
3361 * Force it if link is down.
3363 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3366 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3367 if (ret_val != IXGBE_SUCCESS)
3370 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3371 autoc_reg |= IXGBE_AUTOC_FLU;
3373 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3374 if (ret_val != IXGBE_SUCCESS)
3377 IXGBE_WRITE_FLUSH(hw);
3381 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3382 led_reg |= IXGBE_LED_BLINK(index);
3383 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3384 IXGBE_WRITE_FLUSH(hw);
3391 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3392 * @hw: pointer to hardware structure
3393 * @index: led number to stop blinking
3395 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3398 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3399 s32 ret_val = IXGBE_SUCCESS;
3400 bool locked = false;
3402 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3404 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3405 if (ret_val != IXGBE_SUCCESS)
3408 autoc_reg &= ~IXGBE_AUTOC_FLU;
3409 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3411 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3412 if (ret_val != IXGBE_SUCCESS)
3415 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3416 led_reg &= ~IXGBE_LED_BLINK(index);
3417 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3418 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3419 IXGBE_WRITE_FLUSH(hw);
3426 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3427 * @hw: pointer to hardware structure
3428 * @san_mac_offset: SAN MAC address offset
3430 * This function will read the EEPROM location for the SAN MAC address
3431 * pointer, and returns the value at that location. This is used in both
3432 * get and set mac_addr routines.
3434 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3435 u16 *san_mac_offset)
3439 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3442 * First read the EEPROM pointer to see if the MAC addresses are
3445 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3448 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3449 "eeprom at offset %d failed",
3450 IXGBE_SAN_MAC_ADDR_PTR);
3457 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3458 * @hw: pointer to hardware structure
3459 * @san_mac_addr: SAN MAC address
3461 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3462 * per-port, so set_lan_id() must be called before reading the addresses.
3463 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3464 * upon for non-SFP connections, so we must call it here.
3466 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3468 u16 san_mac_data, san_mac_offset;
3472 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3475 * First read the EEPROM pointer to see if the MAC addresses are
3476 * available. If they're not, no point in calling set_lan_id() here.
3478 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3479 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3480 goto san_mac_addr_out;
3482 /* make sure we know which port we need to program */
3483 hw->mac.ops.set_lan_id(hw);
3484 /* apply the port offset to the address offset */
3485 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3486 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3487 for (i = 0; i < 3; i++) {
3488 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3491 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3492 "eeprom read at offset %d failed",
3494 goto san_mac_addr_out;
3496 san_mac_addr[i * 2] = (u8)(san_mac_data);
3497 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3500 return IXGBE_SUCCESS;
3504 * No addresses available in this EEPROM. It's not an
3505 * error though, so just wipe the local address and return.
3507 for (i = 0; i < 6; i++)
3508 san_mac_addr[i] = 0xFF;
3509 return IXGBE_SUCCESS;
3513 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3514 * @hw: pointer to hardware structure
3515 * @san_mac_addr: SAN MAC address
3517 * Write a SAN MAC address to the EEPROM.
3519 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3522 u16 san_mac_data, san_mac_offset;
3525 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3527 /* Look for SAN mac address pointer. If not defined, return */
3528 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3529 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3530 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3532 /* Make sure we know which port we need to write */
3533 hw->mac.ops.set_lan_id(hw);
3534 /* Apply the port offset to the address offset */
3535 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3536 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3538 for (i = 0; i < 3; i++) {
3539 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3540 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3541 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3545 return IXGBE_SUCCESS;
3549 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3550 * @hw: pointer to hardware structure
3552 * Read PCIe configuration space, and get the MSI-X vector count from
3553 * the capabilities table.
3555 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3561 switch (hw->mac.type) {
3562 case ixgbe_mac_82598EB:
3563 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3564 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3566 case ixgbe_mac_82599EB:
3567 case ixgbe_mac_X540:
3568 case ixgbe_mac_X550:
3569 case ixgbe_mac_X550EM_x:
3570 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3571 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3577 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3578 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3579 if (IXGBE_REMOVED(hw->hw_addr))
3581 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3583 /* MSI-X count is zero-based in HW */
3586 if (msix_count > max_msix_count)
3587 msix_count = max_msix_count;
3593 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3594 * @hw: pointer to hardware structure
3595 * @addr: Address to put into receive address register
3596 * @vmdq: VMDq pool to assign
3598 * Puts an ethernet address into a receive address register, or
3599 * finds the rar that it is aleady in; adds to the pool list
3601 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3603 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3604 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3606 u32 rar_low, rar_high;
3607 u32 addr_low, addr_high;
3609 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3611 /* swap bytes for HW little endian */
3612 addr_low = addr[0] | (addr[1] << 8)
3615 addr_high = addr[4] | (addr[5] << 8);
3618 * Either find the mac_id in rar or find the first empty space.
3619 * rar_highwater points to just after the highest currently used
3620 * rar in order to shorten the search. It grows when we add a new
3623 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3624 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3626 if (((IXGBE_RAH_AV & rar_high) == 0)
3627 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3628 first_empty_rar = rar;
3629 } else if ((rar_high & 0xFFFF) == addr_high) {
3630 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3631 if (rar_low == addr_low)
3632 break; /* found it already in the rars */
3636 if (rar < hw->mac.rar_highwater) {
3637 /* already there so just add to the pool bits */
3638 ixgbe_set_vmdq(hw, rar, vmdq);
3639 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3640 /* stick it into first empty RAR slot we found */
3641 rar = first_empty_rar;
3642 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3643 } else if (rar == hw->mac.rar_highwater) {
3644 /* add it to the top of the list and inc the highwater mark */
3645 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3646 hw->mac.rar_highwater++;
3647 } else if (rar >= hw->mac.num_rar_entries) {
3648 return IXGBE_ERR_INVALID_MAC_ADDR;
3652 * If we found rar[0], make sure the default pool bit (we use pool 0)
3653 * remains cleared to be sure default pool packets will get delivered
3656 ixgbe_clear_vmdq(hw, rar, 0);
3662 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3663 * @hw: pointer to hardware struct
3664 * @rar: receive address register index to disassociate
3665 * @vmdq: VMDq pool index to remove from the rar
3667 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3669 u32 mpsar_lo, mpsar_hi;
3670 u32 rar_entries = hw->mac.num_rar_entries;
3672 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3674 /* Make sure we are using a valid rar index range */
3675 if (rar >= rar_entries) {
3676 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3677 "RAR index %d is out of range.\n", rar);
3678 return IXGBE_ERR_INVALID_ARGUMENT;
3681 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3682 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3684 if (IXGBE_REMOVED(hw->hw_addr))
3687 if (!mpsar_lo && !mpsar_hi)
3690 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3692 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3696 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3699 } else if (vmdq < 32) {
3700 mpsar_lo &= ~(1 << vmdq);
3701 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3703 mpsar_hi &= ~(1 << (vmdq - 32));
3704 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3707 /* was that the last pool using this rar? */
3708 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3709 hw->mac.ops.clear_rar(hw, rar);
3711 return IXGBE_SUCCESS;
3715 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3716 * @hw: pointer to hardware struct
3717 * @rar: receive address register index to associate with a VMDq index
3718 * @vmdq: VMDq pool index
3720 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3723 u32 rar_entries = hw->mac.num_rar_entries;
3725 DEBUGFUNC("ixgbe_set_vmdq_generic");
3727 /* Make sure we are using a valid rar index range */
3728 if (rar >= rar_entries) {
3729 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3730 "RAR index %d is out of range.\n", rar);
3731 return IXGBE_ERR_INVALID_ARGUMENT;
3735 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3737 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3739 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3740 mpsar |= 1 << (vmdq - 32);
3741 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3743 return IXGBE_SUCCESS;
3747 * This function should only be involved in the IOV mode.
3748 * In IOV mode, Default pool is next pool after the number of
3749 * VFs advertized and not 0.
3750 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3752 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3753 * @hw: pointer to hardware struct
3754 * @vmdq: VMDq pool index
3756 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3758 u32 rar = hw->mac.san_mac_rar_index;
3760 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3763 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3764 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3766 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3767 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3770 return IXGBE_SUCCESS;
3774 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3775 * @hw: pointer to hardware structure
3777 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3781 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3782 DEBUGOUT(" Clearing UTA\n");
3784 for (i = 0; i < 128; i++)
3785 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3787 return IXGBE_SUCCESS;
3791 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3792 * @hw: pointer to hardware structure
3793 * @vlan: VLAN id to write to VLAN filter
3795 * return the VLVF index where this VLAN id should be placed
3798 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3801 u32 first_empty_slot = 0;
3804 /* short cut the special case */
3809 * Search for the vlan id in the VLVF entries. Save off the first empty
3810 * slot found along the way
3812 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3813 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3814 if (!bits && !(first_empty_slot))
3815 first_empty_slot = regindex;
3816 else if ((bits & 0x0FFF) == vlan)
3821 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3822 * in the VLVF. Else use the first empty VLVF register for this
3825 if (regindex >= IXGBE_VLVF_ENTRIES) {
3826 if (first_empty_slot)
3827 regindex = first_empty_slot;
3829 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
3830 "No space in VLVF.\n");
3831 regindex = IXGBE_ERR_NO_SPACE;
3839 * ixgbe_set_vfta_generic - Set VLAN filter table
3840 * @hw: pointer to hardware structure
3841 * @vlan: VLAN id to write to VLAN filter
3842 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3843 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3845 * Turn on/off specified VLAN in the VLAN filter table.
3847 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3854 s32 ret_val = IXGBE_SUCCESS;
3855 bool vfta_changed = false;
3857 DEBUGFUNC("ixgbe_set_vfta_generic");
3860 return IXGBE_ERR_PARAM;
3863 * this is a 2 part operation - first the VFTA, then the
3864 * VLVF and VLVFB if VT Mode is set
3865 * We don't write the VFTA until we know the VLVF part succeeded.
3869 * The VFTA is a bitstring made up of 128 32-bit registers
3870 * that enable the particular VLAN id, much like the MTA:
3871 * bits[11-5]: which register
3872 * bits[4-0]: which bit in the register
3874 regindex = (vlan >> 5) & 0x7F;
3875 bitindex = vlan & 0x1F;
3876 targetbit = (1 << bitindex);
3877 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3880 if (!(vfta & targetbit)) {
3882 vfta_changed = true;
3885 if ((vfta & targetbit)) {
3887 vfta_changed = true;
3892 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3894 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3896 if (ret_val != IXGBE_SUCCESS)
3900 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3902 return IXGBE_SUCCESS;
3906 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3907 * @hw: pointer to hardware structure
3908 * @vlan: VLAN id to write to VLAN filter
3909 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3910 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3911 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3914 * Turn on/off specified bit in VLVF table.
3916 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3917 bool vlan_on, bool *vfta_changed)
3921 DEBUGFUNC("ixgbe_set_vlvf_generic");
3924 return IXGBE_ERR_PARAM;
3926 /* If VT Mode is set
3928 * make sure the vlan is in VLVF
3929 * set the vind bit in the matching VLVFB
3931 * clear the pool bit and possibly the vind
3933 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3934 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3938 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3943 /* set the pool bit */
3945 bits = IXGBE_READ_REG(hw,
3946 IXGBE_VLVFB(vlvf_index * 2));
3947 bits |= (1 << vind);
3949 IXGBE_VLVFB(vlvf_index * 2),
3952 bits = IXGBE_READ_REG(hw,
3953 IXGBE_VLVFB((vlvf_index * 2) + 1));
3954 bits |= (1 << (vind - 32));
3956 IXGBE_VLVFB((vlvf_index * 2) + 1),
3960 /* clear the pool bit */
3962 bits = IXGBE_READ_REG(hw,
3963 IXGBE_VLVFB(vlvf_index * 2));
3964 bits &= ~(1 << vind);
3966 IXGBE_VLVFB(vlvf_index * 2),
3968 bits |= IXGBE_READ_REG(hw,
3969 IXGBE_VLVFB((vlvf_index * 2) + 1));
3971 bits = IXGBE_READ_REG(hw,
3972 IXGBE_VLVFB((vlvf_index * 2) + 1));
3973 bits &= ~(1 << (vind - 32));
3975 IXGBE_VLVFB((vlvf_index * 2) + 1),
3977 bits |= IXGBE_READ_REG(hw,
3978 IXGBE_VLVFB(vlvf_index * 2));
3983 * If there are still bits set in the VLVFB registers
3984 * for the VLAN ID indicated we need to see if the
3985 * caller is requesting that we clear the VFTA entry bit.
3986 * If the caller has requested that we clear the VFTA
3987 * entry bit but there are still pools/VFs using this VLAN
3988 * ID entry then ignore the request. We're not worried
3989 * about the case where we're turning the VFTA VLAN ID
3990 * entry bit on, only when requested to turn it off as
3991 * there may be multiple pools and/or VFs using the
3992 * VLAN ID entry. In that case we cannot clear the
3993 * VFTA bit until all pools/VFs using that VLAN ID have also
3994 * been cleared. This will be indicated by "bits" being
3998 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3999 (IXGBE_VLVF_VIEN | vlan));
4000 if ((!vlan_on) && (vfta_changed != NULL)) {
4001 /* someone wants to clear the vfta entry
4002 * but some pools/VFs are still using it.
4004 *vfta_changed = false;
4007 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4010 return IXGBE_SUCCESS;
4014 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4015 * @hw: pointer to hardware structure
4017 * Clears the VLAN filer table, and the VMDq index associated with the filter
4019 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4023 DEBUGFUNC("ixgbe_clear_vfta_generic");
4025 for (offset = 0; offset < hw->mac.vft_size; offset++)
4026 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4028 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4029 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4030 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4031 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
4034 return IXGBE_SUCCESS;
4038 * ixgbe_check_mac_link_generic - Determine link and speed status
4039 * @hw: pointer to hardware structure
4040 * @speed: pointer to link speed
4041 * @link_up: true when link is up
4042 * @link_up_wait_to_complete: bool used to wait for link up or not
4044 * Reads the links register to determine if link is up and the current speed
4046 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4047 bool *link_up, bool link_up_wait_to_complete)
4049 u32 links_reg, links_orig;
4052 DEBUGFUNC("ixgbe_check_mac_link_generic");
4054 /* clear the old state */
4055 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4057 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4059 if (links_orig != links_reg) {
4060 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4061 links_orig, links_reg);
4064 if (link_up_wait_to_complete) {
4065 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
4066 if (links_reg & IXGBE_LINKS_UP) {
4073 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4076 if (links_reg & IXGBE_LINKS_UP)
4082 switch (links_reg & IXGBE_LINKS_SPEED_82599) {
4083 case IXGBE_LINKS_SPEED_10G_82599:
4084 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4085 if (hw->mac.type >= ixgbe_mac_X550) {
4086 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4087 *speed = IXGBE_LINK_SPEED_2_5GB_FULL;
4090 case IXGBE_LINKS_SPEED_1G_82599:
4091 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4093 case IXGBE_LINKS_SPEED_100_82599:
4094 *speed = IXGBE_LINK_SPEED_100_FULL;
4095 if (hw->mac.type >= ixgbe_mac_X550) {
4096 if (links_reg & IXGBE_LINKS_SPEED_NON_STD)
4097 *speed = IXGBE_LINK_SPEED_5GB_FULL;
4101 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4104 return IXGBE_SUCCESS;
4108 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4110 * @hw: pointer to hardware structure
4111 * @wwnn_prefix: the alternative WWNN prefix
4112 * @wwpn_prefix: the alternative WWPN prefix
4114 * This function will read the EEPROM from the alternative SAN MAC address
4115 * block to check the support for the alternative WWNN/WWPN prefix support.
4117 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4121 u16 alt_san_mac_blk_offset;
4123 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4125 /* clear output first */
4126 *wwnn_prefix = 0xFFFF;
4127 *wwpn_prefix = 0xFFFF;
4129 /* check if alternative SAN MAC is supported */
4130 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4131 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4132 goto wwn_prefix_err;
4134 if ((alt_san_mac_blk_offset == 0) ||
4135 (alt_san_mac_blk_offset == 0xFFFF))
4136 goto wwn_prefix_out;
4138 /* check capability in alternative san mac address block */
4139 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4140 if (hw->eeprom.ops.read(hw, offset, &caps))
4141 goto wwn_prefix_err;
4142 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4143 goto wwn_prefix_out;
4145 /* get the corresponding prefix for WWNN/WWPN */
4146 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4147 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4148 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4149 "eeprom read at offset %d failed", offset);
4152 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4153 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4154 goto wwn_prefix_err;
4157 return IXGBE_SUCCESS;
4160 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4161 "eeprom read at offset %d failed", offset);
4162 return IXGBE_SUCCESS;
4166 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4167 * @hw: pointer to hardware structure
4168 * @bs: the fcoe boot status
4170 * This function will read the FCOE boot status from the iSCSI FCOE block
4172 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4174 u16 offset, caps, flags;
4177 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4179 /* clear output first */
4180 *bs = ixgbe_fcoe_bootstatus_unavailable;
4182 /* check if FCOE IBA block is present */
4183 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4184 status = hw->eeprom.ops.read(hw, offset, &caps);
4185 if (status != IXGBE_SUCCESS)
4188 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4191 /* check if iSCSI FCOE block is populated */
4192 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4193 if (status != IXGBE_SUCCESS)
4196 if ((offset == 0) || (offset == 0xFFFF))
4199 /* read fcoe flags in iSCSI FCOE block */
4200 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4201 status = hw->eeprom.ops.read(hw, offset, &flags);
4202 if (status != IXGBE_SUCCESS)
4205 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4206 *bs = ixgbe_fcoe_bootstatus_enabled;
4208 *bs = ixgbe_fcoe_bootstatus_disabled;
4215 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4216 * @hw: pointer to hardware structure
4217 * @enable: enable or disable switch for anti-spoofing
4218 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
4221 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
4224 int pf_target_reg = pf >> 3;
4225 int pf_target_shift = pf % 8;
4228 if (hw->mac.type == ixgbe_mac_82598EB)
4232 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
4235 * PFVFSPOOF register array is size 8 with 8 bits assigned to
4236 * MAC anti-spoof enables in each register array element.
4238 for (j = 0; j < pf_target_reg; j++)
4239 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4242 * The PF should be allowed to spoof so that it can support
4243 * emulation mode NICs. Do not set the bits assigned to the PF
4245 pfvfspoof &= (1 << pf_target_shift) - 1;
4246 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4249 * Remaining pools belong to the PF so they do not need to have
4250 * anti-spoofing enabled.
4252 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
4253 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
4257 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4258 * @hw: pointer to hardware structure
4259 * @enable: enable or disable switch for VLAN anti-spoofing
4260 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4263 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4265 int vf_target_reg = vf >> 3;
4266 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4269 if (hw->mac.type == ixgbe_mac_82598EB)
4272 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4274 pfvfspoof |= (1 << vf_target_shift);
4276 pfvfspoof &= ~(1 << vf_target_shift);
4277 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4281 * ixgbe_get_device_caps_generic - Get additional device capabilities
4282 * @hw: pointer to hardware structure
4283 * @device_caps: the EEPROM word with the extra device capabilities
4285 * This function will read the EEPROM location for the device capabilities,
4286 * and return the word through device_caps.
4288 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4290 DEBUGFUNC("ixgbe_get_device_caps_generic");
4292 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4294 return IXGBE_SUCCESS;
4298 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4299 * @hw: pointer to hardware structure
4302 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4307 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4309 /* Enable relaxed ordering */
4310 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4311 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4312 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4313 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4316 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4317 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4318 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4319 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4320 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4326 * ixgbe_calculate_checksum - Calculate checksum for buffer
4327 * @buffer: pointer to EEPROM
4328 * @length: size of EEPROM to calculate a checksum for
4329 * Calculates the checksum for some buffer on a specified length. The
4330 * checksum calculated is returned.
4332 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4337 DEBUGFUNC("ixgbe_calculate_checksum");
4342 for (i = 0; i < length; i++)
4345 return (u8) (0 - sum);
4349 * ixgbe_host_interface_command - Issue command to manageability block
4350 * @hw: pointer to the HW structure
4351 * @buffer: contains the command to write and where the return status will
4353 * @length: length of buffer, must be multiple of 4 bytes
4354 * @return_data: read and return data from the buffer (true) or not (false)
4355 * Needed because FW structures are big endian and decoding of
4356 * these fields can be 8 bit or 16 bit based on command. Decoding
4357 * is not easily understood without making a table of commands.
4358 * So we will leave this up to the caller to read back the data
4361 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4362 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
4364 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4365 u32 length, bool return_data)
4367 u32 hicr, i, bi, fwsts;
4368 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4372 DEBUGFUNC("ixgbe_host_interface_command");
4374 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4375 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4376 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4378 /* Set bit 9 of FWSTS clearing FW reset indication */
4379 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4380 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4382 /* Check that the host interface is enabled. */
4383 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4384 if ((hicr & IXGBE_HICR_EN) == 0) {
4385 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4386 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4389 /* Calculate length in DWORDs. We must be DWORD aligned */
4390 if ((length % (sizeof(u32))) != 0) {
4391 DEBUGOUT("Buffer length failure, not aligned to dword");
4392 return IXGBE_ERR_INVALID_ARGUMENT;
4395 dword_len = length >> 2;
4397 /* The device driver writes the relevant command block
4398 * into the ram area.
4400 for (i = 0; i < dword_len; i++)
4401 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4402 i, IXGBE_CPU_TO_LE32(buffer[i]));
4404 /* Setting this bit tells the ARC that a new command is pending. */
4405 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4407 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
4408 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4409 if (!(hicr & IXGBE_HICR_C))
4414 /* Check command completion */
4415 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
4416 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4417 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4418 "Command has failed with no status valid.\n");
4419 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4425 /* Calculate length in DWORDs */
4426 dword_len = hdr_size >> 2;
4428 /* first pull in the header so we know the buffer length */
4429 for (bi = 0; bi < dword_len; bi++) {
4430 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4431 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4434 /* If there is any thing in data position pull it in */
4435 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4439 if (length < buf_len + hdr_size) {
4440 DEBUGOUT("Buffer not large enough for reply message.\n");
4441 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4444 /* Calculate length in DWORDs, add 3 for odd lengths */
4445 dword_len = (buf_len + 3) >> 2;
4447 /* Pull in the rest of the buffer (bi is where we left off) */
4448 for (; bi <= dword_len; bi++) {
4449 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4450 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4457 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4458 * @hw: pointer to the HW structure
4459 * @maj: driver version major number
4460 * @min: driver version minor number
4461 * @build: driver version build number
4462 * @sub: driver version sub build number
4464 * Sends driver version number to firmware through the manageability
4465 * block. On success return IXGBE_SUCCESS
4466 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4467 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4469 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4472 struct ixgbe_hic_drv_info fw_cmd;
4474 s32 ret_val = IXGBE_SUCCESS;
4476 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4478 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
4480 ret_val = IXGBE_ERR_SWFW_SYNC;
4484 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4485 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4486 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4487 fw_cmd.port_num = (u8)hw->bus.func;
4488 fw_cmd.ver_maj = maj;
4489 fw_cmd.ver_min = min;
4490 fw_cmd.ver_build = build;
4491 fw_cmd.ver_sub = sub;
4492 fw_cmd.hdr.checksum = 0;
4493 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4494 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4498 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4499 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4500 sizeof(fw_cmd), true);
4501 if (ret_val != IXGBE_SUCCESS)
4504 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4505 FW_CEM_RESP_STATUS_SUCCESS)
4506 ret_val = IXGBE_SUCCESS;
4508 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4513 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4519 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4520 * @hw: pointer to hardware structure
4521 * @num_pb: number of packet buffers to allocate
4522 * @headroom: reserve n KB of headroom
4523 * @strategy: packet buffer allocation strategy
4525 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4528 u32 pbsize = hw->mac.rx_pb_size;
4530 u32 rxpktsize, txpktsize, txpbthresh;
4532 /* Reserve headroom */
4538 /* Divide remaining packet buffer space amongst the number of packet
4539 * buffers requested using supplied strategy.
4542 case PBA_STRATEGY_WEIGHTED:
4543 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4544 * buffer with 5/8 of the packet buffer space.
4546 rxpktsize = (pbsize * 5) / (num_pb * 4);
4547 pbsize -= rxpktsize * (num_pb / 2);
4548 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4549 for (; i < (num_pb / 2); i++)
4550 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4551 /* Fall through to configure remaining packet buffers */
4552 case PBA_STRATEGY_EQUAL:
4553 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4554 for (; i < num_pb; i++)
4555 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4561 /* Only support an equally distributed Tx packet buffer strategy. */
4562 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4563 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4564 for (i = 0; i < num_pb; i++) {
4565 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4566 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4569 /* Clear unused TCs, if any, to zero buffer size*/
4570 for (; i < IXGBE_MAX_PB; i++) {
4571 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4572 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4573 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4578 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4579 * @hw: pointer to the hardware structure
4581 * The 82599 and x540 MACs can experience issues if TX work is still pending
4582 * when a reset occurs. This function prevents this by flushing the PCIe
4583 * buffers on the system.
4585 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4587 u32 gcr_ext, hlreg0, i, poll;
4591 * If double reset is not requested then all transactions should
4592 * already be clear and as such there is no work to do
4594 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4598 * Set loopback enable to prevent any transmits from being sent
4599 * should the link come up. This assumes that the RXCTRL.RXEN bit
4600 * has already been cleared.
4602 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4603 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4605 /* Wait for a last completion before clearing buffers */
4606 IXGBE_WRITE_FLUSH(hw);
4610 * Before proceeding, make sure that the PCIe block does not have
4611 * transactions pending.
4613 poll = ixgbe_pcie_timeout_poll(hw);
4614 for (i = 0; i < poll; i++) {
4616 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
4617 if (IXGBE_REMOVED(hw->hw_addr))
4619 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
4624 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4625 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4626 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4627 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4629 /* Flush all writes and allow 20usec for all transactions to clear */
4630 IXGBE_WRITE_FLUSH(hw);
4633 /* restore previous register values */
4634 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4635 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4638 STATIC const u8 ixgbe_emc_temp_data[4] = {
4639 IXGBE_EMC_INTERNAL_DATA,
4640 IXGBE_EMC_DIODE1_DATA,
4641 IXGBE_EMC_DIODE2_DATA,
4642 IXGBE_EMC_DIODE3_DATA
4644 STATIC const u8 ixgbe_emc_therm_limit[4] = {
4645 IXGBE_EMC_INTERNAL_THERM_LIMIT,
4646 IXGBE_EMC_DIODE1_THERM_LIMIT,
4647 IXGBE_EMC_DIODE2_THERM_LIMIT,
4648 IXGBE_EMC_DIODE3_THERM_LIMIT
4652 * ixgbe_get_thermal_sensor_data - Gathers thermal sensor data
4653 * @hw: pointer to hardware structure
4654 * @data: pointer to the thermal sensor data structure
4656 * Returns the thermal sensor data structure
4658 s32 ixgbe_get_thermal_sensor_data_generic(struct ixgbe_hw *hw)
4660 s32 status = IXGBE_SUCCESS;
4668 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4670 DEBUGFUNC("ixgbe_get_thermal_sensor_data_generic");
4672 /* Only support thermal sensors attached to 82599 physical port 0 */
4673 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4674 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)) {
4675 status = IXGBE_NOT_IMPLEMENTED;
4679 status = hw->eeprom.ops.read(hw, IXGBE_ETS_CFG, &ets_offset);
4683 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF)) {
4684 status = IXGBE_NOT_IMPLEMENTED;
4688 status = hw->eeprom.ops.read(hw, ets_offset, &ets_cfg);
4692 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4693 != IXGBE_ETS_TYPE_EMC) {
4694 status = IXGBE_NOT_IMPLEMENTED;
4698 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4699 if (num_sensors > IXGBE_MAX_SENSORS)
4700 num_sensors = IXGBE_MAX_SENSORS;
4702 for (i = 0; i < num_sensors; i++) {
4703 status = hw->eeprom.ops.read(hw, (ets_offset + 1 + i),
4708 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4709 IXGBE_ETS_DATA_INDEX_SHIFT);
4710 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4711 IXGBE_ETS_DATA_LOC_SHIFT);
4713 if (sensor_location != 0) {
4714 status = hw->phy.ops.read_i2c_byte(hw,
4715 ixgbe_emc_temp_data[sensor_index],
4716 IXGBE_I2C_THERMAL_SENSOR_ADDR,
4717 &data->sensor[i].temp);
4727 * ixgbe_init_thermal_sensor_thresh_generic - Inits thermal sensor thresholds
4728 * @hw: pointer to hardware structure
4730 * Inits the thermal sensor thresholds according to the NVM map
4731 * and save off the threshold and location values into mac.thermal_sensor_data
4733 s32 ixgbe_init_thermal_sensor_thresh_generic(struct ixgbe_hw *hw)
4735 s32 status = IXGBE_SUCCESS;
4740 u8 low_thresh_delta;
4746 struct ixgbe_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
4748 DEBUGFUNC("ixgbe_init_thermal_sensor_thresh_generic");
4750 memset(data, 0, sizeof(struct ixgbe_thermal_sensor_data));
4752 /* Only support thermal sensors attached to 82599 physical port 0 */
4753 if ((hw->mac.type != ixgbe_mac_82599EB) ||
4754 (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1))
4755 return IXGBE_NOT_IMPLEMENTED;
4757 offset = IXGBE_ETS_CFG;
4758 if (hw->eeprom.ops.read(hw, offset, &ets_offset))
4760 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
4761 return IXGBE_NOT_IMPLEMENTED;
4763 offset = ets_offset;
4764 if (hw->eeprom.ops.read(hw, offset, &ets_cfg))
4766 if (((ets_cfg & IXGBE_ETS_TYPE_MASK) >> IXGBE_ETS_TYPE_SHIFT)
4767 != IXGBE_ETS_TYPE_EMC)
4768 return IXGBE_NOT_IMPLEMENTED;
4770 low_thresh_delta = ((ets_cfg & IXGBE_ETS_LTHRES_DELTA_MASK) >>
4771 IXGBE_ETS_LTHRES_DELTA_SHIFT);
4772 num_sensors = (ets_cfg & IXGBE_ETS_NUM_SENSORS_MASK);
4774 for (i = 0; i < num_sensors; i++) {
4775 offset = ets_offset + 1 + i;
4776 if (hw->eeprom.ops.read(hw, offset, &ets_sensor)) {
4777 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4778 "eeprom read at offset %d failed",
4782 sensor_index = ((ets_sensor & IXGBE_ETS_DATA_INDEX_MASK) >>
4783 IXGBE_ETS_DATA_INDEX_SHIFT);
4784 sensor_location = ((ets_sensor & IXGBE_ETS_DATA_LOC_MASK) >>
4785 IXGBE_ETS_DATA_LOC_SHIFT);
4786 therm_limit = ets_sensor & IXGBE_ETS_DATA_HTHRESH_MASK;
4788 hw->phy.ops.write_i2c_byte(hw,
4789 ixgbe_emc_therm_limit[sensor_index],
4790 IXGBE_I2C_THERMAL_SENSOR_ADDR, therm_limit);
4792 if ((i < IXGBE_MAX_SENSORS) && (sensor_location != 0)) {
4793 data->sensor[i].location = sensor_location;
4794 data->sensor[i].caution_thresh = therm_limit;
4795 data->sensor[i].max_op_thresh = therm_limit -
4802 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4803 "eeprom read at offset %d failed", offset);
4804 return IXGBE_NOT_IMPLEMENTED;
4809 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4810 * @hw: pointer to hardware structure
4811 * @map: pointer to u8 arr for returning map
4813 * Read the rtrup2tc HW register and resolve its content into map
4815 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4819 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4820 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4821 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4822 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4826 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4831 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4832 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4833 if (hw->mac.type != ixgbe_mac_82598EB) {
4834 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4835 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4836 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4837 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4838 hw->mac.set_lben = true;
4840 hw->mac.set_lben = false;
4843 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4844 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4848 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4853 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4854 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4856 if (hw->mac.type != ixgbe_mac_82598EB) {
4857 if (hw->mac.set_lben) {
4858 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4859 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4860 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4861 hw->mac.set_lben = false;
4867 * ixgbe_mng_enabled - Is the manageability engine enabled?
4868 * @hw: pointer to hardware structure
4870 * Returns true if the manageability engine is enabled.
4872 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
4874 u32 fwsm, manc, factps;
4876 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4877 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
4880 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
4881 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
4884 if (hw->mac.type <= ixgbe_mac_X540) {
4885 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
4886 if (factps & IXGBE_FACTPS_MNGCG)