1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
39 #ident "$Id: ixgbe_common.c,v 1.382 2013/11/22 01:02:01 jtkirshe Exp $"
41 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
42 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
44 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
46 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
48 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
49 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
51 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
53 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
54 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
56 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
57 u16 words, u16 *data);
58 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
64 * ixgbe_init_ops_generic - Inits function ptrs
65 * @hw: pointer to the hardware structure
67 * Initialize the function pointers.
69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
72 struct ixgbe_mac_info *mac = &hw->mac;
73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
75 DEBUGFUNC("ixgbe_init_ops_generic");
78 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
80 if (eec & IXGBE_EEC_PRES) {
81 eeprom->ops.read = &ixgbe_read_eerd_generic;
82 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
84 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
85 eeprom->ops.read_buffer =
86 &ixgbe_read_eeprom_buffer_bit_bang_generic;
88 eeprom->ops.write = &ixgbe_write_eeprom_generic;
89 eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
90 eeprom->ops.validate_checksum =
91 &ixgbe_validate_eeprom_checksum_generic;
92 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
93 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
96 mac->ops.init_hw = &ixgbe_init_hw_generic;
97 mac->ops.reset_hw = NULL;
98 mac->ops.start_hw = &ixgbe_start_hw_generic;
99 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
100 mac->ops.get_media_type = NULL;
101 mac->ops.get_supported_physical_layer = NULL;
102 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
103 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
104 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
105 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
106 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
107 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
108 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
109 mac->ops.prot_autoc_read = &prot_autoc_read_generic;
110 mac->ops.prot_autoc_write = &prot_autoc_write_generic;
113 mac->ops.led_on = &ixgbe_led_on_generic;
114 mac->ops.led_off = &ixgbe_led_off_generic;
115 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
116 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
118 /* RAR, Multicast, VLAN */
119 mac->ops.set_rar = &ixgbe_set_rar_generic;
120 mac->ops.clear_rar = &ixgbe_clear_rar_generic;
121 mac->ops.insert_mac_addr = NULL;
122 mac->ops.set_vmdq = NULL;
123 mac->ops.clear_vmdq = NULL;
124 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
125 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
126 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
127 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
128 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
129 mac->ops.clear_vfta = NULL;
130 mac->ops.set_vfta = NULL;
131 mac->ops.set_vlvf = NULL;
132 mac->ops.init_uta_tables = NULL;
133 mac->ops.enable_rx = &ixgbe_enable_rx_generic;
134 mac->ops.disable_rx = &ixgbe_disable_rx_generic;
137 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
140 mac->ops.get_link_capabilities = NULL;
141 mac->ops.setup_link = NULL;
142 mac->ops.check_link = NULL;
143 mac->ops.dmac_config = NULL;
144 mac->ops.dmac_update_tcs = NULL;
145 mac->ops.dmac_config_tcs = NULL;
147 return IXGBE_SUCCESS;
151 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
153 * @hw: pointer to hardware structure
155 * This function returns true if the device supports flow control
156 * autonegotiation, and false if it does not.
159 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
161 bool supported = false;
162 ixgbe_link_speed speed;
165 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
167 switch (hw->phy.media_type) {
168 case ixgbe_media_type_fiber:
169 hw->mac.ops.check_link(hw, &speed, &link_up, false);
170 /* if link is down, assume supported */
172 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
177 case ixgbe_media_type_backplane:
180 case ixgbe_media_type_copper:
181 /* only some copper devices support flow control autoneg */
182 switch (hw->device_id) {
183 case IXGBE_DEV_ID_82599_T3_LOM:
184 case IXGBE_DEV_ID_X540T:
185 case IXGBE_DEV_ID_X540T1:
195 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
196 "Device %x does not support flow control autoneg",
202 * ixgbe_setup_fc - Set up flow control
203 * @hw: pointer to hardware structure
205 * Called at init time to set up flow control.
207 STATIC s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
209 s32 ret_val = IXGBE_SUCCESS;
210 u32 reg = 0, reg_bp = 0;
214 DEBUGFUNC("ixgbe_setup_fc");
217 * Validate the requested mode. Strict IEEE mode does not allow
218 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
220 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
221 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
222 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
223 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
228 * 10gig parts do not have a word in the EEPROM to determine the
229 * default flow control setting, so we explicitly set it to full.
231 if (hw->fc.requested_mode == ixgbe_fc_default)
232 hw->fc.requested_mode = ixgbe_fc_full;
235 * Set up the 1G and 10G flow control advertisement registers so the
236 * HW will be able to do fc autoneg once the cable is plugged in. If
237 * we link at 10G, the 1G advertisement is harmless and vice versa.
239 switch (hw->phy.media_type) {
240 case ixgbe_media_type_backplane:
241 /* some MAC's need RMW protection on AUTOC */
242 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
243 if (ret_val != IXGBE_SUCCESS)
246 /* only backplane uses autoc so fall though */
247 case ixgbe_media_type_fiber:
248 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
251 case ixgbe_media_type_copper:
252 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
253 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
260 * The possible values of fc.requested_mode are:
261 * 0: Flow control is completely disabled
262 * 1: Rx flow control is enabled (we can receive pause frames,
263 * but not send pause frames).
264 * 2: Tx flow control is enabled (we can send pause frames but
265 * we do not support receiving pause frames).
266 * 3: Both Rx and Tx flow control (symmetric) are enabled.
269 switch (hw->fc.requested_mode) {
271 /* Flow control completely disabled by software override. */
272 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
273 if (hw->phy.media_type == ixgbe_media_type_backplane)
274 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
275 IXGBE_AUTOC_ASM_PAUSE);
276 else if (hw->phy.media_type == ixgbe_media_type_copper)
277 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
279 case ixgbe_fc_tx_pause:
281 * Tx Flow control is enabled, and Rx Flow control is
282 * disabled by software override.
284 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
285 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
286 if (hw->phy.media_type == ixgbe_media_type_backplane) {
287 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
288 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
289 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
290 reg_cu |= IXGBE_TAF_ASM_PAUSE;
291 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
294 case ixgbe_fc_rx_pause:
296 * Rx Flow control is enabled and Tx Flow control is
297 * disabled by software override. Since there really
298 * isn't a way to advertise that we are capable of RX
299 * Pause ONLY, we will advertise that we support both
300 * symmetric and asymmetric Rx PAUSE, as such we fall
301 * through to the fc_full statement. Later, we will
302 * disable the adapter's ability to send PAUSE frames.
305 /* Flow control (both Rx and Tx) is enabled by SW override. */
306 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
307 if (hw->phy.media_type == ixgbe_media_type_backplane)
308 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
309 IXGBE_AUTOC_ASM_PAUSE;
310 else if (hw->phy.media_type == ixgbe_media_type_copper)
311 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
314 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
315 "Flow control param set incorrectly\n");
316 ret_val = IXGBE_ERR_CONFIG;
321 if (hw->mac.type < ixgbe_mac_X540) {
323 * Enable auto-negotiation between the MAC & PHY;
324 * the MAC will advertise clause 37 flow control.
326 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
327 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
329 /* Disable AN timeout */
330 if (hw->fc.strict_ieee)
331 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
333 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
334 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
338 * AUTOC restart handles negotiation of 1G and 10G on backplane
339 * and copper. There is no need to set the PCS1GCTL register.
342 if (hw->phy.media_type == ixgbe_media_type_backplane) {
343 reg_bp |= IXGBE_AUTOC_AN_RESTART;
344 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
347 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
348 (ixgbe_device_supports_autoneg_fc(hw))) {
349 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
350 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
353 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
359 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
360 * @hw: pointer to hardware structure
362 * Starts the hardware by filling the bus info structure and media type, clears
363 * all on chip counters, initializes receive address registers, multicast
364 * table, VLAN filter table, calls routine to set up link and flow control
365 * settings, and leaves transmit and receive units disabled and uninitialized
367 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
372 DEBUGFUNC("ixgbe_start_hw_generic");
374 /* Set the media type */
375 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
377 /* PHY ops initialization must be done in reset_hw() */
379 /* Clear the VLAN filter table */
380 hw->mac.ops.clear_vfta(hw);
382 /* Clear statistics registers */
383 hw->mac.ops.clear_hw_cntrs(hw);
385 /* Set No Snoop Disable */
386 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
387 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
388 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
389 IXGBE_WRITE_FLUSH(hw);
391 /* Setup flow control */
392 ret_val = ixgbe_setup_fc(hw);
393 if (ret_val != IXGBE_SUCCESS)
396 /* Clear adapter stopped flag */
397 hw->adapter_stopped = false;
404 * ixgbe_start_hw_gen2 - Init sequence for common device family
405 * @hw: pointer to hw structure
407 * Performs the init sequence common to the second generation
409 * Devices in the second generation:
413 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
418 /* Clear the rate limiters */
419 for (i = 0; i < hw->mac.max_tx_queues; i++) {
420 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
421 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
423 IXGBE_WRITE_FLUSH(hw);
425 /* Disable relaxed ordering */
426 for (i = 0; i < hw->mac.max_tx_queues; i++) {
427 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
428 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
429 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
432 for (i = 0; i < hw->mac.max_rx_queues; i++) {
433 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
434 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
435 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
436 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
439 return IXGBE_SUCCESS;
443 * ixgbe_init_hw_generic - Generic hardware initialization
444 * @hw: pointer to hardware structure
446 * Initialize the hardware by resetting the hardware, filling the bus info
447 * structure and media type, clears all on chip counters, initializes receive
448 * address registers, multicast table, VLAN filter table, calls routine to set
449 * up link and flow control settings, and leaves transmit and receive units
450 * disabled and uninitialized
452 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
456 DEBUGFUNC("ixgbe_init_hw_generic");
458 /* Reset the hardware */
459 status = hw->mac.ops.reset_hw(hw);
461 if (status == IXGBE_SUCCESS) {
463 status = hw->mac.ops.start_hw(hw);
470 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
471 * @hw: pointer to hardware structure
473 * Clears all hardware statistics counters by reading them from the hardware
474 * Statistics counters are clear on read.
476 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
480 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
482 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
483 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
484 IXGBE_READ_REG(hw, IXGBE_ERRBC);
485 IXGBE_READ_REG(hw, IXGBE_MSPDC);
486 for (i = 0; i < 8; i++)
487 IXGBE_READ_REG(hw, IXGBE_MPC(i));
489 IXGBE_READ_REG(hw, IXGBE_MLFC);
490 IXGBE_READ_REG(hw, IXGBE_MRFC);
491 IXGBE_READ_REG(hw, IXGBE_RLEC);
492 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
493 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
494 if (hw->mac.type >= ixgbe_mac_82599EB) {
495 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
496 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
498 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
499 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
502 for (i = 0; i < 8; i++) {
503 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
504 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
505 if (hw->mac.type >= ixgbe_mac_82599EB) {
506 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
507 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
509 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
510 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
513 if (hw->mac.type >= ixgbe_mac_82599EB)
514 for (i = 0; i < 8; i++)
515 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
516 IXGBE_READ_REG(hw, IXGBE_PRC64);
517 IXGBE_READ_REG(hw, IXGBE_PRC127);
518 IXGBE_READ_REG(hw, IXGBE_PRC255);
519 IXGBE_READ_REG(hw, IXGBE_PRC511);
520 IXGBE_READ_REG(hw, IXGBE_PRC1023);
521 IXGBE_READ_REG(hw, IXGBE_PRC1522);
522 IXGBE_READ_REG(hw, IXGBE_GPRC);
523 IXGBE_READ_REG(hw, IXGBE_BPRC);
524 IXGBE_READ_REG(hw, IXGBE_MPRC);
525 IXGBE_READ_REG(hw, IXGBE_GPTC);
526 IXGBE_READ_REG(hw, IXGBE_GORCL);
527 IXGBE_READ_REG(hw, IXGBE_GORCH);
528 IXGBE_READ_REG(hw, IXGBE_GOTCL);
529 IXGBE_READ_REG(hw, IXGBE_GOTCH);
530 if (hw->mac.type == ixgbe_mac_82598EB)
531 for (i = 0; i < 8; i++)
532 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
533 IXGBE_READ_REG(hw, IXGBE_RUC);
534 IXGBE_READ_REG(hw, IXGBE_RFC);
535 IXGBE_READ_REG(hw, IXGBE_ROC);
536 IXGBE_READ_REG(hw, IXGBE_RJC);
537 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
538 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
539 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
540 IXGBE_READ_REG(hw, IXGBE_TORL);
541 IXGBE_READ_REG(hw, IXGBE_TORH);
542 IXGBE_READ_REG(hw, IXGBE_TPR);
543 IXGBE_READ_REG(hw, IXGBE_TPT);
544 IXGBE_READ_REG(hw, IXGBE_PTC64);
545 IXGBE_READ_REG(hw, IXGBE_PTC127);
546 IXGBE_READ_REG(hw, IXGBE_PTC255);
547 IXGBE_READ_REG(hw, IXGBE_PTC511);
548 IXGBE_READ_REG(hw, IXGBE_PTC1023);
549 IXGBE_READ_REG(hw, IXGBE_PTC1522);
550 IXGBE_READ_REG(hw, IXGBE_MPTC);
551 IXGBE_READ_REG(hw, IXGBE_BPTC);
552 for (i = 0; i < 16; i++) {
553 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
554 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
555 if (hw->mac.type >= ixgbe_mac_82599EB) {
556 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
557 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
558 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
559 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
560 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
562 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
563 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
567 if (hw->mac.type == ixgbe_mac_X540) {
569 ixgbe_identify_phy(hw);
570 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
571 IXGBE_MDIO_PCS_DEV_TYPE, &i);
572 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
573 IXGBE_MDIO_PCS_DEV_TYPE, &i);
574 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
575 IXGBE_MDIO_PCS_DEV_TYPE, &i);
576 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
577 IXGBE_MDIO_PCS_DEV_TYPE, &i);
580 return IXGBE_SUCCESS;
584 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
585 * @hw: pointer to hardware structure
586 * @pba_num: stores the part number string from the EEPROM
587 * @pba_num_size: part number string buffer length
589 * Reads the part number string from the EEPROM.
591 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
600 DEBUGFUNC("ixgbe_read_pba_string_generic");
602 if (pba_num == NULL) {
603 DEBUGOUT("PBA string buffer was null\n");
604 return IXGBE_ERR_INVALID_ARGUMENT;
607 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
609 DEBUGOUT("NVM Read Error\n");
613 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
615 DEBUGOUT("NVM Read Error\n");
620 * if data is not ptr guard the PBA must be in legacy format which
621 * means pba_ptr is actually our second data word for the PBA number
622 * and we can decode it into an ascii string
624 if (data != IXGBE_PBANUM_PTR_GUARD) {
625 DEBUGOUT("NVM PBA number is not stored as string\n");
627 /* we will need 11 characters to store the PBA */
628 if (pba_num_size < 11) {
629 DEBUGOUT("PBA string buffer too small\n");
630 return IXGBE_ERR_NO_SPACE;
633 /* extract hex string from data and pba_ptr */
634 pba_num[0] = (data >> 12) & 0xF;
635 pba_num[1] = (data >> 8) & 0xF;
636 pba_num[2] = (data >> 4) & 0xF;
637 pba_num[3] = data & 0xF;
638 pba_num[4] = (pba_ptr >> 12) & 0xF;
639 pba_num[5] = (pba_ptr >> 8) & 0xF;
642 pba_num[8] = (pba_ptr >> 4) & 0xF;
643 pba_num[9] = pba_ptr & 0xF;
645 /* put a null character on the end of our string */
648 /* switch all the data but the '-' to hex char */
649 for (offset = 0; offset < 10; offset++) {
650 if (pba_num[offset] < 0xA)
651 pba_num[offset] += '0';
652 else if (pba_num[offset] < 0x10)
653 pba_num[offset] += 'A' - 0xA;
656 return IXGBE_SUCCESS;
659 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
661 DEBUGOUT("NVM Read Error\n");
665 if (length == 0xFFFF || length == 0) {
666 DEBUGOUT("NVM PBA number section invalid length\n");
667 return IXGBE_ERR_PBA_SECTION;
670 /* check if pba_num buffer is big enough */
671 if (pba_num_size < (((u32)length * 2) - 1)) {
672 DEBUGOUT("PBA string buffer too small\n");
673 return IXGBE_ERR_NO_SPACE;
676 /* trim pba length from start of string */
680 for (offset = 0; offset < length; offset++) {
681 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
683 DEBUGOUT("NVM Read Error\n");
686 pba_num[offset * 2] = (u8)(data >> 8);
687 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
689 pba_num[offset * 2] = '\0';
691 return IXGBE_SUCCESS;
695 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
696 * @hw: pointer to hardware structure
697 * @pba_num: stores the part number from the EEPROM
699 * Reads the part number from the EEPROM.
701 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
706 DEBUGFUNC("ixgbe_read_pba_num_generic");
708 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
710 DEBUGOUT("NVM Read Error\n");
712 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
713 DEBUGOUT("NVM Not supported\n");
714 return IXGBE_NOT_IMPLEMENTED;
716 *pba_num = (u32)(data << 16);
718 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
720 DEBUGOUT("NVM Read Error\n");
725 return IXGBE_SUCCESS;
730 * @hw: pointer to the HW structure
731 * @eeprom_buf: optional pointer to EEPROM image
732 * @eeprom_buf_size: size of EEPROM image in words
733 * @max_pba_block_size: PBA block size limit
734 * @pba: pointer to output PBA structure
736 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
737 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
740 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
741 u32 eeprom_buf_size, u16 max_pba_block_size,
742 struct ixgbe_pba *pba)
748 return IXGBE_ERR_PARAM;
750 if (eeprom_buf == NULL) {
751 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
756 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
757 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
758 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
760 return IXGBE_ERR_PARAM;
764 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
765 if (pba->pba_block == NULL)
766 return IXGBE_ERR_PARAM;
768 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
774 if (pba_block_size > max_pba_block_size)
775 return IXGBE_ERR_PARAM;
777 if (eeprom_buf == NULL) {
778 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
784 if (eeprom_buf_size > (u32)(pba->word[1] +
786 memcpy(pba->pba_block,
787 &eeprom_buf[pba->word[1]],
788 pba_block_size * sizeof(u16));
790 return IXGBE_ERR_PARAM;
795 return IXGBE_SUCCESS;
799 * ixgbe_write_pba_raw
800 * @hw: pointer to the HW structure
801 * @eeprom_buf: optional pointer to EEPROM image
802 * @eeprom_buf_size: size of EEPROM image in words
803 * @pba: pointer to PBA structure
805 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
806 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
809 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
810 u32 eeprom_buf_size, struct ixgbe_pba *pba)
815 return IXGBE_ERR_PARAM;
817 if (eeprom_buf == NULL) {
818 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
823 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
824 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
825 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
827 return IXGBE_ERR_PARAM;
831 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
832 if (pba->pba_block == NULL)
833 return IXGBE_ERR_PARAM;
835 if (eeprom_buf == NULL) {
836 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
842 if (eeprom_buf_size > (u32)(pba->word[1] +
843 pba->pba_block[0])) {
844 memcpy(&eeprom_buf[pba->word[1]],
846 pba->pba_block[0] * sizeof(u16));
848 return IXGBE_ERR_PARAM;
853 return IXGBE_SUCCESS;
857 * ixgbe_get_pba_block_size
858 * @hw: pointer to the HW structure
859 * @eeprom_buf: optional pointer to EEPROM image
860 * @eeprom_buf_size: size of EEPROM image in words
861 * @pba_data_size: pointer to output variable
863 * Returns the size of the PBA block in words. Function operates on EEPROM
864 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
868 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
869 u32 eeprom_buf_size, u16 *pba_block_size)
875 DEBUGFUNC("ixgbe_get_pba_block_size");
877 if (eeprom_buf == NULL) {
878 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
883 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
884 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
885 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
887 return IXGBE_ERR_PARAM;
891 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
892 if (eeprom_buf == NULL) {
893 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
898 if (eeprom_buf_size > pba_word[1])
899 length = eeprom_buf[pba_word[1] + 0];
901 return IXGBE_ERR_PARAM;
904 if (length == 0xFFFF || length == 0)
905 return IXGBE_ERR_PBA_SECTION;
907 /* PBA number in legacy format, there is no PBA Block. */
911 if (pba_block_size != NULL)
912 *pba_block_size = length;
914 return IXGBE_SUCCESS;
918 * ixgbe_get_mac_addr_generic - Generic get MAC address
919 * @hw: pointer to hardware structure
920 * @mac_addr: Adapter MAC address
922 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
923 * A reset of the adapter must be performed prior to calling this function
924 * in order for the MAC address to have been loaded from the EEPROM into RAR0
926 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
932 DEBUGFUNC("ixgbe_get_mac_addr_generic");
934 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
935 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
937 for (i = 0; i < 4; i++)
938 mac_addr[i] = (u8)(rar_low >> (i*8));
940 for (i = 0; i < 2; i++)
941 mac_addr[i+4] = (u8)(rar_high >> (i*8));
943 return IXGBE_SUCCESS;
947 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
948 * @hw: pointer to hardware structure
949 * @link_status: the link status returned by the PCI config space
951 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
953 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
955 struct ixgbe_mac_info *mac = &hw->mac;
957 hw->bus.type = ixgbe_bus_type_pci_express;
959 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
960 case IXGBE_PCI_LINK_WIDTH_1:
961 hw->bus.width = ixgbe_bus_width_pcie_x1;
963 case IXGBE_PCI_LINK_WIDTH_2:
964 hw->bus.width = ixgbe_bus_width_pcie_x2;
966 case IXGBE_PCI_LINK_WIDTH_4:
967 hw->bus.width = ixgbe_bus_width_pcie_x4;
969 case IXGBE_PCI_LINK_WIDTH_8:
970 hw->bus.width = ixgbe_bus_width_pcie_x8;
973 hw->bus.width = ixgbe_bus_width_unknown;
977 switch (link_status & IXGBE_PCI_LINK_SPEED) {
978 case IXGBE_PCI_LINK_SPEED_2500:
979 hw->bus.speed = ixgbe_bus_speed_2500;
981 case IXGBE_PCI_LINK_SPEED_5000:
982 hw->bus.speed = ixgbe_bus_speed_5000;
984 case IXGBE_PCI_LINK_SPEED_8000:
985 hw->bus.speed = ixgbe_bus_speed_8000;
988 hw->bus.speed = ixgbe_bus_speed_unknown;
992 mac->ops.set_lan_id(hw);
996 * ixgbe_get_bus_info_generic - Generic set PCI bus info
997 * @hw: pointer to hardware structure
999 * Gets the PCI bus info (speed, width, type) then calls helper function to
1000 * store this data within the ixgbe_hw structure.
1002 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1006 DEBUGFUNC("ixgbe_get_bus_info_generic");
1008 /* Get the negotiated link width and speed from PCI config space */
1009 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1011 ixgbe_set_pci_config_data_generic(hw, link_status);
1013 return IXGBE_SUCCESS;
1017 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1018 * @hw: pointer to the HW structure
1020 * Determines the LAN function id by reading memory-mapped registers
1021 * and swaps the port value if requested.
1023 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1025 struct ixgbe_bus_info *bus = &hw->bus;
1028 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1030 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1031 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1032 bus->lan_id = bus->func;
1034 /* check for a port swap */
1035 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
1036 if (reg & IXGBE_FACTPS_LFS)
1041 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1042 * @hw: pointer to hardware structure
1044 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1045 * disables transmit and receive units. The adapter_stopped flag is used by
1046 * the shared code and drivers to determine if the adapter is in a stopped
1047 * state and should not touch the hardware.
1049 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1054 DEBUGFUNC("ixgbe_stop_adapter_generic");
1057 * Set the adapter_stopped flag so other driver functions stop touching
1060 hw->adapter_stopped = true;
1062 /* Disable the receive unit */
1063 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
1065 /* Clear interrupt mask to stop interrupts from being generated */
1066 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1068 /* Clear any pending interrupts, flush previous writes */
1069 IXGBE_READ_REG(hw, IXGBE_EICR);
1071 /* Disable the transmit unit. Each queue must be disabled. */
1072 for (i = 0; i < hw->mac.max_tx_queues; i++)
1073 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1075 /* Disable the receive unit by stopping each queue */
1076 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1077 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1078 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1079 reg_val |= IXGBE_RXDCTL_SWFLSH;
1080 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1083 /* flush all queues disables */
1084 IXGBE_WRITE_FLUSH(hw);
1088 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
1089 * access and verify no pending requests
1091 return ixgbe_disable_pcie_master(hw);
1095 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1096 * @hw: pointer to hardware structure
1097 * @index: led number to turn on
1099 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1101 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1103 DEBUGFUNC("ixgbe_led_on_generic");
1105 /* To turn on the LED, set mode to ON. */
1106 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1107 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1108 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1109 IXGBE_WRITE_FLUSH(hw);
1111 return IXGBE_SUCCESS;
1115 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1116 * @hw: pointer to hardware structure
1117 * @index: led number to turn off
1119 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1121 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1123 DEBUGFUNC("ixgbe_led_off_generic");
1125 /* To turn off the LED, set mode to OFF. */
1126 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1127 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1128 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1129 IXGBE_WRITE_FLUSH(hw);
1131 return IXGBE_SUCCESS;
1135 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1136 * @hw: pointer to hardware structure
1138 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1139 * ixgbe_hw struct in order to set up EEPROM access.
1141 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1143 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1147 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1149 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1150 eeprom->type = ixgbe_eeprom_none;
1151 /* Set default semaphore delay to 10ms which is a well
1153 eeprom->semaphore_delay = 10;
1154 /* Clear EEPROM page size, it will be initialized as needed */
1155 eeprom->word_page_size = 0;
1158 * Check for EEPROM present first.
1159 * If not present leave as none
1161 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1162 if (eec & IXGBE_EEC_PRES) {
1163 eeprom->type = ixgbe_eeprom_spi;
1166 * SPI EEPROM is assumed here. This code would need to
1167 * change if a future EEPROM is not SPI.
1169 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1170 IXGBE_EEC_SIZE_SHIFT);
1171 eeprom->word_size = 1 << (eeprom_size +
1172 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1175 if (eec & IXGBE_EEC_ADDR_SIZE)
1176 eeprom->address_bits = 16;
1178 eeprom->address_bits = 8;
1179 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1180 "%d\n", eeprom->type, eeprom->word_size,
1181 eeprom->address_bits);
1184 return IXGBE_SUCCESS;
1188 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1189 * @hw: pointer to hardware structure
1190 * @offset: offset within the EEPROM to write
1191 * @words: number of word(s)
1192 * @data: 16 bit word(s) to write to EEPROM
1194 * Reads 16 bit word(s) from EEPROM through bit-bang method
1196 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1197 u16 words, u16 *data)
1199 s32 status = IXGBE_SUCCESS;
1202 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1204 hw->eeprom.ops.init_params(hw);
1207 status = IXGBE_ERR_INVALID_ARGUMENT;
1211 if (offset + words > hw->eeprom.word_size) {
1212 status = IXGBE_ERR_EEPROM;
1217 * The EEPROM page size cannot be queried from the chip. We do lazy
1218 * initialization. It is worth to do that when we write large buffer.
1220 if ((hw->eeprom.word_page_size == 0) &&
1221 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1222 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1225 * We cannot hold synchronization semaphores for too long
1226 * to avoid other entity starvation. However it is more efficient
1227 * to read in bursts than synchronizing access for each word.
1229 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1230 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1231 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1232 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1235 if (status != IXGBE_SUCCESS)
1244 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1245 * @hw: pointer to hardware structure
1246 * @offset: offset within the EEPROM to be written to
1247 * @words: number of word(s)
1248 * @data: 16 bit word(s) to be written to the EEPROM
1250 * If ixgbe_eeprom_update_checksum is not called after this function, the
1251 * EEPROM will most likely contain an invalid checksum.
1253 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1254 u16 words, u16 *data)
1260 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1262 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1264 /* Prepare the EEPROM for writing */
1265 status = ixgbe_acquire_eeprom(hw);
1267 if (status == IXGBE_SUCCESS) {
1268 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1269 ixgbe_release_eeprom(hw);
1270 status = IXGBE_ERR_EEPROM;
1274 if (status == IXGBE_SUCCESS) {
1275 for (i = 0; i < words; i++) {
1276 ixgbe_standby_eeprom(hw);
1278 /* Send the WRITE ENABLE command (8 bit opcode ) */
1279 ixgbe_shift_out_eeprom_bits(hw,
1280 IXGBE_EEPROM_WREN_OPCODE_SPI,
1281 IXGBE_EEPROM_OPCODE_BITS);
1283 ixgbe_standby_eeprom(hw);
1286 * Some SPI eeproms use the 8th address bit embedded
1289 if ((hw->eeprom.address_bits == 8) &&
1290 ((offset + i) >= 128))
1291 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1293 /* Send the Write command (8-bit opcode + addr) */
1294 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1295 IXGBE_EEPROM_OPCODE_BITS);
1296 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1297 hw->eeprom.address_bits);
1299 page_size = hw->eeprom.word_page_size;
1301 /* Send the data in burst via SPI*/
1304 word = (word >> 8) | (word << 8);
1305 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1310 /* do not wrap around page */
1311 if (((offset + i) & (page_size - 1)) ==
1314 } while (++i < words);
1316 ixgbe_standby_eeprom(hw);
1319 /* Done with writing - release the EEPROM */
1320 ixgbe_release_eeprom(hw);
1327 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1328 * @hw: pointer to hardware structure
1329 * @offset: offset within the EEPROM to be written to
1330 * @data: 16 bit word to be written to the EEPROM
1332 * If ixgbe_eeprom_update_checksum is not called after this function, the
1333 * EEPROM will most likely contain an invalid checksum.
1335 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1339 DEBUGFUNC("ixgbe_write_eeprom_generic");
1341 hw->eeprom.ops.init_params(hw);
1343 if (offset >= hw->eeprom.word_size) {
1344 status = IXGBE_ERR_EEPROM;
1348 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1355 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1356 * @hw: pointer to hardware structure
1357 * @offset: offset within the EEPROM to be read
1358 * @data: read 16 bit words(s) from EEPROM
1359 * @words: number of word(s)
1361 * Reads 16 bit word(s) from EEPROM through bit-bang method
1363 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1364 u16 words, u16 *data)
1366 s32 status = IXGBE_SUCCESS;
1369 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1371 hw->eeprom.ops.init_params(hw);
1374 status = IXGBE_ERR_INVALID_ARGUMENT;
1378 if (offset + words > hw->eeprom.word_size) {
1379 status = IXGBE_ERR_EEPROM;
1384 * We cannot hold synchronization semaphores for too long
1385 * to avoid other entity starvation. However it is more efficient
1386 * to read in bursts than synchronizing access for each word.
1388 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1389 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1390 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1392 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1395 if (status != IXGBE_SUCCESS)
1404 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1405 * @hw: pointer to hardware structure
1406 * @offset: offset within the EEPROM to be read
1407 * @words: number of word(s)
1408 * @data: read 16 bit word(s) from EEPROM
1410 * Reads 16 bit word(s) from EEPROM through bit-bang method
1412 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1413 u16 words, u16 *data)
1417 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1420 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1422 /* Prepare the EEPROM for reading */
1423 status = ixgbe_acquire_eeprom(hw);
1425 if (status == IXGBE_SUCCESS) {
1426 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1427 ixgbe_release_eeprom(hw);
1428 status = IXGBE_ERR_EEPROM;
1432 if (status == IXGBE_SUCCESS) {
1433 for (i = 0; i < words; i++) {
1434 ixgbe_standby_eeprom(hw);
1436 * Some SPI eeproms use the 8th address bit embedded
1439 if ((hw->eeprom.address_bits == 8) &&
1440 ((offset + i) >= 128))
1441 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1443 /* Send the READ command (opcode + addr) */
1444 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1445 IXGBE_EEPROM_OPCODE_BITS);
1446 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1447 hw->eeprom.address_bits);
1449 /* Read the data. */
1450 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1451 data[i] = (word_in >> 8) | (word_in << 8);
1454 /* End this read operation */
1455 ixgbe_release_eeprom(hw);
1462 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1463 * @hw: pointer to hardware structure
1464 * @offset: offset within the EEPROM to be read
1465 * @data: read 16 bit value from EEPROM
1467 * Reads 16 bit value from EEPROM through bit-bang method
1469 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1474 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1476 hw->eeprom.ops.init_params(hw);
1478 if (offset >= hw->eeprom.word_size) {
1479 status = IXGBE_ERR_EEPROM;
1483 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1490 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1491 * @hw: pointer to hardware structure
1492 * @offset: offset of word in the EEPROM to read
1493 * @words: number of word(s)
1494 * @data: 16 bit word(s) from the EEPROM
1496 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1498 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1499 u16 words, u16 *data)
1502 s32 status = IXGBE_SUCCESS;
1505 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1507 hw->eeprom.ops.init_params(hw);
1510 status = IXGBE_ERR_INVALID_ARGUMENT;
1511 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1515 if (offset >= hw->eeprom.word_size) {
1516 status = IXGBE_ERR_EEPROM;
1517 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1521 for (i = 0; i < words; i++) {
1522 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1523 IXGBE_EEPROM_RW_REG_START;
1525 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1526 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1528 if (status == IXGBE_SUCCESS) {
1529 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1530 IXGBE_EEPROM_RW_REG_DATA);
1532 DEBUGOUT("Eeprom read timed out\n");
1541 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1542 * @hw: pointer to hardware structure
1543 * @offset: offset within the EEPROM to be used as a scratch pad
1545 * Discover EEPROM page size by writing marching data at given offset.
1546 * This function is called only when we are writing a new large buffer
1547 * at given offset so the data would be overwritten anyway.
1549 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1552 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1553 s32 status = IXGBE_SUCCESS;
1556 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1558 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1561 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1562 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1563 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1564 hw->eeprom.word_page_size = 0;
1565 if (status != IXGBE_SUCCESS)
1568 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1569 if (status != IXGBE_SUCCESS)
1573 * When writing in burst more than the actual page size
1574 * EEPROM address wraps around current page.
1576 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1578 DEBUGOUT1("Detected EEPROM page size = %d words.",
1579 hw->eeprom.word_page_size);
1585 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1586 * @hw: pointer to hardware structure
1587 * @offset: offset of word in the EEPROM to read
1588 * @data: word read from the EEPROM
1590 * Reads a 16 bit word from the EEPROM using the EERD register.
1592 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1594 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1598 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1599 * @hw: pointer to hardware structure
1600 * @offset: offset of word in the EEPROM to write
1601 * @words: number of word(s)
1602 * @data: word(s) write to the EEPROM
1604 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1606 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1607 u16 words, u16 *data)
1610 s32 status = IXGBE_SUCCESS;
1613 DEBUGFUNC("ixgbe_write_eewr_generic");
1615 hw->eeprom.ops.init_params(hw);
1618 status = IXGBE_ERR_INVALID_ARGUMENT;
1619 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1623 if (offset >= hw->eeprom.word_size) {
1624 status = IXGBE_ERR_EEPROM;
1625 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1629 for (i = 0; i < words; i++) {
1630 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1631 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1632 IXGBE_EEPROM_RW_REG_START;
1634 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1635 if (status != IXGBE_SUCCESS) {
1636 DEBUGOUT("Eeprom write EEWR timed out\n");
1640 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1642 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1643 if (status != IXGBE_SUCCESS) {
1644 DEBUGOUT("Eeprom write EEWR timed out\n");
1654 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1655 * @hw: pointer to hardware structure
1656 * @offset: offset of word in the EEPROM to write
1657 * @data: word write to the EEPROM
1659 * Write a 16 bit word to the EEPROM using the EEWR register.
1661 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1663 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1667 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1668 * @hw: pointer to hardware structure
1669 * @ee_reg: EEPROM flag for polling
1671 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1672 * read or write is done respectively.
1674 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1678 s32 status = IXGBE_ERR_EEPROM;
1680 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1682 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1683 if (ee_reg == IXGBE_NVM_POLL_READ)
1684 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1686 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1688 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1689 status = IXGBE_SUCCESS;
1695 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1696 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1697 "EEPROM read/write done polling timed out");
1703 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1704 * @hw: pointer to hardware structure
1706 * Prepares EEPROM for access using bit-bang method. This function should
1707 * be called before issuing a command to the EEPROM.
1709 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1711 s32 status = IXGBE_SUCCESS;
1715 DEBUGFUNC("ixgbe_acquire_eeprom");
1717 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1719 status = IXGBE_ERR_SWFW_SYNC;
1721 if (status == IXGBE_SUCCESS) {
1722 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1724 /* Request EEPROM Access */
1725 eec |= IXGBE_EEC_REQ;
1726 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1728 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1729 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1730 if (eec & IXGBE_EEC_GNT)
1735 /* Release if grant not acquired */
1736 if (!(eec & IXGBE_EEC_GNT)) {
1737 eec &= ~IXGBE_EEC_REQ;
1738 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1739 DEBUGOUT("Could not acquire EEPROM grant\n");
1741 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1742 status = IXGBE_ERR_EEPROM;
1745 /* Setup EEPROM for Read/Write */
1746 if (status == IXGBE_SUCCESS) {
1747 /* Clear CS and SK */
1748 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1749 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1750 IXGBE_WRITE_FLUSH(hw);
1758 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1759 * @hw: pointer to hardware structure
1761 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1763 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1765 s32 status = IXGBE_ERR_EEPROM;
1770 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1773 /* Get SMBI software semaphore between device drivers first */
1774 for (i = 0; i < timeout; i++) {
1776 * If the SMBI bit is 0 when we read it, then the bit will be
1777 * set and we have the semaphore
1779 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1780 if (!(swsm & IXGBE_SWSM_SMBI)) {
1781 status = IXGBE_SUCCESS;
1788 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1791 * this release is particularly important because our attempts
1792 * above to get the semaphore may have succeeded, and if there
1793 * was a timeout, we should unconditionally clear the semaphore
1794 * bits to free the driver to make progress
1796 ixgbe_release_eeprom_semaphore(hw);
1801 * If the SMBI bit is 0 when we read it, then the bit will be
1802 * set and we have the semaphore
1804 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1805 if (!(swsm & IXGBE_SWSM_SMBI))
1806 status = IXGBE_SUCCESS;
1809 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1810 if (status == IXGBE_SUCCESS) {
1811 for (i = 0; i < timeout; i++) {
1812 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1814 /* Set the SW EEPROM semaphore bit to request access */
1815 swsm |= IXGBE_SWSM_SWESMBI;
1816 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1819 * If we set the bit successfully then we got the
1822 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1823 if (swsm & IXGBE_SWSM_SWESMBI)
1830 * Release semaphores and return error if SW EEPROM semaphore
1831 * was not granted because we don't have access to the EEPROM
1834 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1835 "SWESMBI Software EEPROM semaphore not granted.\n");
1836 ixgbe_release_eeprom_semaphore(hw);
1837 status = IXGBE_ERR_EEPROM;
1840 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1841 "Software semaphore SMBI between device drivers "
1849 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1850 * @hw: pointer to hardware structure
1852 * This function clears hardware semaphore bits.
1854 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1858 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1860 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1862 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1863 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1864 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1865 IXGBE_WRITE_FLUSH(hw);
1869 * ixgbe_ready_eeprom - Polls for EEPROM ready
1870 * @hw: pointer to hardware structure
1872 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1874 s32 status = IXGBE_SUCCESS;
1878 DEBUGFUNC("ixgbe_ready_eeprom");
1881 * Read "Status Register" repeatedly until the LSB is cleared. The
1882 * EEPROM will signal that the command has been completed by clearing
1883 * bit 0 of the internal status register. If it's not cleared within
1884 * 5 milliseconds, then error out.
1886 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1887 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1888 IXGBE_EEPROM_OPCODE_BITS);
1889 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1890 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1894 ixgbe_standby_eeprom(hw);
1898 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1899 * devices (and only 0-5mSec on 5V devices)
1901 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1902 DEBUGOUT("SPI EEPROM Status error\n");
1903 status = IXGBE_ERR_EEPROM;
1910 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1911 * @hw: pointer to hardware structure
1913 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1917 DEBUGFUNC("ixgbe_standby_eeprom");
1919 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1921 /* Toggle CS to flush commands */
1922 eec |= IXGBE_EEC_CS;
1923 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1924 IXGBE_WRITE_FLUSH(hw);
1926 eec &= ~IXGBE_EEC_CS;
1927 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1928 IXGBE_WRITE_FLUSH(hw);
1933 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1934 * @hw: pointer to hardware structure
1935 * @data: data to send to the EEPROM
1936 * @count: number of bits to shift out
1938 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1945 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1947 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1950 * Mask is used to shift "count" bits of "data" out to the EEPROM
1951 * one bit at a time. Determine the starting bit based on count
1953 mask = 0x01 << (count - 1);
1955 for (i = 0; i < count; i++) {
1957 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1958 * "1", and then raising and then lowering the clock (the SK
1959 * bit controls the clock input to the EEPROM). A "0" is
1960 * shifted out to the EEPROM by setting "DI" to "0" and then
1961 * raising and then lowering the clock.
1964 eec |= IXGBE_EEC_DI;
1966 eec &= ~IXGBE_EEC_DI;
1968 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1969 IXGBE_WRITE_FLUSH(hw);
1973 ixgbe_raise_eeprom_clk(hw, &eec);
1974 ixgbe_lower_eeprom_clk(hw, &eec);
1977 * Shift mask to signify next bit of data to shift in to the
1983 /* We leave the "DI" bit set to "0" when we leave this routine. */
1984 eec &= ~IXGBE_EEC_DI;
1985 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1986 IXGBE_WRITE_FLUSH(hw);
1990 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1991 * @hw: pointer to hardware structure
1993 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1999 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2002 * In order to read a register from the EEPROM, we need to shift
2003 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2004 * the clock input to the EEPROM (setting the SK bit), and then reading
2005 * the value of the "DO" bit. During this "shifting in" process the
2006 * "DI" bit should always be clear.
2008 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2010 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2012 for (i = 0; i < count; i++) {
2014 ixgbe_raise_eeprom_clk(hw, &eec);
2016 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2018 eec &= ~(IXGBE_EEC_DI);
2019 if (eec & IXGBE_EEC_DO)
2022 ixgbe_lower_eeprom_clk(hw, &eec);
2029 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2030 * @hw: pointer to hardware structure
2031 * @eec: EEC register's current value
2033 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2035 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2038 * Raise the clock input to the EEPROM
2039 * (setting the SK bit), then delay
2041 *eec = *eec | IXGBE_EEC_SK;
2042 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2043 IXGBE_WRITE_FLUSH(hw);
2048 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2049 * @hw: pointer to hardware structure
2050 * @eecd: EECD's current value
2052 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2054 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2057 * Lower the clock input to the EEPROM (clearing the SK bit), then
2060 *eec = *eec & ~IXGBE_EEC_SK;
2061 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2062 IXGBE_WRITE_FLUSH(hw);
2067 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2068 * @hw: pointer to hardware structure
2070 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2074 DEBUGFUNC("ixgbe_release_eeprom");
2076 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2078 eec |= IXGBE_EEC_CS; /* Pull CS high */
2079 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2081 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2082 IXGBE_WRITE_FLUSH(hw);
2086 /* Stop requesting EEPROM access */
2087 eec &= ~IXGBE_EEC_REQ;
2088 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2090 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2092 /* Delay before attempt to obtain semaphore again to allow FW access */
2093 msec_delay(hw->eeprom.semaphore_delay);
2097 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2098 * @hw: pointer to hardware structure
2100 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2109 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2111 /* Include 0x0-0x3F in the checksum */
2112 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2113 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) {
2114 DEBUGOUT("EEPROM read failed\n");
2120 /* Include all data from pointers except for the fw pointer */
2121 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2122 hw->eeprom.ops.read(hw, i, &pointer);
2124 /* Make sure the pointer seems valid */
2125 if (pointer != 0xFFFF && pointer != 0) {
2126 hw->eeprom.ops.read(hw, pointer, &length);
2128 if (length != 0xFFFF && length != 0) {
2129 for (j = pointer+1; j <= pointer+length; j++) {
2130 hw->eeprom.ops.read(hw, j, &word);
2137 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2143 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2144 * @hw: pointer to hardware structure
2145 * @checksum_val: calculated checksum
2147 * Performs checksum calculation and validates the EEPROM checksum. If the
2148 * caller does not need checksum_val, the value can be NULL.
2150 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2155 u16 read_checksum = 0;
2157 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2160 * Read the first word from the EEPROM. If this times out or fails, do
2161 * not continue or we could be in for a very long wait while every
2164 status = hw->eeprom.ops.read(hw, 0, &checksum);
2166 if (status == IXGBE_SUCCESS) {
2167 checksum = hw->eeprom.ops.calc_checksum(hw);
2169 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2172 * Verify read checksum from EEPROM is the same as
2173 * calculated checksum
2175 if (read_checksum != checksum)
2176 status = IXGBE_ERR_EEPROM_CHECKSUM;
2178 /* If the user cares, return the calculated checksum */
2180 *checksum_val = checksum;
2182 DEBUGOUT("EEPROM read failed\n");
2189 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2190 * @hw: pointer to hardware structure
2192 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2197 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2200 * Read the first word from the EEPROM. If this times out or fails, do
2201 * not continue or we could be in for a very long wait while every
2204 status = hw->eeprom.ops.read(hw, 0, &checksum);
2206 if (status == IXGBE_SUCCESS) {
2207 checksum = hw->eeprom.ops.calc_checksum(hw);
2208 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
2211 DEBUGOUT("EEPROM read failed\n");
2218 * ixgbe_validate_mac_addr - Validate MAC address
2219 * @mac_addr: pointer to MAC address.
2221 * Tests a MAC address to ensure it is a valid Individual Address
2223 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2225 s32 status = IXGBE_SUCCESS;
2227 DEBUGFUNC("ixgbe_validate_mac_addr");
2229 /* Make sure it is not a multicast address */
2230 if (IXGBE_IS_MULTICAST(mac_addr)) {
2231 DEBUGOUT("MAC address is multicast\n");
2232 status = IXGBE_ERR_INVALID_MAC_ADDR;
2233 /* Not a broadcast address */
2234 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2235 DEBUGOUT("MAC address is broadcast\n");
2236 status = IXGBE_ERR_INVALID_MAC_ADDR;
2237 /* Reject the zero address */
2238 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2239 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2240 DEBUGOUT("MAC address is all zeros\n");
2241 status = IXGBE_ERR_INVALID_MAC_ADDR;
2247 * ixgbe_set_rar_generic - Set Rx address register
2248 * @hw: pointer to hardware structure
2249 * @index: Receive address register to write
2250 * @addr: Address to put into receive address register
2251 * @vmdq: VMDq "set" or "pool" index
2252 * @enable_addr: set flag that address is active
2254 * Puts an ethernet address into a receive address register.
2256 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2259 u32 rar_low, rar_high;
2260 u32 rar_entries = hw->mac.num_rar_entries;
2262 DEBUGFUNC("ixgbe_set_rar_generic");
2264 /* Make sure we are using a valid rar index range */
2265 if (index >= rar_entries) {
2266 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2267 "RAR index %d is out of range.\n", index);
2268 return IXGBE_ERR_INVALID_ARGUMENT;
2271 /* setup VMDq pool selection before this RAR gets enabled */
2272 hw->mac.ops.set_vmdq(hw, index, vmdq);
2275 * HW expects these in little endian so we reverse the byte
2276 * order from network order (big endian) to little endian
2278 rar_low = ((u32)addr[0] |
2279 ((u32)addr[1] << 8) |
2280 ((u32)addr[2] << 16) |
2281 ((u32)addr[3] << 24));
2283 * Some parts put the VMDq setting in the extra RAH bits,
2284 * so save everything except the lower 16 bits that hold part
2285 * of the address and the address valid bit.
2287 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2288 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2289 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2291 if (enable_addr != 0)
2292 rar_high |= IXGBE_RAH_AV;
2294 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2295 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2297 return IXGBE_SUCCESS;
2301 * ixgbe_clear_rar_generic - Remove Rx address register
2302 * @hw: pointer to hardware structure
2303 * @index: Receive address register to write
2305 * Clears an ethernet address from a receive address register.
2307 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2310 u32 rar_entries = hw->mac.num_rar_entries;
2312 DEBUGFUNC("ixgbe_clear_rar_generic");
2314 /* Make sure we are using a valid rar index range */
2315 if (index >= rar_entries) {
2316 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2317 "RAR index %d is out of range.\n", index);
2318 return IXGBE_ERR_INVALID_ARGUMENT;
2322 * Some parts put the VMDq setting in the extra RAH bits,
2323 * so save everything except the lower 16 bits that hold part
2324 * of the address and the address valid bit.
2326 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2327 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2329 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2330 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2332 /* clear VMDq pool/queue selection for this RAR */
2333 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2335 return IXGBE_SUCCESS;
2339 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2340 * @hw: pointer to hardware structure
2342 * Places the MAC address in receive address register 0 and clears the rest
2343 * of the receive address registers. Clears the multicast table. Assumes
2344 * the receiver is in reset when the routine is called.
2346 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2349 u32 rar_entries = hw->mac.num_rar_entries;
2351 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2354 * If the current mac address is valid, assume it is a software override
2355 * to the permanent address.
2356 * Otherwise, use the permanent address from the eeprom.
2358 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2359 IXGBE_ERR_INVALID_MAC_ADDR) {
2360 /* Get the MAC address from the RAR0 for later reference */
2361 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2363 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2364 hw->mac.addr[0], hw->mac.addr[1],
2366 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2367 hw->mac.addr[4], hw->mac.addr[5]);
2369 /* Setup the receive address. */
2370 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2371 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2372 hw->mac.addr[0], hw->mac.addr[1],
2374 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2375 hw->mac.addr[4], hw->mac.addr[5]);
2377 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2379 /* clear VMDq pool/queue selection for RAR 0 */
2380 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2382 hw->addr_ctrl.overflow_promisc = 0;
2384 hw->addr_ctrl.rar_used_count = 1;
2386 /* Zero out the other receive addresses. */
2387 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2388 for (i = 1; i < rar_entries; i++) {
2389 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2390 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2394 hw->addr_ctrl.mta_in_use = 0;
2395 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2397 DEBUGOUT(" Clearing MTA\n");
2398 for (i = 0; i < hw->mac.mcft_size; i++)
2399 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2401 ixgbe_init_uta_tables(hw);
2403 return IXGBE_SUCCESS;
2407 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2408 * @hw: pointer to hardware structure
2409 * @addr: new address
2411 * Adds it to unused receive address register or goes into promiscuous mode.
2413 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2415 u32 rar_entries = hw->mac.num_rar_entries;
2418 DEBUGFUNC("ixgbe_add_uc_addr");
2420 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2421 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2424 * Place this address in the RAR if there is room,
2425 * else put the controller into promiscuous mode
2427 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2428 rar = hw->addr_ctrl.rar_used_count;
2429 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2430 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2431 hw->addr_ctrl.rar_used_count++;
2433 hw->addr_ctrl.overflow_promisc++;
2436 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2440 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2441 * @hw: pointer to hardware structure
2442 * @addr_list: the list of new addresses
2443 * @addr_count: number of addresses
2444 * @next: iterator function to walk the address list
2446 * The given list replaces any existing list. Clears the secondary addrs from
2447 * receive address registers. Uses unused receive address registers for the
2448 * first secondary addresses, and falls back to promiscuous mode as needed.
2450 * Drivers using secondary unicast addresses must set user_set_promisc when
2451 * manually putting the device into promiscuous mode.
2453 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2454 u32 addr_count, ixgbe_mc_addr_itr next)
2458 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2463 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2466 * Clear accounting of old secondary address list,
2467 * don't count RAR[0]
2469 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2470 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2471 hw->addr_ctrl.overflow_promisc = 0;
2473 /* Zero out the other receive addresses */
2474 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2475 for (i = 0; i < uc_addr_in_use; i++) {
2476 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2477 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2480 /* Add the new addresses */
2481 for (i = 0; i < addr_count; i++) {
2482 DEBUGOUT(" Adding the secondary addresses:\n");
2483 addr = next(hw, &addr_list, &vmdq);
2484 ixgbe_add_uc_addr(hw, addr, vmdq);
2487 if (hw->addr_ctrl.overflow_promisc) {
2488 /* enable promisc if not already in overflow or set by user */
2489 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2490 DEBUGOUT(" Entering address overflow promisc mode\n");
2491 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2492 fctrl |= IXGBE_FCTRL_UPE;
2493 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2496 /* only disable if set by overflow, not by user */
2497 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2498 DEBUGOUT(" Leaving address overflow promisc mode\n");
2499 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2500 fctrl &= ~IXGBE_FCTRL_UPE;
2501 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2505 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2506 return IXGBE_SUCCESS;
2510 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2511 * @hw: pointer to hardware structure
2512 * @mc_addr: the multicast address
2514 * Extracts the 12 bits, from a multicast address, to determine which
2515 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2516 * incoming rx multicast addresses, to determine the bit-vector to check in
2517 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2518 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2519 * to mc_filter_type.
2521 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2525 DEBUGFUNC("ixgbe_mta_vector");
2527 switch (hw->mac.mc_filter_type) {
2528 case 0: /* use bits [47:36] of the address */
2529 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2531 case 1: /* use bits [46:35] of the address */
2532 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2534 case 2: /* use bits [45:34] of the address */
2535 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2537 case 3: /* use bits [43:32] of the address */
2538 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2540 default: /* Invalid mc_filter_type */
2541 DEBUGOUT("MC filter type param set incorrectly\n");
2546 /* vector can only be 12-bits or boundary will be exceeded */
2552 * ixgbe_set_mta - Set bit-vector in multicast table
2553 * @hw: pointer to hardware structure
2554 * @hash_value: Multicast address hash value
2556 * Sets the bit-vector in the multicast table.
2558 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2564 DEBUGFUNC("ixgbe_set_mta");
2566 hw->addr_ctrl.mta_in_use++;
2568 vector = ixgbe_mta_vector(hw, mc_addr);
2569 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2572 * The MTA is a register array of 128 32-bit registers. It is treated
2573 * like an array of 4096 bits. We want to set bit
2574 * BitArray[vector_value]. So we figure out what register the bit is
2575 * in, read it, OR in the new bit, then write back the new value. The
2576 * register is determined by the upper 7 bits of the vector value and
2577 * the bit within that register are determined by the lower 5 bits of
2580 vector_reg = (vector >> 5) & 0x7F;
2581 vector_bit = vector & 0x1F;
2582 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2586 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2587 * @hw: pointer to hardware structure
2588 * @mc_addr_list: the list of new multicast addresses
2589 * @mc_addr_count: number of addresses
2590 * @next: iterator function to walk the multicast address list
2591 * @clear: flag, when set clears the table beforehand
2593 * When the clear flag is set, the given list replaces any existing list.
2594 * Hashes the given addresses into the multicast table.
2596 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2597 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2603 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2606 * Set the new number of MC addresses that we are being requested to
2609 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2610 hw->addr_ctrl.mta_in_use = 0;
2612 /* Clear mta_shadow */
2614 DEBUGOUT(" Clearing MTA\n");
2615 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2618 /* Update mta_shadow */
2619 for (i = 0; i < mc_addr_count; i++) {
2620 DEBUGOUT(" Adding the multicast addresses:\n");
2621 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2625 for (i = 0; i < hw->mac.mcft_size; i++)
2626 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2627 hw->mac.mta_shadow[i]);
2629 if (hw->addr_ctrl.mta_in_use > 0)
2630 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2631 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2633 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2634 return IXGBE_SUCCESS;
2638 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2639 * @hw: pointer to hardware structure
2641 * Enables multicast address in RAR and the use of the multicast hash table.
2643 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2645 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2647 DEBUGFUNC("ixgbe_enable_mc_generic");
2649 if (a->mta_in_use > 0)
2650 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2651 hw->mac.mc_filter_type);
2653 return IXGBE_SUCCESS;
2657 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2658 * @hw: pointer to hardware structure
2660 * Disables multicast address in RAR and the use of the multicast hash table.
2662 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2664 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2666 DEBUGFUNC("ixgbe_disable_mc_generic");
2668 if (a->mta_in_use > 0)
2669 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2671 return IXGBE_SUCCESS;
2675 * ixgbe_fc_enable_generic - Enable flow control
2676 * @hw: pointer to hardware structure
2678 * Enable flow control according to the current settings.
2680 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2682 s32 ret_val = IXGBE_SUCCESS;
2683 u32 mflcn_reg, fccfg_reg;
2688 DEBUGFUNC("ixgbe_fc_enable_generic");
2690 /* Validate the water mark configuration */
2691 if (!hw->fc.pause_time) {
2692 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2696 /* Low water mark of zero causes XOFF floods */
2697 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2698 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2699 hw->fc.high_water[i]) {
2700 if (!hw->fc.low_water[i] ||
2701 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2702 DEBUGOUT("Invalid water mark configuration\n");
2703 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2709 /* Negotiate the fc mode to use */
2710 ixgbe_fc_autoneg(hw);
2712 /* Disable any previous flow control settings */
2713 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2714 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2716 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2717 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2720 * The possible values of fc.current_mode are:
2721 * 0: Flow control is completely disabled
2722 * 1: Rx flow control is enabled (we can receive pause frames,
2723 * but not send pause frames).
2724 * 2: Tx flow control is enabled (we can send pause frames but
2725 * we do not support receiving pause frames).
2726 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2729 switch (hw->fc.current_mode) {
2732 * Flow control is disabled by software override or autoneg.
2733 * The code below will actually disable it in the HW.
2736 case ixgbe_fc_rx_pause:
2738 * Rx Flow control is enabled and Tx Flow control is
2739 * disabled by software override. Since there really
2740 * isn't a way to advertise that we are capable of RX
2741 * Pause ONLY, we will advertise that we support both
2742 * symmetric and asymmetric Rx PAUSE. Later, we will
2743 * disable the adapter's ability to send PAUSE frames.
2745 mflcn_reg |= IXGBE_MFLCN_RFCE;
2747 case ixgbe_fc_tx_pause:
2749 * Tx Flow control is enabled, and Rx Flow control is
2750 * disabled by software override.
2752 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2755 /* Flow control (both Rx and Tx) is enabled by SW override. */
2756 mflcn_reg |= IXGBE_MFLCN_RFCE;
2757 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2760 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2761 "Flow control param set incorrectly\n");
2762 ret_val = IXGBE_ERR_CONFIG;
2767 /* Set 802.3x based flow control settings. */
2768 mflcn_reg |= IXGBE_MFLCN_DPF;
2769 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2770 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2773 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2774 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2775 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2776 hw->fc.high_water[i]) {
2777 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2778 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2779 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2781 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2783 * In order to prevent Tx hangs when the internal Tx
2784 * switch is enabled we must set the high water mark
2785 * to the Rx packet buffer size - 24KB. This allows
2786 * the Tx switch to function even under heavy Rx
2789 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2792 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2795 /* Configure pause time (2 TCs per register) */
2796 reg = hw->fc.pause_time * 0x00010001;
2797 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2798 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2800 /* Configure flow control refresh threshold value */
2801 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2808 * ixgbe_negotiate_fc - Negotiate flow control
2809 * @hw: pointer to hardware structure
2810 * @adv_reg: flow control advertised settings
2811 * @lp_reg: link partner's flow control settings
2812 * @adv_sym: symmetric pause bit in advertisement
2813 * @adv_asm: asymmetric pause bit in advertisement
2814 * @lp_sym: symmetric pause bit in link partner advertisement
2815 * @lp_asm: asymmetric pause bit in link partner advertisement
2817 * Find the intersection between advertised settings and link partner's
2818 * advertised settings
2820 STATIC s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2821 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2823 if ((!(adv_reg)) || (!(lp_reg))) {
2824 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2825 "Local or link partner's advertised flow control "
2826 "settings are NULL. Local: %x, link partner: %x\n",
2828 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2831 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2833 * Now we need to check if the user selected Rx ONLY
2834 * of pause frames. In this case, we had to advertise
2835 * FULL flow control because we could not advertise RX
2836 * ONLY. Hence, we must now check to see if we need to
2837 * turn OFF the TRANSMISSION of PAUSE frames.
2839 if (hw->fc.requested_mode == ixgbe_fc_full) {
2840 hw->fc.current_mode = ixgbe_fc_full;
2841 DEBUGOUT("Flow Control = FULL.\n");
2843 hw->fc.current_mode = ixgbe_fc_rx_pause;
2844 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2846 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2847 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2848 hw->fc.current_mode = ixgbe_fc_tx_pause;
2849 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2850 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2851 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2852 hw->fc.current_mode = ixgbe_fc_rx_pause;
2853 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2855 hw->fc.current_mode = ixgbe_fc_none;
2856 DEBUGOUT("Flow Control = NONE.\n");
2858 return IXGBE_SUCCESS;
2862 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2863 * @hw: pointer to hardware structure
2865 * Enable flow control according on 1 gig fiber.
2867 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2869 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2870 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2873 * On multispeed fiber at 1g, bail out if
2874 * - link is up but AN did not complete, or if
2875 * - link is up and AN completed but timed out
2878 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2879 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2880 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2881 ERROR_REPORT1(IXGBE_ERROR_POLLING,
2882 "Auto-Negotiation did not complete or timed out");
2886 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2887 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2889 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2890 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2891 IXGBE_PCS1GANA_ASM_PAUSE,
2892 IXGBE_PCS1GANA_SYM_PAUSE,
2893 IXGBE_PCS1GANA_ASM_PAUSE);
2900 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2901 * @hw: pointer to hardware structure
2903 * Enable flow control according to IEEE clause 37.
2905 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2907 u32 links2, anlp1_reg, autoc_reg, links;
2908 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2911 * On backplane, bail out if
2912 * - backplane autoneg was not completed, or if
2913 * - we are 82599 and link partner is not AN enabled
2915 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2916 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2917 ERROR_REPORT1(IXGBE_ERROR_POLLING,
2918 "Auto-Negotiation did not complete");
2922 if (hw->mac.type == ixgbe_mac_82599EB) {
2923 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2924 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2925 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2926 "Link partner is not AN enabled");
2931 * Read the 10g AN autoc and LP ability registers and resolve
2932 * local flow control settings accordingly
2934 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2935 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2937 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2938 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2939 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2946 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2947 * @hw: pointer to hardware structure
2949 * Enable flow control according to IEEE clause 37.
2951 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2953 u16 technology_ability_reg = 0;
2954 u16 lp_technology_ability_reg = 0;
2956 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2957 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2958 &technology_ability_reg);
2959 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2960 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2961 &lp_technology_ability_reg);
2963 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2964 (u32)lp_technology_ability_reg,
2965 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2966 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2970 * ixgbe_fc_autoneg - Configure flow control
2971 * @hw: pointer to hardware structure
2973 * Compares our advertised flow control capabilities to those advertised by
2974 * our link partner, and determines the proper flow control mode to use.
2976 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2978 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2979 ixgbe_link_speed speed;
2982 DEBUGFUNC("ixgbe_fc_autoneg");
2985 * AN should have completed when the cable was plugged in.
2986 * Look for reasons to bail out. Bail out if:
2987 * - FC autoneg is disabled, or if
2990 if (hw->fc.disable_fc_autoneg) {
2991 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2992 "Flow control autoneg is disabled");
2996 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2998 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3002 switch (hw->phy.media_type) {
3003 /* Autoneg flow control on fiber adapters */
3004 case ixgbe_media_type_fiber:
3005 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3006 ret_val = ixgbe_fc_autoneg_fiber(hw);
3009 /* Autoneg flow control on backplane adapters */
3010 case ixgbe_media_type_backplane:
3011 ret_val = ixgbe_fc_autoneg_backplane(hw);
3014 /* Autoneg flow control on copper adapters */
3015 case ixgbe_media_type_copper:
3016 if (ixgbe_device_supports_autoneg_fc(hw))
3017 ret_val = ixgbe_fc_autoneg_copper(hw);
3025 if (ret_val == IXGBE_SUCCESS) {
3026 hw->fc.fc_was_autonegged = true;
3028 hw->fc.fc_was_autonegged = false;
3029 hw->fc.current_mode = hw->fc.requested_mode;
3034 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3035 * @hw: pointer to hardware structure
3037 * System-wide timeout range is encoded in PCIe Device Control2 register.
3039 * Add 10% to specified maximum and return the number of times to poll for
3040 * completion timeout, in units of 100 microsec. Never return less than
3041 * 800 = 80 millisec.
3043 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3048 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3049 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3052 case IXGBE_PCIDEVCTRL2_65_130ms:
3053 pollcnt = 1300; /* 130 millisec */
3055 case IXGBE_PCIDEVCTRL2_260_520ms:
3056 pollcnt = 5200; /* 520 millisec */
3058 case IXGBE_PCIDEVCTRL2_1_2s:
3059 pollcnt = 20000; /* 2 sec */
3061 case IXGBE_PCIDEVCTRL2_4_8s:
3062 pollcnt = 80000; /* 8 sec */
3064 case IXGBE_PCIDEVCTRL2_17_34s:
3065 pollcnt = 34000; /* 34 sec */
3067 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3068 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3069 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3070 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3072 pollcnt = 800; /* 80 millisec minimum */
3076 /* add 10% to spec maximum */
3077 return (pollcnt * 11) / 10;
3081 * ixgbe_disable_pcie_master - Disable PCI-express master access
3082 * @hw: pointer to hardware structure
3084 * Disables PCI-Express master access and verifies there are no pending
3085 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3086 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3087 * is returned signifying master requests disabled.
3089 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3091 s32 status = IXGBE_SUCCESS;
3095 DEBUGFUNC("ixgbe_disable_pcie_master");
3097 /* Always set this bit to ensure any future transactions are blocked */
3098 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3100 /* Exit if master requests are blocked */
3101 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3102 IXGBE_REMOVED(hw->hw_addr))
3105 /* Poll for master request bit to clear */
3106 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3108 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3113 * Two consecutive resets are required via CTRL.RST per datasheet
3114 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3115 * of this need. The first reset prevents new master requests from
3116 * being issued by our device. We then must wait 1usec or more for any
3117 * remaining completions from the PCIe bus to trickle in, and then reset
3118 * again to clear out any effects they may have had on our device.
3120 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3121 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3124 * Before proceeding, make sure that the PCIe block does not have
3125 * transactions pending.
3127 poll = ixgbe_pcie_timeout_poll(hw);
3128 for (i = 0; i < poll; i++) {
3130 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3131 if (IXGBE_REMOVED(hw->hw_addr))
3133 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3137 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3138 "PCIe transaction pending bit also did not clear.\n");
3139 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3146 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3147 * @hw: pointer to hardware structure
3148 * @mask: Mask to specify which semaphore to acquire
3150 * Acquires the SWFW semaphore through the GSSR register for the specified
3151 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3153 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
3157 u32 fwmask = mask << 5;
3161 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3163 for (i = 0; i < timeout; i++) {
3165 * SW NVM semaphore bit is used for access to all
3166 * SW_FW_SYNC bits (not just NVM)
3168 if (ixgbe_get_eeprom_semaphore(hw))
3169 return IXGBE_ERR_SWFW_SYNC;
3171 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3172 if (!(gssr & (fwmask | swmask))) {
3174 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3175 ixgbe_release_eeprom_semaphore(hw);
3176 return IXGBE_SUCCESS;
3178 /* Resource is currently in use by FW or SW */
3179 ixgbe_release_eeprom_semaphore(hw);
3184 /* If time expired clear the bits holding the lock and retry */
3185 if (gssr & (fwmask | swmask))
3186 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3189 return IXGBE_ERR_SWFW_SYNC;
3193 * ixgbe_release_swfw_sync - Release SWFW semaphore
3194 * @hw: pointer to hardware structure
3195 * @mask: Mask to specify which semaphore to release
3197 * Releases the SWFW semaphore through the GSSR register for the specified
3198 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3200 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
3205 DEBUGFUNC("ixgbe_release_swfw_sync");
3207 ixgbe_get_eeprom_semaphore(hw);
3209 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3211 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3213 ixgbe_release_eeprom_semaphore(hw);
3217 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3218 * @hw: pointer to hardware structure
3220 * Stops the receive data path and waits for the HW to internally empty
3221 * the Rx security block
3223 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3225 #define IXGBE_MAX_SECRX_POLL 40
3230 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3233 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3234 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3235 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3236 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3237 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3238 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3241 /* Use interrupt-safe sleep just in case */
3245 /* For informational purposes only */
3246 if (i >= IXGBE_MAX_SECRX_POLL)
3247 DEBUGOUT("Rx unit being enabled before security "
3248 "path fully disabled. Continuing with init.\n");
3250 return IXGBE_SUCCESS;
3254 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3255 * @hw: pointer to hardware structure
3256 * @reg_val: Value we read from AUTOC
3258 * The default case requires no protection so just to the register read.
3260 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3263 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3264 return IXGBE_SUCCESS;
3268 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3269 * @hw: pointer to hardware structure
3270 * @reg_val: value to write to AUTOC
3271 * @locked: bool to indicate whether the SW/FW lock was already taken by
3274 * The default case requires no protection so just to the register write.
3276 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3278 UNREFERENCED_1PARAMETER(locked);
3280 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3281 return IXGBE_SUCCESS;
3285 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3286 * @hw: pointer to hardware structure
3288 * Enables the receive data path.
3290 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3294 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3296 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3297 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3298 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3299 IXGBE_WRITE_FLUSH(hw);
3301 return IXGBE_SUCCESS;
3305 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3306 * @hw: pointer to hardware structure
3307 * @regval: register value to write to RXCTRL
3309 * Enables the Rx DMA unit
3311 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3313 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3315 if (regval & IXGBE_RXCTRL_RXEN)
3316 ixgbe_enable_rx(hw);
3318 ixgbe_disable_rx(hw);
3320 return IXGBE_SUCCESS;
3324 * ixgbe_blink_led_start_generic - Blink LED based on index.
3325 * @hw: pointer to hardware structure
3326 * @index: led number to blink
3328 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3330 ixgbe_link_speed speed = 0;
3333 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3334 s32 ret_val = IXGBE_SUCCESS;
3335 bool locked = false;
3337 DEBUGFUNC("ixgbe_blink_led_start_generic");
3340 * Link must be up to auto-blink the LEDs;
3341 * Force it if link is down.
3343 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3346 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3347 if (ret_val != IXGBE_SUCCESS)
3350 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3351 autoc_reg |= IXGBE_AUTOC_FLU;
3353 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3354 if (ret_val != IXGBE_SUCCESS)
3357 IXGBE_WRITE_FLUSH(hw);
3361 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3362 led_reg |= IXGBE_LED_BLINK(index);
3363 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3364 IXGBE_WRITE_FLUSH(hw);
3371 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3372 * @hw: pointer to hardware structure
3373 * @index: led number to stop blinking
3375 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3378 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3379 s32 ret_val = IXGBE_SUCCESS;
3380 bool locked = false;
3382 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3384 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3385 if (ret_val != IXGBE_SUCCESS)
3388 autoc_reg &= ~IXGBE_AUTOC_FLU;
3389 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3391 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3392 if (ret_val != IXGBE_SUCCESS)
3395 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3396 led_reg &= ~IXGBE_LED_BLINK(index);
3397 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3398 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3399 IXGBE_WRITE_FLUSH(hw);
3406 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3407 * @hw: pointer to hardware structure
3408 * @san_mac_offset: SAN MAC address offset
3410 * This function will read the EEPROM location for the SAN MAC address
3411 * pointer, and returns the value at that location. This is used in both
3412 * get and set mac_addr routines.
3414 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3415 u16 *san_mac_offset)
3419 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3422 * First read the EEPROM pointer to see if the MAC addresses are
3425 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3428 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3429 "eeprom at offset %d failed",
3430 IXGBE_SAN_MAC_ADDR_PTR);
3437 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3438 * @hw: pointer to hardware structure
3439 * @san_mac_addr: SAN MAC address
3441 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3442 * per-port, so set_lan_id() must be called before reading the addresses.
3443 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3444 * upon for non-SFP connections, so we must call it here.
3446 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3448 u16 san_mac_data, san_mac_offset;
3452 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3455 * First read the EEPROM pointer to see if the MAC addresses are
3456 * available. If they're not, no point in calling set_lan_id() here.
3458 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3459 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3460 goto san_mac_addr_out;
3462 /* make sure we know which port we need to program */
3463 hw->mac.ops.set_lan_id(hw);
3464 /* apply the port offset to the address offset */
3465 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3466 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3467 for (i = 0; i < 3; i++) {
3468 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3471 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3472 "eeprom read at offset %d failed",
3474 goto san_mac_addr_out;
3476 san_mac_addr[i * 2] = (u8)(san_mac_data);
3477 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3480 return IXGBE_SUCCESS;
3484 * No addresses available in this EEPROM. It's not an
3485 * error though, so just wipe the local address and return.
3487 for (i = 0; i < 6; i++)
3488 san_mac_addr[i] = 0xFF;
3489 return IXGBE_SUCCESS;
3493 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3494 * @hw: pointer to hardware structure
3495 * @san_mac_addr: SAN MAC address
3497 * Write a SAN MAC address to the EEPROM.
3499 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3502 u16 san_mac_data, san_mac_offset;
3505 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3507 /* Look for SAN mac address pointer. If not defined, return */
3508 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3509 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3510 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3512 /* Make sure we know which port we need to write */
3513 hw->mac.ops.set_lan_id(hw);
3514 /* Apply the port offset to the address offset */
3515 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3516 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3518 for (i = 0; i < 3; i++) {
3519 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3520 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3521 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3525 return IXGBE_SUCCESS;
3529 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3530 * @hw: pointer to hardware structure
3532 * Read PCIe configuration space, and get the MSI-X vector count from
3533 * the capabilities table.
3535 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3541 switch (hw->mac.type) {
3542 case ixgbe_mac_82598EB:
3543 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3544 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3546 case ixgbe_mac_82599EB:
3547 case ixgbe_mac_X540:
3548 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3549 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3555 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3556 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3557 if (IXGBE_REMOVED(hw->hw_addr))
3559 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3561 /* MSI-X count is zero-based in HW */
3564 if (msix_count > max_msix_count)
3565 msix_count = max_msix_count;
3571 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3572 * @hw: pointer to hardware structure
3573 * @addr: Address to put into receive address register
3574 * @vmdq: VMDq pool to assign
3576 * Puts an ethernet address into a receive address register, or
3577 * finds the rar that it is aleady in; adds to the pool list
3579 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3581 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3582 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3584 u32 rar_low, rar_high;
3585 u32 addr_low, addr_high;
3587 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3589 /* swap bytes for HW little endian */
3590 addr_low = addr[0] | (addr[1] << 8)
3593 addr_high = addr[4] | (addr[5] << 8);
3596 * Either find the mac_id in rar or find the first empty space.
3597 * rar_highwater points to just after the highest currently used
3598 * rar in order to shorten the search. It grows when we add a new
3601 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3602 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3604 if (((IXGBE_RAH_AV & rar_high) == 0)
3605 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3606 first_empty_rar = rar;
3607 } else if ((rar_high & 0xFFFF) == addr_high) {
3608 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3609 if (rar_low == addr_low)
3610 break; /* found it already in the rars */
3614 if (rar < hw->mac.rar_highwater) {
3615 /* already there so just add to the pool bits */
3616 ixgbe_set_vmdq(hw, rar, vmdq);
3617 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3618 /* stick it into first empty RAR slot we found */
3619 rar = first_empty_rar;
3620 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3621 } else if (rar == hw->mac.rar_highwater) {
3622 /* add it to the top of the list and inc the highwater mark */
3623 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3624 hw->mac.rar_highwater++;
3625 } else if (rar >= hw->mac.num_rar_entries) {
3626 return IXGBE_ERR_INVALID_MAC_ADDR;
3630 * If we found rar[0], make sure the default pool bit (we use pool 0)
3631 * remains cleared to be sure default pool packets will get delivered
3634 ixgbe_clear_vmdq(hw, rar, 0);
3640 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3641 * @hw: pointer to hardware struct
3642 * @rar: receive address register index to disassociate
3643 * @vmdq: VMDq pool index to remove from the rar
3645 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3647 u32 mpsar_lo, mpsar_hi;
3648 u32 rar_entries = hw->mac.num_rar_entries;
3650 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3652 /* Make sure we are using a valid rar index range */
3653 if (rar >= rar_entries) {
3654 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3655 "RAR index %d is out of range.\n", rar);
3656 return IXGBE_ERR_INVALID_ARGUMENT;
3659 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3660 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3662 if (IXGBE_REMOVED(hw->hw_addr))
3665 if (!mpsar_lo && !mpsar_hi)
3668 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3670 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3674 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3677 } else if (vmdq < 32) {
3678 mpsar_lo &= ~(1 << vmdq);
3679 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3681 mpsar_hi &= ~(1 << (vmdq - 32));
3682 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3685 /* was that the last pool using this rar? */
3686 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3687 hw->mac.ops.clear_rar(hw, rar);
3689 return IXGBE_SUCCESS;
3693 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3694 * @hw: pointer to hardware struct
3695 * @rar: receive address register index to associate with a VMDq index
3696 * @vmdq: VMDq pool index
3698 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3701 u32 rar_entries = hw->mac.num_rar_entries;
3703 DEBUGFUNC("ixgbe_set_vmdq_generic");
3705 /* Make sure we are using a valid rar index range */
3706 if (rar >= rar_entries) {
3707 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3708 "RAR index %d is out of range.\n", rar);
3709 return IXGBE_ERR_INVALID_ARGUMENT;
3713 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3715 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3717 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3718 mpsar |= 1 << (vmdq - 32);
3719 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3721 return IXGBE_SUCCESS;
3725 * This function should only be involved in the IOV mode.
3726 * In IOV mode, Default pool is next pool after the number of
3727 * VFs advertized and not 0.
3728 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3730 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3731 * @hw: pointer to hardware struct
3732 * @vmdq: VMDq pool index
3734 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3736 u32 rar = hw->mac.san_mac_rar_index;
3738 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3741 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3742 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3744 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3745 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3748 return IXGBE_SUCCESS;
3752 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3753 * @hw: pointer to hardware structure
3755 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3759 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3760 DEBUGOUT(" Clearing UTA\n");
3762 for (i = 0; i < 128; i++)
3763 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3765 return IXGBE_SUCCESS;
3769 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3770 * @hw: pointer to hardware structure
3771 * @vlan: VLAN id to write to VLAN filter
3773 * return the VLVF index where this VLAN id should be placed
3776 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3779 u32 first_empty_slot = 0;
3782 /* short cut the special case */
3787 * Search for the vlan id in the VLVF entries. Save off the first empty
3788 * slot found along the way
3790 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3791 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3792 if (!bits && !(first_empty_slot))
3793 first_empty_slot = regindex;
3794 else if ((bits & 0x0FFF) == vlan)
3799 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3800 * in the VLVF. Else use the first empty VLVF register for this
3803 if (regindex >= IXGBE_VLVF_ENTRIES) {
3804 if (first_empty_slot)
3805 regindex = first_empty_slot;
3807 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
3808 "No space in VLVF.\n");
3809 regindex = IXGBE_ERR_NO_SPACE;
3817 * ixgbe_set_vfta_generic - Set VLAN filter table
3818 * @hw: pointer to hardware structure
3819 * @vlan: VLAN id to write to VLAN filter
3820 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3821 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3823 * Turn on/off specified VLAN in the VLAN filter table.
3825 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3832 s32 ret_val = IXGBE_SUCCESS;
3833 bool vfta_changed = false;
3835 DEBUGFUNC("ixgbe_set_vfta_generic");
3838 return IXGBE_ERR_PARAM;
3841 * this is a 2 part operation - first the VFTA, then the
3842 * VLVF and VLVFB if VT Mode is set
3843 * We don't write the VFTA until we know the VLVF part succeeded.
3847 * The VFTA is a bitstring made up of 128 32-bit registers
3848 * that enable the particular VLAN id, much like the MTA:
3849 * bits[11-5]: which register
3850 * bits[4-0]: which bit in the register
3852 regindex = (vlan >> 5) & 0x7F;
3853 bitindex = vlan & 0x1F;
3854 targetbit = (1 << bitindex);
3855 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3858 if (!(vfta & targetbit)) {
3860 vfta_changed = true;
3863 if ((vfta & targetbit)) {
3865 vfta_changed = true;
3870 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3872 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3874 if (ret_val != IXGBE_SUCCESS)
3878 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3880 return IXGBE_SUCCESS;
3884 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3885 * @hw: pointer to hardware structure
3886 * @vlan: VLAN id to write to VLAN filter
3887 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3888 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3889 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3892 * Turn on/off specified bit in VLVF table.
3894 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3895 bool vlan_on, bool *vfta_changed)
3899 DEBUGFUNC("ixgbe_set_vlvf_generic");
3902 return IXGBE_ERR_PARAM;
3904 /* If VT Mode is set
3906 * make sure the vlan is in VLVF
3907 * set the vind bit in the matching VLVFB
3909 * clear the pool bit and possibly the vind
3911 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3912 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3916 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3921 /* set the pool bit */
3923 bits = IXGBE_READ_REG(hw,
3924 IXGBE_VLVFB(vlvf_index * 2));
3925 bits |= (1 << vind);
3927 IXGBE_VLVFB(vlvf_index * 2),
3930 bits = IXGBE_READ_REG(hw,
3931 IXGBE_VLVFB((vlvf_index * 2) + 1));
3932 bits |= (1 << (vind - 32));
3934 IXGBE_VLVFB((vlvf_index * 2) + 1),
3938 /* clear the pool bit */
3940 bits = IXGBE_READ_REG(hw,
3941 IXGBE_VLVFB(vlvf_index * 2));
3942 bits &= ~(1 << vind);
3944 IXGBE_VLVFB(vlvf_index * 2),
3946 bits |= IXGBE_READ_REG(hw,
3947 IXGBE_VLVFB((vlvf_index * 2) + 1));
3949 bits = IXGBE_READ_REG(hw,
3950 IXGBE_VLVFB((vlvf_index * 2) + 1));
3951 bits &= ~(1 << (vind - 32));
3953 IXGBE_VLVFB((vlvf_index * 2) + 1),
3955 bits |= IXGBE_READ_REG(hw,
3956 IXGBE_VLVFB(vlvf_index * 2));
3961 * If there are still bits set in the VLVFB registers
3962 * for the VLAN ID indicated we need to see if the
3963 * caller is requesting that we clear the VFTA entry bit.
3964 * If the caller has requested that we clear the VFTA
3965 * entry bit but there are still pools/VFs using this VLAN
3966 * ID entry then ignore the request. We're not worried
3967 * about the case where we're turning the VFTA VLAN ID
3968 * entry bit on, only when requested to turn it off as
3969 * there may be multiple pools and/or VFs using the
3970 * VLAN ID entry. In that case we cannot clear the
3971 * VFTA bit until all pools/VFs using that VLAN ID have also
3972 * been cleared. This will be indicated by "bits" being
3976 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3977 (IXGBE_VLVF_VIEN | vlan));
3978 if ((!vlan_on) && (vfta_changed != NULL)) {
3979 /* someone wants to clear the vfta entry
3980 * but some pools/VFs are still using it.
3982 *vfta_changed = false;
3985 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3988 return IXGBE_SUCCESS;
3992 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3993 * @hw: pointer to hardware structure
3995 * Clears the VLAN filer table, and the VMDq index associated with the filter
3997 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4001 DEBUGFUNC("ixgbe_clear_vfta_generic");
4003 for (offset = 0; offset < hw->mac.vft_size; offset++)
4004 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4006 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4007 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4008 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4009 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
4012 return IXGBE_SUCCESS;
4016 * ixgbe_check_mac_link_generic - Determine link and speed status
4017 * @hw: pointer to hardware structure
4018 * @speed: pointer to link speed
4019 * @link_up: true when link is up
4020 * @link_up_wait_to_complete: bool used to wait for link up or not
4022 * Reads the links register to determine if link is up and the current speed
4024 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4025 bool *link_up, bool link_up_wait_to_complete)
4027 u32 links_reg, links_orig;
4030 DEBUGFUNC("ixgbe_check_mac_link_generic");
4032 /* clear the old state */
4033 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4035 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4037 if (links_orig != links_reg) {
4038 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4039 links_orig, links_reg);
4042 if (link_up_wait_to_complete) {
4043 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
4044 if (links_reg & IXGBE_LINKS_UP) {
4051 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4054 if (links_reg & IXGBE_LINKS_UP)
4060 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4061 IXGBE_LINKS_SPEED_10G_82599)
4062 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4063 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4064 IXGBE_LINKS_SPEED_1G_82599)
4065 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4066 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4067 IXGBE_LINKS_SPEED_100_82599)
4068 *speed = IXGBE_LINK_SPEED_100_FULL;
4070 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4072 return IXGBE_SUCCESS;
4076 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4078 * @hw: pointer to hardware structure
4079 * @wwnn_prefix: the alternative WWNN prefix
4080 * @wwpn_prefix: the alternative WWPN prefix
4082 * This function will read the EEPROM from the alternative SAN MAC address
4083 * block to check the support for the alternative WWNN/WWPN prefix support.
4085 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4089 u16 alt_san_mac_blk_offset;
4091 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4093 /* clear output first */
4094 *wwnn_prefix = 0xFFFF;
4095 *wwpn_prefix = 0xFFFF;
4097 /* check if alternative SAN MAC is supported */
4098 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4099 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4100 goto wwn_prefix_err;
4102 if ((alt_san_mac_blk_offset == 0) ||
4103 (alt_san_mac_blk_offset == 0xFFFF))
4104 goto wwn_prefix_out;
4106 /* check capability in alternative san mac address block */
4107 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4108 if (hw->eeprom.ops.read(hw, offset, &caps))
4109 goto wwn_prefix_err;
4110 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4111 goto wwn_prefix_out;
4113 /* get the corresponding prefix for WWNN/WWPN */
4114 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4115 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4116 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4117 "eeprom read at offset %d failed", offset);
4120 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4121 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4122 goto wwn_prefix_err;
4125 return IXGBE_SUCCESS;
4128 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4129 "eeprom read at offset %d failed", offset);
4130 return IXGBE_SUCCESS;
4134 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4135 * @hw: pointer to hardware structure
4136 * @bs: the fcoe boot status
4138 * This function will read the FCOE boot status from the iSCSI FCOE block
4140 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4142 u16 offset, caps, flags;
4145 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4147 /* clear output first */
4148 *bs = ixgbe_fcoe_bootstatus_unavailable;
4150 /* check if FCOE IBA block is present */
4151 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4152 status = hw->eeprom.ops.read(hw, offset, &caps);
4153 if (status != IXGBE_SUCCESS)
4156 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4159 /* check if iSCSI FCOE block is populated */
4160 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4161 if (status != IXGBE_SUCCESS)
4164 if ((offset == 0) || (offset == 0xFFFF))
4167 /* read fcoe flags in iSCSI FCOE block */
4168 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4169 status = hw->eeprom.ops.read(hw, offset, &flags);
4170 if (status != IXGBE_SUCCESS)
4173 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4174 *bs = ixgbe_fcoe_bootstatus_enabled;
4176 *bs = ixgbe_fcoe_bootstatus_disabled;
4183 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4184 * @hw: pointer to hardware structure
4185 * @enable: enable or disable switch for anti-spoofing
4186 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
4189 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
4192 int pf_target_reg = pf >> 3;
4193 int pf_target_shift = pf % 8;
4196 if (hw->mac.type == ixgbe_mac_82598EB)
4200 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
4203 * PFVFSPOOF register array is size 8 with 8 bits assigned to
4204 * MAC anti-spoof enables in each register array element.
4206 for (j = 0; j < pf_target_reg; j++)
4207 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4210 * The PF should be allowed to spoof so that it can support
4211 * emulation mode NICs. Do not set the bits assigned to the PF
4213 pfvfspoof &= (1 << pf_target_shift) - 1;
4214 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4217 * Remaining pools belong to the PF so they do not need to have
4218 * anti-spoofing enabled.
4220 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
4221 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
4225 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4226 * @hw: pointer to hardware structure
4227 * @enable: enable or disable switch for VLAN anti-spoofing
4228 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4231 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4233 int vf_target_reg = vf >> 3;
4234 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4237 if (hw->mac.type == ixgbe_mac_82598EB)
4240 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4242 pfvfspoof |= (1 << vf_target_shift);
4244 pfvfspoof &= ~(1 << vf_target_shift);
4245 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4249 * ixgbe_get_device_caps_generic - Get additional device capabilities
4250 * @hw: pointer to hardware structure
4251 * @device_caps: the EEPROM word with the extra device capabilities
4253 * This function will read the EEPROM location for the device capabilities,
4254 * and return the word through device_caps.
4256 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4258 DEBUGFUNC("ixgbe_get_device_caps_generic");
4260 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4262 return IXGBE_SUCCESS;
4266 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4267 * @hw: pointer to hardware structure
4270 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4275 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4277 /* Enable relaxed ordering */
4278 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4279 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4280 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4281 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4284 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4285 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4286 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4287 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4288 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4294 * ixgbe_calculate_checksum - Calculate checksum for buffer
4295 * @buffer: pointer to EEPROM
4296 * @length: size of EEPROM to calculate a checksum for
4297 * Calculates the checksum for some buffer on a specified length. The
4298 * checksum calculated is returned.
4300 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4305 DEBUGFUNC("ixgbe_calculate_checksum");
4310 for (i = 0; i < length; i++)
4313 return (u8) (0 - sum);
4317 * ixgbe_host_interface_command - Issue command to manageability block
4318 * @hw: pointer to the HW structure
4319 * @buffer: contains the command to write and where the return status will
4321 * @length: length of buffer, must be multiple of 4 bytes
4323 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4324 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
4326 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4330 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4331 u8 buf_len, dword_len;
4333 s32 ret_val = IXGBE_SUCCESS;
4335 DEBUGFUNC("ixgbe_host_interface_command");
4337 if (length == 0 || length & 0x3 ||
4338 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4339 DEBUGOUT("Buffer length failure.\n");
4340 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4344 /* Check that the host interface is enabled. */
4345 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4346 if ((hicr & IXGBE_HICR_EN) == 0) {
4347 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4348 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4352 /* Calculate length in DWORDs */
4353 dword_len = length >> 2;
4356 * The device driver writes the relevant command block
4357 * into the ram area.
4359 for (i = 0; i < dword_len; i++)
4360 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4361 i, IXGBE_CPU_TO_LE32(buffer[i]));
4363 /* Setting this bit tells the ARC that a new command is pending. */
4364 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4366 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
4367 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4368 if (!(hicr & IXGBE_HICR_C))
4373 /* Check command successful completion. */
4374 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
4375 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
4376 DEBUGOUT("Command has failed with no status valid.\n");
4377 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4381 /* Calculate length in DWORDs */
4382 dword_len = hdr_size >> 2;
4384 /* first pull in the header so we know the buffer length */
4385 for (bi = 0; bi < dword_len; bi++) {
4386 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4387 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4390 /* If there is any thing in data position pull it in */
4391 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4395 if (length < (buf_len + hdr_size)) {
4396 DEBUGOUT("Buffer not large enough for reply message.\n");
4397 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4401 /* Calculate length in DWORDs, add 3 for odd lengths */
4402 dword_len = (buf_len + 3) >> 2;
4404 /* Pull in the rest of the buffer (bi is where we left off)*/
4405 for (; bi <= dword_len; bi++) {
4406 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4407 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4415 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4416 * @hw: pointer to the HW structure
4417 * @maj: driver version major number
4418 * @min: driver version minor number
4419 * @build: driver version build number
4420 * @sub: driver version sub build number
4422 * Sends driver version number to firmware through the manageability
4423 * block. On success return IXGBE_SUCCESS
4424 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4425 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4427 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4430 struct ixgbe_hic_drv_info fw_cmd;
4432 s32 ret_val = IXGBE_SUCCESS;
4434 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4436 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
4438 ret_val = IXGBE_ERR_SWFW_SYNC;
4442 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4443 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4444 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4445 fw_cmd.port_num = (u8)hw->bus.func;
4446 fw_cmd.ver_maj = maj;
4447 fw_cmd.ver_min = min;
4448 fw_cmd.ver_build = build;
4449 fw_cmd.ver_sub = sub;
4450 fw_cmd.hdr.checksum = 0;
4451 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4452 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4456 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4457 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4459 if (ret_val != IXGBE_SUCCESS)
4462 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4463 FW_CEM_RESP_STATUS_SUCCESS)
4464 ret_val = IXGBE_SUCCESS;
4466 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4471 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4477 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4478 * @hw: pointer to hardware structure
4479 * @num_pb: number of packet buffers to allocate
4480 * @headroom: reserve n KB of headroom
4481 * @strategy: packet buffer allocation strategy
4483 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4486 u32 pbsize = hw->mac.rx_pb_size;
4488 u32 rxpktsize, txpktsize, txpbthresh;
4490 /* Reserve headroom */
4496 /* Divide remaining packet buffer space amongst the number of packet
4497 * buffers requested using supplied strategy.
4500 case PBA_STRATEGY_WEIGHTED:
4501 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4502 * buffer with 5/8 of the packet buffer space.
4504 rxpktsize = (pbsize * 5) / (num_pb * 4);
4505 pbsize -= rxpktsize * (num_pb / 2);
4506 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4507 for (; i < (num_pb / 2); i++)
4508 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4509 /* Fall through to configure remaining packet buffers */
4510 case PBA_STRATEGY_EQUAL:
4511 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4512 for (; i < num_pb; i++)
4513 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4519 /* Only support an equally distributed Tx packet buffer strategy. */
4520 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4521 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4522 for (i = 0; i < num_pb; i++) {
4523 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4524 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4527 /* Clear unused TCs, if any, to zero buffer size*/
4528 for (; i < IXGBE_MAX_PB; i++) {
4529 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4530 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4531 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4536 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4537 * @hw: pointer to the hardware structure
4539 * The 82599 and x540 MACs can experience issues if TX work is still pending
4540 * when a reset occurs. This function prevents this by flushing the PCIe
4541 * buffers on the system.
4543 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4545 u32 gcr_ext, hlreg0;
4548 * If double reset is not requested then all transactions should
4549 * already be clear and as such there is no work to do
4551 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4555 * Set loopback enable to prevent any transmits from being sent
4556 * should the link come up. This assumes that the RXCTRL.RXEN bit
4557 * has already been cleared.
4559 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4560 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4562 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4563 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4564 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4565 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4567 /* Flush all writes and allow 20usec for all transactions to clear */
4568 IXGBE_WRITE_FLUSH(hw);
4571 /* restore previous register values */
4572 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4573 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4578 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4579 * @hw: pointer to hardware structure
4580 * @map: pointer to u8 arr for returning map
4582 * Read the rtrup2tc HW register and resolve its content into map
4584 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4588 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4589 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4590 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4591 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4595 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4600 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4601 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4602 if (hw->mac.type != ixgbe_mac_82598EB) {
4603 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4604 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4605 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4606 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4607 hw->mac.set_lben = true;
4609 hw->mac.set_lben = false;
4612 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4613 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4617 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4622 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4623 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4625 if (hw->mac.type != ixgbe_mac_82598EB) {
4626 if (hw->mac.set_lben) {
4627 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4628 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4629 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4630 hw->mac.set_lben = false;