1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
39 #ident "$Id: ixgbe_common.c,v 1.382 2013/11/22 01:02:01 jtkirshe Exp $"
41 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
42 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
44 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
46 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
48 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
49 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
51 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
53 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
54 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
56 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
57 u16 words, u16 *data);
58 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
64 * ixgbe_init_ops_generic - Inits function ptrs
65 * @hw: pointer to the hardware structure
67 * Initialize the function pointers.
69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
72 struct ixgbe_mac_info *mac = &hw->mac;
73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
75 DEBUGFUNC("ixgbe_init_ops_generic");
78 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
80 if (eec & IXGBE_EEC_PRES) {
81 eeprom->ops.read = &ixgbe_read_eerd_generic;
82 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
84 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
85 eeprom->ops.read_buffer =
86 &ixgbe_read_eeprom_buffer_bit_bang_generic;
88 eeprom->ops.write = &ixgbe_write_eeprom_generic;
89 eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
90 eeprom->ops.validate_checksum =
91 &ixgbe_validate_eeprom_checksum_generic;
92 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
93 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
96 mac->ops.init_hw = &ixgbe_init_hw_generic;
97 mac->ops.reset_hw = NULL;
98 mac->ops.start_hw = &ixgbe_start_hw_generic;
99 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
100 mac->ops.get_media_type = NULL;
101 mac->ops.get_supported_physical_layer = NULL;
102 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
103 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
104 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
105 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
106 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
107 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
108 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
109 mac->ops.prot_autoc_read = &prot_autoc_read_generic;
110 mac->ops.prot_autoc_write = &prot_autoc_write_generic;
113 mac->ops.led_on = &ixgbe_led_on_generic;
114 mac->ops.led_off = &ixgbe_led_off_generic;
115 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
116 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
118 /* RAR, Multicast, VLAN */
119 mac->ops.set_rar = &ixgbe_set_rar_generic;
120 mac->ops.clear_rar = &ixgbe_clear_rar_generic;
121 mac->ops.insert_mac_addr = NULL;
122 mac->ops.set_vmdq = NULL;
123 mac->ops.clear_vmdq = NULL;
124 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
125 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
126 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
127 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
128 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
129 mac->ops.clear_vfta = NULL;
130 mac->ops.set_vfta = NULL;
131 mac->ops.set_vlvf = NULL;
132 mac->ops.init_uta_tables = NULL;
133 mac->ops.enable_rx = &ixgbe_enable_rx_generic;
134 mac->ops.disable_rx = &ixgbe_disable_rx_generic;
137 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
140 mac->ops.get_link_capabilities = NULL;
141 mac->ops.setup_link = NULL;
142 mac->ops.check_link = NULL;
143 mac->ops.dmac_config = NULL;
144 mac->ops.dmac_update_tcs = NULL;
145 mac->ops.dmac_config_tcs = NULL;
147 return IXGBE_SUCCESS;
151 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
153 * @hw: pointer to hardware structure
155 * This function returns true if the device supports flow control
156 * autonegotiation, and false if it does not.
159 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
161 bool supported = false;
162 ixgbe_link_speed speed;
165 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
167 switch (hw->phy.media_type) {
168 case ixgbe_media_type_fiber_qsfp:
169 case ixgbe_media_type_fiber:
170 hw->mac.ops.check_link(hw, &speed, &link_up, false);
171 /* if link is down, assume supported */
173 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
178 case ixgbe_media_type_backplane:
181 case ixgbe_media_type_copper:
182 /* only some copper devices support flow control autoneg */
183 switch (hw->device_id) {
184 case IXGBE_DEV_ID_82599_T3_LOM:
185 case IXGBE_DEV_ID_X540T:
186 case IXGBE_DEV_ID_X540T1:
196 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
197 "Device %x does not support flow control autoneg",
203 * ixgbe_setup_fc - Set up flow control
204 * @hw: pointer to hardware structure
206 * Called at init time to set up flow control.
208 STATIC s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
210 s32 ret_val = IXGBE_SUCCESS;
211 u32 reg = 0, reg_bp = 0;
215 DEBUGFUNC("ixgbe_setup_fc");
217 /* Validate the requested mode */
218 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
219 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
220 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
221 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
226 * 10gig parts do not have a word in the EEPROM to determine the
227 * default flow control setting, so we explicitly set it to full.
229 if (hw->fc.requested_mode == ixgbe_fc_default)
230 hw->fc.requested_mode = ixgbe_fc_full;
233 * Set up the 1G and 10G flow control advertisement registers so the
234 * HW will be able to do fc autoneg once the cable is plugged in. If
235 * we link at 10G, the 1G advertisement is harmless and vice versa.
237 switch (hw->phy.media_type) {
238 case ixgbe_media_type_backplane:
239 /* some MAC's need RMW protection on AUTOC */
240 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
241 if (ret_val != IXGBE_SUCCESS)
244 /* only backplane uses autoc so fall though */
245 case ixgbe_media_type_fiber_qsfp:
246 case ixgbe_media_type_fiber:
247 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
250 case ixgbe_media_type_copper:
251 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
252 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
259 * The possible values of fc.requested_mode are:
260 * 0: Flow control is completely disabled
261 * 1: Rx flow control is enabled (we can receive pause frames,
262 * but not send pause frames).
263 * 2: Tx flow control is enabled (we can send pause frames but
264 * we do not support receiving pause frames).
265 * 3: Both Rx and Tx flow control (symmetric) are enabled.
268 switch (hw->fc.requested_mode) {
270 /* Flow control completely disabled by software override. */
271 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
272 if (hw->phy.media_type == ixgbe_media_type_backplane)
273 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
274 IXGBE_AUTOC_ASM_PAUSE);
275 else if (hw->phy.media_type == ixgbe_media_type_copper)
276 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
278 case ixgbe_fc_tx_pause:
280 * Tx Flow control is enabled, and Rx Flow control is
281 * disabled by software override.
283 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
284 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
285 if (hw->phy.media_type == ixgbe_media_type_backplane) {
286 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
287 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
288 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
289 reg_cu |= IXGBE_TAF_ASM_PAUSE;
290 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
293 case ixgbe_fc_rx_pause:
295 * Rx Flow control is enabled and Tx Flow control is
296 * disabled by software override. Since there really
297 * isn't a way to advertise that we are capable of RX
298 * Pause ONLY, we will advertise that we support both
299 * symmetric and asymmetric Rx PAUSE, as such we fall
300 * through to the fc_full statement. Later, we will
301 * disable the adapter's ability to send PAUSE frames.
304 /* Flow control (both Rx and Tx) is enabled by SW override. */
305 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
306 if (hw->phy.media_type == ixgbe_media_type_backplane)
307 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
308 IXGBE_AUTOC_ASM_PAUSE;
309 else if (hw->phy.media_type == ixgbe_media_type_copper)
310 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
313 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
314 "Flow control param set incorrectly\n");
315 ret_val = IXGBE_ERR_CONFIG;
320 if (hw->mac.type < ixgbe_mac_X540) {
322 * Enable auto-negotiation between the MAC & PHY;
323 * the MAC will advertise clause 37 flow control.
325 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
326 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
328 /* Disable AN timeout */
329 if (hw->fc.strict_ieee)
330 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
332 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
333 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
337 * AUTOC restart handles negotiation of 1G and 10G on backplane
338 * and copper. There is no need to set the PCS1GCTL register.
341 if (hw->phy.media_type == ixgbe_media_type_backplane) {
342 reg_bp |= IXGBE_AUTOC_AN_RESTART;
343 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
346 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
347 (ixgbe_device_supports_autoneg_fc(hw))) {
348 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
349 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
352 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
358 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
359 * @hw: pointer to hardware structure
361 * Starts the hardware by filling the bus info structure and media type, clears
362 * all on chip counters, initializes receive address registers, multicast
363 * table, VLAN filter table, calls routine to set up link and flow control
364 * settings, and leaves transmit and receive units disabled and uninitialized
366 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
371 DEBUGFUNC("ixgbe_start_hw_generic");
373 /* Set the media type */
374 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
376 /* PHY ops initialization must be done in reset_hw() */
378 /* Clear the VLAN filter table */
379 hw->mac.ops.clear_vfta(hw);
381 /* Clear statistics registers */
382 hw->mac.ops.clear_hw_cntrs(hw);
384 /* Set No Snoop Disable */
385 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
386 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
387 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
388 IXGBE_WRITE_FLUSH(hw);
390 /* Setup flow control */
391 ret_val = ixgbe_setup_fc(hw);
392 if (ret_val != IXGBE_SUCCESS)
395 /* Clear adapter stopped flag */
396 hw->adapter_stopped = false;
403 * ixgbe_start_hw_gen2 - Init sequence for common device family
404 * @hw: pointer to hw structure
406 * Performs the init sequence common to the second generation
408 * Devices in the second generation:
412 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
417 /* Clear the rate limiters */
418 for (i = 0; i < hw->mac.max_tx_queues; i++) {
419 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
420 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
422 IXGBE_WRITE_FLUSH(hw);
424 /* Disable relaxed ordering */
425 for (i = 0; i < hw->mac.max_tx_queues; i++) {
426 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
427 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
428 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
431 for (i = 0; i < hw->mac.max_rx_queues; i++) {
432 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
433 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
434 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
435 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
438 return IXGBE_SUCCESS;
442 * ixgbe_init_hw_generic - Generic hardware initialization
443 * @hw: pointer to hardware structure
445 * Initialize the hardware by resetting the hardware, filling the bus info
446 * structure and media type, clears all on chip counters, initializes receive
447 * address registers, multicast table, VLAN filter table, calls routine to set
448 * up link and flow control settings, and leaves transmit and receive units
449 * disabled and uninitialized
451 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
455 DEBUGFUNC("ixgbe_init_hw_generic");
457 /* Reset the hardware */
458 status = hw->mac.ops.reset_hw(hw);
460 if (status == IXGBE_SUCCESS) {
462 status = hw->mac.ops.start_hw(hw);
469 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
470 * @hw: pointer to hardware structure
472 * Clears all hardware statistics counters by reading them from the hardware
473 * Statistics counters are clear on read.
475 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
479 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
481 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
482 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
483 IXGBE_READ_REG(hw, IXGBE_ERRBC);
484 IXGBE_READ_REG(hw, IXGBE_MSPDC);
485 for (i = 0; i < 8; i++)
486 IXGBE_READ_REG(hw, IXGBE_MPC(i));
488 IXGBE_READ_REG(hw, IXGBE_MLFC);
489 IXGBE_READ_REG(hw, IXGBE_MRFC);
490 IXGBE_READ_REG(hw, IXGBE_RLEC);
491 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
492 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
493 if (hw->mac.type >= ixgbe_mac_82599EB) {
494 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
495 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
497 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
498 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
501 for (i = 0; i < 8; i++) {
502 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
503 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
504 if (hw->mac.type >= ixgbe_mac_82599EB) {
505 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
506 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
508 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
509 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
512 if (hw->mac.type >= ixgbe_mac_82599EB)
513 for (i = 0; i < 8; i++)
514 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
515 IXGBE_READ_REG(hw, IXGBE_PRC64);
516 IXGBE_READ_REG(hw, IXGBE_PRC127);
517 IXGBE_READ_REG(hw, IXGBE_PRC255);
518 IXGBE_READ_REG(hw, IXGBE_PRC511);
519 IXGBE_READ_REG(hw, IXGBE_PRC1023);
520 IXGBE_READ_REG(hw, IXGBE_PRC1522);
521 IXGBE_READ_REG(hw, IXGBE_GPRC);
522 IXGBE_READ_REG(hw, IXGBE_BPRC);
523 IXGBE_READ_REG(hw, IXGBE_MPRC);
524 IXGBE_READ_REG(hw, IXGBE_GPTC);
525 IXGBE_READ_REG(hw, IXGBE_GORCL);
526 IXGBE_READ_REG(hw, IXGBE_GORCH);
527 IXGBE_READ_REG(hw, IXGBE_GOTCL);
528 IXGBE_READ_REG(hw, IXGBE_GOTCH);
529 if (hw->mac.type == ixgbe_mac_82598EB)
530 for (i = 0; i < 8; i++)
531 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
532 IXGBE_READ_REG(hw, IXGBE_RUC);
533 IXGBE_READ_REG(hw, IXGBE_RFC);
534 IXGBE_READ_REG(hw, IXGBE_ROC);
535 IXGBE_READ_REG(hw, IXGBE_RJC);
536 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
537 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
538 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
539 IXGBE_READ_REG(hw, IXGBE_TORL);
540 IXGBE_READ_REG(hw, IXGBE_TORH);
541 IXGBE_READ_REG(hw, IXGBE_TPR);
542 IXGBE_READ_REG(hw, IXGBE_TPT);
543 IXGBE_READ_REG(hw, IXGBE_PTC64);
544 IXGBE_READ_REG(hw, IXGBE_PTC127);
545 IXGBE_READ_REG(hw, IXGBE_PTC255);
546 IXGBE_READ_REG(hw, IXGBE_PTC511);
547 IXGBE_READ_REG(hw, IXGBE_PTC1023);
548 IXGBE_READ_REG(hw, IXGBE_PTC1522);
549 IXGBE_READ_REG(hw, IXGBE_MPTC);
550 IXGBE_READ_REG(hw, IXGBE_BPTC);
551 for (i = 0; i < 16; i++) {
552 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
553 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
554 if (hw->mac.type >= ixgbe_mac_82599EB) {
555 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
556 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
557 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
558 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
559 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
561 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
562 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
566 if (hw->mac.type == ixgbe_mac_X540) {
568 ixgbe_identify_phy(hw);
569 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
570 IXGBE_MDIO_PCS_DEV_TYPE, &i);
571 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
572 IXGBE_MDIO_PCS_DEV_TYPE, &i);
573 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
574 IXGBE_MDIO_PCS_DEV_TYPE, &i);
575 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
576 IXGBE_MDIO_PCS_DEV_TYPE, &i);
579 return IXGBE_SUCCESS;
583 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
584 * @hw: pointer to hardware structure
585 * @pba_num: stores the part number string from the EEPROM
586 * @pba_num_size: part number string buffer length
588 * Reads the part number string from the EEPROM.
590 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
599 DEBUGFUNC("ixgbe_read_pba_string_generic");
601 if (pba_num == NULL) {
602 DEBUGOUT("PBA string buffer was null\n");
603 return IXGBE_ERR_INVALID_ARGUMENT;
606 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
608 DEBUGOUT("NVM Read Error\n");
612 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
614 DEBUGOUT("NVM Read Error\n");
619 * if data is not ptr guard the PBA must be in legacy format which
620 * means pba_ptr is actually our second data word for the PBA number
621 * and we can decode it into an ascii string
623 if (data != IXGBE_PBANUM_PTR_GUARD) {
624 DEBUGOUT("NVM PBA number is not stored as string\n");
626 /* we will need 11 characters to store the PBA */
627 if (pba_num_size < 11) {
628 DEBUGOUT("PBA string buffer too small\n");
629 return IXGBE_ERR_NO_SPACE;
632 /* extract hex string from data and pba_ptr */
633 pba_num[0] = (data >> 12) & 0xF;
634 pba_num[1] = (data >> 8) & 0xF;
635 pba_num[2] = (data >> 4) & 0xF;
636 pba_num[3] = data & 0xF;
637 pba_num[4] = (pba_ptr >> 12) & 0xF;
638 pba_num[5] = (pba_ptr >> 8) & 0xF;
641 pba_num[8] = (pba_ptr >> 4) & 0xF;
642 pba_num[9] = pba_ptr & 0xF;
644 /* put a null character on the end of our string */
647 /* switch all the data but the '-' to hex char */
648 for (offset = 0; offset < 10; offset++) {
649 if (pba_num[offset] < 0xA)
650 pba_num[offset] += '0';
651 else if (pba_num[offset] < 0x10)
652 pba_num[offset] += 'A' - 0xA;
655 return IXGBE_SUCCESS;
658 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
660 DEBUGOUT("NVM Read Error\n");
664 if (length == 0xFFFF || length == 0) {
665 DEBUGOUT("NVM PBA number section invalid length\n");
666 return IXGBE_ERR_PBA_SECTION;
669 /* check if pba_num buffer is big enough */
670 if (pba_num_size < (((u32)length * 2) - 1)) {
671 DEBUGOUT("PBA string buffer too small\n");
672 return IXGBE_ERR_NO_SPACE;
675 /* trim pba length from start of string */
679 for (offset = 0; offset < length; offset++) {
680 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
682 DEBUGOUT("NVM Read Error\n");
685 pba_num[offset * 2] = (u8)(data >> 8);
686 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
688 pba_num[offset * 2] = '\0';
690 return IXGBE_SUCCESS;
694 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
695 * @hw: pointer to hardware structure
696 * @pba_num: stores the part number from the EEPROM
698 * Reads the part number from the EEPROM.
700 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
705 DEBUGFUNC("ixgbe_read_pba_num_generic");
707 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
709 DEBUGOUT("NVM Read Error\n");
711 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
712 DEBUGOUT("NVM Not supported\n");
713 return IXGBE_NOT_IMPLEMENTED;
715 *pba_num = (u32)(data << 16);
717 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
719 DEBUGOUT("NVM Read Error\n");
724 return IXGBE_SUCCESS;
729 * @hw: pointer to the HW structure
730 * @eeprom_buf: optional pointer to EEPROM image
731 * @eeprom_buf_size: size of EEPROM image in words
732 * @max_pba_block_size: PBA block size limit
733 * @pba: pointer to output PBA structure
735 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
736 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
739 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
740 u32 eeprom_buf_size, u16 max_pba_block_size,
741 struct ixgbe_pba *pba)
747 return IXGBE_ERR_PARAM;
749 if (eeprom_buf == NULL) {
750 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
755 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
756 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
757 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
759 return IXGBE_ERR_PARAM;
763 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
764 if (pba->pba_block == NULL)
765 return IXGBE_ERR_PARAM;
767 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
773 if (pba_block_size > max_pba_block_size)
774 return IXGBE_ERR_PARAM;
776 if (eeprom_buf == NULL) {
777 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
783 if (eeprom_buf_size > (u32)(pba->word[1] +
785 memcpy(pba->pba_block,
786 &eeprom_buf[pba->word[1]],
787 pba_block_size * sizeof(u16));
789 return IXGBE_ERR_PARAM;
794 return IXGBE_SUCCESS;
798 * ixgbe_write_pba_raw
799 * @hw: pointer to the HW structure
800 * @eeprom_buf: optional pointer to EEPROM image
801 * @eeprom_buf_size: size of EEPROM image in words
802 * @pba: pointer to PBA structure
804 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
805 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
808 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
809 u32 eeprom_buf_size, struct ixgbe_pba *pba)
814 return IXGBE_ERR_PARAM;
816 if (eeprom_buf == NULL) {
817 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
822 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
823 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
824 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
826 return IXGBE_ERR_PARAM;
830 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
831 if (pba->pba_block == NULL)
832 return IXGBE_ERR_PARAM;
834 if (eeprom_buf == NULL) {
835 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
841 if (eeprom_buf_size > (u32)(pba->word[1] +
842 pba->pba_block[0])) {
843 memcpy(&eeprom_buf[pba->word[1]],
845 pba->pba_block[0] * sizeof(u16));
847 return IXGBE_ERR_PARAM;
852 return IXGBE_SUCCESS;
856 * ixgbe_get_pba_block_size
857 * @hw: pointer to the HW structure
858 * @eeprom_buf: optional pointer to EEPROM image
859 * @eeprom_buf_size: size of EEPROM image in words
860 * @pba_data_size: pointer to output variable
862 * Returns the size of the PBA block in words. Function operates on EEPROM
863 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
867 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
868 u32 eeprom_buf_size, u16 *pba_block_size)
874 DEBUGFUNC("ixgbe_get_pba_block_size");
876 if (eeprom_buf == NULL) {
877 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
882 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
883 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
884 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
886 return IXGBE_ERR_PARAM;
890 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
891 if (eeprom_buf == NULL) {
892 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
897 if (eeprom_buf_size > pba_word[1])
898 length = eeprom_buf[pba_word[1] + 0];
900 return IXGBE_ERR_PARAM;
903 if (length == 0xFFFF || length == 0)
904 return IXGBE_ERR_PBA_SECTION;
906 /* PBA number in legacy format, there is no PBA Block. */
910 if (pba_block_size != NULL)
911 *pba_block_size = length;
913 return IXGBE_SUCCESS;
917 * ixgbe_get_mac_addr_generic - Generic get MAC address
918 * @hw: pointer to hardware structure
919 * @mac_addr: Adapter MAC address
921 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
922 * A reset of the adapter must be performed prior to calling this function
923 * in order for the MAC address to have been loaded from the EEPROM into RAR0
925 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
931 DEBUGFUNC("ixgbe_get_mac_addr_generic");
933 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
934 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
936 for (i = 0; i < 4; i++)
937 mac_addr[i] = (u8)(rar_low >> (i*8));
939 for (i = 0; i < 2; i++)
940 mac_addr[i+4] = (u8)(rar_high >> (i*8));
942 return IXGBE_SUCCESS;
946 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
947 * @hw: pointer to hardware structure
948 * @link_status: the link status returned by the PCI config space
950 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
952 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
954 struct ixgbe_mac_info *mac = &hw->mac;
956 hw->bus.type = ixgbe_bus_type_pci_express;
958 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
959 case IXGBE_PCI_LINK_WIDTH_1:
960 hw->bus.width = ixgbe_bus_width_pcie_x1;
962 case IXGBE_PCI_LINK_WIDTH_2:
963 hw->bus.width = ixgbe_bus_width_pcie_x2;
965 case IXGBE_PCI_LINK_WIDTH_4:
966 hw->bus.width = ixgbe_bus_width_pcie_x4;
968 case IXGBE_PCI_LINK_WIDTH_8:
969 hw->bus.width = ixgbe_bus_width_pcie_x8;
972 hw->bus.width = ixgbe_bus_width_unknown;
976 switch (link_status & IXGBE_PCI_LINK_SPEED) {
977 case IXGBE_PCI_LINK_SPEED_2500:
978 hw->bus.speed = ixgbe_bus_speed_2500;
980 case IXGBE_PCI_LINK_SPEED_5000:
981 hw->bus.speed = ixgbe_bus_speed_5000;
983 case IXGBE_PCI_LINK_SPEED_8000:
984 hw->bus.speed = ixgbe_bus_speed_8000;
987 hw->bus.speed = ixgbe_bus_speed_unknown;
991 mac->ops.set_lan_id(hw);
995 * ixgbe_get_bus_info_generic - Generic set PCI bus info
996 * @hw: pointer to hardware structure
998 * Gets the PCI bus info (speed, width, type) then calls helper function to
999 * store this data within the ixgbe_hw structure.
1001 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1005 DEBUGFUNC("ixgbe_get_bus_info_generic");
1007 /* Get the negotiated link width and speed from PCI config space */
1008 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1010 ixgbe_set_pci_config_data_generic(hw, link_status);
1012 return IXGBE_SUCCESS;
1016 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1017 * @hw: pointer to the HW structure
1019 * Determines the LAN function id by reading memory-mapped registers
1020 * and swaps the port value if requested.
1022 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1024 struct ixgbe_bus_info *bus = &hw->bus;
1027 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1029 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1030 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1031 bus->lan_id = bus->func;
1033 /* check for a port swap */
1034 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
1035 if (reg & IXGBE_FACTPS_LFS)
1040 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1041 * @hw: pointer to hardware structure
1043 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1044 * disables transmit and receive units. The adapter_stopped flag is used by
1045 * the shared code and drivers to determine if the adapter is in a stopped
1046 * state and should not touch the hardware.
1048 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1053 DEBUGFUNC("ixgbe_stop_adapter_generic");
1056 * Set the adapter_stopped flag so other driver functions stop touching
1059 hw->adapter_stopped = true;
1061 /* Disable the receive unit */
1062 ixgbe_disable_rx(hw);
1064 /* Clear interrupt mask to stop interrupts from being generated */
1065 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1067 /* Clear any pending interrupts, flush previous writes */
1068 IXGBE_READ_REG(hw, IXGBE_EICR);
1070 /* Disable the transmit unit. Each queue must be disabled. */
1071 for (i = 0; i < hw->mac.max_tx_queues; i++)
1072 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1074 /* Disable the receive unit by stopping each queue */
1075 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1076 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1077 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1078 reg_val |= IXGBE_RXDCTL_SWFLSH;
1079 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1082 /* flush all queues disables */
1083 IXGBE_WRITE_FLUSH(hw);
1087 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
1088 * access and verify no pending requests
1090 return ixgbe_disable_pcie_master(hw);
1094 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1095 * @hw: pointer to hardware structure
1096 * @index: led number to turn on
1098 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1100 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1102 DEBUGFUNC("ixgbe_led_on_generic");
1104 /* To turn on the LED, set mode to ON. */
1105 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1106 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1107 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1108 IXGBE_WRITE_FLUSH(hw);
1110 return IXGBE_SUCCESS;
1114 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1115 * @hw: pointer to hardware structure
1116 * @index: led number to turn off
1118 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1120 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1122 DEBUGFUNC("ixgbe_led_off_generic");
1124 /* To turn off the LED, set mode to OFF. */
1125 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1126 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1127 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1128 IXGBE_WRITE_FLUSH(hw);
1130 return IXGBE_SUCCESS;
1134 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1135 * @hw: pointer to hardware structure
1137 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1138 * ixgbe_hw struct in order to set up EEPROM access.
1140 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1142 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1146 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1148 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1149 eeprom->type = ixgbe_eeprom_none;
1150 /* Set default semaphore delay to 10ms which is a well
1152 eeprom->semaphore_delay = 10;
1153 /* Clear EEPROM page size, it will be initialized as needed */
1154 eeprom->word_page_size = 0;
1157 * Check for EEPROM present first.
1158 * If not present leave as none
1160 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1161 if (eec & IXGBE_EEC_PRES) {
1162 eeprom->type = ixgbe_eeprom_spi;
1165 * SPI EEPROM is assumed here. This code would need to
1166 * change if a future EEPROM is not SPI.
1168 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1169 IXGBE_EEC_SIZE_SHIFT);
1170 eeprom->word_size = 1 << (eeprom_size +
1171 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1174 if (eec & IXGBE_EEC_ADDR_SIZE)
1175 eeprom->address_bits = 16;
1177 eeprom->address_bits = 8;
1178 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1179 "%d\n", eeprom->type, eeprom->word_size,
1180 eeprom->address_bits);
1183 return IXGBE_SUCCESS;
1187 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1188 * @hw: pointer to hardware structure
1189 * @offset: offset within the EEPROM to write
1190 * @words: number of word(s)
1191 * @data: 16 bit word(s) to write to EEPROM
1193 * Reads 16 bit word(s) from EEPROM through bit-bang method
1195 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1196 u16 words, u16 *data)
1198 s32 status = IXGBE_SUCCESS;
1201 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1203 hw->eeprom.ops.init_params(hw);
1206 status = IXGBE_ERR_INVALID_ARGUMENT;
1210 if (offset + words > hw->eeprom.word_size) {
1211 status = IXGBE_ERR_EEPROM;
1216 * The EEPROM page size cannot be queried from the chip. We do lazy
1217 * initialization. It is worth to do that when we write large buffer.
1219 if ((hw->eeprom.word_page_size == 0) &&
1220 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1221 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1224 * We cannot hold synchronization semaphores for too long
1225 * to avoid other entity starvation. However it is more efficient
1226 * to read in bursts than synchronizing access for each word.
1228 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1229 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1230 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1231 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1234 if (status != IXGBE_SUCCESS)
1243 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1244 * @hw: pointer to hardware structure
1245 * @offset: offset within the EEPROM to be written to
1246 * @words: number of word(s)
1247 * @data: 16 bit word(s) to be written to the EEPROM
1249 * If ixgbe_eeprom_update_checksum is not called after this function, the
1250 * EEPROM will most likely contain an invalid checksum.
1252 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1253 u16 words, u16 *data)
1259 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1261 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1263 /* Prepare the EEPROM for writing */
1264 status = ixgbe_acquire_eeprom(hw);
1266 if (status == IXGBE_SUCCESS) {
1267 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1268 ixgbe_release_eeprom(hw);
1269 status = IXGBE_ERR_EEPROM;
1273 if (status == IXGBE_SUCCESS) {
1274 for (i = 0; i < words; i++) {
1275 ixgbe_standby_eeprom(hw);
1277 /* Send the WRITE ENABLE command (8 bit opcode ) */
1278 ixgbe_shift_out_eeprom_bits(hw,
1279 IXGBE_EEPROM_WREN_OPCODE_SPI,
1280 IXGBE_EEPROM_OPCODE_BITS);
1282 ixgbe_standby_eeprom(hw);
1285 * Some SPI eeproms use the 8th address bit embedded
1288 if ((hw->eeprom.address_bits == 8) &&
1289 ((offset + i) >= 128))
1290 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1292 /* Send the Write command (8-bit opcode + addr) */
1293 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1294 IXGBE_EEPROM_OPCODE_BITS);
1295 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1296 hw->eeprom.address_bits);
1298 page_size = hw->eeprom.word_page_size;
1300 /* Send the data in burst via SPI*/
1303 word = (word >> 8) | (word << 8);
1304 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1309 /* do not wrap around page */
1310 if (((offset + i) & (page_size - 1)) ==
1313 } while (++i < words);
1315 ixgbe_standby_eeprom(hw);
1318 /* Done with writing - release the EEPROM */
1319 ixgbe_release_eeprom(hw);
1326 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1327 * @hw: pointer to hardware structure
1328 * @offset: offset within the EEPROM to be written to
1329 * @data: 16 bit word to be written to the EEPROM
1331 * If ixgbe_eeprom_update_checksum is not called after this function, the
1332 * EEPROM will most likely contain an invalid checksum.
1334 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1338 DEBUGFUNC("ixgbe_write_eeprom_generic");
1340 hw->eeprom.ops.init_params(hw);
1342 if (offset >= hw->eeprom.word_size) {
1343 status = IXGBE_ERR_EEPROM;
1347 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1354 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1355 * @hw: pointer to hardware structure
1356 * @offset: offset within the EEPROM to be read
1357 * @data: read 16 bit words(s) from EEPROM
1358 * @words: number of word(s)
1360 * Reads 16 bit word(s) from EEPROM through bit-bang method
1362 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1363 u16 words, u16 *data)
1365 s32 status = IXGBE_SUCCESS;
1368 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1370 hw->eeprom.ops.init_params(hw);
1373 status = IXGBE_ERR_INVALID_ARGUMENT;
1377 if (offset + words > hw->eeprom.word_size) {
1378 status = IXGBE_ERR_EEPROM;
1383 * We cannot hold synchronization semaphores for too long
1384 * to avoid other entity starvation. However it is more efficient
1385 * to read in bursts than synchronizing access for each word.
1387 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1388 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1389 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1391 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1394 if (status != IXGBE_SUCCESS)
1403 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1404 * @hw: pointer to hardware structure
1405 * @offset: offset within the EEPROM to be read
1406 * @words: number of word(s)
1407 * @data: read 16 bit word(s) from EEPROM
1409 * Reads 16 bit word(s) from EEPROM through bit-bang method
1411 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1412 u16 words, u16 *data)
1416 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1419 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1421 /* Prepare the EEPROM for reading */
1422 status = ixgbe_acquire_eeprom(hw);
1424 if (status == IXGBE_SUCCESS) {
1425 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1426 ixgbe_release_eeprom(hw);
1427 status = IXGBE_ERR_EEPROM;
1431 if (status == IXGBE_SUCCESS) {
1432 for (i = 0; i < words; i++) {
1433 ixgbe_standby_eeprom(hw);
1435 * Some SPI eeproms use the 8th address bit embedded
1438 if ((hw->eeprom.address_bits == 8) &&
1439 ((offset + i) >= 128))
1440 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1442 /* Send the READ command (opcode + addr) */
1443 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1444 IXGBE_EEPROM_OPCODE_BITS);
1445 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1446 hw->eeprom.address_bits);
1448 /* Read the data. */
1449 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1450 data[i] = (word_in >> 8) | (word_in << 8);
1453 /* End this read operation */
1454 ixgbe_release_eeprom(hw);
1461 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1462 * @hw: pointer to hardware structure
1463 * @offset: offset within the EEPROM to be read
1464 * @data: read 16 bit value from EEPROM
1466 * Reads 16 bit value from EEPROM through bit-bang method
1468 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1473 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1475 hw->eeprom.ops.init_params(hw);
1477 if (offset >= hw->eeprom.word_size) {
1478 status = IXGBE_ERR_EEPROM;
1482 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1489 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1490 * @hw: pointer to hardware structure
1491 * @offset: offset of word in the EEPROM to read
1492 * @words: number of word(s)
1493 * @data: 16 bit word(s) from the EEPROM
1495 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1497 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1498 u16 words, u16 *data)
1501 s32 status = IXGBE_SUCCESS;
1504 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1506 hw->eeprom.ops.init_params(hw);
1509 status = IXGBE_ERR_INVALID_ARGUMENT;
1510 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1514 if (offset >= hw->eeprom.word_size) {
1515 status = IXGBE_ERR_EEPROM;
1516 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1520 for (i = 0; i < words; i++) {
1521 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1522 IXGBE_EEPROM_RW_REG_START;
1524 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1525 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1527 if (status == IXGBE_SUCCESS) {
1528 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1529 IXGBE_EEPROM_RW_REG_DATA);
1531 DEBUGOUT("Eeprom read timed out\n");
1540 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1541 * @hw: pointer to hardware structure
1542 * @offset: offset within the EEPROM to be used as a scratch pad
1544 * Discover EEPROM page size by writing marching data at given offset.
1545 * This function is called only when we are writing a new large buffer
1546 * at given offset so the data would be overwritten anyway.
1548 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1551 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1552 s32 status = IXGBE_SUCCESS;
1555 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1557 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1560 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1561 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1562 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1563 hw->eeprom.word_page_size = 0;
1564 if (status != IXGBE_SUCCESS)
1567 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1568 if (status != IXGBE_SUCCESS)
1572 * When writing in burst more than the actual page size
1573 * EEPROM address wraps around current page.
1575 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1577 DEBUGOUT1("Detected EEPROM page size = %d words.",
1578 hw->eeprom.word_page_size);
1584 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1585 * @hw: pointer to hardware structure
1586 * @offset: offset of word in the EEPROM to read
1587 * @data: word read from the EEPROM
1589 * Reads a 16 bit word from the EEPROM using the EERD register.
1591 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1593 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1597 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1598 * @hw: pointer to hardware structure
1599 * @offset: offset of word in the EEPROM to write
1600 * @words: number of word(s)
1601 * @data: word(s) write to the EEPROM
1603 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1605 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1606 u16 words, u16 *data)
1609 s32 status = IXGBE_SUCCESS;
1612 DEBUGFUNC("ixgbe_write_eewr_generic");
1614 hw->eeprom.ops.init_params(hw);
1617 status = IXGBE_ERR_INVALID_ARGUMENT;
1618 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1622 if (offset >= hw->eeprom.word_size) {
1623 status = IXGBE_ERR_EEPROM;
1624 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1628 for (i = 0; i < words; i++) {
1629 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1630 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1631 IXGBE_EEPROM_RW_REG_START;
1633 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1634 if (status != IXGBE_SUCCESS) {
1635 DEBUGOUT("Eeprom write EEWR timed out\n");
1639 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1641 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1642 if (status != IXGBE_SUCCESS) {
1643 DEBUGOUT("Eeprom write EEWR timed out\n");
1653 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1654 * @hw: pointer to hardware structure
1655 * @offset: offset of word in the EEPROM to write
1656 * @data: word write to the EEPROM
1658 * Write a 16 bit word to the EEPROM using the EEWR register.
1660 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1662 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1666 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1667 * @hw: pointer to hardware structure
1668 * @ee_reg: EEPROM flag for polling
1670 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1671 * read or write is done respectively.
1673 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1677 s32 status = IXGBE_ERR_EEPROM;
1679 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1681 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1682 if (ee_reg == IXGBE_NVM_POLL_READ)
1683 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1685 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1687 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1688 status = IXGBE_SUCCESS;
1694 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1695 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1696 "EEPROM read/write done polling timed out");
1702 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1703 * @hw: pointer to hardware structure
1705 * Prepares EEPROM for access using bit-bang method. This function should
1706 * be called before issuing a command to the EEPROM.
1708 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1710 s32 status = IXGBE_SUCCESS;
1714 DEBUGFUNC("ixgbe_acquire_eeprom");
1716 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1718 status = IXGBE_ERR_SWFW_SYNC;
1720 if (status == IXGBE_SUCCESS) {
1721 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1723 /* Request EEPROM Access */
1724 eec |= IXGBE_EEC_REQ;
1725 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1727 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1728 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1729 if (eec & IXGBE_EEC_GNT)
1734 /* Release if grant not acquired */
1735 if (!(eec & IXGBE_EEC_GNT)) {
1736 eec &= ~IXGBE_EEC_REQ;
1737 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1738 DEBUGOUT("Could not acquire EEPROM grant\n");
1740 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1741 status = IXGBE_ERR_EEPROM;
1744 /* Setup EEPROM for Read/Write */
1745 if (status == IXGBE_SUCCESS) {
1746 /* Clear CS and SK */
1747 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1748 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1749 IXGBE_WRITE_FLUSH(hw);
1757 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1758 * @hw: pointer to hardware structure
1760 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1762 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1764 s32 status = IXGBE_ERR_EEPROM;
1769 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1772 /* Get SMBI software semaphore between device drivers first */
1773 for (i = 0; i < timeout; i++) {
1775 * If the SMBI bit is 0 when we read it, then the bit will be
1776 * set and we have the semaphore
1778 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1779 if (!(swsm & IXGBE_SWSM_SMBI)) {
1780 status = IXGBE_SUCCESS;
1787 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1790 * this release is particularly important because our attempts
1791 * above to get the semaphore may have succeeded, and if there
1792 * was a timeout, we should unconditionally clear the semaphore
1793 * bits to free the driver to make progress
1795 ixgbe_release_eeprom_semaphore(hw);
1800 * If the SMBI bit is 0 when we read it, then the bit will be
1801 * set and we have the semaphore
1803 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1804 if (!(swsm & IXGBE_SWSM_SMBI))
1805 status = IXGBE_SUCCESS;
1808 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1809 if (status == IXGBE_SUCCESS) {
1810 for (i = 0; i < timeout; i++) {
1811 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1813 /* Set the SW EEPROM semaphore bit to request access */
1814 swsm |= IXGBE_SWSM_SWESMBI;
1815 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1818 * If we set the bit successfully then we got the
1821 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1822 if (swsm & IXGBE_SWSM_SWESMBI)
1829 * Release semaphores and return error if SW EEPROM semaphore
1830 * was not granted because we don't have access to the EEPROM
1833 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1834 "SWESMBI Software EEPROM semaphore not granted.\n");
1835 ixgbe_release_eeprom_semaphore(hw);
1836 status = IXGBE_ERR_EEPROM;
1839 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1840 "Software semaphore SMBI between device drivers "
1848 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1849 * @hw: pointer to hardware structure
1851 * This function clears hardware semaphore bits.
1853 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1857 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1859 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1861 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1862 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1863 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1864 IXGBE_WRITE_FLUSH(hw);
1868 * ixgbe_ready_eeprom - Polls for EEPROM ready
1869 * @hw: pointer to hardware structure
1871 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1873 s32 status = IXGBE_SUCCESS;
1877 DEBUGFUNC("ixgbe_ready_eeprom");
1880 * Read "Status Register" repeatedly until the LSB is cleared. The
1881 * EEPROM will signal that the command has been completed by clearing
1882 * bit 0 of the internal status register. If it's not cleared within
1883 * 5 milliseconds, then error out.
1885 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1886 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1887 IXGBE_EEPROM_OPCODE_BITS);
1888 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1889 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1893 ixgbe_standby_eeprom(hw);
1897 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1898 * devices (and only 0-5mSec on 5V devices)
1900 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1901 DEBUGOUT("SPI EEPROM Status error\n");
1902 status = IXGBE_ERR_EEPROM;
1909 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1910 * @hw: pointer to hardware structure
1912 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1916 DEBUGFUNC("ixgbe_standby_eeprom");
1918 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1920 /* Toggle CS to flush commands */
1921 eec |= IXGBE_EEC_CS;
1922 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1923 IXGBE_WRITE_FLUSH(hw);
1925 eec &= ~IXGBE_EEC_CS;
1926 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1927 IXGBE_WRITE_FLUSH(hw);
1932 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1933 * @hw: pointer to hardware structure
1934 * @data: data to send to the EEPROM
1935 * @count: number of bits to shift out
1937 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1944 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1946 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1949 * Mask is used to shift "count" bits of "data" out to the EEPROM
1950 * one bit at a time. Determine the starting bit based on count
1952 mask = 0x01 << (count - 1);
1954 for (i = 0; i < count; i++) {
1956 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1957 * "1", and then raising and then lowering the clock (the SK
1958 * bit controls the clock input to the EEPROM). A "0" is
1959 * shifted out to the EEPROM by setting "DI" to "0" and then
1960 * raising and then lowering the clock.
1963 eec |= IXGBE_EEC_DI;
1965 eec &= ~IXGBE_EEC_DI;
1967 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1968 IXGBE_WRITE_FLUSH(hw);
1972 ixgbe_raise_eeprom_clk(hw, &eec);
1973 ixgbe_lower_eeprom_clk(hw, &eec);
1976 * Shift mask to signify next bit of data to shift in to the
1982 /* We leave the "DI" bit set to "0" when we leave this routine. */
1983 eec &= ~IXGBE_EEC_DI;
1984 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1985 IXGBE_WRITE_FLUSH(hw);
1989 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1990 * @hw: pointer to hardware structure
1992 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1998 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2001 * In order to read a register from the EEPROM, we need to shift
2002 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2003 * the clock input to the EEPROM (setting the SK bit), and then reading
2004 * the value of the "DO" bit. During this "shifting in" process the
2005 * "DI" bit should always be clear.
2007 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2009 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2011 for (i = 0; i < count; i++) {
2013 ixgbe_raise_eeprom_clk(hw, &eec);
2015 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2017 eec &= ~(IXGBE_EEC_DI);
2018 if (eec & IXGBE_EEC_DO)
2021 ixgbe_lower_eeprom_clk(hw, &eec);
2028 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2029 * @hw: pointer to hardware structure
2030 * @eec: EEC register's current value
2032 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2034 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2037 * Raise the clock input to the EEPROM
2038 * (setting the SK bit), then delay
2040 *eec = *eec | IXGBE_EEC_SK;
2041 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2042 IXGBE_WRITE_FLUSH(hw);
2047 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2048 * @hw: pointer to hardware structure
2049 * @eecd: EECD's current value
2051 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2053 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2056 * Lower the clock input to the EEPROM (clearing the SK bit), then
2059 *eec = *eec & ~IXGBE_EEC_SK;
2060 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2061 IXGBE_WRITE_FLUSH(hw);
2066 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2067 * @hw: pointer to hardware structure
2069 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2073 DEBUGFUNC("ixgbe_release_eeprom");
2075 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2077 eec |= IXGBE_EEC_CS; /* Pull CS high */
2078 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2080 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2081 IXGBE_WRITE_FLUSH(hw);
2085 /* Stop requesting EEPROM access */
2086 eec &= ~IXGBE_EEC_REQ;
2087 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2089 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2091 /* Delay before attempt to obtain semaphore again to allow FW access */
2092 msec_delay(hw->eeprom.semaphore_delay);
2096 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2097 * @hw: pointer to hardware structure
2099 * Returns a negative error code on error, or the 16-bit checksum
2101 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2110 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2112 /* Include 0x0-0x3F in the checksum */
2113 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2114 if (hw->eeprom.ops.read(hw, i, &word)) {
2115 DEBUGOUT("EEPROM read failed\n");
2116 return IXGBE_ERR_EEPROM;
2121 /* Include all data from pointers except for the fw pointer */
2122 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2123 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2124 DEBUGOUT("EEPROM read failed\n");
2125 return IXGBE_ERR_EEPROM;
2128 /* If the pointer seems invalid */
2129 if (pointer == 0xFFFF || pointer == 0)
2132 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2133 DEBUGOUT("EEPROM read failed\n");
2134 return IXGBE_ERR_EEPROM;
2137 if (length == 0xFFFF || length == 0)
2140 for (j = pointer + 1; j <= pointer + length; j++) {
2141 if (hw->eeprom.ops.read(hw, j, &word)) {
2142 DEBUGOUT("EEPROM read failed\n");
2143 return IXGBE_ERR_EEPROM;
2149 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2151 return (s32)checksum;
2155 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2156 * @hw: pointer to hardware structure
2157 * @checksum_val: calculated checksum
2159 * Performs checksum calculation and validates the EEPROM checksum. If the
2160 * caller does not need checksum_val, the value can be NULL.
2162 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2167 u16 read_checksum = 0;
2169 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2171 /* Read the first word from the EEPROM. If this times out or fails, do
2172 * not continue or we could be in for a very long wait while every
2175 status = hw->eeprom.ops.read(hw, 0, &checksum);
2177 DEBUGOUT("EEPROM read failed\n");
2181 status = hw->eeprom.ops.calc_checksum(hw);
2185 checksum = (u16)(status & 0xffff);
2187 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2189 DEBUGOUT("EEPROM read failed\n");
2193 /* Verify read checksum from EEPROM is the same as
2194 * calculated checksum
2196 if (read_checksum != checksum)
2197 status = IXGBE_ERR_EEPROM_CHECKSUM;
2199 /* If the user cares, return the calculated checksum */
2201 *checksum_val = checksum;
2207 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2208 * @hw: pointer to hardware structure
2210 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2215 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2217 /* Read the first word from the EEPROM. If this times out or fails, do
2218 * not continue or we could be in for a very long wait while every
2221 status = hw->eeprom.ops.read(hw, 0, &checksum);
2223 DEBUGOUT("EEPROM read failed\n");
2227 status = hw->eeprom.ops.calc_checksum(hw);
2231 checksum = (u16)(status & 0xffff);
2233 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2239 * ixgbe_validate_mac_addr - Validate MAC address
2240 * @mac_addr: pointer to MAC address.
2242 * Tests a MAC address to ensure it is a valid Individual Address
2244 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2246 s32 status = IXGBE_SUCCESS;
2248 DEBUGFUNC("ixgbe_validate_mac_addr");
2250 /* Make sure it is not a multicast address */
2251 if (IXGBE_IS_MULTICAST(mac_addr)) {
2252 DEBUGOUT("MAC address is multicast\n");
2253 status = IXGBE_ERR_INVALID_MAC_ADDR;
2254 /* Not a broadcast address */
2255 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2256 DEBUGOUT("MAC address is broadcast\n");
2257 status = IXGBE_ERR_INVALID_MAC_ADDR;
2258 /* Reject the zero address */
2259 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2260 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2261 DEBUGOUT("MAC address is all zeros\n");
2262 status = IXGBE_ERR_INVALID_MAC_ADDR;
2268 * ixgbe_set_rar_generic - Set Rx address register
2269 * @hw: pointer to hardware structure
2270 * @index: Receive address register to write
2271 * @addr: Address to put into receive address register
2272 * @vmdq: VMDq "set" or "pool" index
2273 * @enable_addr: set flag that address is active
2275 * Puts an ethernet address into a receive address register.
2277 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2280 u32 rar_low, rar_high;
2281 u32 rar_entries = hw->mac.num_rar_entries;
2283 DEBUGFUNC("ixgbe_set_rar_generic");
2285 /* Make sure we are using a valid rar index range */
2286 if (index >= rar_entries) {
2287 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2288 "RAR index %d is out of range.\n", index);
2289 return IXGBE_ERR_INVALID_ARGUMENT;
2292 /* setup VMDq pool selection before this RAR gets enabled */
2293 hw->mac.ops.set_vmdq(hw, index, vmdq);
2296 * HW expects these in little endian so we reverse the byte
2297 * order from network order (big endian) to little endian
2299 rar_low = ((u32)addr[0] |
2300 ((u32)addr[1] << 8) |
2301 ((u32)addr[2] << 16) |
2302 ((u32)addr[3] << 24));
2304 * Some parts put the VMDq setting in the extra RAH bits,
2305 * so save everything except the lower 16 bits that hold part
2306 * of the address and the address valid bit.
2308 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2309 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2310 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2312 if (enable_addr != 0)
2313 rar_high |= IXGBE_RAH_AV;
2315 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2316 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2318 return IXGBE_SUCCESS;
2322 * ixgbe_clear_rar_generic - Remove Rx address register
2323 * @hw: pointer to hardware structure
2324 * @index: Receive address register to write
2326 * Clears an ethernet address from a receive address register.
2328 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2331 u32 rar_entries = hw->mac.num_rar_entries;
2333 DEBUGFUNC("ixgbe_clear_rar_generic");
2335 /* Make sure we are using a valid rar index range */
2336 if (index >= rar_entries) {
2337 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2338 "RAR index %d is out of range.\n", index);
2339 return IXGBE_ERR_INVALID_ARGUMENT;
2343 * Some parts put the VMDq setting in the extra RAH bits,
2344 * so save everything except the lower 16 bits that hold part
2345 * of the address and the address valid bit.
2347 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2348 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2350 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2351 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2353 /* clear VMDq pool/queue selection for this RAR */
2354 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2356 return IXGBE_SUCCESS;
2360 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2361 * @hw: pointer to hardware structure
2363 * Places the MAC address in receive address register 0 and clears the rest
2364 * of the receive address registers. Clears the multicast table. Assumes
2365 * the receiver is in reset when the routine is called.
2367 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2370 u32 rar_entries = hw->mac.num_rar_entries;
2372 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2375 * If the current mac address is valid, assume it is a software override
2376 * to the permanent address.
2377 * Otherwise, use the permanent address from the eeprom.
2379 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2380 IXGBE_ERR_INVALID_MAC_ADDR) {
2381 /* Get the MAC address from the RAR0 for later reference */
2382 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2384 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2385 hw->mac.addr[0], hw->mac.addr[1],
2387 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2388 hw->mac.addr[4], hw->mac.addr[5]);
2390 /* Setup the receive address. */
2391 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2392 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2393 hw->mac.addr[0], hw->mac.addr[1],
2395 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2396 hw->mac.addr[4], hw->mac.addr[5]);
2398 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2400 /* clear VMDq pool/queue selection for RAR 0 */
2401 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2403 hw->addr_ctrl.overflow_promisc = 0;
2405 hw->addr_ctrl.rar_used_count = 1;
2407 /* Zero out the other receive addresses. */
2408 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2409 for (i = 1; i < rar_entries; i++) {
2410 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2411 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2415 hw->addr_ctrl.mta_in_use = 0;
2416 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2418 DEBUGOUT(" Clearing MTA\n");
2419 for (i = 0; i < hw->mac.mcft_size; i++)
2420 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2422 ixgbe_init_uta_tables(hw);
2424 return IXGBE_SUCCESS;
2428 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2429 * @hw: pointer to hardware structure
2430 * @addr: new address
2432 * Adds it to unused receive address register or goes into promiscuous mode.
2434 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2436 u32 rar_entries = hw->mac.num_rar_entries;
2439 DEBUGFUNC("ixgbe_add_uc_addr");
2441 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2442 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2445 * Place this address in the RAR if there is room,
2446 * else put the controller into promiscuous mode
2448 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2449 rar = hw->addr_ctrl.rar_used_count;
2450 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2451 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2452 hw->addr_ctrl.rar_used_count++;
2454 hw->addr_ctrl.overflow_promisc++;
2457 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2461 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2462 * @hw: pointer to hardware structure
2463 * @addr_list: the list of new addresses
2464 * @addr_count: number of addresses
2465 * @next: iterator function to walk the address list
2467 * The given list replaces any existing list. Clears the secondary addrs from
2468 * receive address registers. Uses unused receive address registers for the
2469 * first secondary addresses, and falls back to promiscuous mode as needed.
2471 * Drivers using secondary unicast addresses must set user_set_promisc when
2472 * manually putting the device into promiscuous mode.
2474 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2475 u32 addr_count, ixgbe_mc_addr_itr next)
2479 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2484 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2487 * Clear accounting of old secondary address list,
2488 * don't count RAR[0]
2490 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2491 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2492 hw->addr_ctrl.overflow_promisc = 0;
2494 /* Zero out the other receive addresses */
2495 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2496 for (i = 0; i < uc_addr_in_use; i++) {
2497 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2498 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2501 /* Add the new addresses */
2502 for (i = 0; i < addr_count; i++) {
2503 DEBUGOUT(" Adding the secondary addresses:\n");
2504 addr = next(hw, &addr_list, &vmdq);
2505 ixgbe_add_uc_addr(hw, addr, vmdq);
2508 if (hw->addr_ctrl.overflow_promisc) {
2509 /* enable promisc if not already in overflow or set by user */
2510 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2511 DEBUGOUT(" Entering address overflow promisc mode\n");
2512 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2513 fctrl |= IXGBE_FCTRL_UPE;
2514 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2517 /* only disable if set by overflow, not by user */
2518 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2519 DEBUGOUT(" Leaving address overflow promisc mode\n");
2520 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2521 fctrl &= ~IXGBE_FCTRL_UPE;
2522 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2526 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2527 return IXGBE_SUCCESS;
2531 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2532 * @hw: pointer to hardware structure
2533 * @mc_addr: the multicast address
2535 * Extracts the 12 bits, from a multicast address, to determine which
2536 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2537 * incoming rx multicast addresses, to determine the bit-vector to check in
2538 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2539 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2540 * to mc_filter_type.
2542 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2546 DEBUGFUNC("ixgbe_mta_vector");
2548 switch (hw->mac.mc_filter_type) {
2549 case 0: /* use bits [47:36] of the address */
2550 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2552 case 1: /* use bits [46:35] of the address */
2553 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2555 case 2: /* use bits [45:34] of the address */
2556 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2558 case 3: /* use bits [43:32] of the address */
2559 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2561 default: /* Invalid mc_filter_type */
2562 DEBUGOUT("MC filter type param set incorrectly\n");
2567 /* vector can only be 12-bits or boundary will be exceeded */
2573 * ixgbe_set_mta - Set bit-vector in multicast table
2574 * @hw: pointer to hardware structure
2575 * @hash_value: Multicast address hash value
2577 * Sets the bit-vector in the multicast table.
2579 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2585 DEBUGFUNC("ixgbe_set_mta");
2587 hw->addr_ctrl.mta_in_use++;
2589 vector = ixgbe_mta_vector(hw, mc_addr);
2590 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2593 * The MTA is a register array of 128 32-bit registers. It is treated
2594 * like an array of 4096 bits. We want to set bit
2595 * BitArray[vector_value]. So we figure out what register the bit is
2596 * in, read it, OR in the new bit, then write back the new value. The
2597 * register is determined by the upper 7 bits of the vector value and
2598 * the bit within that register are determined by the lower 5 bits of
2601 vector_reg = (vector >> 5) & 0x7F;
2602 vector_bit = vector & 0x1F;
2603 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2607 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2608 * @hw: pointer to hardware structure
2609 * @mc_addr_list: the list of new multicast addresses
2610 * @mc_addr_count: number of addresses
2611 * @next: iterator function to walk the multicast address list
2612 * @clear: flag, when set clears the table beforehand
2614 * When the clear flag is set, the given list replaces any existing list.
2615 * Hashes the given addresses into the multicast table.
2617 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2618 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2624 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2627 * Set the new number of MC addresses that we are being requested to
2630 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2631 hw->addr_ctrl.mta_in_use = 0;
2633 /* Clear mta_shadow */
2635 DEBUGOUT(" Clearing MTA\n");
2636 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2639 /* Update mta_shadow */
2640 for (i = 0; i < mc_addr_count; i++) {
2641 DEBUGOUT(" Adding the multicast addresses:\n");
2642 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2646 for (i = 0; i < hw->mac.mcft_size; i++)
2647 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2648 hw->mac.mta_shadow[i]);
2650 if (hw->addr_ctrl.mta_in_use > 0)
2651 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2652 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2654 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2655 return IXGBE_SUCCESS;
2659 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2660 * @hw: pointer to hardware structure
2662 * Enables multicast address in RAR and the use of the multicast hash table.
2664 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2666 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2668 DEBUGFUNC("ixgbe_enable_mc_generic");
2670 if (a->mta_in_use > 0)
2671 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2672 hw->mac.mc_filter_type);
2674 return IXGBE_SUCCESS;
2678 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2679 * @hw: pointer to hardware structure
2681 * Disables multicast address in RAR and the use of the multicast hash table.
2683 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2685 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2687 DEBUGFUNC("ixgbe_disable_mc_generic");
2689 if (a->mta_in_use > 0)
2690 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2692 return IXGBE_SUCCESS;
2696 * ixgbe_fc_enable_generic - Enable flow control
2697 * @hw: pointer to hardware structure
2699 * Enable flow control according to the current settings.
2701 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2703 s32 ret_val = IXGBE_SUCCESS;
2704 u32 mflcn_reg, fccfg_reg;
2709 DEBUGFUNC("ixgbe_fc_enable_generic");
2711 /* Validate the water mark configuration */
2712 if (!hw->fc.pause_time) {
2713 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2717 /* Low water mark of zero causes XOFF floods */
2718 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2719 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2720 hw->fc.high_water[i]) {
2721 if (!hw->fc.low_water[i] ||
2722 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2723 DEBUGOUT("Invalid water mark configuration\n");
2724 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2730 /* Negotiate the fc mode to use */
2731 ixgbe_fc_autoneg(hw);
2733 /* Disable any previous flow control settings */
2734 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2735 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2737 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2738 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2741 * The possible values of fc.current_mode are:
2742 * 0: Flow control is completely disabled
2743 * 1: Rx flow control is enabled (we can receive pause frames,
2744 * but not send pause frames).
2745 * 2: Tx flow control is enabled (we can send pause frames but
2746 * we do not support receiving pause frames).
2747 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2750 switch (hw->fc.current_mode) {
2753 * Flow control is disabled by software override or autoneg.
2754 * The code below will actually disable it in the HW.
2757 case ixgbe_fc_rx_pause:
2759 * Rx Flow control is enabled and Tx Flow control is
2760 * disabled by software override. Since there really
2761 * isn't a way to advertise that we are capable of RX
2762 * Pause ONLY, we will advertise that we support both
2763 * symmetric and asymmetric Rx PAUSE. Later, we will
2764 * disable the adapter's ability to send PAUSE frames.
2766 mflcn_reg |= IXGBE_MFLCN_RFCE;
2768 case ixgbe_fc_tx_pause:
2770 * Tx Flow control is enabled, and Rx Flow control is
2771 * disabled by software override.
2773 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2776 /* Flow control (both Rx and Tx) is enabled by SW override. */
2777 mflcn_reg |= IXGBE_MFLCN_RFCE;
2778 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2781 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2782 "Flow control param set incorrectly\n");
2783 ret_val = IXGBE_ERR_CONFIG;
2788 /* Set 802.3x based flow control settings. */
2789 mflcn_reg |= IXGBE_MFLCN_DPF;
2790 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2791 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2794 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2795 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2796 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2797 hw->fc.high_water[i]) {
2798 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2799 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2800 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2802 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2804 * In order to prevent Tx hangs when the internal Tx
2805 * switch is enabled we must set the high water mark
2806 * to the Rx packet buffer size - 24KB. This allows
2807 * the Tx switch to function even under heavy Rx
2810 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2813 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2816 /* Configure pause time (2 TCs per register) */
2817 reg = hw->fc.pause_time * 0x00010001;
2818 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2819 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2821 /* Configure flow control refresh threshold value */
2822 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2829 * ixgbe_negotiate_fc - Negotiate flow control
2830 * @hw: pointer to hardware structure
2831 * @adv_reg: flow control advertised settings
2832 * @lp_reg: link partner's flow control settings
2833 * @adv_sym: symmetric pause bit in advertisement
2834 * @adv_asm: asymmetric pause bit in advertisement
2835 * @lp_sym: symmetric pause bit in link partner advertisement
2836 * @lp_asm: asymmetric pause bit in link partner advertisement
2838 * Find the intersection between advertised settings and link partner's
2839 * advertised settings
2841 STATIC s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2842 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2844 if ((!(adv_reg)) || (!(lp_reg))) {
2845 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2846 "Local or link partner's advertised flow control "
2847 "settings are NULL. Local: %x, link partner: %x\n",
2849 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2852 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2854 * Now we need to check if the user selected Rx ONLY
2855 * of pause frames. In this case, we had to advertise
2856 * FULL flow control because we could not advertise RX
2857 * ONLY. Hence, we must now check to see if we need to
2858 * turn OFF the TRANSMISSION of PAUSE frames.
2860 if (hw->fc.requested_mode == ixgbe_fc_full) {
2861 hw->fc.current_mode = ixgbe_fc_full;
2862 DEBUGOUT("Flow Control = FULL.\n");
2864 hw->fc.current_mode = ixgbe_fc_rx_pause;
2865 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2867 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2868 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2869 hw->fc.current_mode = ixgbe_fc_tx_pause;
2870 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2871 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2872 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2873 hw->fc.current_mode = ixgbe_fc_rx_pause;
2874 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2876 hw->fc.current_mode = ixgbe_fc_none;
2877 DEBUGOUT("Flow Control = NONE.\n");
2879 return IXGBE_SUCCESS;
2883 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2884 * @hw: pointer to hardware structure
2886 * Enable flow control according on 1 gig fiber.
2888 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2890 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2891 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2894 * On multispeed fiber at 1g, bail out if
2895 * - link is up but AN did not complete, or if
2896 * - link is up and AN completed but timed out
2899 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2900 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2901 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2902 ERROR_REPORT1(IXGBE_ERROR_POLLING,
2903 "Auto-Negotiation did not complete or timed out");
2907 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2908 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2910 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2911 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2912 IXGBE_PCS1GANA_ASM_PAUSE,
2913 IXGBE_PCS1GANA_SYM_PAUSE,
2914 IXGBE_PCS1GANA_ASM_PAUSE);
2921 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2922 * @hw: pointer to hardware structure
2924 * Enable flow control according to IEEE clause 37.
2926 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2928 u32 links2, anlp1_reg, autoc_reg, links;
2929 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2932 * On backplane, bail out if
2933 * - backplane autoneg was not completed, or if
2934 * - we are 82599 and link partner is not AN enabled
2936 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2937 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2938 ERROR_REPORT1(IXGBE_ERROR_POLLING,
2939 "Auto-Negotiation did not complete");
2943 if (hw->mac.type == ixgbe_mac_82599EB) {
2944 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2945 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2946 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2947 "Link partner is not AN enabled");
2952 * Read the 10g AN autoc and LP ability registers and resolve
2953 * local flow control settings accordingly
2955 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2956 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2958 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2959 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2960 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2967 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2968 * @hw: pointer to hardware structure
2970 * Enable flow control according to IEEE clause 37.
2972 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2974 u16 technology_ability_reg = 0;
2975 u16 lp_technology_ability_reg = 0;
2977 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2978 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2979 &technology_ability_reg);
2980 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2981 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2982 &lp_technology_ability_reg);
2984 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2985 (u32)lp_technology_ability_reg,
2986 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2987 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2991 * ixgbe_fc_autoneg - Configure flow control
2992 * @hw: pointer to hardware structure
2994 * Compares our advertised flow control capabilities to those advertised by
2995 * our link partner, and determines the proper flow control mode to use.
2997 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2999 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
3000 ixgbe_link_speed speed;
3003 DEBUGFUNC("ixgbe_fc_autoneg");
3006 * AN should have completed when the cable was plugged in.
3007 * Look for reasons to bail out. Bail out if:
3008 * - FC autoneg is disabled, or if
3011 if (hw->fc.disable_fc_autoneg) {
3012 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3013 "Flow control autoneg is disabled");
3017 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3019 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3023 switch (hw->phy.media_type) {
3024 /* Autoneg flow control on fiber adapters */
3025 case ixgbe_media_type_fiber_qsfp:
3026 case ixgbe_media_type_fiber:
3027 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3028 ret_val = ixgbe_fc_autoneg_fiber(hw);
3031 /* Autoneg flow control on backplane adapters */
3032 case ixgbe_media_type_backplane:
3033 ret_val = ixgbe_fc_autoneg_backplane(hw);
3036 /* Autoneg flow control on copper adapters */
3037 case ixgbe_media_type_copper:
3038 if (ixgbe_device_supports_autoneg_fc(hw))
3039 ret_val = ixgbe_fc_autoneg_copper(hw);
3047 if (ret_val == IXGBE_SUCCESS) {
3048 hw->fc.fc_was_autonegged = true;
3050 hw->fc.fc_was_autonegged = false;
3051 hw->fc.current_mode = hw->fc.requested_mode;
3056 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3057 * @hw: pointer to hardware structure
3059 * System-wide timeout range is encoded in PCIe Device Control2 register.
3061 * Add 10% to specified maximum and return the number of times to poll for
3062 * completion timeout, in units of 100 microsec. Never return less than
3063 * 800 = 80 millisec.
3065 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3070 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3071 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3074 case IXGBE_PCIDEVCTRL2_65_130ms:
3075 pollcnt = 1300; /* 130 millisec */
3077 case IXGBE_PCIDEVCTRL2_260_520ms:
3078 pollcnt = 5200; /* 520 millisec */
3080 case IXGBE_PCIDEVCTRL2_1_2s:
3081 pollcnt = 20000; /* 2 sec */
3083 case IXGBE_PCIDEVCTRL2_4_8s:
3084 pollcnt = 80000; /* 8 sec */
3086 case IXGBE_PCIDEVCTRL2_17_34s:
3087 pollcnt = 34000; /* 34 sec */
3089 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3090 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3091 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3092 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3094 pollcnt = 800; /* 80 millisec minimum */
3098 /* add 10% to spec maximum */
3099 return (pollcnt * 11) / 10;
3103 * ixgbe_disable_pcie_master - Disable PCI-express master access
3104 * @hw: pointer to hardware structure
3106 * Disables PCI-Express master access and verifies there are no pending
3107 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3108 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3109 * is returned signifying master requests disabled.
3111 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3113 s32 status = IXGBE_SUCCESS;
3117 DEBUGFUNC("ixgbe_disable_pcie_master");
3119 /* Always set this bit to ensure any future transactions are blocked */
3120 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3122 /* Exit if master requests are blocked */
3123 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3124 IXGBE_REMOVED(hw->hw_addr))
3127 /* Poll for master request bit to clear */
3128 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3130 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3135 * Two consecutive resets are required via CTRL.RST per datasheet
3136 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3137 * of this need. The first reset prevents new master requests from
3138 * being issued by our device. We then must wait 1usec or more for any
3139 * remaining completions from the PCIe bus to trickle in, and then reset
3140 * again to clear out any effects they may have had on our device.
3142 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3143 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3146 * Before proceeding, make sure that the PCIe block does not have
3147 * transactions pending.
3149 poll = ixgbe_pcie_timeout_poll(hw);
3150 for (i = 0; i < poll; i++) {
3152 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3153 if (IXGBE_REMOVED(hw->hw_addr))
3155 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3159 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3160 "PCIe transaction pending bit also did not clear.\n");
3161 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3168 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3169 * @hw: pointer to hardware structure
3170 * @mask: Mask to specify which semaphore to acquire
3172 * Acquires the SWFW semaphore through the GSSR register for the specified
3173 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3175 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3179 u32 fwmask = mask << 5;
3183 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3185 for (i = 0; i < timeout; i++) {
3187 * SW NVM semaphore bit is used for access to all
3188 * SW_FW_SYNC bits (not just NVM)
3190 if (ixgbe_get_eeprom_semaphore(hw))
3191 return IXGBE_ERR_SWFW_SYNC;
3193 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3194 if (!(gssr & (fwmask | swmask))) {
3196 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3197 ixgbe_release_eeprom_semaphore(hw);
3198 return IXGBE_SUCCESS;
3200 /* Resource is currently in use by FW or SW */
3201 ixgbe_release_eeprom_semaphore(hw);
3206 /* If time expired clear the bits holding the lock and retry */
3207 if (gssr & (fwmask | swmask))
3208 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3211 return IXGBE_ERR_SWFW_SYNC;
3215 * ixgbe_release_swfw_sync - Release SWFW semaphore
3216 * @hw: pointer to hardware structure
3217 * @mask: Mask to specify which semaphore to release
3219 * Releases the SWFW semaphore through the GSSR register for the specified
3220 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3222 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u32 mask)
3227 DEBUGFUNC("ixgbe_release_swfw_sync");
3229 ixgbe_get_eeprom_semaphore(hw);
3231 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3233 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3235 ixgbe_release_eeprom_semaphore(hw);
3239 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3240 * @hw: pointer to hardware structure
3242 * Stops the receive data path and waits for the HW to internally empty
3243 * the Rx security block
3245 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3247 #define IXGBE_MAX_SECRX_POLL 40
3252 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3255 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3256 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3257 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3258 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3259 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3260 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3263 /* Use interrupt-safe sleep just in case */
3267 /* For informational purposes only */
3268 if (i >= IXGBE_MAX_SECRX_POLL)
3269 DEBUGOUT("Rx unit being enabled before security "
3270 "path fully disabled. Continuing with init.\n");
3272 return IXGBE_SUCCESS;
3276 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3277 * @hw: pointer to hardware structure
3278 * @reg_val: Value we read from AUTOC
3280 * The default case requires no protection so just to the register read.
3282 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3285 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3286 return IXGBE_SUCCESS;
3290 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3291 * @hw: pointer to hardware structure
3292 * @reg_val: value to write to AUTOC
3293 * @locked: bool to indicate whether the SW/FW lock was already taken by
3296 * The default case requires no protection so just to the register write.
3298 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3300 UNREFERENCED_1PARAMETER(locked);
3302 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3303 return IXGBE_SUCCESS;
3307 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3308 * @hw: pointer to hardware structure
3310 * Enables the receive data path.
3312 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3316 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3318 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3319 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3320 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3321 IXGBE_WRITE_FLUSH(hw);
3323 return IXGBE_SUCCESS;
3327 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3328 * @hw: pointer to hardware structure
3329 * @regval: register value to write to RXCTRL
3331 * Enables the Rx DMA unit
3333 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3335 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3337 if (regval & IXGBE_RXCTRL_RXEN)
3338 ixgbe_enable_rx(hw);
3340 ixgbe_disable_rx(hw);
3342 return IXGBE_SUCCESS;
3346 * ixgbe_blink_led_start_generic - Blink LED based on index.
3347 * @hw: pointer to hardware structure
3348 * @index: led number to blink
3350 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3352 ixgbe_link_speed speed = 0;
3355 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3356 s32 ret_val = IXGBE_SUCCESS;
3357 bool locked = false;
3359 DEBUGFUNC("ixgbe_blink_led_start_generic");
3362 * Link must be up to auto-blink the LEDs;
3363 * Force it if link is down.
3365 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3368 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3369 if (ret_val != IXGBE_SUCCESS)
3372 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3373 autoc_reg |= IXGBE_AUTOC_FLU;
3375 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3376 if (ret_val != IXGBE_SUCCESS)
3379 IXGBE_WRITE_FLUSH(hw);
3383 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3384 led_reg |= IXGBE_LED_BLINK(index);
3385 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3386 IXGBE_WRITE_FLUSH(hw);
3393 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3394 * @hw: pointer to hardware structure
3395 * @index: led number to stop blinking
3397 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3400 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3401 s32 ret_val = IXGBE_SUCCESS;
3402 bool locked = false;
3404 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3406 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3407 if (ret_val != IXGBE_SUCCESS)
3410 autoc_reg &= ~IXGBE_AUTOC_FLU;
3411 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3413 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3414 if (ret_val != IXGBE_SUCCESS)
3417 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3418 led_reg &= ~IXGBE_LED_BLINK(index);
3419 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3420 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3421 IXGBE_WRITE_FLUSH(hw);
3428 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3429 * @hw: pointer to hardware structure
3430 * @san_mac_offset: SAN MAC address offset
3432 * This function will read the EEPROM location for the SAN MAC address
3433 * pointer, and returns the value at that location. This is used in both
3434 * get and set mac_addr routines.
3436 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3437 u16 *san_mac_offset)
3441 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3444 * First read the EEPROM pointer to see if the MAC addresses are
3447 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3450 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3451 "eeprom at offset %d failed",
3452 IXGBE_SAN_MAC_ADDR_PTR);
3459 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3460 * @hw: pointer to hardware structure
3461 * @san_mac_addr: SAN MAC address
3463 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3464 * per-port, so set_lan_id() must be called before reading the addresses.
3465 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3466 * upon for non-SFP connections, so we must call it here.
3468 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3470 u16 san_mac_data, san_mac_offset;
3474 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3477 * First read the EEPROM pointer to see if the MAC addresses are
3478 * available. If they're not, no point in calling set_lan_id() here.
3480 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3481 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3482 goto san_mac_addr_out;
3484 /* make sure we know which port we need to program */
3485 hw->mac.ops.set_lan_id(hw);
3486 /* apply the port offset to the address offset */
3487 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3488 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3489 for (i = 0; i < 3; i++) {
3490 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3493 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3494 "eeprom read at offset %d failed",
3496 goto san_mac_addr_out;
3498 san_mac_addr[i * 2] = (u8)(san_mac_data);
3499 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3502 return IXGBE_SUCCESS;
3506 * No addresses available in this EEPROM. It's not an
3507 * error though, so just wipe the local address and return.
3509 for (i = 0; i < 6; i++)
3510 san_mac_addr[i] = 0xFF;
3511 return IXGBE_SUCCESS;
3515 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3516 * @hw: pointer to hardware structure
3517 * @san_mac_addr: SAN MAC address
3519 * Write a SAN MAC address to the EEPROM.
3521 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3524 u16 san_mac_data, san_mac_offset;
3527 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3529 /* Look for SAN mac address pointer. If not defined, return */
3530 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3531 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3532 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3534 /* Make sure we know which port we need to write */
3535 hw->mac.ops.set_lan_id(hw);
3536 /* Apply the port offset to the address offset */
3537 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3538 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3540 for (i = 0; i < 3; i++) {
3541 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3542 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3543 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3547 return IXGBE_SUCCESS;
3551 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3552 * @hw: pointer to hardware structure
3554 * Read PCIe configuration space, and get the MSI-X vector count from
3555 * the capabilities table.
3557 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3563 switch (hw->mac.type) {
3564 case ixgbe_mac_82598EB:
3565 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3566 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3568 case ixgbe_mac_82599EB:
3569 case ixgbe_mac_X540:
3570 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3571 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3577 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3578 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3579 if (IXGBE_REMOVED(hw->hw_addr))
3581 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3583 /* MSI-X count is zero-based in HW */
3586 if (msix_count > max_msix_count)
3587 msix_count = max_msix_count;
3593 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3594 * @hw: pointer to hardware structure
3595 * @addr: Address to put into receive address register
3596 * @vmdq: VMDq pool to assign
3598 * Puts an ethernet address into a receive address register, or
3599 * finds the rar that it is aleady in; adds to the pool list
3601 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3603 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3604 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3606 u32 rar_low, rar_high;
3607 u32 addr_low, addr_high;
3609 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3611 /* swap bytes for HW little endian */
3612 addr_low = addr[0] | (addr[1] << 8)
3615 addr_high = addr[4] | (addr[5] << 8);
3618 * Either find the mac_id in rar or find the first empty space.
3619 * rar_highwater points to just after the highest currently used
3620 * rar in order to shorten the search. It grows when we add a new
3623 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3624 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3626 if (((IXGBE_RAH_AV & rar_high) == 0)
3627 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3628 first_empty_rar = rar;
3629 } else if ((rar_high & 0xFFFF) == addr_high) {
3630 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3631 if (rar_low == addr_low)
3632 break; /* found it already in the rars */
3636 if (rar < hw->mac.rar_highwater) {
3637 /* already there so just add to the pool bits */
3638 ixgbe_set_vmdq(hw, rar, vmdq);
3639 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3640 /* stick it into first empty RAR slot we found */
3641 rar = first_empty_rar;
3642 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3643 } else if (rar == hw->mac.rar_highwater) {
3644 /* add it to the top of the list and inc the highwater mark */
3645 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3646 hw->mac.rar_highwater++;
3647 } else if (rar >= hw->mac.num_rar_entries) {
3648 return IXGBE_ERR_INVALID_MAC_ADDR;
3652 * If we found rar[0], make sure the default pool bit (we use pool 0)
3653 * remains cleared to be sure default pool packets will get delivered
3656 ixgbe_clear_vmdq(hw, rar, 0);
3662 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3663 * @hw: pointer to hardware struct
3664 * @rar: receive address register index to disassociate
3665 * @vmdq: VMDq pool index to remove from the rar
3667 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3669 u32 mpsar_lo, mpsar_hi;
3670 u32 rar_entries = hw->mac.num_rar_entries;
3672 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3674 /* Make sure we are using a valid rar index range */
3675 if (rar >= rar_entries) {
3676 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3677 "RAR index %d is out of range.\n", rar);
3678 return IXGBE_ERR_INVALID_ARGUMENT;
3681 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3682 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3684 if (IXGBE_REMOVED(hw->hw_addr))
3687 if (!mpsar_lo && !mpsar_hi)
3690 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3692 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3696 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3699 } else if (vmdq < 32) {
3700 mpsar_lo &= ~(1 << vmdq);
3701 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3703 mpsar_hi &= ~(1 << (vmdq - 32));
3704 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3707 /* was that the last pool using this rar? */
3708 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3709 hw->mac.ops.clear_rar(hw, rar);
3711 return IXGBE_SUCCESS;
3715 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3716 * @hw: pointer to hardware struct
3717 * @rar: receive address register index to associate with a VMDq index
3718 * @vmdq: VMDq pool index
3720 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3723 u32 rar_entries = hw->mac.num_rar_entries;
3725 DEBUGFUNC("ixgbe_set_vmdq_generic");
3727 /* Make sure we are using a valid rar index range */
3728 if (rar >= rar_entries) {
3729 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3730 "RAR index %d is out of range.\n", rar);
3731 return IXGBE_ERR_INVALID_ARGUMENT;
3735 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3737 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3739 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3740 mpsar |= 1 << (vmdq - 32);
3741 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3743 return IXGBE_SUCCESS;
3747 * This function should only be involved in the IOV mode.
3748 * In IOV mode, Default pool is next pool after the number of
3749 * VFs advertized and not 0.
3750 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3752 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3753 * @hw: pointer to hardware struct
3754 * @vmdq: VMDq pool index
3756 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3758 u32 rar = hw->mac.san_mac_rar_index;
3760 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3763 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3764 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3766 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3767 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3770 return IXGBE_SUCCESS;
3774 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3775 * @hw: pointer to hardware structure
3777 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3781 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3782 DEBUGOUT(" Clearing UTA\n");
3784 for (i = 0; i < 128; i++)
3785 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3787 return IXGBE_SUCCESS;
3791 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3792 * @hw: pointer to hardware structure
3793 * @vlan: VLAN id to write to VLAN filter
3795 * return the VLVF index where this VLAN id should be placed
3798 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3801 u32 first_empty_slot = 0;
3804 /* short cut the special case */
3809 * Search for the vlan id in the VLVF entries. Save off the first empty
3810 * slot found along the way
3812 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3813 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3814 if (!bits && !(first_empty_slot))
3815 first_empty_slot = regindex;
3816 else if ((bits & 0x0FFF) == vlan)
3821 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3822 * in the VLVF. Else use the first empty VLVF register for this
3825 if (regindex >= IXGBE_VLVF_ENTRIES) {
3826 if (first_empty_slot)
3827 regindex = first_empty_slot;
3829 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
3830 "No space in VLVF.\n");
3831 regindex = IXGBE_ERR_NO_SPACE;
3839 * ixgbe_set_vfta_generic - Set VLAN filter table
3840 * @hw: pointer to hardware structure
3841 * @vlan: VLAN id to write to VLAN filter
3842 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3843 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3845 * Turn on/off specified VLAN in the VLAN filter table.
3847 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3854 s32 ret_val = IXGBE_SUCCESS;
3855 bool vfta_changed = false;
3857 DEBUGFUNC("ixgbe_set_vfta_generic");
3860 return IXGBE_ERR_PARAM;
3863 * this is a 2 part operation - first the VFTA, then the
3864 * VLVF and VLVFB if VT Mode is set
3865 * We don't write the VFTA until we know the VLVF part succeeded.
3869 * The VFTA is a bitstring made up of 128 32-bit registers
3870 * that enable the particular VLAN id, much like the MTA:
3871 * bits[11-5]: which register
3872 * bits[4-0]: which bit in the register
3874 regindex = (vlan >> 5) & 0x7F;
3875 bitindex = vlan & 0x1F;
3876 targetbit = (1 << bitindex);
3877 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3880 if (!(vfta & targetbit)) {
3882 vfta_changed = true;
3885 if ((vfta & targetbit)) {
3887 vfta_changed = true;
3892 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3894 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3896 if (ret_val != IXGBE_SUCCESS)
3900 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3902 return IXGBE_SUCCESS;
3906 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3907 * @hw: pointer to hardware structure
3908 * @vlan: VLAN id to write to VLAN filter
3909 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3910 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3911 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3914 * Turn on/off specified bit in VLVF table.
3916 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3917 bool vlan_on, bool *vfta_changed)
3921 DEBUGFUNC("ixgbe_set_vlvf_generic");
3924 return IXGBE_ERR_PARAM;
3926 /* If VT Mode is set
3928 * make sure the vlan is in VLVF
3929 * set the vind bit in the matching VLVFB
3931 * clear the pool bit and possibly the vind
3933 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3934 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3938 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3943 /* set the pool bit */
3945 bits = IXGBE_READ_REG(hw,
3946 IXGBE_VLVFB(vlvf_index * 2));
3947 bits |= (1 << vind);
3949 IXGBE_VLVFB(vlvf_index * 2),
3952 bits = IXGBE_READ_REG(hw,
3953 IXGBE_VLVFB((vlvf_index * 2) + 1));
3954 bits |= (1 << (vind - 32));
3956 IXGBE_VLVFB((vlvf_index * 2) + 1),
3960 /* clear the pool bit */
3962 bits = IXGBE_READ_REG(hw,
3963 IXGBE_VLVFB(vlvf_index * 2));
3964 bits &= ~(1 << vind);
3966 IXGBE_VLVFB(vlvf_index * 2),
3968 bits |= IXGBE_READ_REG(hw,
3969 IXGBE_VLVFB((vlvf_index * 2) + 1));
3971 bits = IXGBE_READ_REG(hw,
3972 IXGBE_VLVFB((vlvf_index * 2) + 1));
3973 bits &= ~(1 << (vind - 32));
3975 IXGBE_VLVFB((vlvf_index * 2) + 1),
3977 bits |= IXGBE_READ_REG(hw,
3978 IXGBE_VLVFB(vlvf_index * 2));
3983 * If there are still bits set in the VLVFB registers
3984 * for the VLAN ID indicated we need to see if the
3985 * caller is requesting that we clear the VFTA entry bit.
3986 * If the caller has requested that we clear the VFTA
3987 * entry bit but there are still pools/VFs using this VLAN
3988 * ID entry then ignore the request. We're not worried
3989 * about the case where we're turning the VFTA VLAN ID
3990 * entry bit on, only when requested to turn it off as
3991 * there may be multiple pools and/or VFs using the
3992 * VLAN ID entry. In that case we cannot clear the
3993 * VFTA bit until all pools/VFs using that VLAN ID have also
3994 * been cleared. This will be indicated by "bits" being
3998 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3999 (IXGBE_VLVF_VIEN | vlan));
4000 if ((!vlan_on) && (vfta_changed != NULL)) {
4001 /* someone wants to clear the vfta entry
4002 * but some pools/VFs are still using it.
4004 *vfta_changed = false;
4007 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4010 return IXGBE_SUCCESS;
4014 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4015 * @hw: pointer to hardware structure
4017 * Clears the VLAN filer table, and the VMDq index associated with the filter
4019 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4023 DEBUGFUNC("ixgbe_clear_vfta_generic");
4025 for (offset = 0; offset < hw->mac.vft_size; offset++)
4026 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4028 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4029 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4030 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4031 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
4034 return IXGBE_SUCCESS;
4038 * ixgbe_check_mac_link_generic - Determine link and speed status
4039 * @hw: pointer to hardware structure
4040 * @speed: pointer to link speed
4041 * @link_up: true when link is up
4042 * @link_up_wait_to_complete: bool used to wait for link up or not
4044 * Reads the links register to determine if link is up and the current speed
4046 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4047 bool *link_up, bool link_up_wait_to_complete)
4049 u32 links_reg, links_orig;
4052 DEBUGFUNC("ixgbe_check_mac_link_generic");
4054 /* clear the old state */
4055 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4057 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4059 if (links_orig != links_reg) {
4060 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4061 links_orig, links_reg);
4064 if (link_up_wait_to_complete) {
4065 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
4066 if (links_reg & IXGBE_LINKS_UP) {
4073 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4076 if (links_reg & IXGBE_LINKS_UP)
4082 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4083 IXGBE_LINKS_SPEED_10G_82599)
4084 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4085 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4086 IXGBE_LINKS_SPEED_1G_82599)
4087 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4088 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4089 IXGBE_LINKS_SPEED_100_82599)
4090 *speed = IXGBE_LINK_SPEED_100_FULL;
4092 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4094 return IXGBE_SUCCESS;
4098 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4100 * @hw: pointer to hardware structure
4101 * @wwnn_prefix: the alternative WWNN prefix
4102 * @wwpn_prefix: the alternative WWPN prefix
4104 * This function will read the EEPROM from the alternative SAN MAC address
4105 * block to check the support for the alternative WWNN/WWPN prefix support.
4107 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4111 u16 alt_san_mac_blk_offset;
4113 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4115 /* clear output first */
4116 *wwnn_prefix = 0xFFFF;
4117 *wwpn_prefix = 0xFFFF;
4119 /* check if alternative SAN MAC is supported */
4120 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4121 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4122 goto wwn_prefix_err;
4124 if ((alt_san_mac_blk_offset == 0) ||
4125 (alt_san_mac_blk_offset == 0xFFFF))
4126 goto wwn_prefix_out;
4128 /* check capability in alternative san mac address block */
4129 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4130 if (hw->eeprom.ops.read(hw, offset, &caps))
4131 goto wwn_prefix_err;
4132 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4133 goto wwn_prefix_out;
4135 /* get the corresponding prefix for WWNN/WWPN */
4136 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4137 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4138 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4139 "eeprom read at offset %d failed", offset);
4142 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4143 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4144 goto wwn_prefix_err;
4147 return IXGBE_SUCCESS;
4150 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4151 "eeprom read at offset %d failed", offset);
4152 return IXGBE_SUCCESS;
4156 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4157 * @hw: pointer to hardware structure
4158 * @bs: the fcoe boot status
4160 * This function will read the FCOE boot status from the iSCSI FCOE block
4162 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4164 u16 offset, caps, flags;
4167 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4169 /* clear output first */
4170 *bs = ixgbe_fcoe_bootstatus_unavailable;
4172 /* check if FCOE IBA block is present */
4173 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4174 status = hw->eeprom.ops.read(hw, offset, &caps);
4175 if (status != IXGBE_SUCCESS)
4178 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4181 /* check if iSCSI FCOE block is populated */
4182 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4183 if (status != IXGBE_SUCCESS)
4186 if ((offset == 0) || (offset == 0xFFFF))
4189 /* read fcoe flags in iSCSI FCOE block */
4190 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4191 status = hw->eeprom.ops.read(hw, offset, &flags);
4192 if (status != IXGBE_SUCCESS)
4195 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4196 *bs = ixgbe_fcoe_bootstatus_enabled;
4198 *bs = ixgbe_fcoe_bootstatus_disabled;
4205 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4206 * @hw: pointer to hardware structure
4207 * @enable: enable or disable switch for anti-spoofing
4208 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
4211 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
4214 int pf_target_reg = pf >> 3;
4215 int pf_target_shift = pf % 8;
4218 if (hw->mac.type == ixgbe_mac_82598EB)
4222 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
4225 * PFVFSPOOF register array is size 8 with 8 bits assigned to
4226 * MAC anti-spoof enables in each register array element.
4228 for (j = 0; j < pf_target_reg; j++)
4229 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4232 * The PF should be allowed to spoof so that it can support
4233 * emulation mode NICs. Do not set the bits assigned to the PF
4235 pfvfspoof &= (1 << pf_target_shift) - 1;
4236 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4239 * Remaining pools belong to the PF so they do not need to have
4240 * anti-spoofing enabled.
4242 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
4243 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
4247 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4248 * @hw: pointer to hardware structure
4249 * @enable: enable or disable switch for VLAN anti-spoofing
4250 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4253 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4255 int vf_target_reg = vf >> 3;
4256 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4259 if (hw->mac.type == ixgbe_mac_82598EB)
4262 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4264 pfvfspoof |= (1 << vf_target_shift);
4266 pfvfspoof &= ~(1 << vf_target_shift);
4267 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4271 * ixgbe_get_device_caps_generic - Get additional device capabilities
4272 * @hw: pointer to hardware structure
4273 * @device_caps: the EEPROM word with the extra device capabilities
4275 * This function will read the EEPROM location for the device capabilities,
4276 * and return the word through device_caps.
4278 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4280 DEBUGFUNC("ixgbe_get_device_caps_generic");
4282 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4284 return IXGBE_SUCCESS;
4288 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4289 * @hw: pointer to hardware structure
4292 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4297 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4299 /* Enable relaxed ordering */
4300 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4301 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4302 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4303 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4306 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4307 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4308 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4309 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4310 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4316 * ixgbe_calculate_checksum - Calculate checksum for buffer
4317 * @buffer: pointer to EEPROM
4318 * @length: size of EEPROM to calculate a checksum for
4319 * Calculates the checksum for some buffer on a specified length. The
4320 * checksum calculated is returned.
4322 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4327 DEBUGFUNC("ixgbe_calculate_checksum");
4332 for (i = 0; i < length; i++)
4335 return (u8) (0 - sum);
4339 * ixgbe_host_interface_command - Issue command to manageability block
4340 * @hw: pointer to the HW structure
4341 * @buffer: contains the command to write and where the return status will
4343 * @length: length of buffer, must be multiple of 4 bytes
4344 * @return_data: read and return data from the buffer (true) or not (false)
4345 * Needed because FW structures are big endian and decoding of
4346 * these fields can be 8 bit or 16 bit based on command. Decoding
4347 * is not easily understood without making a table of commands.
4348 * So we will leave this up to the caller to read back the data
4351 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4352 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
4354 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4355 u32 length, bool return_data)
4357 u32 hicr, i, bi, fwsts;
4358 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4362 DEBUGFUNC("ixgbe_host_interface_command");
4364 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4365 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4366 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4368 /* Set bit 9 of FWSTS clearing FW reset indication */
4369 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4370 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4372 /* Check that the host interface is enabled. */
4373 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4374 if ((hicr & IXGBE_HICR_EN) == 0) {
4375 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4376 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4379 /* Calculate length in DWORDs. We must be DWORD aligned */
4380 if ((length % (sizeof(u32))) != 0) {
4381 DEBUGOUT("Buffer length failure, not aligned to dword");
4382 return IXGBE_ERR_INVALID_ARGUMENT;
4385 dword_len = length >> 2;
4387 /* The device driver writes the relevant command block
4388 * into the ram area.
4390 for (i = 0; i < dword_len; i++)
4391 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4392 i, IXGBE_CPU_TO_LE32(buffer[i]));
4394 /* Setting this bit tells the ARC that a new command is pending. */
4395 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4397 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
4398 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4399 if (!(hicr & IXGBE_HICR_C))
4404 /* Check command completion */
4405 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
4406 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4407 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4408 "Command has failed with no status valid.\n");
4409 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4415 /* Calculate length in DWORDs */
4416 dword_len = hdr_size >> 2;
4418 /* first pull in the header so we know the buffer length */
4419 for (bi = 0; bi < dword_len; bi++) {
4420 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4421 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4424 /* If there is any thing in data position pull it in */
4425 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4429 if (length < buf_len + hdr_size) {
4430 DEBUGOUT("Buffer not large enough for reply message.\n");
4431 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4434 /* Calculate length in DWORDs, add 3 for odd lengths */
4435 dword_len = (buf_len + 3) >> 2;
4437 /* Pull in the rest of the buffer (bi is where we left off) */
4438 for (; bi <= dword_len; bi++) {
4439 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4440 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4447 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4448 * @hw: pointer to the HW structure
4449 * @maj: driver version major number
4450 * @min: driver version minor number
4451 * @build: driver version build number
4452 * @sub: driver version sub build number
4454 * Sends driver version number to firmware through the manageability
4455 * block. On success return IXGBE_SUCCESS
4456 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4457 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4459 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4462 struct ixgbe_hic_drv_info fw_cmd;
4464 s32 ret_val = IXGBE_SUCCESS;
4466 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4468 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
4470 ret_val = IXGBE_ERR_SWFW_SYNC;
4474 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4475 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4476 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4477 fw_cmd.port_num = (u8)hw->bus.func;
4478 fw_cmd.ver_maj = maj;
4479 fw_cmd.ver_min = min;
4480 fw_cmd.ver_build = build;
4481 fw_cmd.ver_sub = sub;
4482 fw_cmd.hdr.checksum = 0;
4483 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4484 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4488 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4489 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4490 sizeof(fw_cmd), true);
4491 if (ret_val != IXGBE_SUCCESS)
4494 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4495 FW_CEM_RESP_STATUS_SUCCESS)
4496 ret_val = IXGBE_SUCCESS;
4498 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4503 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4509 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4510 * @hw: pointer to hardware structure
4511 * @num_pb: number of packet buffers to allocate
4512 * @headroom: reserve n KB of headroom
4513 * @strategy: packet buffer allocation strategy
4515 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4518 u32 pbsize = hw->mac.rx_pb_size;
4520 u32 rxpktsize, txpktsize, txpbthresh;
4522 /* Reserve headroom */
4528 /* Divide remaining packet buffer space amongst the number of packet
4529 * buffers requested using supplied strategy.
4532 case PBA_STRATEGY_WEIGHTED:
4533 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4534 * buffer with 5/8 of the packet buffer space.
4536 rxpktsize = (pbsize * 5) / (num_pb * 4);
4537 pbsize -= rxpktsize * (num_pb / 2);
4538 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4539 for (; i < (num_pb / 2); i++)
4540 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4541 /* Fall through to configure remaining packet buffers */
4542 case PBA_STRATEGY_EQUAL:
4543 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4544 for (; i < num_pb; i++)
4545 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4551 /* Only support an equally distributed Tx packet buffer strategy. */
4552 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4553 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4554 for (i = 0; i < num_pb; i++) {
4555 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4556 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4559 /* Clear unused TCs, if any, to zero buffer size*/
4560 for (; i < IXGBE_MAX_PB; i++) {
4561 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4562 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4563 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4568 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4569 * @hw: pointer to the hardware structure
4571 * The 82599 and x540 MACs can experience issues if TX work is still pending
4572 * when a reset occurs. This function prevents this by flushing the PCIe
4573 * buffers on the system.
4575 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4577 u32 gcr_ext, hlreg0;
4580 * If double reset is not requested then all transactions should
4581 * already be clear and as such there is no work to do
4583 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4587 * Set loopback enable to prevent any transmits from being sent
4588 * should the link come up. This assumes that the RXCTRL.RXEN bit
4589 * has already been cleared.
4591 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4592 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4594 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4595 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4596 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4597 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4599 /* Flush all writes and allow 20usec for all transactions to clear */
4600 IXGBE_WRITE_FLUSH(hw);
4603 /* restore previous register values */
4604 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4605 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4610 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4611 * @hw: pointer to hardware structure
4612 * @map: pointer to u8 arr for returning map
4614 * Read the rtrup2tc HW register and resolve its content into map
4616 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4620 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4621 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4622 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4623 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4627 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4632 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4633 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4634 if (hw->mac.type != ixgbe_mac_82598EB) {
4635 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4636 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4637 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4638 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4639 hw->mac.set_lben = true;
4641 hw->mac.set_lben = false;
4644 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4645 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4649 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4654 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4655 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4657 if (hw->mac.type != ixgbe_mac_82598EB) {
4658 if (hw->mac.set_lben) {
4659 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4660 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4661 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4662 hw->mac.set_lben = false;
4668 * ixgbe_mng_enabled - Is the manageability engine enabled?
4669 * @hw: pointer to hardware structure
4671 * Returns true if the manageability engine is enabled.
4673 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
4675 u32 fwsm, manc, factps;
4677 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4678 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
4681 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
4682 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
4685 if (hw->mac.type <= ixgbe_mac_X540) {
4686 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
4687 if (factps & IXGBE_FACTPS_MNGCG)