1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
39 #ident "$Id: ixgbe_common.c,v 1.382 2013/11/22 01:02:01 jtkirshe Exp $"
41 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
42 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
44 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
46 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
48 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
49 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
51 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
53 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
54 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
56 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
57 u16 words, u16 *data);
58 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
64 * ixgbe_init_ops_generic - Inits function ptrs
65 * @hw: pointer to the hardware structure
67 * Initialize the function pointers.
69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
72 struct ixgbe_mac_info *mac = &hw->mac;
73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
75 DEBUGFUNC("ixgbe_init_ops_generic");
78 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
80 if (eec & IXGBE_EEC_PRES) {
81 eeprom->ops.read = &ixgbe_read_eerd_generic;
82 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
84 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
85 eeprom->ops.read_buffer =
86 &ixgbe_read_eeprom_buffer_bit_bang_generic;
88 eeprom->ops.write = &ixgbe_write_eeprom_generic;
89 eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
90 eeprom->ops.validate_checksum =
91 &ixgbe_validate_eeprom_checksum_generic;
92 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
93 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
96 mac->ops.init_hw = &ixgbe_init_hw_generic;
97 mac->ops.reset_hw = NULL;
98 mac->ops.start_hw = &ixgbe_start_hw_generic;
99 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
100 mac->ops.get_media_type = NULL;
101 mac->ops.get_supported_physical_layer = NULL;
102 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
103 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
104 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
105 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
106 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
107 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
108 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
109 mac->ops.prot_autoc_read = &prot_autoc_read_generic;
110 mac->ops.prot_autoc_write = &prot_autoc_write_generic;
113 mac->ops.led_on = &ixgbe_led_on_generic;
114 mac->ops.led_off = &ixgbe_led_off_generic;
115 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
116 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
118 /* RAR, Multicast, VLAN */
119 mac->ops.set_rar = &ixgbe_set_rar_generic;
120 mac->ops.clear_rar = &ixgbe_clear_rar_generic;
121 mac->ops.insert_mac_addr = NULL;
122 mac->ops.set_vmdq = NULL;
123 mac->ops.clear_vmdq = NULL;
124 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
125 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
126 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
127 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
128 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
129 mac->ops.clear_vfta = NULL;
130 mac->ops.set_vfta = NULL;
131 mac->ops.set_vlvf = NULL;
132 mac->ops.init_uta_tables = NULL;
133 mac->ops.enable_rx = &ixgbe_enable_rx_generic;
134 mac->ops.disable_rx = &ixgbe_disable_rx_generic;
137 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
140 mac->ops.get_link_capabilities = NULL;
141 mac->ops.setup_link = NULL;
142 mac->ops.check_link = NULL;
144 return IXGBE_SUCCESS;
148 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
150 * @hw: pointer to hardware structure
152 * This function returns true if the device supports flow control
153 * autonegotiation, and false if it does not.
156 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
158 bool supported = false;
159 ixgbe_link_speed speed;
162 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
164 switch (hw->phy.media_type) {
165 case ixgbe_media_type_fiber:
166 hw->mac.ops.check_link(hw, &speed, &link_up, false);
167 /* if link is down, assume supported */
169 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
174 case ixgbe_media_type_backplane:
177 case ixgbe_media_type_copper:
178 /* only some copper devices support flow control autoneg */
179 switch (hw->device_id) {
180 case IXGBE_DEV_ID_82599_T3_LOM:
181 case IXGBE_DEV_ID_X540T:
182 case IXGBE_DEV_ID_X540T1:
192 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
193 "Device %x does not support flow control autoneg",
199 * ixgbe_setup_fc - Set up flow control
200 * @hw: pointer to hardware structure
202 * Called at init time to set up flow control.
204 STATIC s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
206 s32 ret_val = IXGBE_SUCCESS;
207 u32 reg = 0, reg_bp = 0;
211 DEBUGFUNC("ixgbe_setup_fc");
214 * Validate the requested mode. Strict IEEE mode does not allow
215 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
217 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
218 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
219 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
220 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
225 * 10gig parts do not have a word in the EEPROM to determine the
226 * default flow control setting, so we explicitly set it to full.
228 if (hw->fc.requested_mode == ixgbe_fc_default)
229 hw->fc.requested_mode = ixgbe_fc_full;
232 * Set up the 1G and 10G flow control advertisement registers so the
233 * HW will be able to do fc autoneg once the cable is plugged in. If
234 * we link at 10G, the 1G advertisement is harmless and vice versa.
236 switch (hw->phy.media_type) {
237 case ixgbe_media_type_backplane:
238 /* some MAC's need RMW protection on AUTOC */
239 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
240 if (ret_val != IXGBE_SUCCESS)
243 /* only backplane uses autoc so fall though */
244 case ixgbe_media_type_fiber:
245 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
248 case ixgbe_media_type_copper:
249 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
250 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
257 * The possible values of fc.requested_mode are:
258 * 0: Flow control is completely disabled
259 * 1: Rx flow control is enabled (we can receive pause frames,
260 * but not send pause frames).
261 * 2: Tx flow control is enabled (we can send pause frames but
262 * we do not support receiving pause frames).
263 * 3: Both Rx and Tx flow control (symmetric) are enabled.
266 switch (hw->fc.requested_mode) {
268 /* Flow control completely disabled by software override. */
269 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
270 if (hw->phy.media_type == ixgbe_media_type_backplane)
271 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
272 IXGBE_AUTOC_ASM_PAUSE);
273 else if (hw->phy.media_type == ixgbe_media_type_copper)
274 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
276 case ixgbe_fc_tx_pause:
278 * Tx Flow control is enabled, and Rx Flow control is
279 * disabled by software override.
281 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
282 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
283 if (hw->phy.media_type == ixgbe_media_type_backplane) {
284 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
285 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
286 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
287 reg_cu |= IXGBE_TAF_ASM_PAUSE;
288 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
291 case ixgbe_fc_rx_pause:
293 * Rx Flow control is enabled and Tx Flow control is
294 * disabled by software override. Since there really
295 * isn't a way to advertise that we are capable of RX
296 * Pause ONLY, we will advertise that we support both
297 * symmetric and asymmetric Rx PAUSE, as such we fall
298 * through to the fc_full statement. Later, we will
299 * disable the adapter's ability to send PAUSE frames.
302 /* Flow control (both Rx and Tx) is enabled by SW override. */
303 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
304 if (hw->phy.media_type == ixgbe_media_type_backplane)
305 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
306 IXGBE_AUTOC_ASM_PAUSE;
307 else if (hw->phy.media_type == ixgbe_media_type_copper)
308 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
311 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
312 "Flow control param set incorrectly\n");
313 ret_val = IXGBE_ERR_CONFIG;
318 if (hw->mac.type < ixgbe_mac_X540) {
320 * Enable auto-negotiation between the MAC & PHY;
321 * the MAC will advertise clause 37 flow control.
323 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
324 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
326 /* Disable AN timeout */
327 if (hw->fc.strict_ieee)
328 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
330 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
331 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
335 * AUTOC restart handles negotiation of 1G and 10G on backplane
336 * and copper. There is no need to set the PCS1GCTL register.
339 if (hw->phy.media_type == ixgbe_media_type_backplane) {
340 reg_bp |= IXGBE_AUTOC_AN_RESTART;
341 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
344 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
345 (ixgbe_device_supports_autoneg_fc(hw))) {
346 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
347 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
350 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
356 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
357 * @hw: pointer to hardware structure
359 * Starts the hardware by filling the bus info structure and media type, clears
360 * all on chip counters, initializes receive address registers, multicast
361 * table, VLAN filter table, calls routine to set up link and flow control
362 * settings, and leaves transmit and receive units disabled and uninitialized
364 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
369 DEBUGFUNC("ixgbe_start_hw_generic");
371 /* Set the media type */
372 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
374 /* PHY ops initialization must be done in reset_hw() */
376 /* Clear the VLAN filter table */
377 hw->mac.ops.clear_vfta(hw);
379 /* Clear statistics registers */
380 hw->mac.ops.clear_hw_cntrs(hw);
382 /* Set No Snoop Disable */
383 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
384 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
385 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
386 IXGBE_WRITE_FLUSH(hw);
388 /* Setup flow control */
389 ret_val = ixgbe_setup_fc(hw);
390 if (ret_val != IXGBE_SUCCESS)
393 /* Clear adapter stopped flag */
394 hw->adapter_stopped = false;
401 * ixgbe_start_hw_gen2 - Init sequence for common device family
402 * @hw: pointer to hw structure
404 * Performs the init sequence common to the second generation
406 * Devices in the second generation:
410 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
415 /* Clear the rate limiters */
416 for (i = 0; i < hw->mac.max_tx_queues; i++) {
417 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
418 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
420 IXGBE_WRITE_FLUSH(hw);
422 /* Disable relaxed ordering */
423 for (i = 0; i < hw->mac.max_tx_queues; i++) {
424 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
425 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
426 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
429 for (i = 0; i < hw->mac.max_rx_queues; i++) {
430 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
431 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
432 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
433 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
436 return IXGBE_SUCCESS;
440 * ixgbe_init_hw_generic - Generic hardware initialization
441 * @hw: pointer to hardware structure
443 * Initialize the hardware by resetting the hardware, filling the bus info
444 * structure and media type, clears all on chip counters, initializes receive
445 * address registers, multicast table, VLAN filter table, calls routine to set
446 * up link and flow control settings, and leaves transmit and receive units
447 * disabled and uninitialized
449 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
453 DEBUGFUNC("ixgbe_init_hw_generic");
455 /* Reset the hardware */
456 status = hw->mac.ops.reset_hw(hw);
458 if (status == IXGBE_SUCCESS) {
460 status = hw->mac.ops.start_hw(hw);
467 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
468 * @hw: pointer to hardware structure
470 * Clears all hardware statistics counters by reading them from the hardware
471 * Statistics counters are clear on read.
473 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
477 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
479 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
480 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
481 IXGBE_READ_REG(hw, IXGBE_ERRBC);
482 IXGBE_READ_REG(hw, IXGBE_MSPDC);
483 for (i = 0; i < 8; i++)
484 IXGBE_READ_REG(hw, IXGBE_MPC(i));
486 IXGBE_READ_REG(hw, IXGBE_MLFC);
487 IXGBE_READ_REG(hw, IXGBE_MRFC);
488 IXGBE_READ_REG(hw, IXGBE_RLEC);
489 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
490 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
491 if (hw->mac.type >= ixgbe_mac_82599EB) {
492 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
493 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
495 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
496 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
499 for (i = 0; i < 8; i++) {
500 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
501 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
502 if (hw->mac.type >= ixgbe_mac_82599EB) {
503 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
504 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
506 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
507 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
510 if (hw->mac.type >= ixgbe_mac_82599EB)
511 for (i = 0; i < 8; i++)
512 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
513 IXGBE_READ_REG(hw, IXGBE_PRC64);
514 IXGBE_READ_REG(hw, IXGBE_PRC127);
515 IXGBE_READ_REG(hw, IXGBE_PRC255);
516 IXGBE_READ_REG(hw, IXGBE_PRC511);
517 IXGBE_READ_REG(hw, IXGBE_PRC1023);
518 IXGBE_READ_REG(hw, IXGBE_PRC1522);
519 IXGBE_READ_REG(hw, IXGBE_GPRC);
520 IXGBE_READ_REG(hw, IXGBE_BPRC);
521 IXGBE_READ_REG(hw, IXGBE_MPRC);
522 IXGBE_READ_REG(hw, IXGBE_GPTC);
523 IXGBE_READ_REG(hw, IXGBE_GORCL);
524 IXGBE_READ_REG(hw, IXGBE_GORCH);
525 IXGBE_READ_REG(hw, IXGBE_GOTCL);
526 IXGBE_READ_REG(hw, IXGBE_GOTCH);
527 if (hw->mac.type == ixgbe_mac_82598EB)
528 for (i = 0; i < 8; i++)
529 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
530 IXGBE_READ_REG(hw, IXGBE_RUC);
531 IXGBE_READ_REG(hw, IXGBE_RFC);
532 IXGBE_READ_REG(hw, IXGBE_ROC);
533 IXGBE_READ_REG(hw, IXGBE_RJC);
534 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
535 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
536 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
537 IXGBE_READ_REG(hw, IXGBE_TORL);
538 IXGBE_READ_REG(hw, IXGBE_TORH);
539 IXGBE_READ_REG(hw, IXGBE_TPR);
540 IXGBE_READ_REG(hw, IXGBE_TPT);
541 IXGBE_READ_REG(hw, IXGBE_PTC64);
542 IXGBE_READ_REG(hw, IXGBE_PTC127);
543 IXGBE_READ_REG(hw, IXGBE_PTC255);
544 IXGBE_READ_REG(hw, IXGBE_PTC511);
545 IXGBE_READ_REG(hw, IXGBE_PTC1023);
546 IXGBE_READ_REG(hw, IXGBE_PTC1522);
547 IXGBE_READ_REG(hw, IXGBE_MPTC);
548 IXGBE_READ_REG(hw, IXGBE_BPTC);
549 for (i = 0; i < 16; i++) {
550 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
551 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
552 if (hw->mac.type >= ixgbe_mac_82599EB) {
553 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
554 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
555 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
556 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
557 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
559 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
560 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
564 if (hw->mac.type == ixgbe_mac_X540) {
566 ixgbe_identify_phy(hw);
567 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
568 IXGBE_MDIO_PCS_DEV_TYPE, &i);
569 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
570 IXGBE_MDIO_PCS_DEV_TYPE, &i);
571 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
572 IXGBE_MDIO_PCS_DEV_TYPE, &i);
573 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
574 IXGBE_MDIO_PCS_DEV_TYPE, &i);
577 return IXGBE_SUCCESS;
581 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
582 * @hw: pointer to hardware structure
583 * @pba_num: stores the part number string from the EEPROM
584 * @pba_num_size: part number string buffer length
586 * Reads the part number string from the EEPROM.
588 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
597 DEBUGFUNC("ixgbe_read_pba_string_generic");
599 if (pba_num == NULL) {
600 DEBUGOUT("PBA string buffer was null\n");
601 return IXGBE_ERR_INVALID_ARGUMENT;
604 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
606 DEBUGOUT("NVM Read Error\n");
610 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
612 DEBUGOUT("NVM Read Error\n");
617 * if data is not ptr guard the PBA must be in legacy format which
618 * means pba_ptr is actually our second data word for the PBA number
619 * and we can decode it into an ascii string
621 if (data != IXGBE_PBANUM_PTR_GUARD) {
622 DEBUGOUT("NVM PBA number is not stored as string\n");
624 /* we will need 11 characters to store the PBA */
625 if (pba_num_size < 11) {
626 DEBUGOUT("PBA string buffer too small\n");
627 return IXGBE_ERR_NO_SPACE;
630 /* extract hex string from data and pba_ptr */
631 pba_num[0] = (data >> 12) & 0xF;
632 pba_num[1] = (data >> 8) & 0xF;
633 pba_num[2] = (data >> 4) & 0xF;
634 pba_num[3] = data & 0xF;
635 pba_num[4] = (pba_ptr >> 12) & 0xF;
636 pba_num[5] = (pba_ptr >> 8) & 0xF;
639 pba_num[8] = (pba_ptr >> 4) & 0xF;
640 pba_num[9] = pba_ptr & 0xF;
642 /* put a null character on the end of our string */
645 /* switch all the data but the '-' to hex char */
646 for (offset = 0; offset < 10; offset++) {
647 if (pba_num[offset] < 0xA)
648 pba_num[offset] += '0';
649 else if (pba_num[offset] < 0x10)
650 pba_num[offset] += 'A' - 0xA;
653 return IXGBE_SUCCESS;
656 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
658 DEBUGOUT("NVM Read Error\n");
662 if (length == 0xFFFF || length == 0) {
663 DEBUGOUT("NVM PBA number section invalid length\n");
664 return IXGBE_ERR_PBA_SECTION;
667 /* check if pba_num buffer is big enough */
668 if (pba_num_size < (((u32)length * 2) - 1)) {
669 DEBUGOUT("PBA string buffer too small\n");
670 return IXGBE_ERR_NO_SPACE;
673 /* trim pba length from start of string */
677 for (offset = 0; offset < length; offset++) {
678 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
680 DEBUGOUT("NVM Read Error\n");
683 pba_num[offset * 2] = (u8)(data >> 8);
684 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
686 pba_num[offset * 2] = '\0';
688 return IXGBE_SUCCESS;
692 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
693 * @hw: pointer to hardware structure
694 * @pba_num: stores the part number from the EEPROM
696 * Reads the part number from the EEPROM.
698 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
703 DEBUGFUNC("ixgbe_read_pba_num_generic");
705 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
707 DEBUGOUT("NVM Read Error\n");
709 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
710 DEBUGOUT("NVM Not supported\n");
711 return IXGBE_NOT_IMPLEMENTED;
713 *pba_num = (u32)(data << 16);
715 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
717 DEBUGOUT("NVM Read Error\n");
722 return IXGBE_SUCCESS;
727 * @hw: pointer to the HW structure
728 * @eeprom_buf: optional pointer to EEPROM image
729 * @eeprom_buf_size: size of EEPROM image in words
730 * @max_pba_block_size: PBA block size limit
731 * @pba: pointer to output PBA structure
733 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
734 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
737 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
738 u32 eeprom_buf_size, u16 max_pba_block_size,
739 struct ixgbe_pba *pba)
745 return IXGBE_ERR_PARAM;
747 if (eeprom_buf == NULL) {
748 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
753 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
754 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
755 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
757 return IXGBE_ERR_PARAM;
761 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
762 if (pba->pba_block == NULL)
763 return IXGBE_ERR_PARAM;
765 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
771 if (pba_block_size > max_pba_block_size)
772 return IXGBE_ERR_PARAM;
774 if (eeprom_buf == NULL) {
775 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
781 if (eeprom_buf_size > (u32)(pba->word[1] +
782 pba->pba_block[0])) {
783 memcpy(pba->pba_block,
784 &eeprom_buf[pba->word[1]],
785 pba_block_size * sizeof(u16));
787 return IXGBE_ERR_PARAM;
792 return IXGBE_SUCCESS;
796 * ixgbe_write_pba_raw
797 * @hw: pointer to the HW structure
798 * @eeprom_buf: optional pointer to EEPROM image
799 * @eeprom_buf_size: size of EEPROM image in words
800 * @pba: pointer to PBA structure
802 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
803 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
806 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
807 u32 eeprom_buf_size, struct ixgbe_pba *pba)
812 return IXGBE_ERR_PARAM;
814 if (eeprom_buf == NULL) {
815 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
820 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
821 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
822 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
824 return IXGBE_ERR_PARAM;
828 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
829 if (pba->pba_block == NULL)
830 return IXGBE_ERR_PARAM;
832 if (eeprom_buf == NULL) {
833 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
839 if (eeprom_buf_size > (u32)(pba->word[1] +
840 pba->pba_block[0])) {
841 memcpy(&eeprom_buf[pba->word[1]],
843 pba->pba_block[0] * sizeof(u16));
845 return IXGBE_ERR_PARAM;
850 return IXGBE_SUCCESS;
854 * ixgbe_get_pba_block_size
855 * @hw: pointer to the HW structure
856 * @eeprom_buf: optional pointer to EEPROM image
857 * @eeprom_buf_size: size of EEPROM image in words
858 * @pba_data_size: pointer to output variable
860 * Returns the size of the PBA block in words. Function operates on EEPROM
861 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
865 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
866 u32 eeprom_buf_size, u16 *pba_block_size)
872 DEBUGFUNC("ixgbe_get_pba_block_size");
874 if (eeprom_buf == NULL) {
875 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
880 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
881 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
882 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
884 return IXGBE_ERR_PARAM;
888 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
889 if (eeprom_buf == NULL) {
890 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
895 if (eeprom_buf_size > pba_word[1])
896 length = eeprom_buf[pba_word[1] + 0];
898 return IXGBE_ERR_PARAM;
901 if (length == 0xFFFF || length == 0)
902 return IXGBE_ERR_PBA_SECTION;
904 /* PBA number in legacy format, there is no PBA Block. */
908 if (pba_block_size != NULL)
909 *pba_block_size = length;
911 return IXGBE_SUCCESS;
915 * ixgbe_get_mac_addr_generic - Generic get MAC address
916 * @hw: pointer to hardware structure
917 * @mac_addr: Adapter MAC address
919 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
920 * A reset of the adapter must be performed prior to calling this function
921 * in order for the MAC address to have been loaded from the EEPROM into RAR0
923 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
929 DEBUGFUNC("ixgbe_get_mac_addr_generic");
931 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
932 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
934 for (i = 0; i < 4; i++)
935 mac_addr[i] = (u8)(rar_low >> (i*8));
937 for (i = 0; i < 2; i++)
938 mac_addr[i+4] = (u8)(rar_high >> (i*8));
940 return IXGBE_SUCCESS;
944 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
945 * @hw: pointer to hardware structure
946 * @link_status: the link status returned by the PCI config space
948 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
950 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
952 struct ixgbe_mac_info *mac = &hw->mac;
954 hw->bus.type = ixgbe_bus_type_pci_express;
956 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
957 case IXGBE_PCI_LINK_WIDTH_1:
958 hw->bus.width = ixgbe_bus_width_pcie_x1;
960 case IXGBE_PCI_LINK_WIDTH_2:
961 hw->bus.width = ixgbe_bus_width_pcie_x2;
963 case IXGBE_PCI_LINK_WIDTH_4:
964 hw->bus.width = ixgbe_bus_width_pcie_x4;
966 case IXGBE_PCI_LINK_WIDTH_8:
967 hw->bus.width = ixgbe_bus_width_pcie_x8;
970 hw->bus.width = ixgbe_bus_width_unknown;
974 switch (link_status & IXGBE_PCI_LINK_SPEED) {
975 case IXGBE_PCI_LINK_SPEED_2500:
976 hw->bus.speed = ixgbe_bus_speed_2500;
978 case IXGBE_PCI_LINK_SPEED_5000:
979 hw->bus.speed = ixgbe_bus_speed_5000;
981 case IXGBE_PCI_LINK_SPEED_8000:
982 hw->bus.speed = ixgbe_bus_speed_8000;
985 hw->bus.speed = ixgbe_bus_speed_unknown;
989 mac->ops.set_lan_id(hw);
993 * ixgbe_get_bus_info_generic - Generic set PCI bus info
994 * @hw: pointer to hardware structure
996 * Gets the PCI bus info (speed, width, type) then calls helper function to
997 * store this data within the ixgbe_hw structure.
999 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1003 DEBUGFUNC("ixgbe_get_bus_info_generic");
1005 /* Get the negotiated link width and speed from PCI config space */
1006 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1008 ixgbe_set_pci_config_data_generic(hw, link_status);
1010 return IXGBE_SUCCESS;
1014 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1015 * @hw: pointer to the HW structure
1017 * Determines the LAN function id by reading memory-mapped registers
1018 * and swaps the port value if requested.
1020 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1022 struct ixgbe_bus_info *bus = &hw->bus;
1025 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1027 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1028 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1029 bus->lan_id = bus->func;
1031 /* check for a port swap */
1032 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
1033 if (reg & IXGBE_FACTPS_LFS)
1038 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1039 * @hw: pointer to hardware structure
1041 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1042 * disables transmit and receive units. The adapter_stopped flag is used by
1043 * the shared code and drivers to determine if the adapter is in a stopped
1044 * state and should not touch the hardware.
1046 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1051 DEBUGFUNC("ixgbe_stop_adapter_generic");
1054 * Set the adapter_stopped flag so other driver functions stop touching
1057 hw->adapter_stopped = true;
1059 /* Disable the receive unit */
1060 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
1062 /* Clear interrupt mask to stop interrupts from being generated */
1063 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1065 /* Clear any pending interrupts, flush previous writes */
1066 IXGBE_READ_REG(hw, IXGBE_EICR);
1068 /* Disable the transmit unit. Each queue must be disabled. */
1069 for (i = 0; i < hw->mac.max_tx_queues; i++)
1070 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1072 /* Disable the receive unit by stopping each queue */
1073 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1074 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1075 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1076 reg_val |= IXGBE_RXDCTL_SWFLSH;
1077 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1080 /* flush all queues disables */
1081 IXGBE_WRITE_FLUSH(hw);
1085 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
1086 * access and verify no pending requests
1088 return ixgbe_disable_pcie_master(hw);
1092 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1093 * @hw: pointer to hardware structure
1094 * @index: led number to turn on
1096 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1098 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1100 DEBUGFUNC("ixgbe_led_on_generic");
1102 /* To turn on the LED, set mode to ON. */
1103 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1104 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1105 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1106 IXGBE_WRITE_FLUSH(hw);
1108 return IXGBE_SUCCESS;
1112 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1113 * @hw: pointer to hardware structure
1114 * @index: led number to turn off
1116 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1118 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1120 DEBUGFUNC("ixgbe_led_off_generic");
1122 /* To turn off the LED, set mode to OFF. */
1123 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1124 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1125 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1126 IXGBE_WRITE_FLUSH(hw);
1128 return IXGBE_SUCCESS;
1132 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1133 * @hw: pointer to hardware structure
1135 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1136 * ixgbe_hw struct in order to set up EEPROM access.
1138 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1140 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1144 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1146 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1147 eeprom->type = ixgbe_eeprom_none;
1148 /* Set default semaphore delay to 10ms which is a well
1150 eeprom->semaphore_delay = 10;
1151 /* Clear EEPROM page size, it will be initialized as needed */
1152 eeprom->word_page_size = 0;
1155 * Check for EEPROM present first.
1156 * If not present leave as none
1158 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1159 if (eec & IXGBE_EEC_PRES) {
1160 eeprom->type = ixgbe_eeprom_spi;
1163 * SPI EEPROM is assumed here. This code would need to
1164 * change if a future EEPROM is not SPI.
1166 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1167 IXGBE_EEC_SIZE_SHIFT);
1168 eeprom->word_size = 1 << (eeprom_size +
1169 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1172 if (eec & IXGBE_EEC_ADDR_SIZE)
1173 eeprom->address_bits = 16;
1175 eeprom->address_bits = 8;
1176 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1177 "%d\n", eeprom->type, eeprom->word_size,
1178 eeprom->address_bits);
1181 return IXGBE_SUCCESS;
1185 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1186 * @hw: pointer to hardware structure
1187 * @offset: offset within the EEPROM to write
1188 * @words: number of word(s)
1189 * @data: 16 bit word(s) to write to EEPROM
1191 * Reads 16 bit word(s) from EEPROM through bit-bang method
1193 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1194 u16 words, u16 *data)
1196 s32 status = IXGBE_SUCCESS;
1199 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1201 hw->eeprom.ops.init_params(hw);
1204 status = IXGBE_ERR_INVALID_ARGUMENT;
1208 if (offset + words > hw->eeprom.word_size) {
1209 status = IXGBE_ERR_EEPROM;
1214 * The EEPROM page size cannot be queried from the chip. We do lazy
1215 * initialization. It is worth to do that when we write large buffer.
1217 if ((hw->eeprom.word_page_size == 0) &&
1218 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1219 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1222 * We cannot hold synchronization semaphores for too long
1223 * to avoid other entity starvation. However it is more efficient
1224 * to read in bursts than synchronizing access for each word.
1226 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1227 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1228 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1229 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1232 if (status != IXGBE_SUCCESS)
1241 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1242 * @hw: pointer to hardware structure
1243 * @offset: offset within the EEPROM to be written to
1244 * @words: number of word(s)
1245 * @data: 16 bit word(s) to be written to the EEPROM
1247 * If ixgbe_eeprom_update_checksum is not called after this function, the
1248 * EEPROM will most likely contain an invalid checksum.
1250 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1251 u16 words, u16 *data)
1257 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1259 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1261 /* Prepare the EEPROM for writing */
1262 status = ixgbe_acquire_eeprom(hw);
1264 if (status == IXGBE_SUCCESS) {
1265 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1266 ixgbe_release_eeprom(hw);
1267 status = IXGBE_ERR_EEPROM;
1271 if (status == IXGBE_SUCCESS) {
1272 for (i = 0; i < words; i++) {
1273 ixgbe_standby_eeprom(hw);
1275 /* Send the WRITE ENABLE command (8 bit opcode ) */
1276 ixgbe_shift_out_eeprom_bits(hw,
1277 IXGBE_EEPROM_WREN_OPCODE_SPI,
1278 IXGBE_EEPROM_OPCODE_BITS);
1280 ixgbe_standby_eeprom(hw);
1283 * Some SPI eeproms use the 8th address bit embedded
1286 if ((hw->eeprom.address_bits == 8) &&
1287 ((offset + i) >= 128))
1288 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1290 /* Send the Write command (8-bit opcode + addr) */
1291 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1292 IXGBE_EEPROM_OPCODE_BITS);
1293 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1294 hw->eeprom.address_bits);
1296 page_size = hw->eeprom.word_page_size;
1298 /* Send the data in burst via SPI*/
1301 word = (word >> 8) | (word << 8);
1302 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1307 /* do not wrap around page */
1308 if (((offset + i) & (page_size - 1)) ==
1311 } while (++i < words);
1313 ixgbe_standby_eeprom(hw);
1316 /* Done with writing - release the EEPROM */
1317 ixgbe_release_eeprom(hw);
1324 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1325 * @hw: pointer to hardware structure
1326 * @offset: offset within the EEPROM to be written to
1327 * @data: 16 bit word to be written to the EEPROM
1329 * If ixgbe_eeprom_update_checksum is not called after this function, the
1330 * EEPROM will most likely contain an invalid checksum.
1332 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1336 DEBUGFUNC("ixgbe_write_eeprom_generic");
1338 hw->eeprom.ops.init_params(hw);
1340 if (offset >= hw->eeprom.word_size) {
1341 status = IXGBE_ERR_EEPROM;
1345 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1352 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1353 * @hw: pointer to hardware structure
1354 * @offset: offset within the EEPROM to be read
1355 * @data: read 16 bit words(s) from EEPROM
1356 * @words: number of word(s)
1358 * Reads 16 bit word(s) from EEPROM through bit-bang method
1360 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1361 u16 words, u16 *data)
1363 s32 status = IXGBE_SUCCESS;
1366 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1368 hw->eeprom.ops.init_params(hw);
1371 status = IXGBE_ERR_INVALID_ARGUMENT;
1375 if (offset + words > hw->eeprom.word_size) {
1376 status = IXGBE_ERR_EEPROM;
1381 * We cannot hold synchronization semaphores for too long
1382 * to avoid other entity starvation. However it is more efficient
1383 * to read in bursts than synchronizing access for each word.
1385 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1386 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1387 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1389 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1392 if (status != IXGBE_SUCCESS)
1401 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1402 * @hw: pointer to hardware structure
1403 * @offset: offset within the EEPROM to be read
1404 * @words: number of word(s)
1405 * @data: read 16 bit word(s) from EEPROM
1407 * Reads 16 bit word(s) from EEPROM through bit-bang method
1409 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1410 u16 words, u16 *data)
1414 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1417 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1419 /* Prepare the EEPROM for reading */
1420 status = ixgbe_acquire_eeprom(hw);
1422 if (status == IXGBE_SUCCESS) {
1423 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1424 ixgbe_release_eeprom(hw);
1425 status = IXGBE_ERR_EEPROM;
1429 if (status == IXGBE_SUCCESS) {
1430 for (i = 0; i < words; i++) {
1431 ixgbe_standby_eeprom(hw);
1433 * Some SPI eeproms use the 8th address bit embedded
1436 if ((hw->eeprom.address_bits == 8) &&
1437 ((offset + i) >= 128))
1438 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1440 /* Send the READ command (opcode + addr) */
1441 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1442 IXGBE_EEPROM_OPCODE_BITS);
1443 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1444 hw->eeprom.address_bits);
1446 /* Read the data. */
1447 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1448 data[i] = (word_in >> 8) | (word_in << 8);
1451 /* End this read operation */
1452 ixgbe_release_eeprom(hw);
1459 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1460 * @hw: pointer to hardware structure
1461 * @offset: offset within the EEPROM to be read
1462 * @data: read 16 bit value from EEPROM
1464 * Reads 16 bit value from EEPROM through bit-bang method
1466 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1471 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1473 hw->eeprom.ops.init_params(hw);
1475 if (offset >= hw->eeprom.word_size) {
1476 status = IXGBE_ERR_EEPROM;
1480 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1487 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1488 * @hw: pointer to hardware structure
1489 * @offset: offset of word in the EEPROM to read
1490 * @words: number of word(s)
1491 * @data: 16 bit word(s) from the EEPROM
1493 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1495 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1496 u16 words, u16 *data)
1499 s32 status = IXGBE_SUCCESS;
1502 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1504 hw->eeprom.ops.init_params(hw);
1507 status = IXGBE_ERR_INVALID_ARGUMENT;
1508 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1512 if (offset >= hw->eeprom.word_size) {
1513 status = IXGBE_ERR_EEPROM;
1514 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1518 for (i = 0; i < words; i++) {
1519 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1520 IXGBE_EEPROM_RW_REG_START;
1522 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1523 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1525 if (status == IXGBE_SUCCESS) {
1526 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1527 IXGBE_EEPROM_RW_REG_DATA);
1529 DEBUGOUT("Eeprom read timed out\n");
1538 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1539 * @hw: pointer to hardware structure
1540 * @offset: offset within the EEPROM to be used as a scratch pad
1542 * Discover EEPROM page size by writing marching data at given offset.
1543 * This function is called only when we are writing a new large buffer
1544 * at given offset so the data would be overwritten anyway.
1546 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1549 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1550 s32 status = IXGBE_SUCCESS;
1553 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1555 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1558 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1559 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1560 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1561 hw->eeprom.word_page_size = 0;
1562 if (status != IXGBE_SUCCESS)
1565 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1566 if (status != IXGBE_SUCCESS)
1570 * When writing in burst more than the actual page size
1571 * EEPROM address wraps around current page.
1573 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1575 DEBUGOUT1("Detected EEPROM page size = %d words.",
1576 hw->eeprom.word_page_size);
1582 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1583 * @hw: pointer to hardware structure
1584 * @offset: offset of word in the EEPROM to read
1585 * @data: word read from the EEPROM
1587 * Reads a 16 bit word from the EEPROM using the EERD register.
1589 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1591 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1595 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1596 * @hw: pointer to hardware structure
1597 * @offset: offset of word in the EEPROM to write
1598 * @words: number of word(s)
1599 * @data: word(s) write to the EEPROM
1601 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1603 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1604 u16 words, u16 *data)
1607 s32 status = IXGBE_SUCCESS;
1610 DEBUGFUNC("ixgbe_write_eewr_generic");
1612 hw->eeprom.ops.init_params(hw);
1615 status = IXGBE_ERR_INVALID_ARGUMENT;
1616 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1620 if (offset >= hw->eeprom.word_size) {
1621 status = IXGBE_ERR_EEPROM;
1622 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1626 for (i = 0; i < words; i++) {
1627 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1628 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1629 IXGBE_EEPROM_RW_REG_START;
1631 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1632 if (status != IXGBE_SUCCESS) {
1633 DEBUGOUT("Eeprom write EEWR timed out\n");
1637 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1639 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1640 if (status != IXGBE_SUCCESS) {
1641 DEBUGOUT("Eeprom write EEWR timed out\n");
1651 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1652 * @hw: pointer to hardware structure
1653 * @offset: offset of word in the EEPROM to write
1654 * @data: word write to the EEPROM
1656 * Write a 16 bit word to the EEPROM using the EEWR register.
1658 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1660 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1664 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1665 * @hw: pointer to hardware structure
1666 * @ee_reg: EEPROM flag for polling
1668 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1669 * read or write is done respectively.
1671 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1675 s32 status = IXGBE_ERR_EEPROM;
1677 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1679 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1680 if (ee_reg == IXGBE_NVM_POLL_READ)
1681 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1683 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1685 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1686 status = IXGBE_SUCCESS;
1692 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1693 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1694 "EEPROM read/write done polling timed out");
1700 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1701 * @hw: pointer to hardware structure
1703 * Prepares EEPROM for access using bit-bang method. This function should
1704 * be called before issuing a command to the EEPROM.
1706 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1708 s32 status = IXGBE_SUCCESS;
1712 DEBUGFUNC("ixgbe_acquire_eeprom");
1714 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1716 status = IXGBE_ERR_SWFW_SYNC;
1718 if (status == IXGBE_SUCCESS) {
1719 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1721 /* Request EEPROM Access */
1722 eec |= IXGBE_EEC_REQ;
1723 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1725 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1726 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1727 if (eec & IXGBE_EEC_GNT)
1732 /* Release if grant not acquired */
1733 if (!(eec & IXGBE_EEC_GNT)) {
1734 eec &= ~IXGBE_EEC_REQ;
1735 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1736 DEBUGOUT("Could not acquire EEPROM grant\n");
1738 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1739 status = IXGBE_ERR_EEPROM;
1742 /* Setup EEPROM for Read/Write */
1743 if (status == IXGBE_SUCCESS) {
1744 /* Clear CS and SK */
1745 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1746 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1747 IXGBE_WRITE_FLUSH(hw);
1755 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1756 * @hw: pointer to hardware structure
1758 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1760 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1762 s32 status = IXGBE_ERR_EEPROM;
1767 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1770 /* Get SMBI software semaphore between device drivers first */
1771 for (i = 0; i < timeout; i++) {
1773 * If the SMBI bit is 0 when we read it, then the bit will be
1774 * set and we have the semaphore
1776 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1777 if (!(swsm & IXGBE_SWSM_SMBI)) {
1778 status = IXGBE_SUCCESS;
1785 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1788 * this release is particularly important because our attempts
1789 * above to get the semaphore may have succeeded, and if there
1790 * was a timeout, we should unconditionally clear the semaphore
1791 * bits to free the driver to make progress
1793 ixgbe_release_eeprom_semaphore(hw);
1798 * If the SMBI bit is 0 when we read it, then the bit will be
1799 * set and we have the semaphore
1801 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1802 if (!(swsm & IXGBE_SWSM_SMBI))
1803 status = IXGBE_SUCCESS;
1806 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1807 if (status == IXGBE_SUCCESS) {
1808 for (i = 0; i < timeout; i++) {
1809 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1811 /* Set the SW EEPROM semaphore bit to request access */
1812 swsm |= IXGBE_SWSM_SWESMBI;
1813 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1816 * If we set the bit successfully then we got the
1819 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1820 if (swsm & IXGBE_SWSM_SWESMBI)
1827 * Release semaphores and return error if SW EEPROM semaphore
1828 * was not granted because we don't have access to the EEPROM
1831 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1832 "SWESMBI Software EEPROM semaphore not granted.\n");
1833 ixgbe_release_eeprom_semaphore(hw);
1834 status = IXGBE_ERR_EEPROM;
1837 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1838 "Software semaphore SMBI between device drivers "
1846 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1847 * @hw: pointer to hardware structure
1849 * This function clears hardware semaphore bits.
1851 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1855 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1857 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1859 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1860 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1861 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1862 IXGBE_WRITE_FLUSH(hw);
1866 * ixgbe_ready_eeprom - Polls for EEPROM ready
1867 * @hw: pointer to hardware structure
1869 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1871 s32 status = IXGBE_SUCCESS;
1875 DEBUGFUNC("ixgbe_ready_eeprom");
1878 * Read "Status Register" repeatedly until the LSB is cleared. The
1879 * EEPROM will signal that the command has been completed by clearing
1880 * bit 0 of the internal status register. If it's not cleared within
1881 * 5 milliseconds, then error out.
1883 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1884 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1885 IXGBE_EEPROM_OPCODE_BITS);
1886 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1887 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1891 ixgbe_standby_eeprom(hw);
1895 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1896 * devices (and only 0-5mSec on 5V devices)
1898 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1899 DEBUGOUT("SPI EEPROM Status error\n");
1900 status = IXGBE_ERR_EEPROM;
1907 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1908 * @hw: pointer to hardware structure
1910 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1914 DEBUGFUNC("ixgbe_standby_eeprom");
1916 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1918 /* Toggle CS to flush commands */
1919 eec |= IXGBE_EEC_CS;
1920 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1921 IXGBE_WRITE_FLUSH(hw);
1923 eec &= ~IXGBE_EEC_CS;
1924 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1925 IXGBE_WRITE_FLUSH(hw);
1930 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1931 * @hw: pointer to hardware structure
1932 * @data: data to send to the EEPROM
1933 * @count: number of bits to shift out
1935 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1942 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1944 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1947 * Mask is used to shift "count" bits of "data" out to the EEPROM
1948 * one bit at a time. Determine the starting bit based on count
1950 mask = 0x01 << (count - 1);
1952 for (i = 0; i < count; i++) {
1954 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1955 * "1", and then raising and then lowering the clock (the SK
1956 * bit controls the clock input to the EEPROM). A "0" is
1957 * shifted out to the EEPROM by setting "DI" to "0" and then
1958 * raising and then lowering the clock.
1961 eec |= IXGBE_EEC_DI;
1963 eec &= ~IXGBE_EEC_DI;
1965 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1966 IXGBE_WRITE_FLUSH(hw);
1970 ixgbe_raise_eeprom_clk(hw, &eec);
1971 ixgbe_lower_eeprom_clk(hw, &eec);
1974 * Shift mask to signify next bit of data to shift in to the
1980 /* We leave the "DI" bit set to "0" when we leave this routine. */
1981 eec &= ~IXGBE_EEC_DI;
1982 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1983 IXGBE_WRITE_FLUSH(hw);
1987 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1988 * @hw: pointer to hardware structure
1990 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1996 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
1999 * In order to read a register from the EEPROM, we need to shift
2000 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2001 * the clock input to the EEPROM (setting the SK bit), and then reading
2002 * the value of the "DO" bit. During this "shifting in" process the
2003 * "DI" bit should always be clear.
2005 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2007 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2009 for (i = 0; i < count; i++) {
2011 ixgbe_raise_eeprom_clk(hw, &eec);
2013 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2015 eec &= ~(IXGBE_EEC_DI);
2016 if (eec & IXGBE_EEC_DO)
2019 ixgbe_lower_eeprom_clk(hw, &eec);
2026 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2027 * @hw: pointer to hardware structure
2028 * @eec: EEC register's current value
2030 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2032 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2035 * Raise the clock input to the EEPROM
2036 * (setting the SK bit), then delay
2038 *eec = *eec | IXGBE_EEC_SK;
2039 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2040 IXGBE_WRITE_FLUSH(hw);
2045 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2046 * @hw: pointer to hardware structure
2047 * @eecd: EECD's current value
2049 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2051 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2054 * Lower the clock input to the EEPROM (clearing the SK bit), then
2057 *eec = *eec & ~IXGBE_EEC_SK;
2058 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2059 IXGBE_WRITE_FLUSH(hw);
2064 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2065 * @hw: pointer to hardware structure
2067 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2071 DEBUGFUNC("ixgbe_release_eeprom");
2073 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2075 eec |= IXGBE_EEC_CS; /* Pull CS high */
2076 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2078 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2079 IXGBE_WRITE_FLUSH(hw);
2083 /* Stop requesting EEPROM access */
2084 eec &= ~IXGBE_EEC_REQ;
2085 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2087 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2089 /* Delay before attempt to obtain semaphore again to allow FW access */
2090 msec_delay(hw->eeprom.semaphore_delay);
2094 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2095 * @hw: pointer to hardware structure
2097 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2106 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2108 /* Include 0x0-0x3F in the checksum */
2109 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2110 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) {
2111 DEBUGOUT("EEPROM read failed\n");
2117 /* Include all data from pointers except for the fw pointer */
2118 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2119 hw->eeprom.ops.read(hw, i, &pointer);
2121 /* Make sure the pointer seems valid */
2122 if (pointer != 0xFFFF && pointer != 0) {
2123 hw->eeprom.ops.read(hw, pointer, &length);
2125 if (length != 0xFFFF && length != 0) {
2126 for (j = pointer+1; j <= pointer+length; j++) {
2127 hw->eeprom.ops.read(hw, j, &word);
2134 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2140 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2141 * @hw: pointer to hardware structure
2142 * @checksum_val: calculated checksum
2144 * Performs checksum calculation and validates the EEPROM checksum. If the
2145 * caller does not need checksum_val, the value can be NULL.
2147 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2152 u16 read_checksum = 0;
2154 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2157 * Read the first word from the EEPROM. If this times out or fails, do
2158 * not continue or we could be in for a very long wait while every
2161 status = hw->eeprom.ops.read(hw, 0, &checksum);
2163 if (status == IXGBE_SUCCESS) {
2164 checksum = hw->eeprom.ops.calc_checksum(hw);
2166 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2169 * Verify read checksum from EEPROM is the same as
2170 * calculated checksum
2172 if (read_checksum != checksum)
2173 status = IXGBE_ERR_EEPROM_CHECKSUM;
2175 /* If the user cares, return the calculated checksum */
2177 *checksum_val = checksum;
2179 DEBUGOUT("EEPROM read failed\n");
2186 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2187 * @hw: pointer to hardware structure
2189 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2194 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2197 * Read the first word from the EEPROM. If this times out or fails, do
2198 * not continue or we could be in for a very long wait while every
2201 status = hw->eeprom.ops.read(hw, 0, &checksum);
2203 if (status == IXGBE_SUCCESS) {
2204 checksum = hw->eeprom.ops.calc_checksum(hw);
2205 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
2208 DEBUGOUT("EEPROM read failed\n");
2215 * ixgbe_validate_mac_addr - Validate MAC address
2216 * @mac_addr: pointer to MAC address.
2218 * Tests a MAC address to ensure it is a valid Individual Address
2220 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2222 s32 status = IXGBE_SUCCESS;
2224 DEBUGFUNC("ixgbe_validate_mac_addr");
2226 /* Make sure it is not a multicast address */
2227 if (IXGBE_IS_MULTICAST(mac_addr)) {
2228 DEBUGOUT("MAC address is multicast\n");
2229 status = IXGBE_ERR_INVALID_MAC_ADDR;
2230 /* Not a broadcast address */
2231 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2232 DEBUGOUT("MAC address is broadcast\n");
2233 status = IXGBE_ERR_INVALID_MAC_ADDR;
2234 /* Reject the zero address */
2235 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2236 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2237 DEBUGOUT("MAC address is all zeros\n");
2238 status = IXGBE_ERR_INVALID_MAC_ADDR;
2244 * ixgbe_set_rar_generic - Set Rx address register
2245 * @hw: pointer to hardware structure
2246 * @index: Receive address register to write
2247 * @addr: Address to put into receive address register
2248 * @vmdq: VMDq "set" or "pool" index
2249 * @enable_addr: set flag that address is active
2251 * Puts an ethernet address into a receive address register.
2253 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2256 u32 rar_low, rar_high;
2257 u32 rar_entries = hw->mac.num_rar_entries;
2259 DEBUGFUNC("ixgbe_set_rar_generic");
2261 /* Make sure we are using a valid rar index range */
2262 if (index >= rar_entries) {
2263 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2264 "RAR index %d is out of range.\n", index);
2265 return IXGBE_ERR_INVALID_ARGUMENT;
2268 /* setup VMDq pool selection before this RAR gets enabled */
2269 hw->mac.ops.set_vmdq(hw, index, vmdq);
2272 * HW expects these in little endian so we reverse the byte
2273 * order from network order (big endian) to little endian
2275 rar_low = ((u32)addr[0] |
2276 ((u32)addr[1] << 8) |
2277 ((u32)addr[2] << 16) |
2278 ((u32)addr[3] << 24));
2280 * Some parts put the VMDq setting in the extra RAH bits,
2281 * so save everything except the lower 16 bits that hold part
2282 * of the address and the address valid bit.
2284 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2285 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2286 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2288 if (enable_addr != 0)
2289 rar_high |= IXGBE_RAH_AV;
2291 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2292 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2294 return IXGBE_SUCCESS;
2298 * ixgbe_clear_rar_generic - Remove Rx address register
2299 * @hw: pointer to hardware structure
2300 * @index: Receive address register to write
2302 * Clears an ethernet address from a receive address register.
2304 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2307 u32 rar_entries = hw->mac.num_rar_entries;
2309 DEBUGFUNC("ixgbe_clear_rar_generic");
2311 /* Make sure we are using a valid rar index range */
2312 if (index >= rar_entries) {
2313 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2314 "RAR index %d is out of range.\n", index);
2315 return IXGBE_ERR_INVALID_ARGUMENT;
2319 * Some parts put the VMDq setting in the extra RAH bits,
2320 * so save everything except the lower 16 bits that hold part
2321 * of the address and the address valid bit.
2323 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2324 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2326 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2327 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2329 /* clear VMDq pool/queue selection for this RAR */
2330 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2332 return IXGBE_SUCCESS;
2336 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2337 * @hw: pointer to hardware structure
2339 * Places the MAC address in receive address register 0 and clears the rest
2340 * of the receive address registers. Clears the multicast table. Assumes
2341 * the receiver is in reset when the routine is called.
2343 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2346 u32 rar_entries = hw->mac.num_rar_entries;
2348 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2351 * If the current mac address is valid, assume it is a software override
2352 * to the permanent address.
2353 * Otherwise, use the permanent address from the eeprom.
2355 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2356 IXGBE_ERR_INVALID_MAC_ADDR) {
2357 /* Get the MAC address from the RAR0 for later reference */
2358 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2360 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2361 hw->mac.addr[0], hw->mac.addr[1],
2363 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2364 hw->mac.addr[4], hw->mac.addr[5]);
2366 /* Setup the receive address. */
2367 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2368 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2369 hw->mac.addr[0], hw->mac.addr[1],
2371 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2372 hw->mac.addr[4], hw->mac.addr[5]);
2374 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2376 /* clear VMDq pool/queue selection for RAR 0 */
2377 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2379 hw->addr_ctrl.overflow_promisc = 0;
2381 hw->addr_ctrl.rar_used_count = 1;
2383 /* Zero out the other receive addresses. */
2384 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2385 for (i = 1; i < rar_entries; i++) {
2386 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2387 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2391 hw->addr_ctrl.mta_in_use = 0;
2392 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2394 DEBUGOUT(" Clearing MTA\n");
2395 for (i = 0; i < hw->mac.mcft_size; i++)
2396 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2398 ixgbe_init_uta_tables(hw);
2400 return IXGBE_SUCCESS;
2404 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2405 * @hw: pointer to hardware structure
2406 * @addr: new address
2408 * Adds it to unused receive address register or goes into promiscuous mode.
2410 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2412 u32 rar_entries = hw->mac.num_rar_entries;
2415 DEBUGFUNC("ixgbe_add_uc_addr");
2417 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2418 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2421 * Place this address in the RAR if there is room,
2422 * else put the controller into promiscuous mode
2424 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2425 rar = hw->addr_ctrl.rar_used_count;
2426 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2427 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2428 hw->addr_ctrl.rar_used_count++;
2430 hw->addr_ctrl.overflow_promisc++;
2433 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2437 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2438 * @hw: pointer to hardware structure
2439 * @addr_list: the list of new addresses
2440 * @addr_count: number of addresses
2441 * @next: iterator function to walk the address list
2443 * The given list replaces any existing list. Clears the secondary addrs from
2444 * receive address registers. Uses unused receive address registers for the
2445 * first secondary addresses, and falls back to promiscuous mode as needed.
2447 * Drivers using secondary unicast addresses must set user_set_promisc when
2448 * manually putting the device into promiscuous mode.
2450 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2451 u32 addr_count, ixgbe_mc_addr_itr next)
2455 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2460 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2463 * Clear accounting of old secondary address list,
2464 * don't count RAR[0]
2466 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2467 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2468 hw->addr_ctrl.overflow_promisc = 0;
2470 /* Zero out the other receive addresses */
2471 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2472 for (i = 0; i < uc_addr_in_use; i++) {
2473 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2474 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2477 /* Add the new addresses */
2478 for (i = 0; i < addr_count; i++) {
2479 DEBUGOUT(" Adding the secondary addresses:\n");
2480 addr = next(hw, &addr_list, &vmdq);
2481 ixgbe_add_uc_addr(hw, addr, vmdq);
2484 if (hw->addr_ctrl.overflow_promisc) {
2485 /* enable promisc if not already in overflow or set by user */
2486 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2487 DEBUGOUT(" Entering address overflow promisc mode\n");
2488 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2489 fctrl |= IXGBE_FCTRL_UPE;
2490 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2493 /* only disable if set by overflow, not by user */
2494 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2495 DEBUGOUT(" Leaving address overflow promisc mode\n");
2496 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2497 fctrl &= ~IXGBE_FCTRL_UPE;
2498 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2502 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2503 return IXGBE_SUCCESS;
2507 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2508 * @hw: pointer to hardware structure
2509 * @mc_addr: the multicast address
2511 * Extracts the 12 bits, from a multicast address, to determine which
2512 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2513 * incoming rx multicast addresses, to determine the bit-vector to check in
2514 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2515 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2516 * to mc_filter_type.
2518 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2522 DEBUGFUNC("ixgbe_mta_vector");
2524 switch (hw->mac.mc_filter_type) {
2525 case 0: /* use bits [47:36] of the address */
2526 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2528 case 1: /* use bits [46:35] of the address */
2529 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2531 case 2: /* use bits [45:34] of the address */
2532 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2534 case 3: /* use bits [43:32] of the address */
2535 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2537 default: /* Invalid mc_filter_type */
2538 DEBUGOUT("MC filter type param set incorrectly\n");
2543 /* vector can only be 12-bits or boundary will be exceeded */
2549 * ixgbe_set_mta - Set bit-vector in multicast table
2550 * @hw: pointer to hardware structure
2551 * @hash_value: Multicast address hash value
2553 * Sets the bit-vector in the multicast table.
2555 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2561 DEBUGFUNC("ixgbe_set_mta");
2563 hw->addr_ctrl.mta_in_use++;
2565 vector = ixgbe_mta_vector(hw, mc_addr);
2566 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2569 * The MTA is a register array of 128 32-bit registers. It is treated
2570 * like an array of 4096 bits. We want to set bit
2571 * BitArray[vector_value]. So we figure out what register the bit is
2572 * in, read it, OR in the new bit, then write back the new value. The
2573 * register is determined by the upper 7 bits of the vector value and
2574 * the bit within that register are determined by the lower 5 bits of
2577 vector_reg = (vector >> 5) & 0x7F;
2578 vector_bit = vector & 0x1F;
2579 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2583 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2584 * @hw: pointer to hardware structure
2585 * @mc_addr_list: the list of new multicast addresses
2586 * @mc_addr_count: number of addresses
2587 * @next: iterator function to walk the multicast address list
2588 * @clear: flag, when set clears the table beforehand
2590 * When the clear flag is set, the given list replaces any existing list.
2591 * Hashes the given addresses into the multicast table.
2593 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2594 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2600 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2603 * Set the new number of MC addresses that we are being requested to
2606 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2607 hw->addr_ctrl.mta_in_use = 0;
2609 /* Clear mta_shadow */
2611 DEBUGOUT(" Clearing MTA\n");
2612 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2615 /* Update mta_shadow */
2616 for (i = 0; i < mc_addr_count; i++) {
2617 DEBUGOUT(" Adding the multicast addresses:\n");
2618 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2622 for (i = 0; i < hw->mac.mcft_size; i++)
2623 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2624 hw->mac.mta_shadow[i]);
2626 if (hw->addr_ctrl.mta_in_use > 0)
2627 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2628 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2630 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2631 return IXGBE_SUCCESS;
2635 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2636 * @hw: pointer to hardware structure
2638 * Enables multicast address in RAR and the use of the multicast hash table.
2640 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2642 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2644 DEBUGFUNC("ixgbe_enable_mc_generic");
2646 if (a->mta_in_use > 0)
2647 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2648 hw->mac.mc_filter_type);
2650 return IXGBE_SUCCESS;
2654 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2655 * @hw: pointer to hardware structure
2657 * Disables multicast address in RAR and the use of the multicast hash table.
2659 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2661 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2663 DEBUGFUNC("ixgbe_disable_mc_generic");
2665 if (a->mta_in_use > 0)
2666 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2668 return IXGBE_SUCCESS;
2672 * ixgbe_fc_enable_generic - Enable flow control
2673 * @hw: pointer to hardware structure
2675 * Enable flow control according to the current settings.
2677 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2679 s32 ret_val = IXGBE_SUCCESS;
2680 u32 mflcn_reg, fccfg_reg;
2685 DEBUGFUNC("ixgbe_fc_enable_generic");
2687 /* Validate the water mark configuration */
2688 if (!hw->fc.pause_time) {
2689 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2693 /* Low water mark of zero causes XOFF floods */
2694 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2695 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2696 hw->fc.high_water[i]) {
2697 if (!hw->fc.low_water[i] ||
2698 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2699 DEBUGOUT("Invalid water mark configuration\n");
2700 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2706 /* Negotiate the fc mode to use */
2707 ixgbe_fc_autoneg(hw);
2709 /* Disable any previous flow control settings */
2710 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2711 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2713 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2714 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2717 * The possible values of fc.current_mode are:
2718 * 0: Flow control is completely disabled
2719 * 1: Rx flow control is enabled (we can receive pause frames,
2720 * but not send pause frames).
2721 * 2: Tx flow control is enabled (we can send pause frames but
2722 * we do not support receiving pause frames).
2723 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2726 switch (hw->fc.current_mode) {
2729 * Flow control is disabled by software override or autoneg.
2730 * The code below will actually disable it in the HW.
2733 case ixgbe_fc_rx_pause:
2735 * Rx Flow control is enabled and Tx Flow control is
2736 * disabled by software override. Since there really
2737 * isn't a way to advertise that we are capable of RX
2738 * Pause ONLY, we will advertise that we support both
2739 * symmetric and asymmetric Rx PAUSE. Later, we will
2740 * disable the adapter's ability to send PAUSE frames.
2742 mflcn_reg |= IXGBE_MFLCN_RFCE;
2744 case ixgbe_fc_tx_pause:
2746 * Tx Flow control is enabled, and Rx Flow control is
2747 * disabled by software override.
2749 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2752 /* Flow control (both Rx and Tx) is enabled by SW override. */
2753 mflcn_reg |= IXGBE_MFLCN_RFCE;
2754 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2757 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2758 "Flow control param set incorrectly\n");
2759 ret_val = IXGBE_ERR_CONFIG;
2764 /* Set 802.3x based flow control settings. */
2765 mflcn_reg |= IXGBE_MFLCN_DPF;
2766 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2767 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2770 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2771 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2772 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2773 hw->fc.high_water[i]) {
2774 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2775 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2776 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2778 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2780 * In order to prevent Tx hangs when the internal Tx
2781 * switch is enabled we must set the high water mark
2782 * to the Rx packet buffer size - 24KB. This allows
2783 * the Tx switch to function even under heavy Rx
2786 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2789 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2792 /* Configure pause time (2 TCs per register) */
2793 reg = hw->fc.pause_time * 0x00010001;
2794 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2795 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2797 /* Configure flow control refresh threshold value */
2798 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2805 * ixgbe_negotiate_fc - Negotiate flow control
2806 * @hw: pointer to hardware structure
2807 * @adv_reg: flow control advertised settings
2808 * @lp_reg: link partner's flow control settings
2809 * @adv_sym: symmetric pause bit in advertisement
2810 * @adv_asm: asymmetric pause bit in advertisement
2811 * @lp_sym: symmetric pause bit in link partner advertisement
2812 * @lp_asm: asymmetric pause bit in link partner advertisement
2814 * Find the intersection between advertised settings and link partner's
2815 * advertised settings
2817 STATIC s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2818 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2820 if ((!(adv_reg)) || (!(lp_reg))) {
2821 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2822 "Local or link partner's advertised flow control "
2823 "settings are NULL. Local: %x, link partner: %x\n",
2825 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2828 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2830 * Now we need to check if the user selected Rx ONLY
2831 * of pause frames. In this case, we had to advertise
2832 * FULL flow control because we could not advertise RX
2833 * ONLY. Hence, we must now check to see if we need to
2834 * turn OFF the TRANSMISSION of PAUSE frames.
2836 if (hw->fc.requested_mode == ixgbe_fc_full) {
2837 hw->fc.current_mode = ixgbe_fc_full;
2838 DEBUGOUT("Flow Control = FULL.\n");
2840 hw->fc.current_mode = ixgbe_fc_rx_pause;
2841 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2843 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2844 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2845 hw->fc.current_mode = ixgbe_fc_tx_pause;
2846 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2847 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2848 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2849 hw->fc.current_mode = ixgbe_fc_rx_pause;
2850 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2852 hw->fc.current_mode = ixgbe_fc_none;
2853 DEBUGOUT("Flow Control = NONE.\n");
2855 return IXGBE_SUCCESS;
2859 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2860 * @hw: pointer to hardware structure
2862 * Enable flow control according on 1 gig fiber.
2864 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2866 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2867 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2870 * On multispeed fiber at 1g, bail out if
2871 * - link is up but AN did not complete, or if
2872 * - link is up and AN completed but timed out
2875 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2876 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2877 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2878 ERROR_REPORT1(IXGBE_ERROR_POLLING,
2879 "Auto-Negotiation did not complete or timed out");
2883 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2884 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2886 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2887 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2888 IXGBE_PCS1GANA_ASM_PAUSE,
2889 IXGBE_PCS1GANA_SYM_PAUSE,
2890 IXGBE_PCS1GANA_ASM_PAUSE);
2897 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2898 * @hw: pointer to hardware structure
2900 * Enable flow control according to IEEE clause 37.
2902 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2904 u32 links2, anlp1_reg, autoc_reg, links;
2905 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2908 * On backplane, bail out if
2909 * - backplane autoneg was not completed, or if
2910 * - we are 82599 and link partner is not AN enabled
2912 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2913 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2914 ERROR_REPORT1(IXGBE_ERROR_POLLING,
2915 "Auto-Negotiation did not complete");
2919 if (hw->mac.type == ixgbe_mac_82599EB) {
2920 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2921 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2922 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2923 "Link partner is not AN enabled");
2928 * Read the 10g AN autoc and LP ability registers and resolve
2929 * local flow control settings accordingly
2931 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2932 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2934 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2935 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2936 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2943 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2944 * @hw: pointer to hardware structure
2946 * Enable flow control according to IEEE clause 37.
2948 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2950 u16 technology_ability_reg = 0;
2951 u16 lp_technology_ability_reg = 0;
2953 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2954 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2955 &technology_ability_reg);
2956 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2957 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2958 &lp_technology_ability_reg);
2960 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2961 (u32)lp_technology_ability_reg,
2962 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2963 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2967 * ixgbe_fc_autoneg - Configure flow control
2968 * @hw: pointer to hardware structure
2970 * Compares our advertised flow control capabilities to those advertised by
2971 * our link partner, and determines the proper flow control mode to use.
2973 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2975 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2976 ixgbe_link_speed speed;
2979 DEBUGFUNC("ixgbe_fc_autoneg");
2982 * AN should have completed when the cable was plugged in.
2983 * Look for reasons to bail out. Bail out if:
2984 * - FC autoneg is disabled, or if
2987 if (hw->fc.disable_fc_autoneg) {
2988 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2989 "Flow control autoneg is disabled");
2993 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2995 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
2999 switch (hw->phy.media_type) {
3000 /* Autoneg flow control on fiber adapters */
3001 case ixgbe_media_type_fiber:
3002 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3003 ret_val = ixgbe_fc_autoneg_fiber(hw);
3006 /* Autoneg flow control on backplane adapters */
3007 case ixgbe_media_type_backplane:
3008 ret_val = ixgbe_fc_autoneg_backplane(hw);
3011 /* Autoneg flow control on copper adapters */
3012 case ixgbe_media_type_copper:
3013 if (ixgbe_device_supports_autoneg_fc(hw))
3014 ret_val = ixgbe_fc_autoneg_copper(hw);
3022 if (ret_val == IXGBE_SUCCESS) {
3023 hw->fc.fc_was_autonegged = true;
3025 hw->fc.fc_was_autonegged = false;
3026 hw->fc.current_mode = hw->fc.requested_mode;
3031 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3032 * @hw: pointer to hardware structure
3034 * System-wide timeout range is encoded in PCIe Device Control2 register.
3036 * Add 10% to specified maximum and return the number of times to poll for
3037 * completion timeout, in units of 100 microsec. Never return less than
3038 * 800 = 80 millisec.
3040 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3045 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3046 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3049 case IXGBE_PCIDEVCTRL2_65_130ms:
3050 pollcnt = 1300; /* 130 millisec */
3052 case IXGBE_PCIDEVCTRL2_260_520ms:
3053 pollcnt = 5200; /* 520 millisec */
3055 case IXGBE_PCIDEVCTRL2_1_2s:
3056 pollcnt = 20000; /* 2 sec */
3058 case IXGBE_PCIDEVCTRL2_4_8s:
3059 pollcnt = 80000; /* 8 sec */
3061 case IXGBE_PCIDEVCTRL2_17_34s:
3062 pollcnt = 34000; /* 34 sec */
3064 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3065 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3066 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3067 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3069 pollcnt = 800; /* 80 millisec minimum */
3073 /* add 10% to spec maximum */
3074 return (pollcnt * 11) / 10;
3078 * ixgbe_disable_pcie_master - Disable PCI-express master access
3079 * @hw: pointer to hardware structure
3081 * Disables PCI-Express master access and verifies there are no pending
3082 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3083 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3084 * is returned signifying master requests disabled.
3086 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3088 s32 status = IXGBE_SUCCESS;
3092 DEBUGFUNC("ixgbe_disable_pcie_master");
3094 /* Always set this bit to ensure any future transactions are blocked */
3095 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3097 /* Exit if master requests are blocked */
3098 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3099 IXGBE_REMOVED(hw->hw_addr))
3102 /* Poll for master request bit to clear */
3103 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3105 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3110 * Two consecutive resets are required via CTRL.RST per datasheet
3111 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3112 * of this need. The first reset prevents new master requests from
3113 * being issued by our device. We then must wait 1usec or more for any
3114 * remaining completions from the PCIe bus to trickle in, and then reset
3115 * again to clear out any effects they may have had on our device.
3117 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3118 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3121 * Before proceeding, make sure that the PCIe block does not have
3122 * transactions pending.
3124 poll = ixgbe_pcie_timeout_poll(hw);
3125 for (i = 0; i < poll; i++) {
3127 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3128 if (IXGBE_REMOVED(hw->hw_addr))
3130 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3134 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3135 "PCIe transaction pending bit also did not clear.\n");
3136 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3143 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3144 * @hw: pointer to hardware structure
3145 * @mask: Mask to specify which semaphore to acquire
3147 * Acquires the SWFW semaphore through the GSSR register for the specified
3148 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3150 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
3154 u32 fwmask = mask << 5;
3158 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3160 for (i = 0; i < timeout; i++) {
3162 * SW NVM semaphore bit is used for access to all
3163 * SW_FW_SYNC bits (not just NVM)
3165 if (ixgbe_get_eeprom_semaphore(hw))
3166 return IXGBE_ERR_SWFW_SYNC;
3168 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3169 if (!(gssr & (fwmask | swmask))) {
3171 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3172 ixgbe_release_eeprom_semaphore(hw);
3173 return IXGBE_SUCCESS;
3175 /* Resource is currently in use by FW or SW */
3176 ixgbe_release_eeprom_semaphore(hw);
3181 /* If time expired clear the bits holding the lock and retry */
3182 if (gssr & (fwmask | swmask))
3183 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3186 return IXGBE_ERR_SWFW_SYNC;
3190 * ixgbe_release_swfw_sync - Release SWFW semaphore
3191 * @hw: pointer to hardware structure
3192 * @mask: Mask to specify which semaphore to release
3194 * Releases the SWFW semaphore through the GSSR register for the specified
3195 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3197 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
3202 DEBUGFUNC("ixgbe_release_swfw_sync");
3204 ixgbe_get_eeprom_semaphore(hw);
3206 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3208 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3210 ixgbe_release_eeprom_semaphore(hw);
3214 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3215 * @hw: pointer to hardware structure
3217 * Stops the receive data path and waits for the HW to internally empty
3218 * the Rx security block
3220 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3222 #define IXGBE_MAX_SECRX_POLL 40
3227 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3230 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3231 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3232 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3233 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3234 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3235 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3238 /* Use interrupt-safe sleep just in case */
3242 /* For informational purposes only */
3243 if (i >= IXGBE_MAX_SECRX_POLL)
3244 DEBUGOUT("Rx unit being enabled before security "
3245 "path fully disabled. Continuing with init.\n");
3247 return IXGBE_SUCCESS;
3251 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3252 * @hw: pointer to hardware structure
3253 * @reg_val: Value we read from AUTOC
3255 * The default case requires no protection so just to the register read.
3257 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3260 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3261 return IXGBE_SUCCESS;
3265 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3266 * @hw: pointer to hardware structure
3267 * @reg_val: value to write to AUTOC
3268 * @locked: bool to indicate whether the SW/FW lock was already taken by
3271 * The default case requires no protection so just to the register write.
3273 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3275 UNREFERENCED_1PARAMETER(locked);
3277 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3278 return IXGBE_SUCCESS;
3282 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3283 * @hw: pointer to hardware structure
3285 * Enables the receive data path.
3287 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3291 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3293 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3294 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3295 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3296 IXGBE_WRITE_FLUSH(hw);
3298 return IXGBE_SUCCESS;
3302 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3303 * @hw: pointer to hardware structure
3304 * @regval: register value to write to RXCTRL
3306 * Enables the Rx DMA unit
3308 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3310 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3312 if (regval & IXGBE_RXCTRL_RXEN)
3313 ixgbe_enable_rx(hw);
3315 ixgbe_disable_rx(hw);
3317 return IXGBE_SUCCESS;
3321 * ixgbe_blink_led_start_generic - Blink LED based on index.
3322 * @hw: pointer to hardware structure
3323 * @index: led number to blink
3325 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3327 ixgbe_link_speed speed = 0;
3330 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3331 s32 ret_val = IXGBE_SUCCESS;
3332 bool locked = false;
3334 DEBUGFUNC("ixgbe_blink_led_start_generic");
3337 * Link must be up to auto-blink the LEDs;
3338 * Force it if link is down.
3340 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3343 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3344 if (ret_val != IXGBE_SUCCESS)
3347 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3348 autoc_reg |= IXGBE_AUTOC_FLU;
3350 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3351 if (ret_val != IXGBE_SUCCESS)
3354 IXGBE_WRITE_FLUSH(hw);
3358 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3359 led_reg |= IXGBE_LED_BLINK(index);
3360 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3361 IXGBE_WRITE_FLUSH(hw);
3368 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3369 * @hw: pointer to hardware structure
3370 * @index: led number to stop blinking
3372 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3375 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3376 s32 ret_val = IXGBE_SUCCESS;
3377 bool locked = false;
3379 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3381 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3382 if (ret_val != IXGBE_SUCCESS)
3385 autoc_reg &= ~IXGBE_AUTOC_FLU;
3386 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3388 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3389 if (ret_val != IXGBE_SUCCESS)
3392 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3393 led_reg &= ~IXGBE_LED_BLINK(index);
3394 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3395 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3396 IXGBE_WRITE_FLUSH(hw);
3403 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3404 * @hw: pointer to hardware structure
3405 * @san_mac_offset: SAN MAC address offset
3407 * This function will read the EEPROM location for the SAN MAC address
3408 * pointer, and returns the value at that location. This is used in both
3409 * get and set mac_addr routines.
3411 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3412 u16 *san_mac_offset)
3416 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3419 * First read the EEPROM pointer to see if the MAC addresses are
3422 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3425 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3426 "eeprom at offset %d failed",
3427 IXGBE_SAN_MAC_ADDR_PTR);
3434 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3435 * @hw: pointer to hardware structure
3436 * @san_mac_addr: SAN MAC address
3438 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3439 * per-port, so set_lan_id() must be called before reading the addresses.
3440 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3441 * upon for non-SFP connections, so we must call it here.
3443 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3445 u16 san_mac_data, san_mac_offset;
3449 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3452 * First read the EEPROM pointer to see if the MAC addresses are
3453 * available. If they're not, no point in calling set_lan_id() here.
3455 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3456 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3457 goto san_mac_addr_out;
3459 /* make sure we know which port we need to program */
3460 hw->mac.ops.set_lan_id(hw);
3461 /* apply the port offset to the address offset */
3462 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3463 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3464 for (i = 0; i < 3; i++) {
3465 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3468 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3469 "eeprom read at offset %d failed",
3471 goto san_mac_addr_out;
3473 san_mac_addr[i * 2] = (u8)(san_mac_data);
3474 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3477 return IXGBE_SUCCESS;
3481 * No addresses available in this EEPROM. It's not an
3482 * error though, so just wipe the local address and return.
3484 for (i = 0; i < 6; i++)
3485 san_mac_addr[i] = 0xFF;
3486 return IXGBE_SUCCESS;
3490 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3491 * @hw: pointer to hardware structure
3492 * @san_mac_addr: SAN MAC address
3494 * Write a SAN MAC address to the EEPROM.
3496 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3499 u16 san_mac_data, san_mac_offset;
3502 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3504 /* Look for SAN mac address pointer. If not defined, return */
3505 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3506 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3507 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3509 /* Make sure we know which port we need to write */
3510 hw->mac.ops.set_lan_id(hw);
3511 /* Apply the port offset to the address offset */
3512 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3513 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3515 for (i = 0; i < 3; i++) {
3516 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3517 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3518 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3522 return IXGBE_SUCCESS;
3526 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3527 * @hw: pointer to hardware structure
3529 * Read PCIe configuration space, and get the MSI-X vector count from
3530 * the capabilities table.
3532 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3538 switch (hw->mac.type) {
3539 case ixgbe_mac_82598EB:
3540 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3541 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3543 case ixgbe_mac_82599EB:
3544 case ixgbe_mac_X540:
3545 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3546 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3552 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3553 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3554 if (IXGBE_REMOVED(hw->hw_addr))
3556 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3558 /* MSI-X count is zero-based in HW */
3561 if (msix_count > max_msix_count)
3562 msix_count = max_msix_count;
3568 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3569 * @hw: pointer to hardware structure
3570 * @addr: Address to put into receive address register
3571 * @vmdq: VMDq pool to assign
3573 * Puts an ethernet address into a receive address register, or
3574 * finds the rar that it is aleady in; adds to the pool list
3576 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3578 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3579 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3581 u32 rar_low, rar_high;
3582 u32 addr_low, addr_high;
3584 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3586 /* swap bytes for HW little endian */
3587 addr_low = addr[0] | (addr[1] << 8)
3590 addr_high = addr[4] | (addr[5] << 8);
3593 * Either find the mac_id in rar or find the first empty space.
3594 * rar_highwater points to just after the highest currently used
3595 * rar in order to shorten the search. It grows when we add a new
3598 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3599 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3601 if (((IXGBE_RAH_AV & rar_high) == 0)
3602 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3603 first_empty_rar = rar;
3604 } else if ((rar_high & 0xFFFF) == addr_high) {
3605 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3606 if (rar_low == addr_low)
3607 break; /* found it already in the rars */
3611 if (rar < hw->mac.rar_highwater) {
3612 /* already there so just add to the pool bits */
3613 ixgbe_set_vmdq(hw, rar, vmdq);
3614 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3615 /* stick it into first empty RAR slot we found */
3616 rar = first_empty_rar;
3617 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3618 } else if (rar == hw->mac.rar_highwater) {
3619 /* add it to the top of the list and inc the highwater mark */
3620 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3621 hw->mac.rar_highwater++;
3622 } else if (rar >= hw->mac.num_rar_entries) {
3623 return IXGBE_ERR_INVALID_MAC_ADDR;
3627 * If we found rar[0], make sure the default pool bit (we use pool 0)
3628 * remains cleared to be sure default pool packets will get delivered
3631 ixgbe_clear_vmdq(hw, rar, 0);
3637 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3638 * @hw: pointer to hardware struct
3639 * @rar: receive address register index to disassociate
3640 * @vmdq: VMDq pool index to remove from the rar
3642 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3644 u32 mpsar_lo, mpsar_hi;
3645 u32 rar_entries = hw->mac.num_rar_entries;
3647 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3649 /* Make sure we are using a valid rar index range */
3650 if (rar >= rar_entries) {
3651 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3652 "RAR index %d is out of range.\n", rar);
3653 return IXGBE_ERR_INVALID_ARGUMENT;
3656 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3657 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3659 if (IXGBE_REMOVED(hw->hw_addr))
3662 if (!mpsar_lo && !mpsar_hi)
3665 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3667 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3671 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3674 } else if (vmdq < 32) {
3675 mpsar_lo &= ~(1 << vmdq);
3676 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3678 mpsar_hi &= ~(1 << (vmdq - 32));
3679 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3682 /* was that the last pool using this rar? */
3683 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3684 hw->mac.ops.clear_rar(hw, rar);
3686 return IXGBE_SUCCESS;
3690 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3691 * @hw: pointer to hardware struct
3692 * @rar: receive address register index to associate with a VMDq index
3693 * @vmdq: VMDq pool index
3695 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3698 u32 rar_entries = hw->mac.num_rar_entries;
3700 DEBUGFUNC("ixgbe_set_vmdq_generic");
3702 /* Make sure we are using a valid rar index range */
3703 if (rar >= rar_entries) {
3704 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3705 "RAR index %d is out of range.\n", rar);
3706 return IXGBE_ERR_INVALID_ARGUMENT;
3710 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3712 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3714 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3715 mpsar |= 1 << (vmdq - 32);
3716 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3718 return IXGBE_SUCCESS;
3722 * This function should only be involved in the IOV mode.
3723 * In IOV mode, Default pool is next pool after the number of
3724 * VFs advertized and not 0.
3725 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3727 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3728 * @hw: pointer to hardware struct
3729 * @vmdq: VMDq pool index
3731 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3733 u32 rar = hw->mac.san_mac_rar_index;
3735 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3738 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3739 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3741 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3742 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3745 return IXGBE_SUCCESS;
3749 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3750 * @hw: pointer to hardware structure
3752 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3756 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3757 DEBUGOUT(" Clearing UTA\n");
3759 for (i = 0; i < 128; i++)
3760 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3762 return IXGBE_SUCCESS;
3766 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3767 * @hw: pointer to hardware structure
3768 * @vlan: VLAN id to write to VLAN filter
3770 * return the VLVF index where this VLAN id should be placed
3773 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3776 u32 first_empty_slot = 0;
3779 /* short cut the special case */
3784 * Search for the vlan id in the VLVF entries. Save off the first empty
3785 * slot found along the way
3787 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3788 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3789 if (!bits && !(first_empty_slot))
3790 first_empty_slot = regindex;
3791 else if ((bits & 0x0FFF) == vlan)
3796 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3797 * in the VLVF. Else use the first empty VLVF register for this
3800 if (regindex >= IXGBE_VLVF_ENTRIES) {
3801 if (first_empty_slot)
3802 regindex = first_empty_slot;
3804 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
3805 "No space in VLVF.\n");
3806 regindex = IXGBE_ERR_NO_SPACE;
3814 * ixgbe_set_vfta_generic - Set VLAN filter table
3815 * @hw: pointer to hardware structure
3816 * @vlan: VLAN id to write to VLAN filter
3817 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3818 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3820 * Turn on/off specified VLAN in the VLAN filter table.
3822 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3829 s32 ret_val = IXGBE_SUCCESS;
3830 bool vfta_changed = false;
3832 DEBUGFUNC("ixgbe_set_vfta_generic");
3835 return IXGBE_ERR_PARAM;
3838 * this is a 2 part operation - first the VFTA, then the
3839 * VLVF and VLVFB if VT Mode is set
3840 * We don't write the VFTA until we know the VLVF part succeeded.
3844 * The VFTA is a bitstring made up of 128 32-bit registers
3845 * that enable the particular VLAN id, much like the MTA:
3846 * bits[11-5]: which register
3847 * bits[4-0]: which bit in the register
3849 regindex = (vlan >> 5) & 0x7F;
3850 bitindex = vlan & 0x1F;
3851 targetbit = (1 << bitindex);
3852 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3855 if (!(vfta & targetbit)) {
3857 vfta_changed = true;
3860 if ((vfta & targetbit)) {
3862 vfta_changed = true;
3867 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3869 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3871 if (ret_val != IXGBE_SUCCESS)
3875 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3877 return IXGBE_SUCCESS;
3881 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3882 * @hw: pointer to hardware structure
3883 * @vlan: VLAN id to write to VLAN filter
3884 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3885 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3886 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3889 * Turn on/off specified bit in VLVF table.
3891 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3892 bool vlan_on, bool *vfta_changed)
3896 DEBUGFUNC("ixgbe_set_vlvf_generic");
3899 return IXGBE_ERR_PARAM;
3901 /* If VT Mode is set
3903 * make sure the vlan is in VLVF
3904 * set the vind bit in the matching VLVFB
3906 * clear the pool bit and possibly the vind
3908 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3909 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3913 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3918 /* set the pool bit */
3920 bits = IXGBE_READ_REG(hw,
3921 IXGBE_VLVFB(vlvf_index * 2));
3922 bits |= (1 << vind);
3924 IXGBE_VLVFB(vlvf_index * 2),
3927 bits = IXGBE_READ_REG(hw,
3928 IXGBE_VLVFB((vlvf_index * 2) + 1));
3929 bits |= (1 << (vind - 32));
3931 IXGBE_VLVFB((vlvf_index * 2) + 1),
3935 /* clear the pool bit */
3937 bits = IXGBE_READ_REG(hw,
3938 IXGBE_VLVFB(vlvf_index * 2));
3939 bits &= ~(1 << vind);
3941 IXGBE_VLVFB(vlvf_index * 2),
3943 bits |= IXGBE_READ_REG(hw,
3944 IXGBE_VLVFB((vlvf_index * 2) + 1));
3946 bits = IXGBE_READ_REG(hw,
3947 IXGBE_VLVFB((vlvf_index * 2) + 1));
3948 bits &= ~(1 << (vind - 32));
3950 IXGBE_VLVFB((vlvf_index * 2) + 1),
3952 bits |= IXGBE_READ_REG(hw,
3953 IXGBE_VLVFB(vlvf_index * 2));
3958 * If there are still bits set in the VLVFB registers
3959 * for the VLAN ID indicated we need to see if the
3960 * caller is requesting that we clear the VFTA entry bit.
3961 * If the caller has requested that we clear the VFTA
3962 * entry bit but there are still pools/VFs using this VLAN
3963 * ID entry then ignore the request. We're not worried
3964 * about the case where we're turning the VFTA VLAN ID
3965 * entry bit on, only when requested to turn it off as
3966 * there may be multiple pools and/or VFs using the
3967 * VLAN ID entry. In that case we cannot clear the
3968 * VFTA bit until all pools/VFs using that VLAN ID have also
3969 * been cleared. This will be indicated by "bits" being
3973 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3974 (IXGBE_VLVF_VIEN | vlan));
3975 if ((!vlan_on) && (vfta_changed != NULL)) {
3976 /* someone wants to clear the vfta entry
3977 * but some pools/VFs are still using it.
3979 *vfta_changed = false;
3982 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3985 return IXGBE_SUCCESS;
3989 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3990 * @hw: pointer to hardware structure
3992 * Clears the VLAN filer table, and the VMDq index associated with the filter
3994 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3998 DEBUGFUNC("ixgbe_clear_vfta_generic");
4000 for (offset = 0; offset < hw->mac.vft_size; offset++)
4001 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4003 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4004 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4005 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4006 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
4009 return IXGBE_SUCCESS;
4013 * ixgbe_check_mac_link_generic - Determine link and speed status
4014 * @hw: pointer to hardware structure
4015 * @speed: pointer to link speed
4016 * @link_up: true when link is up
4017 * @link_up_wait_to_complete: bool used to wait for link up or not
4019 * Reads the links register to determine if link is up and the current speed
4021 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4022 bool *link_up, bool link_up_wait_to_complete)
4024 u32 links_reg, links_orig;
4027 DEBUGFUNC("ixgbe_check_mac_link_generic");
4029 /* clear the old state */
4030 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4032 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4034 if (links_orig != links_reg) {
4035 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4036 links_orig, links_reg);
4039 if (link_up_wait_to_complete) {
4040 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
4041 if (links_reg & IXGBE_LINKS_UP) {
4048 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4051 if (links_reg & IXGBE_LINKS_UP)
4057 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4058 IXGBE_LINKS_SPEED_10G_82599)
4059 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4060 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4061 IXGBE_LINKS_SPEED_1G_82599)
4062 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4063 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4064 IXGBE_LINKS_SPEED_100_82599)
4065 *speed = IXGBE_LINK_SPEED_100_FULL;
4067 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4069 return IXGBE_SUCCESS;
4073 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4075 * @hw: pointer to hardware structure
4076 * @wwnn_prefix: the alternative WWNN prefix
4077 * @wwpn_prefix: the alternative WWPN prefix
4079 * This function will read the EEPROM from the alternative SAN MAC address
4080 * block to check the support for the alternative WWNN/WWPN prefix support.
4082 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4086 u16 alt_san_mac_blk_offset;
4088 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4090 /* clear output first */
4091 *wwnn_prefix = 0xFFFF;
4092 *wwpn_prefix = 0xFFFF;
4094 /* check if alternative SAN MAC is supported */
4095 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4096 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4097 goto wwn_prefix_err;
4099 if ((alt_san_mac_blk_offset == 0) ||
4100 (alt_san_mac_blk_offset == 0xFFFF))
4101 goto wwn_prefix_out;
4103 /* check capability in alternative san mac address block */
4104 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4105 if (hw->eeprom.ops.read(hw, offset, &caps))
4106 goto wwn_prefix_err;
4107 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4108 goto wwn_prefix_out;
4110 /* get the corresponding prefix for WWNN/WWPN */
4111 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4112 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4113 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4114 "eeprom read at offset %d failed", offset);
4117 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4118 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4119 goto wwn_prefix_err;
4122 return IXGBE_SUCCESS;
4125 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4126 "eeprom read at offset %d failed", offset);
4127 return IXGBE_SUCCESS;
4131 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4132 * @hw: pointer to hardware structure
4133 * @bs: the fcoe boot status
4135 * This function will read the FCOE boot status from the iSCSI FCOE block
4137 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4139 u16 offset, caps, flags;
4142 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4144 /* clear output first */
4145 *bs = ixgbe_fcoe_bootstatus_unavailable;
4147 /* check if FCOE IBA block is present */
4148 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4149 status = hw->eeprom.ops.read(hw, offset, &caps);
4150 if (status != IXGBE_SUCCESS)
4153 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4156 /* check if iSCSI FCOE block is populated */
4157 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4158 if (status != IXGBE_SUCCESS)
4161 if ((offset == 0) || (offset == 0xFFFF))
4164 /* read fcoe flags in iSCSI FCOE block */
4165 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4166 status = hw->eeprom.ops.read(hw, offset, &flags);
4167 if (status != IXGBE_SUCCESS)
4170 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4171 *bs = ixgbe_fcoe_bootstatus_enabled;
4173 *bs = ixgbe_fcoe_bootstatus_disabled;
4180 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4181 * @hw: pointer to hardware structure
4182 * @enable: enable or disable switch for anti-spoofing
4183 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
4186 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
4189 int pf_target_reg = pf >> 3;
4190 int pf_target_shift = pf % 8;
4193 if (hw->mac.type == ixgbe_mac_82598EB)
4197 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
4200 * PFVFSPOOF register array is size 8 with 8 bits assigned to
4201 * MAC anti-spoof enables in each register array element.
4203 for (j = 0; j < pf_target_reg; j++)
4204 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4207 * The PF should be allowed to spoof so that it can support
4208 * emulation mode NICs. Do not set the bits assigned to the PF
4210 pfvfspoof &= (1 << pf_target_shift) - 1;
4211 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4214 * Remaining pools belong to the PF so they do not need to have
4215 * anti-spoofing enabled.
4217 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
4218 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
4222 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4223 * @hw: pointer to hardware structure
4224 * @enable: enable or disable switch for VLAN anti-spoofing
4225 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4228 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4230 int vf_target_reg = vf >> 3;
4231 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4234 if (hw->mac.type == ixgbe_mac_82598EB)
4237 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4239 pfvfspoof |= (1 << vf_target_shift);
4241 pfvfspoof &= ~(1 << vf_target_shift);
4242 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4246 * ixgbe_get_device_caps_generic - Get additional device capabilities
4247 * @hw: pointer to hardware structure
4248 * @device_caps: the EEPROM word with the extra device capabilities
4250 * This function will read the EEPROM location for the device capabilities,
4251 * and return the word through device_caps.
4253 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4255 DEBUGFUNC("ixgbe_get_device_caps_generic");
4257 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4259 return IXGBE_SUCCESS;
4263 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4264 * @hw: pointer to hardware structure
4267 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4272 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4274 /* Enable relaxed ordering */
4275 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4276 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4277 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4278 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4281 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4282 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4283 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4284 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4285 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4291 * ixgbe_calculate_checksum - Calculate checksum for buffer
4292 * @buffer: pointer to EEPROM
4293 * @length: size of EEPROM to calculate a checksum for
4294 * Calculates the checksum for some buffer on a specified length. The
4295 * checksum calculated is returned.
4297 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4302 DEBUGFUNC("ixgbe_calculate_checksum");
4307 for (i = 0; i < length; i++)
4310 return (u8) (0 - sum);
4314 * ixgbe_host_interface_command - Issue command to manageability block
4315 * @hw: pointer to the HW structure
4316 * @buffer: contains the command to write and where the return status will
4318 * @length: length of buffer, must be multiple of 4 bytes
4320 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4321 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
4323 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4327 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4328 u8 buf_len, dword_len;
4330 s32 ret_val = IXGBE_SUCCESS;
4332 DEBUGFUNC("ixgbe_host_interface_command");
4334 if (length == 0 || length & 0x3 ||
4335 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4336 DEBUGOUT("Buffer length failure.\n");
4337 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4341 /* Check that the host interface is enabled. */
4342 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4343 if ((hicr & IXGBE_HICR_EN) == 0) {
4344 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4345 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4349 /* Calculate length in DWORDs */
4350 dword_len = length >> 2;
4353 * The device driver writes the relevant command block
4354 * into the ram area.
4356 for (i = 0; i < dword_len; i++)
4357 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4358 i, IXGBE_CPU_TO_LE32(buffer[i]));
4360 /* Setting this bit tells the ARC that a new command is pending. */
4361 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4363 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
4364 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4365 if (!(hicr & IXGBE_HICR_C))
4370 /* Check command successful completion. */
4371 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
4372 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
4373 DEBUGOUT("Command has failed with no status valid.\n");
4374 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4378 /* Calculate length in DWORDs */
4379 dword_len = hdr_size >> 2;
4381 /* first pull in the header so we know the buffer length */
4382 for (bi = 0; bi < dword_len; bi++) {
4383 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4384 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4387 /* If there is any thing in data position pull it in */
4388 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4392 if (length < (buf_len + hdr_size)) {
4393 DEBUGOUT("Buffer not large enough for reply message.\n");
4394 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4398 /* Calculate length in DWORDs, add 3 for odd lengths */
4399 dword_len = (buf_len + 3) >> 2;
4401 /* Pull in the rest of the buffer (bi is where we left off)*/
4402 for (; bi <= dword_len; bi++) {
4403 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4404 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4412 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4413 * @hw: pointer to the HW structure
4414 * @maj: driver version major number
4415 * @min: driver version minor number
4416 * @build: driver version build number
4417 * @sub: driver version sub build number
4419 * Sends driver version number to firmware through the manageability
4420 * block. On success return IXGBE_SUCCESS
4421 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4422 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4424 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4427 struct ixgbe_hic_drv_info fw_cmd;
4429 s32 ret_val = IXGBE_SUCCESS;
4431 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4433 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
4435 ret_val = IXGBE_ERR_SWFW_SYNC;
4439 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4440 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4441 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4442 fw_cmd.port_num = (u8)hw->bus.func;
4443 fw_cmd.ver_maj = maj;
4444 fw_cmd.ver_min = min;
4445 fw_cmd.ver_build = build;
4446 fw_cmd.ver_sub = sub;
4447 fw_cmd.hdr.checksum = 0;
4448 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4449 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4453 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4454 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4456 if (ret_val != IXGBE_SUCCESS)
4459 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4460 FW_CEM_RESP_STATUS_SUCCESS)
4461 ret_val = IXGBE_SUCCESS;
4463 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4468 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4474 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4475 * @hw: pointer to hardware structure
4476 * @num_pb: number of packet buffers to allocate
4477 * @headroom: reserve n KB of headroom
4478 * @strategy: packet buffer allocation strategy
4480 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4483 u32 pbsize = hw->mac.rx_pb_size;
4485 u32 rxpktsize, txpktsize, txpbthresh;
4487 /* Reserve headroom */
4493 /* Divide remaining packet buffer space amongst the number of packet
4494 * buffers requested using supplied strategy.
4497 case PBA_STRATEGY_WEIGHTED:
4498 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4499 * buffer with 5/8 of the packet buffer space.
4501 rxpktsize = (pbsize * 5) / (num_pb * 4);
4502 pbsize -= rxpktsize * (num_pb / 2);
4503 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4504 for (; i < (num_pb / 2); i++)
4505 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4506 /* Fall through to configure remaining packet buffers */
4507 case PBA_STRATEGY_EQUAL:
4508 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4509 for (; i < num_pb; i++)
4510 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4516 /* Only support an equally distributed Tx packet buffer strategy. */
4517 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4518 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4519 for (i = 0; i < num_pb; i++) {
4520 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4521 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4524 /* Clear unused TCs, if any, to zero buffer size*/
4525 for (; i < IXGBE_MAX_PB; i++) {
4526 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4527 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4528 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4533 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4534 * @hw: pointer to the hardware structure
4536 * The 82599 and x540 MACs can experience issues if TX work is still pending
4537 * when a reset occurs. This function prevents this by flushing the PCIe
4538 * buffers on the system.
4540 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4542 u32 gcr_ext, hlreg0;
4545 * If double reset is not requested then all transactions should
4546 * already be clear and as such there is no work to do
4548 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4552 * Set loopback enable to prevent any transmits from being sent
4553 * should the link come up. This assumes that the RXCTRL.RXEN bit
4554 * has already been cleared.
4556 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4557 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4559 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4560 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4561 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4562 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4564 /* Flush all writes and allow 20usec for all transactions to clear */
4565 IXGBE_WRITE_FLUSH(hw);
4568 /* restore previous register values */
4569 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4570 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4575 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4576 * @hw: pointer to hardware structure
4577 * @map: pointer to u8 arr for returning map
4579 * Read the rtrup2tc HW register and resolve its content into map
4581 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4585 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4586 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4587 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4588 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4592 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4597 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4598 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4599 if (hw->mac.type != ixgbe_mac_82598EB) {
4600 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4601 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4602 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4603 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4604 hw->mac.set_lben = true;
4606 hw->mac.set_lben = false;
4609 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4610 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4614 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4619 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4620 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4622 if (hw->mac.type != ixgbe_mac_82598EB) {
4623 if (hw->mac.set_lben) {
4624 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4625 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4626 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4627 hw->mac.set_lben = false;