1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
39 #ident "$Id: ixgbe_common.c,v 1.382 2013/11/22 01:02:01 jtkirshe Exp $"
41 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
42 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
44 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
46 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
48 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
49 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
51 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
53 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
54 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
56 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
57 u16 words, u16 *data);
58 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
64 * ixgbe_init_ops_generic - Inits function ptrs
65 * @hw: pointer to the hardware structure
67 * Initialize the function pointers.
69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
72 struct ixgbe_mac_info *mac = &hw->mac;
73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
75 DEBUGFUNC("ixgbe_init_ops_generic");
78 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
80 if (eec & IXGBE_EEC_PRES) {
81 eeprom->ops.read = &ixgbe_read_eerd_generic;
82 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
84 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
85 eeprom->ops.read_buffer =
86 &ixgbe_read_eeprom_buffer_bit_bang_generic;
88 eeprom->ops.write = &ixgbe_write_eeprom_generic;
89 eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
90 eeprom->ops.validate_checksum =
91 &ixgbe_validate_eeprom_checksum_generic;
92 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
93 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
96 mac->ops.init_hw = &ixgbe_init_hw_generic;
97 mac->ops.reset_hw = NULL;
98 mac->ops.start_hw = &ixgbe_start_hw_generic;
99 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
100 mac->ops.get_media_type = NULL;
101 mac->ops.get_supported_physical_layer = NULL;
102 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
103 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
104 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
105 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
106 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
107 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
108 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
111 mac->ops.led_on = &ixgbe_led_on_generic;
112 mac->ops.led_off = &ixgbe_led_off_generic;
113 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
114 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
116 /* RAR, Multicast, VLAN */
117 mac->ops.set_rar = &ixgbe_set_rar_generic;
118 mac->ops.clear_rar = &ixgbe_clear_rar_generic;
119 mac->ops.insert_mac_addr = NULL;
120 mac->ops.set_vmdq = NULL;
121 mac->ops.clear_vmdq = NULL;
122 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
123 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
124 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
125 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
126 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
127 mac->ops.clear_vfta = NULL;
128 mac->ops.set_vfta = NULL;
129 mac->ops.set_vlvf = NULL;
130 mac->ops.init_uta_tables = NULL;
131 mac->ops.enable_rx = &ixgbe_enable_rx_generic;
132 mac->ops.disable_rx = &ixgbe_disable_rx_generic;
135 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
138 mac->ops.get_link_capabilities = NULL;
139 mac->ops.setup_link = NULL;
140 mac->ops.check_link = NULL;
142 return IXGBE_SUCCESS;
146 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
148 * @hw: pointer to hardware structure
150 * This function returns true if the device supports flow control
151 * autonegotiation, and false if it does not.
154 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
156 bool supported = false;
157 ixgbe_link_speed speed;
160 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
162 switch (hw->phy.media_type) {
163 case ixgbe_media_type_fiber:
164 hw->mac.ops.check_link(hw, &speed, &link_up, false);
165 /* if link is down, assume supported */
167 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
172 case ixgbe_media_type_backplane:
175 case ixgbe_media_type_copper:
176 /* only some copper devices support flow control autoneg */
177 switch (hw->device_id) {
178 case IXGBE_DEV_ID_82599_T3_LOM:
179 case IXGBE_DEV_ID_X540T:
180 case IXGBE_DEV_ID_X540T1:
190 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
191 "Device %x does not support flow control autoneg",
197 * ixgbe_setup_fc - Set up flow control
198 * @hw: pointer to hardware structure
200 * Called at init time to set up flow control.
202 STATIC s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
204 s32 ret_val = IXGBE_SUCCESS;
205 u32 reg = 0, reg_bp = 0;
207 bool got_lock = false;
209 DEBUGFUNC("ixgbe_setup_fc");
212 * Validate the requested mode. Strict IEEE mode does not allow
213 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
215 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
216 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
217 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
218 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
223 * 10gig parts do not have a word in the EEPROM to determine the
224 * default flow control setting, so we explicitly set it to full.
226 if (hw->fc.requested_mode == ixgbe_fc_default)
227 hw->fc.requested_mode = ixgbe_fc_full;
230 * Set up the 1G and 10G flow control advertisement registers so the
231 * HW will be able to do fc autoneg once the cable is plugged in. If
232 * we link at 10G, the 1G advertisement is harmless and vice versa.
234 switch (hw->phy.media_type) {
235 case ixgbe_media_type_fiber:
236 case ixgbe_media_type_backplane:
237 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
238 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
240 case ixgbe_media_type_copper:
241 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
242 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
249 * The possible values of fc.requested_mode are:
250 * 0: Flow control is completely disabled
251 * 1: Rx flow control is enabled (we can receive pause frames,
252 * but not send pause frames).
253 * 2: Tx flow control is enabled (we can send pause frames but
254 * we do not support receiving pause frames).
255 * 3: Both Rx and Tx flow control (symmetric) are enabled.
258 switch (hw->fc.requested_mode) {
260 /* Flow control completely disabled by software override. */
261 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
262 if (hw->phy.media_type == ixgbe_media_type_backplane)
263 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
264 IXGBE_AUTOC_ASM_PAUSE);
265 else if (hw->phy.media_type == ixgbe_media_type_copper)
266 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
268 case ixgbe_fc_tx_pause:
270 * Tx Flow control is enabled, and Rx Flow control is
271 * disabled by software override.
273 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
274 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
275 if (hw->phy.media_type == ixgbe_media_type_backplane) {
276 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
277 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
278 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
279 reg_cu |= IXGBE_TAF_ASM_PAUSE;
280 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
283 case ixgbe_fc_rx_pause:
285 * Rx Flow control is enabled and Tx Flow control is
286 * disabled by software override. Since there really
287 * isn't a way to advertise that we are capable of RX
288 * Pause ONLY, we will advertise that we support both
289 * symmetric and asymmetric Rx PAUSE, as such we fall
290 * through to the fc_full statement. Later, we will
291 * disable the adapter's ability to send PAUSE frames.
294 /* Flow control (both Rx and Tx) is enabled by SW override. */
295 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
296 if (hw->phy.media_type == ixgbe_media_type_backplane)
297 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
298 IXGBE_AUTOC_ASM_PAUSE;
299 else if (hw->phy.media_type == ixgbe_media_type_copper)
300 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
303 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
304 "Flow control param set incorrectly\n");
305 ret_val = IXGBE_ERR_CONFIG;
310 if (hw->mac.type < ixgbe_mac_X540) {
312 * Enable auto-negotiation between the MAC & PHY;
313 * the MAC will advertise clause 37 flow control.
315 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
316 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
318 /* Disable AN timeout */
319 if (hw->fc.strict_ieee)
320 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
322 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
323 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
327 * AUTOC restart handles negotiation of 1G and 10G on backplane
328 * and copper. There is no need to set the PCS1GCTL register.
331 if (hw->phy.media_type == ixgbe_media_type_backplane) {
332 reg_bp |= IXGBE_AUTOC_AN_RESTART;
333 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
334 * LESM is on, likewise reset_pipeline requries the lock as
335 * it also writes AUTOC.
337 if ((hw->mac.type == ixgbe_mac_82599EB) &&
338 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
339 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
340 IXGBE_GSSR_MAC_CSR_SM);
341 if (ret_val != IXGBE_SUCCESS) {
342 ret_val = IXGBE_ERR_SWFW_SYNC;
348 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
349 if (hw->mac.type == ixgbe_mac_82599EB)
350 ixgbe_reset_pipeline_82599(hw);
353 hw->mac.ops.release_swfw_sync(hw,
354 IXGBE_GSSR_MAC_CSR_SM);
355 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
356 (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
357 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
358 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
361 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
367 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
368 * @hw: pointer to hardware structure
370 * Starts the hardware by filling the bus info structure and media type, clears
371 * all on chip counters, initializes receive address registers, multicast
372 * table, VLAN filter table, calls routine to set up link and flow control
373 * settings, and leaves transmit and receive units disabled and uninitialized
375 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
380 DEBUGFUNC("ixgbe_start_hw_generic");
382 /* Set the media type */
383 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
385 /* PHY ops initialization must be done in reset_hw() */
387 /* Clear the VLAN filter table */
388 hw->mac.ops.clear_vfta(hw);
390 /* Clear statistics registers */
391 hw->mac.ops.clear_hw_cntrs(hw);
393 /* Set No Snoop Disable */
394 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
395 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
396 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
397 IXGBE_WRITE_FLUSH(hw);
399 /* Setup flow control */
400 ret_val = ixgbe_setup_fc(hw);
401 if (ret_val != IXGBE_SUCCESS)
404 /* Clear adapter stopped flag */
405 hw->adapter_stopped = false;
412 * ixgbe_start_hw_gen2 - Init sequence for common device family
413 * @hw: pointer to hw structure
415 * Performs the init sequence common to the second generation
417 * Devices in the second generation:
421 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
426 /* Clear the rate limiters */
427 for (i = 0; i < hw->mac.max_tx_queues; i++) {
428 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
429 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
431 IXGBE_WRITE_FLUSH(hw);
433 /* Disable relaxed ordering */
434 for (i = 0; i < hw->mac.max_tx_queues; i++) {
435 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
436 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
437 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
440 for (i = 0; i < hw->mac.max_rx_queues; i++) {
441 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
442 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
443 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
444 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
447 return IXGBE_SUCCESS;
451 * ixgbe_init_hw_generic - Generic hardware initialization
452 * @hw: pointer to hardware structure
454 * Initialize the hardware by resetting the hardware, filling the bus info
455 * structure and media type, clears all on chip counters, initializes receive
456 * address registers, multicast table, VLAN filter table, calls routine to set
457 * up link and flow control settings, and leaves transmit and receive units
458 * disabled and uninitialized
460 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
464 DEBUGFUNC("ixgbe_init_hw_generic");
466 /* Reset the hardware */
467 status = hw->mac.ops.reset_hw(hw);
469 if (status == IXGBE_SUCCESS) {
471 status = hw->mac.ops.start_hw(hw);
478 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
479 * @hw: pointer to hardware structure
481 * Clears all hardware statistics counters by reading them from the hardware
482 * Statistics counters are clear on read.
484 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
488 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
490 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
491 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
492 IXGBE_READ_REG(hw, IXGBE_ERRBC);
493 IXGBE_READ_REG(hw, IXGBE_MSPDC);
494 for (i = 0; i < 8; i++)
495 IXGBE_READ_REG(hw, IXGBE_MPC(i));
497 IXGBE_READ_REG(hw, IXGBE_MLFC);
498 IXGBE_READ_REG(hw, IXGBE_MRFC);
499 IXGBE_READ_REG(hw, IXGBE_RLEC);
500 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
501 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
502 if (hw->mac.type >= ixgbe_mac_82599EB) {
503 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
504 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
506 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
507 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
510 for (i = 0; i < 8; i++) {
511 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
512 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
513 if (hw->mac.type >= ixgbe_mac_82599EB) {
514 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
515 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
517 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
518 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
521 if (hw->mac.type >= ixgbe_mac_82599EB)
522 for (i = 0; i < 8; i++)
523 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
524 IXGBE_READ_REG(hw, IXGBE_PRC64);
525 IXGBE_READ_REG(hw, IXGBE_PRC127);
526 IXGBE_READ_REG(hw, IXGBE_PRC255);
527 IXGBE_READ_REG(hw, IXGBE_PRC511);
528 IXGBE_READ_REG(hw, IXGBE_PRC1023);
529 IXGBE_READ_REG(hw, IXGBE_PRC1522);
530 IXGBE_READ_REG(hw, IXGBE_GPRC);
531 IXGBE_READ_REG(hw, IXGBE_BPRC);
532 IXGBE_READ_REG(hw, IXGBE_MPRC);
533 IXGBE_READ_REG(hw, IXGBE_GPTC);
534 IXGBE_READ_REG(hw, IXGBE_GORCL);
535 IXGBE_READ_REG(hw, IXGBE_GORCH);
536 IXGBE_READ_REG(hw, IXGBE_GOTCL);
537 IXGBE_READ_REG(hw, IXGBE_GOTCH);
538 if (hw->mac.type == ixgbe_mac_82598EB)
539 for (i = 0; i < 8; i++)
540 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
541 IXGBE_READ_REG(hw, IXGBE_RUC);
542 IXGBE_READ_REG(hw, IXGBE_RFC);
543 IXGBE_READ_REG(hw, IXGBE_ROC);
544 IXGBE_READ_REG(hw, IXGBE_RJC);
545 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
546 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
547 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
548 IXGBE_READ_REG(hw, IXGBE_TORL);
549 IXGBE_READ_REG(hw, IXGBE_TORH);
550 IXGBE_READ_REG(hw, IXGBE_TPR);
551 IXGBE_READ_REG(hw, IXGBE_TPT);
552 IXGBE_READ_REG(hw, IXGBE_PTC64);
553 IXGBE_READ_REG(hw, IXGBE_PTC127);
554 IXGBE_READ_REG(hw, IXGBE_PTC255);
555 IXGBE_READ_REG(hw, IXGBE_PTC511);
556 IXGBE_READ_REG(hw, IXGBE_PTC1023);
557 IXGBE_READ_REG(hw, IXGBE_PTC1522);
558 IXGBE_READ_REG(hw, IXGBE_MPTC);
559 IXGBE_READ_REG(hw, IXGBE_BPTC);
560 for (i = 0; i < 16; i++) {
561 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
562 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
563 if (hw->mac.type >= ixgbe_mac_82599EB) {
564 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
565 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
566 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
567 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
568 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
570 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
571 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
575 if (hw->mac.type == ixgbe_mac_X540) {
577 ixgbe_identify_phy(hw);
578 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
579 IXGBE_MDIO_PCS_DEV_TYPE, &i);
580 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
581 IXGBE_MDIO_PCS_DEV_TYPE, &i);
582 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
583 IXGBE_MDIO_PCS_DEV_TYPE, &i);
584 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
585 IXGBE_MDIO_PCS_DEV_TYPE, &i);
588 return IXGBE_SUCCESS;
592 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
593 * @hw: pointer to hardware structure
594 * @pba_num: stores the part number string from the EEPROM
595 * @pba_num_size: part number string buffer length
597 * Reads the part number string from the EEPROM.
599 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
608 DEBUGFUNC("ixgbe_read_pba_string_generic");
610 if (pba_num == NULL) {
611 DEBUGOUT("PBA string buffer was null\n");
612 return IXGBE_ERR_INVALID_ARGUMENT;
615 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
617 DEBUGOUT("NVM Read Error\n");
621 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
623 DEBUGOUT("NVM Read Error\n");
628 * if data is not ptr guard the PBA must be in legacy format which
629 * means pba_ptr is actually our second data word for the PBA number
630 * and we can decode it into an ascii string
632 if (data != IXGBE_PBANUM_PTR_GUARD) {
633 DEBUGOUT("NVM PBA number is not stored as string\n");
635 /* we will need 11 characters to store the PBA */
636 if (pba_num_size < 11) {
637 DEBUGOUT("PBA string buffer too small\n");
638 return IXGBE_ERR_NO_SPACE;
641 /* extract hex string from data and pba_ptr */
642 pba_num[0] = (data >> 12) & 0xF;
643 pba_num[1] = (data >> 8) & 0xF;
644 pba_num[2] = (data >> 4) & 0xF;
645 pba_num[3] = data & 0xF;
646 pba_num[4] = (pba_ptr >> 12) & 0xF;
647 pba_num[5] = (pba_ptr >> 8) & 0xF;
650 pba_num[8] = (pba_ptr >> 4) & 0xF;
651 pba_num[9] = pba_ptr & 0xF;
653 /* put a null character on the end of our string */
656 /* switch all the data but the '-' to hex char */
657 for (offset = 0; offset < 10; offset++) {
658 if (pba_num[offset] < 0xA)
659 pba_num[offset] += '0';
660 else if (pba_num[offset] < 0x10)
661 pba_num[offset] += 'A' - 0xA;
664 return IXGBE_SUCCESS;
667 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
669 DEBUGOUT("NVM Read Error\n");
673 if (length == 0xFFFF || length == 0) {
674 DEBUGOUT("NVM PBA number section invalid length\n");
675 return IXGBE_ERR_PBA_SECTION;
678 /* check if pba_num buffer is big enough */
679 if (pba_num_size < (((u32)length * 2) - 1)) {
680 DEBUGOUT("PBA string buffer too small\n");
681 return IXGBE_ERR_NO_SPACE;
684 /* trim pba length from start of string */
688 for (offset = 0; offset < length; offset++) {
689 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
691 DEBUGOUT("NVM Read Error\n");
694 pba_num[offset * 2] = (u8)(data >> 8);
695 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
697 pba_num[offset * 2] = '\0';
699 return IXGBE_SUCCESS;
703 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
704 * @hw: pointer to hardware structure
705 * @pba_num: stores the part number from the EEPROM
707 * Reads the part number from the EEPROM.
709 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
714 DEBUGFUNC("ixgbe_read_pba_num_generic");
716 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
718 DEBUGOUT("NVM Read Error\n");
720 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
721 DEBUGOUT("NVM Not supported\n");
722 return IXGBE_NOT_IMPLEMENTED;
724 *pba_num = (u32)(data << 16);
726 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
728 DEBUGOUT("NVM Read Error\n");
733 return IXGBE_SUCCESS;
738 * @hw: pointer to the HW structure
739 * @eeprom_buf: optional pointer to EEPROM image
740 * @eeprom_buf_size: size of EEPROM image in words
741 * @max_pba_block_size: PBA block size limit
742 * @pba: pointer to output PBA structure
744 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
745 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
748 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
749 u32 eeprom_buf_size, u16 max_pba_block_size,
750 struct ixgbe_pba *pba)
756 return IXGBE_ERR_PARAM;
758 if (eeprom_buf == NULL) {
759 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
764 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
765 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
766 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
768 return IXGBE_ERR_PARAM;
772 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
773 if (pba->pba_block == NULL)
774 return IXGBE_ERR_PARAM;
776 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
782 if (pba_block_size > max_pba_block_size)
783 return IXGBE_ERR_PARAM;
785 if (eeprom_buf == NULL) {
786 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
792 if (eeprom_buf_size > (u32)(pba->word[1] +
793 pba->pba_block[0])) {
794 memcpy(pba->pba_block,
795 &eeprom_buf[pba->word[1]],
796 pba_block_size * sizeof(u16));
798 return IXGBE_ERR_PARAM;
803 return IXGBE_SUCCESS;
807 * ixgbe_write_pba_raw
808 * @hw: pointer to the HW structure
809 * @eeprom_buf: optional pointer to EEPROM image
810 * @eeprom_buf_size: size of EEPROM image in words
811 * @pba: pointer to PBA structure
813 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
814 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
817 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
818 u32 eeprom_buf_size, struct ixgbe_pba *pba)
823 return IXGBE_ERR_PARAM;
825 if (eeprom_buf == NULL) {
826 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
831 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
832 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
833 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
835 return IXGBE_ERR_PARAM;
839 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
840 if (pba->pba_block == NULL)
841 return IXGBE_ERR_PARAM;
843 if (eeprom_buf == NULL) {
844 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
850 if (eeprom_buf_size > (u32)(pba->word[1] +
851 pba->pba_block[0])) {
852 memcpy(&eeprom_buf[pba->word[1]],
854 pba->pba_block[0] * sizeof(u16));
856 return IXGBE_ERR_PARAM;
861 return IXGBE_SUCCESS;
865 * ixgbe_get_pba_block_size
866 * @hw: pointer to the HW structure
867 * @eeprom_buf: optional pointer to EEPROM image
868 * @eeprom_buf_size: size of EEPROM image in words
869 * @pba_data_size: pointer to output variable
871 * Returns the size of the PBA block in words. Function operates on EEPROM
872 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
876 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
877 u32 eeprom_buf_size, u16 *pba_block_size)
883 DEBUGFUNC("ixgbe_get_pba_block_size");
885 if (eeprom_buf == NULL) {
886 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
891 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
892 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
893 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
895 return IXGBE_ERR_PARAM;
899 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
900 if (eeprom_buf == NULL) {
901 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
906 if (eeprom_buf_size > pba_word[1])
907 length = eeprom_buf[pba_word[1] + 0];
909 return IXGBE_ERR_PARAM;
912 if (length == 0xFFFF || length == 0)
913 return IXGBE_ERR_PBA_SECTION;
915 /* PBA number in legacy format, there is no PBA Block. */
919 if (pba_block_size != NULL)
920 *pba_block_size = length;
922 return IXGBE_SUCCESS;
926 * ixgbe_get_mac_addr_generic - Generic get MAC address
927 * @hw: pointer to hardware structure
928 * @mac_addr: Adapter MAC address
930 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
931 * A reset of the adapter must be performed prior to calling this function
932 * in order for the MAC address to have been loaded from the EEPROM into RAR0
934 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
940 DEBUGFUNC("ixgbe_get_mac_addr_generic");
942 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
943 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
945 for (i = 0; i < 4; i++)
946 mac_addr[i] = (u8)(rar_low >> (i*8));
948 for (i = 0; i < 2; i++)
949 mac_addr[i+4] = (u8)(rar_high >> (i*8));
951 return IXGBE_SUCCESS;
955 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
956 * @hw: pointer to hardware structure
957 * @link_status: the link status returned by the PCI config space
959 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
961 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
963 struct ixgbe_mac_info *mac = &hw->mac;
965 hw->bus.type = ixgbe_bus_type_pci_express;
967 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
968 case IXGBE_PCI_LINK_WIDTH_1:
969 hw->bus.width = ixgbe_bus_width_pcie_x1;
971 case IXGBE_PCI_LINK_WIDTH_2:
972 hw->bus.width = ixgbe_bus_width_pcie_x2;
974 case IXGBE_PCI_LINK_WIDTH_4:
975 hw->bus.width = ixgbe_bus_width_pcie_x4;
977 case IXGBE_PCI_LINK_WIDTH_8:
978 hw->bus.width = ixgbe_bus_width_pcie_x8;
981 hw->bus.width = ixgbe_bus_width_unknown;
985 switch (link_status & IXGBE_PCI_LINK_SPEED) {
986 case IXGBE_PCI_LINK_SPEED_2500:
987 hw->bus.speed = ixgbe_bus_speed_2500;
989 case IXGBE_PCI_LINK_SPEED_5000:
990 hw->bus.speed = ixgbe_bus_speed_5000;
992 case IXGBE_PCI_LINK_SPEED_8000:
993 hw->bus.speed = ixgbe_bus_speed_8000;
996 hw->bus.speed = ixgbe_bus_speed_unknown;
1000 mac->ops.set_lan_id(hw);
1004 * ixgbe_get_bus_info_generic - Generic set PCI bus info
1005 * @hw: pointer to hardware structure
1007 * Gets the PCI bus info (speed, width, type) then calls helper function to
1008 * store this data within the ixgbe_hw structure.
1010 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1014 DEBUGFUNC("ixgbe_get_bus_info_generic");
1016 /* Get the negotiated link width and speed from PCI config space */
1017 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1019 ixgbe_set_pci_config_data_generic(hw, link_status);
1021 return IXGBE_SUCCESS;
1025 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1026 * @hw: pointer to the HW structure
1028 * Determines the LAN function id by reading memory-mapped registers
1029 * and swaps the port value if requested.
1031 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1033 struct ixgbe_bus_info *bus = &hw->bus;
1036 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1038 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1039 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1040 bus->lan_id = bus->func;
1042 /* check for a port swap */
1043 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
1044 if (reg & IXGBE_FACTPS_LFS)
1049 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1050 * @hw: pointer to hardware structure
1052 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1053 * disables transmit and receive units. The adapter_stopped flag is used by
1054 * the shared code and drivers to determine if the adapter is in a stopped
1055 * state and should not touch the hardware.
1057 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1062 DEBUGFUNC("ixgbe_stop_adapter_generic");
1065 * Set the adapter_stopped flag so other driver functions stop touching
1068 hw->adapter_stopped = true;
1070 /* Disable the receive unit */
1071 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
1073 /* Clear interrupt mask to stop interrupts from being generated */
1074 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1076 /* Clear any pending interrupts, flush previous writes */
1077 IXGBE_READ_REG(hw, IXGBE_EICR);
1079 /* Disable the transmit unit. Each queue must be disabled. */
1080 for (i = 0; i < hw->mac.max_tx_queues; i++)
1081 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1083 /* Disable the receive unit by stopping each queue */
1084 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1085 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1086 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1087 reg_val |= IXGBE_RXDCTL_SWFLSH;
1088 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1091 /* flush all queues disables */
1092 IXGBE_WRITE_FLUSH(hw);
1096 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
1097 * access and verify no pending requests
1099 return ixgbe_disable_pcie_master(hw);
1103 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1104 * @hw: pointer to hardware structure
1105 * @index: led number to turn on
1107 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1109 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1111 DEBUGFUNC("ixgbe_led_on_generic");
1113 /* To turn on the LED, set mode to ON. */
1114 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1115 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1116 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1117 IXGBE_WRITE_FLUSH(hw);
1119 return IXGBE_SUCCESS;
1123 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1124 * @hw: pointer to hardware structure
1125 * @index: led number to turn off
1127 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1129 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1131 DEBUGFUNC("ixgbe_led_off_generic");
1133 /* To turn off the LED, set mode to OFF. */
1134 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1135 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1136 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1137 IXGBE_WRITE_FLUSH(hw);
1139 return IXGBE_SUCCESS;
1143 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1144 * @hw: pointer to hardware structure
1146 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1147 * ixgbe_hw struct in order to set up EEPROM access.
1149 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1151 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1155 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1157 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1158 eeprom->type = ixgbe_eeprom_none;
1159 /* Set default semaphore delay to 10ms which is a well
1161 eeprom->semaphore_delay = 10;
1162 /* Clear EEPROM page size, it will be initialized as needed */
1163 eeprom->word_page_size = 0;
1166 * Check for EEPROM present first.
1167 * If not present leave as none
1169 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1170 if (eec & IXGBE_EEC_PRES) {
1171 eeprom->type = ixgbe_eeprom_spi;
1174 * SPI EEPROM is assumed here. This code would need to
1175 * change if a future EEPROM is not SPI.
1177 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1178 IXGBE_EEC_SIZE_SHIFT);
1179 eeprom->word_size = 1 << (eeprom_size +
1180 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1183 if (eec & IXGBE_EEC_ADDR_SIZE)
1184 eeprom->address_bits = 16;
1186 eeprom->address_bits = 8;
1187 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1188 "%d\n", eeprom->type, eeprom->word_size,
1189 eeprom->address_bits);
1192 return IXGBE_SUCCESS;
1196 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1197 * @hw: pointer to hardware structure
1198 * @offset: offset within the EEPROM to write
1199 * @words: number of word(s)
1200 * @data: 16 bit word(s) to write to EEPROM
1202 * Reads 16 bit word(s) from EEPROM through bit-bang method
1204 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1205 u16 words, u16 *data)
1207 s32 status = IXGBE_SUCCESS;
1210 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1212 hw->eeprom.ops.init_params(hw);
1215 status = IXGBE_ERR_INVALID_ARGUMENT;
1219 if (offset + words > hw->eeprom.word_size) {
1220 status = IXGBE_ERR_EEPROM;
1225 * The EEPROM page size cannot be queried from the chip. We do lazy
1226 * initialization. It is worth to do that when we write large buffer.
1228 if ((hw->eeprom.word_page_size == 0) &&
1229 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1230 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1233 * We cannot hold synchronization semaphores for too long
1234 * to avoid other entity starvation. However it is more efficient
1235 * to read in bursts than synchronizing access for each word.
1237 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1238 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1239 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1240 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1243 if (status != IXGBE_SUCCESS)
1252 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1253 * @hw: pointer to hardware structure
1254 * @offset: offset within the EEPROM to be written to
1255 * @words: number of word(s)
1256 * @data: 16 bit word(s) to be written to the EEPROM
1258 * If ixgbe_eeprom_update_checksum is not called after this function, the
1259 * EEPROM will most likely contain an invalid checksum.
1261 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1262 u16 words, u16 *data)
1268 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1270 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1272 /* Prepare the EEPROM for writing */
1273 status = ixgbe_acquire_eeprom(hw);
1275 if (status == IXGBE_SUCCESS) {
1276 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1277 ixgbe_release_eeprom(hw);
1278 status = IXGBE_ERR_EEPROM;
1282 if (status == IXGBE_SUCCESS) {
1283 for (i = 0; i < words; i++) {
1284 ixgbe_standby_eeprom(hw);
1286 /* Send the WRITE ENABLE command (8 bit opcode ) */
1287 ixgbe_shift_out_eeprom_bits(hw,
1288 IXGBE_EEPROM_WREN_OPCODE_SPI,
1289 IXGBE_EEPROM_OPCODE_BITS);
1291 ixgbe_standby_eeprom(hw);
1294 * Some SPI eeproms use the 8th address bit embedded
1297 if ((hw->eeprom.address_bits == 8) &&
1298 ((offset + i) >= 128))
1299 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1301 /* Send the Write command (8-bit opcode + addr) */
1302 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1303 IXGBE_EEPROM_OPCODE_BITS);
1304 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1305 hw->eeprom.address_bits);
1307 page_size = hw->eeprom.word_page_size;
1309 /* Send the data in burst via SPI*/
1312 word = (word >> 8) | (word << 8);
1313 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1318 /* do not wrap around page */
1319 if (((offset + i) & (page_size - 1)) ==
1322 } while (++i < words);
1324 ixgbe_standby_eeprom(hw);
1327 /* Done with writing - release the EEPROM */
1328 ixgbe_release_eeprom(hw);
1335 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1336 * @hw: pointer to hardware structure
1337 * @offset: offset within the EEPROM to be written to
1338 * @data: 16 bit word to be written to the EEPROM
1340 * If ixgbe_eeprom_update_checksum is not called after this function, the
1341 * EEPROM will most likely contain an invalid checksum.
1343 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1347 DEBUGFUNC("ixgbe_write_eeprom_generic");
1349 hw->eeprom.ops.init_params(hw);
1351 if (offset >= hw->eeprom.word_size) {
1352 status = IXGBE_ERR_EEPROM;
1356 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1363 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1364 * @hw: pointer to hardware structure
1365 * @offset: offset within the EEPROM to be read
1366 * @data: read 16 bit words(s) from EEPROM
1367 * @words: number of word(s)
1369 * Reads 16 bit word(s) from EEPROM through bit-bang method
1371 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1372 u16 words, u16 *data)
1374 s32 status = IXGBE_SUCCESS;
1377 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1379 hw->eeprom.ops.init_params(hw);
1382 status = IXGBE_ERR_INVALID_ARGUMENT;
1386 if (offset + words > hw->eeprom.word_size) {
1387 status = IXGBE_ERR_EEPROM;
1392 * We cannot hold synchronization semaphores for too long
1393 * to avoid other entity starvation. However it is more efficient
1394 * to read in bursts than synchronizing access for each word.
1396 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1397 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1398 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1400 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1403 if (status != IXGBE_SUCCESS)
1412 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1413 * @hw: pointer to hardware structure
1414 * @offset: offset within the EEPROM to be read
1415 * @words: number of word(s)
1416 * @data: read 16 bit word(s) from EEPROM
1418 * Reads 16 bit word(s) from EEPROM through bit-bang method
1420 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1421 u16 words, u16 *data)
1425 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1428 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1430 /* Prepare the EEPROM for reading */
1431 status = ixgbe_acquire_eeprom(hw);
1433 if (status == IXGBE_SUCCESS) {
1434 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1435 ixgbe_release_eeprom(hw);
1436 status = IXGBE_ERR_EEPROM;
1440 if (status == IXGBE_SUCCESS) {
1441 for (i = 0; i < words; i++) {
1442 ixgbe_standby_eeprom(hw);
1444 * Some SPI eeproms use the 8th address bit embedded
1447 if ((hw->eeprom.address_bits == 8) &&
1448 ((offset + i) >= 128))
1449 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1451 /* Send the READ command (opcode + addr) */
1452 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1453 IXGBE_EEPROM_OPCODE_BITS);
1454 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1455 hw->eeprom.address_bits);
1457 /* Read the data. */
1458 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1459 data[i] = (word_in >> 8) | (word_in << 8);
1462 /* End this read operation */
1463 ixgbe_release_eeprom(hw);
1470 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1471 * @hw: pointer to hardware structure
1472 * @offset: offset within the EEPROM to be read
1473 * @data: read 16 bit value from EEPROM
1475 * Reads 16 bit value from EEPROM through bit-bang method
1477 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1482 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1484 hw->eeprom.ops.init_params(hw);
1486 if (offset >= hw->eeprom.word_size) {
1487 status = IXGBE_ERR_EEPROM;
1491 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1498 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1499 * @hw: pointer to hardware structure
1500 * @offset: offset of word in the EEPROM to read
1501 * @words: number of word(s)
1502 * @data: 16 bit word(s) from the EEPROM
1504 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1506 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1507 u16 words, u16 *data)
1510 s32 status = IXGBE_SUCCESS;
1513 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1515 hw->eeprom.ops.init_params(hw);
1518 status = IXGBE_ERR_INVALID_ARGUMENT;
1519 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1523 if (offset >= hw->eeprom.word_size) {
1524 status = IXGBE_ERR_EEPROM;
1525 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1529 for (i = 0; i < words; i++) {
1530 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1531 IXGBE_EEPROM_RW_REG_START;
1533 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1534 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1536 if (status == IXGBE_SUCCESS) {
1537 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1538 IXGBE_EEPROM_RW_REG_DATA);
1540 DEBUGOUT("Eeprom read timed out\n");
1549 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1550 * @hw: pointer to hardware structure
1551 * @offset: offset within the EEPROM to be used as a scratch pad
1553 * Discover EEPROM page size by writing marching data at given offset.
1554 * This function is called only when we are writing a new large buffer
1555 * at given offset so the data would be overwritten anyway.
1557 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1560 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1561 s32 status = IXGBE_SUCCESS;
1564 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1566 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1569 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1570 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1571 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1572 hw->eeprom.word_page_size = 0;
1573 if (status != IXGBE_SUCCESS)
1576 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1577 if (status != IXGBE_SUCCESS)
1581 * When writing in burst more than the actual page size
1582 * EEPROM address wraps around current page.
1584 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1586 DEBUGOUT1("Detected EEPROM page size = %d words.",
1587 hw->eeprom.word_page_size);
1593 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1594 * @hw: pointer to hardware structure
1595 * @offset: offset of word in the EEPROM to read
1596 * @data: word read from the EEPROM
1598 * Reads a 16 bit word from the EEPROM using the EERD register.
1600 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1602 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1606 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1607 * @hw: pointer to hardware structure
1608 * @offset: offset of word in the EEPROM to write
1609 * @words: number of word(s)
1610 * @data: word(s) write to the EEPROM
1612 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1614 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1615 u16 words, u16 *data)
1618 s32 status = IXGBE_SUCCESS;
1621 DEBUGFUNC("ixgbe_write_eewr_generic");
1623 hw->eeprom.ops.init_params(hw);
1626 status = IXGBE_ERR_INVALID_ARGUMENT;
1627 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1631 if (offset >= hw->eeprom.word_size) {
1632 status = IXGBE_ERR_EEPROM;
1633 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1637 for (i = 0; i < words; i++) {
1638 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1639 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1640 IXGBE_EEPROM_RW_REG_START;
1642 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1643 if (status != IXGBE_SUCCESS) {
1644 DEBUGOUT("Eeprom write EEWR timed out\n");
1648 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1650 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1651 if (status != IXGBE_SUCCESS) {
1652 DEBUGOUT("Eeprom write EEWR timed out\n");
1662 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1663 * @hw: pointer to hardware structure
1664 * @offset: offset of word in the EEPROM to write
1665 * @data: word write to the EEPROM
1667 * Write a 16 bit word to the EEPROM using the EEWR register.
1669 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1671 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1675 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1676 * @hw: pointer to hardware structure
1677 * @ee_reg: EEPROM flag for polling
1679 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1680 * read or write is done respectively.
1682 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1686 s32 status = IXGBE_ERR_EEPROM;
1688 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1690 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1691 if (ee_reg == IXGBE_NVM_POLL_READ)
1692 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1694 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1696 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1697 status = IXGBE_SUCCESS;
1703 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1704 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1705 "EEPROM read/write done polling timed out");
1711 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1712 * @hw: pointer to hardware structure
1714 * Prepares EEPROM for access using bit-bang method. This function should
1715 * be called before issuing a command to the EEPROM.
1717 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1719 s32 status = IXGBE_SUCCESS;
1723 DEBUGFUNC("ixgbe_acquire_eeprom");
1725 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1727 status = IXGBE_ERR_SWFW_SYNC;
1729 if (status == IXGBE_SUCCESS) {
1730 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1732 /* Request EEPROM Access */
1733 eec |= IXGBE_EEC_REQ;
1734 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1736 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1737 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1738 if (eec & IXGBE_EEC_GNT)
1743 /* Release if grant not acquired */
1744 if (!(eec & IXGBE_EEC_GNT)) {
1745 eec &= ~IXGBE_EEC_REQ;
1746 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1747 DEBUGOUT("Could not acquire EEPROM grant\n");
1749 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1750 status = IXGBE_ERR_EEPROM;
1753 /* Setup EEPROM for Read/Write */
1754 if (status == IXGBE_SUCCESS) {
1755 /* Clear CS and SK */
1756 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1757 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1758 IXGBE_WRITE_FLUSH(hw);
1766 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1767 * @hw: pointer to hardware structure
1769 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1771 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1773 s32 status = IXGBE_ERR_EEPROM;
1778 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1781 /* Get SMBI software semaphore between device drivers first */
1782 for (i = 0; i < timeout; i++) {
1784 * If the SMBI bit is 0 when we read it, then the bit will be
1785 * set and we have the semaphore
1787 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1788 if (!(swsm & IXGBE_SWSM_SMBI)) {
1789 status = IXGBE_SUCCESS;
1796 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1799 * this release is particularly important because our attempts
1800 * above to get the semaphore may have succeeded, and if there
1801 * was a timeout, we should unconditionally clear the semaphore
1802 * bits to free the driver to make progress
1804 ixgbe_release_eeprom_semaphore(hw);
1809 * If the SMBI bit is 0 when we read it, then the bit will be
1810 * set and we have the semaphore
1812 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1813 if (!(swsm & IXGBE_SWSM_SMBI))
1814 status = IXGBE_SUCCESS;
1817 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1818 if (status == IXGBE_SUCCESS) {
1819 for (i = 0; i < timeout; i++) {
1820 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1822 /* Set the SW EEPROM semaphore bit to request access */
1823 swsm |= IXGBE_SWSM_SWESMBI;
1824 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1827 * If we set the bit successfully then we got the
1830 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1831 if (swsm & IXGBE_SWSM_SWESMBI)
1838 * Release semaphores and return error if SW EEPROM semaphore
1839 * was not granted because we don't have access to the EEPROM
1842 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1843 "SWESMBI Software EEPROM semaphore not granted.\n");
1844 ixgbe_release_eeprom_semaphore(hw);
1845 status = IXGBE_ERR_EEPROM;
1848 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1849 "Software semaphore SMBI between device drivers "
1857 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1858 * @hw: pointer to hardware structure
1860 * This function clears hardware semaphore bits.
1862 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1866 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1868 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1870 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1871 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1872 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1873 IXGBE_WRITE_FLUSH(hw);
1877 * ixgbe_ready_eeprom - Polls for EEPROM ready
1878 * @hw: pointer to hardware structure
1880 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1882 s32 status = IXGBE_SUCCESS;
1886 DEBUGFUNC("ixgbe_ready_eeprom");
1889 * Read "Status Register" repeatedly until the LSB is cleared. The
1890 * EEPROM will signal that the command has been completed by clearing
1891 * bit 0 of the internal status register. If it's not cleared within
1892 * 5 milliseconds, then error out.
1894 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1895 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1896 IXGBE_EEPROM_OPCODE_BITS);
1897 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1898 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1902 ixgbe_standby_eeprom(hw);
1906 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1907 * devices (and only 0-5mSec on 5V devices)
1909 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1910 DEBUGOUT("SPI EEPROM Status error\n");
1911 status = IXGBE_ERR_EEPROM;
1918 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1919 * @hw: pointer to hardware structure
1921 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1925 DEBUGFUNC("ixgbe_standby_eeprom");
1927 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1929 /* Toggle CS to flush commands */
1930 eec |= IXGBE_EEC_CS;
1931 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1932 IXGBE_WRITE_FLUSH(hw);
1934 eec &= ~IXGBE_EEC_CS;
1935 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1936 IXGBE_WRITE_FLUSH(hw);
1941 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1942 * @hw: pointer to hardware structure
1943 * @data: data to send to the EEPROM
1944 * @count: number of bits to shift out
1946 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1953 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1955 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1958 * Mask is used to shift "count" bits of "data" out to the EEPROM
1959 * one bit at a time. Determine the starting bit based on count
1961 mask = 0x01 << (count - 1);
1963 for (i = 0; i < count; i++) {
1965 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1966 * "1", and then raising and then lowering the clock (the SK
1967 * bit controls the clock input to the EEPROM). A "0" is
1968 * shifted out to the EEPROM by setting "DI" to "0" and then
1969 * raising and then lowering the clock.
1972 eec |= IXGBE_EEC_DI;
1974 eec &= ~IXGBE_EEC_DI;
1976 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1977 IXGBE_WRITE_FLUSH(hw);
1981 ixgbe_raise_eeprom_clk(hw, &eec);
1982 ixgbe_lower_eeprom_clk(hw, &eec);
1985 * Shift mask to signify next bit of data to shift in to the
1991 /* We leave the "DI" bit set to "0" when we leave this routine. */
1992 eec &= ~IXGBE_EEC_DI;
1993 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1994 IXGBE_WRITE_FLUSH(hw);
1998 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1999 * @hw: pointer to hardware structure
2001 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
2007 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
2010 * In order to read a register from the EEPROM, we need to shift
2011 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2012 * the clock input to the EEPROM (setting the SK bit), and then reading
2013 * the value of the "DO" bit. During this "shifting in" process the
2014 * "DI" bit should always be clear.
2016 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2018 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2020 for (i = 0; i < count; i++) {
2022 ixgbe_raise_eeprom_clk(hw, &eec);
2024 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2026 eec &= ~(IXGBE_EEC_DI);
2027 if (eec & IXGBE_EEC_DO)
2030 ixgbe_lower_eeprom_clk(hw, &eec);
2037 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2038 * @hw: pointer to hardware structure
2039 * @eec: EEC register's current value
2041 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2043 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2046 * Raise the clock input to the EEPROM
2047 * (setting the SK bit), then delay
2049 *eec = *eec | IXGBE_EEC_SK;
2050 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2051 IXGBE_WRITE_FLUSH(hw);
2056 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2057 * @hw: pointer to hardware structure
2058 * @eecd: EECD's current value
2060 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2062 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2065 * Lower the clock input to the EEPROM (clearing the SK bit), then
2068 *eec = *eec & ~IXGBE_EEC_SK;
2069 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2070 IXGBE_WRITE_FLUSH(hw);
2075 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2076 * @hw: pointer to hardware structure
2078 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2082 DEBUGFUNC("ixgbe_release_eeprom");
2084 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2086 eec |= IXGBE_EEC_CS; /* Pull CS high */
2087 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2089 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2090 IXGBE_WRITE_FLUSH(hw);
2094 /* Stop requesting EEPROM access */
2095 eec &= ~IXGBE_EEC_REQ;
2096 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2098 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2100 /* Delay before attempt to obtain semaphore again to allow FW access */
2101 msec_delay(hw->eeprom.semaphore_delay);
2105 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2106 * @hw: pointer to hardware structure
2108 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2117 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2119 /* Include 0x0-0x3F in the checksum */
2120 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2121 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) {
2122 DEBUGOUT("EEPROM read failed\n");
2128 /* Include all data from pointers except for the fw pointer */
2129 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2130 hw->eeprom.ops.read(hw, i, &pointer);
2132 /* Make sure the pointer seems valid */
2133 if (pointer != 0xFFFF && pointer != 0) {
2134 hw->eeprom.ops.read(hw, pointer, &length);
2136 if (length != 0xFFFF && length != 0) {
2137 for (j = pointer+1; j <= pointer+length; j++) {
2138 hw->eeprom.ops.read(hw, j, &word);
2145 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2151 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2152 * @hw: pointer to hardware structure
2153 * @checksum_val: calculated checksum
2155 * Performs checksum calculation and validates the EEPROM checksum. If the
2156 * caller does not need checksum_val, the value can be NULL.
2158 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2163 u16 read_checksum = 0;
2165 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2168 * Read the first word from the EEPROM. If this times out or fails, do
2169 * not continue or we could be in for a very long wait while every
2172 status = hw->eeprom.ops.read(hw, 0, &checksum);
2174 if (status == IXGBE_SUCCESS) {
2175 checksum = hw->eeprom.ops.calc_checksum(hw);
2177 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2180 * Verify read checksum from EEPROM is the same as
2181 * calculated checksum
2183 if (read_checksum != checksum)
2184 status = IXGBE_ERR_EEPROM_CHECKSUM;
2186 /* If the user cares, return the calculated checksum */
2188 *checksum_val = checksum;
2190 DEBUGOUT("EEPROM read failed\n");
2197 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2198 * @hw: pointer to hardware structure
2200 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2205 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2208 * Read the first word from the EEPROM. If this times out or fails, do
2209 * not continue or we could be in for a very long wait while every
2212 status = hw->eeprom.ops.read(hw, 0, &checksum);
2214 if (status == IXGBE_SUCCESS) {
2215 checksum = hw->eeprom.ops.calc_checksum(hw);
2216 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
2219 DEBUGOUT("EEPROM read failed\n");
2226 * ixgbe_validate_mac_addr - Validate MAC address
2227 * @mac_addr: pointer to MAC address.
2229 * Tests a MAC address to ensure it is a valid Individual Address
2231 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2233 s32 status = IXGBE_SUCCESS;
2235 DEBUGFUNC("ixgbe_validate_mac_addr");
2237 /* Make sure it is not a multicast address */
2238 if (IXGBE_IS_MULTICAST(mac_addr)) {
2239 DEBUGOUT("MAC address is multicast\n");
2240 status = IXGBE_ERR_INVALID_MAC_ADDR;
2241 /* Not a broadcast address */
2242 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2243 DEBUGOUT("MAC address is broadcast\n");
2244 status = IXGBE_ERR_INVALID_MAC_ADDR;
2245 /* Reject the zero address */
2246 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2247 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2248 DEBUGOUT("MAC address is all zeros\n");
2249 status = IXGBE_ERR_INVALID_MAC_ADDR;
2255 * ixgbe_set_rar_generic - Set Rx address register
2256 * @hw: pointer to hardware structure
2257 * @index: Receive address register to write
2258 * @addr: Address to put into receive address register
2259 * @vmdq: VMDq "set" or "pool" index
2260 * @enable_addr: set flag that address is active
2262 * Puts an ethernet address into a receive address register.
2264 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2267 u32 rar_low, rar_high;
2268 u32 rar_entries = hw->mac.num_rar_entries;
2270 DEBUGFUNC("ixgbe_set_rar_generic");
2272 /* Make sure we are using a valid rar index range */
2273 if (index >= rar_entries) {
2274 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2275 "RAR index %d is out of range.\n", index);
2276 return IXGBE_ERR_INVALID_ARGUMENT;
2279 /* setup VMDq pool selection before this RAR gets enabled */
2280 hw->mac.ops.set_vmdq(hw, index, vmdq);
2283 * HW expects these in little endian so we reverse the byte
2284 * order from network order (big endian) to little endian
2286 rar_low = ((u32)addr[0] |
2287 ((u32)addr[1] << 8) |
2288 ((u32)addr[2] << 16) |
2289 ((u32)addr[3] << 24));
2291 * Some parts put the VMDq setting in the extra RAH bits,
2292 * so save everything except the lower 16 bits that hold part
2293 * of the address and the address valid bit.
2295 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2296 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2297 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2299 if (enable_addr != 0)
2300 rar_high |= IXGBE_RAH_AV;
2302 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2303 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2305 return IXGBE_SUCCESS;
2309 * ixgbe_clear_rar_generic - Remove Rx address register
2310 * @hw: pointer to hardware structure
2311 * @index: Receive address register to write
2313 * Clears an ethernet address from a receive address register.
2315 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2318 u32 rar_entries = hw->mac.num_rar_entries;
2320 DEBUGFUNC("ixgbe_clear_rar_generic");
2322 /* Make sure we are using a valid rar index range */
2323 if (index >= rar_entries) {
2324 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2325 "RAR index %d is out of range.\n", index);
2326 return IXGBE_ERR_INVALID_ARGUMENT;
2330 * Some parts put the VMDq setting in the extra RAH bits,
2331 * so save everything except the lower 16 bits that hold part
2332 * of the address and the address valid bit.
2334 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2335 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2337 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2338 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2340 /* clear VMDq pool/queue selection for this RAR */
2341 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2343 return IXGBE_SUCCESS;
2347 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2348 * @hw: pointer to hardware structure
2350 * Places the MAC address in receive address register 0 and clears the rest
2351 * of the receive address registers. Clears the multicast table. Assumes
2352 * the receiver is in reset when the routine is called.
2354 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2357 u32 rar_entries = hw->mac.num_rar_entries;
2359 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2362 * If the current mac address is valid, assume it is a software override
2363 * to the permanent address.
2364 * Otherwise, use the permanent address from the eeprom.
2366 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2367 IXGBE_ERR_INVALID_MAC_ADDR) {
2368 /* Get the MAC address from the RAR0 for later reference */
2369 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2371 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2372 hw->mac.addr[0], hw->mac.addr[1],
2374 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2375 hw->mac.addr[4], hw->mac.addr[5]);
2377 /* Setup the receive address. */
2378 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2379 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2380 hw->mac.addr[0], hw->mac.addr[1],
2382 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2383 hw->mac.addr[4], hw->mac.addr[5]);
2385 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2387 /* clear VMDq pool/queue selection for RAR 0 */
2388 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2390 hw->addr_ctrl.overflow_promisc = 0;
2392 hw->addr_ctrl.rar_used_count = 1;
2394 /* Zero out the other receive addresses. */
2395 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2396 for (i = 1; i < rar_entries; i++) {
2397 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2398 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2402 hw->addr_ctrl.mta_in_use = 0;
2403 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2405 DEBUGOUT(" Clearing MTA\n");
2406 for (i = 0; i < hw->mac.mcft_size; i++)
2407 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2409 ixgbe_init_uta_tables(hw);
2411 return IXGBE_SUCCESS;
2415 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2416 * @hw: pointer to hardware structure
2417 * @addr: new address
2419 * Adds it to unused receive address register or goes into promiscuous mode.
2421 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2423 u32 rar_entries = hw->mac.num_rar_entries;
2426 DEBUGFUNC("ixgbe_add_uc_addr");
2428 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2429 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2432 * Place this address in the RAR if there is room,
2433 * else put the controller into promiscuous mode
2435 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2436 rar = hw->addr_ctrl.rar_used_count;
2437 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2438 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2439 hw->addr_ctrl.rar_used_count++;
2441 hw->addr_ctrl.overflow_promisc++;
2444 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2448 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2449 * @hw: pointer to hardware structure
2450 * @addr_list: the list of new addresses
2451 * @addr_count: number of addresses
2452 * @next: iterator function to walk the address list
2454 * The given list replaces any existing list. Clears the secondary addrs from
2455 * receive address registers. Uses unused receive address registers for the
2456 * first secondary addresses, and falls back to promiscuous mode as needed.
2458 * Drivers using secondary unicast addresses must set user_set_promisc when
2459 * manually putting the device into promiscuous mode.
2461 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2462 u32 addr_count, ixgbe_mc_addr_itr next)
2466 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2471 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2474 * Clear accounting of old secondary address list,
2475 * don't count RAR[0]
2477 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2478 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2479 hw->addr_ctrl.overflow_promisc = 0;
2481 /* Zero out the other receive addresses */
2482 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2483 for (i = 0; i < uc_addr_in_use; i++) {
2484 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2485 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2488 /* Add the new addresses */
2489 for (i = 0; i < addr_count; i++) {
2490 DEBUGOUT(" Adding the secondary addresses:\n");
2491 addr = next(hw, &addr_list, &vmdq);
2492 ixgbe_add_uc_addr(hw, addr, vmdq);
2495 if (hw->addr_ctrl.overflow_promisc) {
2496 /* enable promisc if not already in overflow or set by user */
2497 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2498 DEBUGOUT(" Entering address overflow promisc mode\n");
2499 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2500 fctrl |= IXGBE_FCTRL_UPE;
2501 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2504 /* only disable if set by overflow, not by user */
2505 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2506 DEBUGOUT(" Leaving address overflow promisc mode\n");
2507 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2508 fctrl &= ~IXGBE_FCTRL_UPE;
2509 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2513 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2514 return IXGBE_SUCCESS;
2518 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2519 * @hw: pointer to hardware structure
2520 * @mc_addr: the multicast address
2522 * Extracts the 12 bits, from a multicast address, to determine which
2523 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2524 * incoming rx multicast addresses, to determine the bit-vector to check in
2525 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2526 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2527 * to mc_filter_type.
2529 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2533 DEBUGFUNC("ixgbe_mta_vector");
2535 switch (hw->mac.mc_filter_type) {
2536 case 0: /* use bits [47:36] of the address */
2537 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2539 case 1: /* use bits [46:35] of the address */
2540 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2542 case 2: /* use bits [45:34] of the address */
2543 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2545 case 3: /* use bits [43:32] of the address */
2546 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2548 default: /* Invalid mc_filter_type */
2549 DEBUGOUT("MC filter type param set incorrectly\n");
2554 /* vector can only be 12-bits or boundary will be exceeded */
2560 * ixgbe_set_mta - Set bit-vector in multicast table
2561 * @hw: pointer to hardware structure
2562 * @hash_value: Multicast address hash value
2564 * Sets the bit-vector in the multicast table.
2566 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2572 DEBUGFUNC("ixgbe_set_mta");
2574 hw->addr_ctrl.mta_in_use++;
2576 vector = ixgbe_mta_vector(hw, mc_addr);
2577 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2580 * The MTA is a register array of 128 32-bit registers. It is treated
2581 * like an array of 4096 bits. We want to set bit
2582 * BitArray[vector_value]. So we figure out what register the bit is
2583 * in, read it, OR in the new bit, then write back the new value. The
2584 * register is determined by the upper 7 bits of the vector value and
2585 * the bit within that register are determined by the lower 5 bits of
2588 vector_reg = (vector >> 5) & 0x7F;
2589 vector_bit = vector & 0x1F;
2590 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2594 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2595 * @hw: pointer to hardware structure
2596 * @mc_addr_list: the list of new multicast addresses
2597 * @mc_addr_count: number of addresses
2598 * @next: iterator function to walk the multicast address list
2599 * @clear: flag, when set clears the table beforehand
2601 * When the clear flag is set, the given list replaces any existing list.
2602 * Hashes the given addresses into the multicast table.
2604 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2605 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2611 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2614 * Set the new number of MC addresses that we are being requested to
2617 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2618 hw->addr_ctrl.mta_in_use = 0;
2620 /* Clear mta_shadow */
2622 DEBUGOUT(" Clearing MTA\n");
2623 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2626 /* Update mta_shadow */
2627 for (i = 0; i < mc_addr_count; i++) {
2628 DEBUGOUT(" Adding the multicast addresses:\n");
2629 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2633 for (i = 0; i < hw->mac.mcft_size; i++)
2634 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2635 hw->mac.mta_shadow[i]);
2637 if (hw->addr_ctrl.mta_in_use > 0)
2638 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2639 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2641 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2642 return IXGBE_SUCCESS;
2646 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2647 * @hw: pointer to hardware structure
2649 * Enables multicast address in RAR and the use of the multicast hash table.
2651 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2653 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2655 DEBUGFUNC("ixgbe_enable_mc_generic");
2657 if (a->mta_in_use > 0)
2658 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2659 hw->mac.mc_filter_type);
2661 return IXGBE_SUCCESS;
2665 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2666 * @hw: pointer to hardware structure
2668 * Disables multicast address in RAR and the use of the multicast hash table.
2670 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2672 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2674 DEBUGFUNC("ixgbe_disable_mc_generic");
2676 if (a->mta_in_use > 0)
2677 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2679 return IXGBE_SUCCESS;
2683 * ixgbe_fc_enable_generic - Enable flow control
2684 * @hw: pointer to hardware structure
2686 * Enable flow control according to the current settings.
2688 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2690 s32 ret_val = IXGBE_SUCCESS;
2691 u32 mflcn_reg, fccfg_reg;
2696 DEBUGFUNC("ixgbe_fc_enable_generic");
2698 /* Validate the water mark configuration */
2699 if (!hw->fc.pause_time) {
2700 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2704 /* Low water mark of zero causes XOFF floods */
2705 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2706 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2707 hw->fc.high_water[i]) {
2708 if (!hw->fc.low_water[i] ||
2709 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2710 DEBUGOUT("Invalid water mark configuration\n");
2711 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2717 /* Negotiate the fc mode to use */
2718 ixgbe_fc_autoneg(hw);
2720 /* Disable any previous flow control settings */
2721 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2722 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2724 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2725 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2728 * The possible values of fc.current_mode are:
2729 * 0: Flow control is completely disabled
2730 * 1: Rx flow control is enabled (we can receive pause frames,
2731 * but not send pause frames).
2732 * 2: Tx flow control is enabled (we can send pause frames but
2733 * we do not support receiving pause frames).
2734 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2737 switch (hw->fc.current_mode) {
2740 * Flow control is disabled by software override or autoneg.
2741 * The code below will actually disable it in the HW.
2744 case ixgbe_fc_rx_pause:
2746 * Rx Flow control is enabled and Tx Flow control is
2747 * disabled by software override. Since there really
2748 * isn't a way to advertise that we are capable of RX
2749 * Pause ONLY, we will advertise that we support both
2750 * symmetric and asymmetric Rx PAUSE. Later, we will
2751 * disable the adapter's ability to send PAUSE frames.
2753 mflcn_reg |= IXGBE_MFLCN_RFCE;
2755 case ixgbe_fc_tx_pause:
2757 * Tx Flow control is enabled, and Rx Flow control is
2758 * disabled by software override.
2760 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2763 /* Flow control (both Rx and Tx) is enabled by SW override. */
2764 mflcn_reg |= IXGBE_MFLCN_RFCE;
2765 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2768 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2769 "Flow control param set incorrectly\n");
2770 ret_val = IXGBE_ERR_CONFIG;
2775 /* Set 802.3x based flow control settings. */
2776 mflcn_reg |= IXGBE_MFLCN_DPF;
2777 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2778 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2781 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2782 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2783 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2784 hw->fc.high_water[i]) {
2785 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2786 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2787 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2789 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2791 * In order to prevent Tx hangs when the internal Tx
2792 * switch is enabled we must set the high water mark
2793 * to the Rx packet buffer size - 24KB. This allows
2794 * the Tx switch to function even under heavy Rx
2797 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2800 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2803 /* Configure pause time (2 TCs per register) */
2804 reg = hw->fc.pause_time * 0x00010001;
2805 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2806 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2808 /* Configure flow control refresh threshold value */
2809 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2816 * ixgbe_negotiate_fc - Negotiate flow control
2817 * @hw: pointer to hardware structure
2818 * @adv_reg: flow control advertised settings
2819 * @lp_reg: link partner's flow control settings
2820 * @adv_sym: symmetric pause bit in advertisement
2821 * @adv_asm: asymmetric pause bit in advertisement
2822 * @lp_sym: symmetric pause bit in link partner advertisement
2823 * @lp_asm: asymmetric pause bit in link partner advertisement
2825 * Find the intersection between advertised settings and link partner's
2826 * advertised settings
2828 STATIC s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2829 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2831 if ((!(adv_reg)) || (!(lp_reg))) {
2832 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2833 "Local or link partner's advertised flow control "
2834 "settings are NULL. Local: %x, link partner: %x\n",
2836 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2839 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2841 * Now we need to check if the user selected Rx ONLY
2842 * of pause frames. In this case, we had to advertise
2843 * FULL flow control because we could not advertise RX
2844 * ONLY. Hence, we must now check to see if we need to
2845 * turn OFF the TRANSMISSION of PAUSE frames.
2847 if (hw->fc.requested_mode == ixgbe_fc_full) {
2848 hw->fc.current_mode = ixgbe_fc_full;
2849 DEBUGOUT("Flow Control = FULL.\n");
2851 hw->fc.current_mode = ixgbe_fc_rx_pause;
2852 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2854 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2855 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2856 hw->fc.current_mode = ixgbe_fc_tx_pause;
2857 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2858 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2859 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2860 hw->fc.current_mode = ixgbe_fc_rx_pause;
2861 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2863 hw->fc.current_mode = ixgbe_fc_none;
2864 DEBUGOUT("Flow Control = NONE.\n");
2866 return IXGBE_SUCCESS;
2870 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2871 * @hw: pointer to hardware structure
2873 * Enable flow control according on 1 gig fiber.
2875 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2877 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2878 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2881 * On multispeed fiber at 1g, bail out if
2882 * - link is up but AN did not complete, or if
2883 * - link is up and AN completed but timed out
2886 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2887 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2888 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2889 ERROR_REPORT1(IXGBE_ERROR_POLLING,
2890 "Auto-Negotiation did not complete or timed out");
2894 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2895 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2897 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2898 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2899 IXGBE_PCS1GANA_ASM_PAUSE,
2900 IXGBE_PCS1GANA_SYM_PAUSE,
2901 IXGBE_PCS1GANA_ASM_PAUSE);
2908 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2909 * @hw: pointer to hardware structure
2911 * Enable flow control according to IEEE clause 37.
2913 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2915 u32 links2, anlp1_reg, autoc_reg, links;
2916 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2919 * On backplane, bail out if
2920 * - backplane autoneg was not completed, or if
2921 * - we are 82599 and link partner is not AN enabled
2923 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2924 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2925 ERROR_REPORT1(IXGBE_ERROR_POLLING,
2926 "Auto-Negotiation did not complete");
2930 if (hw->mac.type == ixgbe_mac_82599EB) {
2931 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2932 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2933 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2934 "Link partner is not AN enabled");
2939 * Read the 10g AN autoc and LP ability registers and resolve
2940 * local flow control settings accordingly
2942 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2943 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2945 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2946 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2947 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2954 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2955 * @hw: pointer to hardware structure
2957 * Enable flow control according to IEEE clause 37.
2959 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2961 u16 technology_ability_reg = 0;
2962 u16 lp_technology_ability_reg = 0;
2964 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2965 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2966 &technology_ability_reg);
2967 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2968 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2969 &lp_technology_ability_reg);
2971 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2972 (u32)lp_technology_ability_reg,
2973 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2974 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2978 * ixgbe_fc_autoneg - Configure flow control
2979 * @hw: pointer to hardware structure
2981 * Compares our advertised flow control capabilities to those advertised by
2982 * our link partner, and determines the proper flow control mode to use.
2984 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2986 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2987 ixgbe_link_speed speed;
2990 DEBUGFUNC("ixgbe_fc_autoneg");
2993 * AN should have completed when the cable was plugged in.
2994 * Look for reasons to bail out. Bail out if:
2995 * - FC autoneg is disabled, or if
2998 if (hw->fc.disable_fc_autoneg) {
2999 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3000 "Flow control autoneg is disabled");
3004 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3006 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3010 switch (hw->phy.media_type) {
3011 /* Autoneg flow control on fiber adapters */
3012 case ixgbe_media_type_fiber:
3013 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3014 ret_val = ixgbe_fc_autoneg_fiber(hw);
3017 /* Autoneg flow control on backplane adapters */
3018 case ixgbe_media_type_backplane:
3019 ret_val = ixgbe_fc_autoneg_backplane(hw);
3022 /* Autoneg flow control on copper adapters */
3023 case ixgbe_media_type_copper:
3024 if (ixgbe_device_supports_autoneg_fc(hw))
3025 ret_val = ixgbe_fc_autoneg_copper(hw);
3033 if (ret_val == IXGBE_SUCCESS) {
3034 hw->fc.fc_was_autonegged = true;
3036 hw->fc.fc_was_autonegged = false;
3037 hw->fc.current_mode = hw->fc.requested_mode;
3042 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3043 * @hw: pointer to hardware structure
3045 * System-wide timeout range is encoded in PCIe Device Control2 register.
3047 * Add 10% to specified maximum and return the number of times to poll for
3048 * completion timeout, in units of 100 microsec. Never return less than
3049 * 800 = 80 millisec.
3051 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3056 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3057 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3060 case IXGBE_PCIDEVCTRL2_65_130ms:
3061 pollcnt = 1300; /* 130 millisec */
3063 case IXGBE_PCIDEVCTRL2_260_520ms:
3064 pollcnt = 5200; /* 520 millisec */
3066 case IXGBE_PCIDEVCTRL2_1_2s:
3067 pollcnt = 20000; /* 2 sec */
3069 case IXGBE_PCIDEVCTRL2_4_8s:
3070 pollcnt = 80000; /* 8 sec */
3072 case IXGBE_PCIDEVCTRL2_17_34s:
3073 pollcnt = 34000; /* 34 sec */
3075 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3076 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3077 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3078 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3080 pollcnt = 800; /* 80 millisec minimum */
3084 /* add 10% to spec maximum */
3085 return (pollcnt * 11) / 10;
3089 * ixgbe_disable_pcie_master - Disable PCI-express master access
3090 * @hw: pointer to hardware structure
3092 * Disables PCI-Express master access and verifies there are no pending
3093 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3094 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3095 * is returned signifying master requests disabled.
3097 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3099 s32 status = IXGBE_SUCCESS;
3103 DEBUGFUNC("ixgbe_disable_pcie_master");
3105 /* Always set this bit to ensure any future transactions are blocked */
3106 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3108 /* Exit if master requests are blocked */
3109 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3110 IXGBE_REMOVED(hw->hw_addr))
3113 /* Poll for master request bit to clear */
3114 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3116 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3121 * Two consecutive resets are required via CTRL.RST per datasheet
3122 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3123 * of this need. The first reset prevents new master requests from
3124 * being issued by our device. We then must wait 1usec or more for any
3125 * remaining completions from the PCIe bus to trickle in, and then reset
3126 * again to clear out any effects they may have had on our device.
3128 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3129 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3132 * Before proceeding, make sure that the PCIe block does not have
3133 * transactions pending.
3135 poll = ixgbe_pcie_timeout_poll(hw);
3136 for (i = 0; i < poll; i++) {
3138 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3139 if (IXGBE_REMOVED(hw->hw_addr))
3141 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3145 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3146 "PCIe transaction pending bit also did not clear.\n");
3147 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3154 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3155 * @hw: pointer to hardware structure
3156 * @mask: Mask to specify which semaphore to acquire
3158 * Acquires the SWFW semaphore through the GSSR register for the specified
3159 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3161 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
3165 u32 fwmask = mask << 5;
3168 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3172 * SW EEPROM semaphore bit is used for access to all
3173 * SW_FW_SYNC/GSSR bits (not just EEPROM)
3175 if (ixgbe_get_eeprom_semaphore(hw))
3176 return IXGBE_ERR_SWFW_SYNC;
3178 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3179 if (!(gssr & (fwmask | swmask)))
3183 * Firmware currently using resource (fwmask) or other software
3184 * thread currently using resource (swmask)
3186 ixgbe_release_eeprom_semaphore(hw);
3192 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3193 return IXGBE_ERR_SWFW_SYNC;
3197 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3199 ixgbe_release_eeprom_semaphore(hw);
3200 return IXGBE_SUCCESS;
3204 * ixgbe_release_swfw_sync - Release SWFW semaphore
3205 * @hw: pointer to hardware structure
3206 * @mask: Mask to specify which semaphore to release
3208 * Releases the SWFW semaphore through the GSSR register for the specified
3209 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3211 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
3216 DEBUGFUNC("ixgbe_release_swfw_sync");
3218 ixgbe_get_eeprom_semaphore(hw);
3220 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3222 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3224 ixgbe_release_eeprom_semaphore(hw);
3228 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3229 * @hw: pointer to hardware structure
3231 * Stops the receive data path and waits for the HW to internally empty
3232 * the Rx security block
3234 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3236 #define IXGBE_MAX_SECRX_POLL 40
3241 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3244 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3245 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3246 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3247 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3248 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3249 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3252 /* Use interrupt-safe sleep just in case */
3256 /* For informational purposes only */
3257 if (i >= IXGBE_MAX_SECRX_POLL)
3258 DEBUGOUT("Rx unit being enabled before security "
3259 "path fully disabled. Continuing with init.\n");
3261 return IXGBE_SUCCESS;
3265 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3266 * @hw: pointer to hardware structure
3268 * Enables the receive data path.
3270 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3274 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3276 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3277 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3278 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3279 IXGBE_WRITE_FLUSH(hw);
3281 return IXGBE_SUCCESS;
3285 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3286 * @hw: pointer to hardware structure
3287 * @regval: register value to write to RXCTRL
3289 * Enables the Rx DMA unit
3291 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3293 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3295 if (regval & IXGBE_RXCTRL_RXEN)
3296 ixgbe_enable_rx(hw);
3298 ixgbe_disable_rx(hw);
3300 return IXGBE_SUCCESS;
3304 * ixgbe_blink_led_start_generic - Blink LED based on index.
3305 * @hw: pointer to hardware structure
3306 * @index: led number to blink
3308 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3310 ixgbe_link_speed speed = 0;
3312 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3313 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3314 s32 ret_val = IXGBE_SUCCESS;
3316 DEBUGFUNC("ixgbe_blink_led_start_generic");
3319 * Link must be up to auto-blink the LEDs;
3320 * Force it if link is down.
3322 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3325 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
3328 bool got_lock = false;
3329 if ((hw->mac.type == ixgbe_mac_82599EB) &&
3330 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3331 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
3332 IXGBE_GSSR_MAC_CSR_SM);
3333 if (ret_val != IXGBE_SUCCESS) {
3334 ret_val = IXGBE_ERR_SWFW_SYNC;
3340 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3341 autoc_reg |= IXGBE_AUTOC_FLU;
3342 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3343 IXGBE_WRITE_FLUSH(hw);
3346 hw->mac.ops.release_swfw_sync(hw,
3347 IXGBE_GSSR_MAC_CSR_SM);
3351 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3352 led_reg |= IXGBE_LED_BLINK(index);
3353 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3354 IXGBE_WRITE_FLUSH(hw);
3361 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3362 * @hw: pointer to hardware structure
3363 * @index: led number to stop blinking
3365 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3367 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3368 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3369 s32 ret_val = IXGBE_SUCCESS;
3370 bool got_lock = false;
3372 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3373 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
3376 if ((hw->mac.type == ixgbe_mac_82599EB) &&
3377 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3378 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
3379 IXGBE_GSSR_MAC_CSR_SM);
3380 if (ret_val != IXGBE_SUCCESS) {
3381 ret_val = IXGBE_ERR_SWFW_SYNC;
3388 autoc_reg &= ~IXGBE_AUTOC_FLU;
3389 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3390 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3392 if (hw->mac.type == ixgbe_mac_82599EB)
3393 ixgbe_reset_pipeline_82599(hw);
3396 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3398 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3399 led_reg &= ~IXGBE_LED_BLINK(index);
3400 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3401 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3402 IXGBE_WRITE_FLUSH(hw);
3409 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3410 * @hw: pointer to hardware structure
3411 * @san_mac_offset: SAN MAC address offset
3413 * This function will read the EEPROM location for the SAN MAC address
3414 * pointer, and returns the value at that location. This is used in both
3415 * get and set mac_addr routines.
3417 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3418 u16 *san_mac_offset)
3422 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3425 * First read the EEPROM pointer to see if the MAC addresses are
3428 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3431 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3432 "eeprom at offset %d failed",
3433 IXGBE_SAN_MAC_ADDR_PTR);
3440 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3441 * @hw: pointer to hardware structure
3442 * @san_mac_addr: SAN MAC address
3444 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3445 * per-port, so set_lan_id() must be called before reading the addresses.
3446 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3447 * upon for non-SFP connections, so we must call it here.
3449 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3451 u16 san_mac_data, san_mac_offset;
3455 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3458 * First read the EEPROM pointer to see if the MAC addresses are
3459 * available. If they're not, no point in calling set_lan_id() here.
3461 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3462 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3463 goto san_mac_addr_out;
3465 /* make sure we know which port we need to program */
3466 hw->mac.ops.set_lan_id(hw);
3467 /* apply the port offset to the address offset */
3468 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3469 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3470 for (i = 0; i < 3; i++) {
3471 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3474 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3475 "eeprom read at offset %d failed",
3477 goto san_mac_addr_out;
3479 san_mac_addr[i * 2] = (u8)(san_mac_data);
3480 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3483 return IXGBE_SUCCESS;
3487 * No addresses available in this EEPROM. It's not an
3488 * error though, so just wipe the local address and return.
3490 for (i = 0; i < 6; i++)
3491 san_mac_addr[i] = 0xFF;
3492 return IXGBE_SUCCESS;
3496 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3497 * @hw: pointer to hardware structure
3498 * @san_mac_addr: SAN MAC address
3500 * Write a SAN MAC address to the EEPROM.
3502 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3505 u16 san_mac_data, san_mac_offset;
3508 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3510 /* Look for SAN mac address pointer. If not defined, return */
3511 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3512 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3513 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3515 /* Make sure we know which port we need to write */
3516 hw->mac.ops.set_lan_id(hw);
3517 /* Apply the port offset to the address offset */
3518 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3519 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3521 for (i = 0; i < 3; i++) {
3522 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3523 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3524 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3528 return IXGBE_SUCCESS;
3532 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3533 * @hw: pointer to hardware structure
3535 * Read PCIe configuration space, and get the MSI-X vector count from
3536 * the capabilities table.
3538 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3544 switch (hw->mac.type) {
3545 case ixgbe_mac_82598EB:
3546 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3547 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3549 case ixgbe_mac_82599EB:
3550 case ixgbe_mac_X540:
3551 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3552 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3558 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3559 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3560 if (IXGBE_REMOVED(hw->hw_addr))
3562 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3564 /* MSI-X count is zero-based in HW */
3567 if (msix_count > max_msix_count)
3568 msix_count = max_msix_count;
3574 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3575 * @hw: pointer to hardware structure
3576 * @addr: Address to put into receive address register
3577 * @vmdq: VMDq pool to assign
3579 * Puts an ethernet address into a receive address register, or
3580 * finds the rar that it is aleady in; adds to the pool list
3582 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3584 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3585 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3587 u32 rar_low, rar_high;
3588 u32 addr_low, addr_high;
3590 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3592 /* swap bytes for HW little endian */
3593 addr_low = addr[0] | (addr[1] << 8)
3596 addr_high = addr[4] | (addr[5] << 8);
3599 * Either find the mac_id in rar or find the first empty space.
3600 * rar_highwater points to just after the highest currently used
3601 * rar in order to shorten the search. It grows when we add a new
3604 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3605 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3607 if (((IXGBE_RAH_AV & rar_high) == 0)
3608 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3609 first_empty_rar = rar;
3610 } else if ((rar_high & 0xFFFF) == addr_high) {
3611 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3612 if (rar_low == addr_low)
3613 break; /* found it already in the rars */
3617 if (rar < hw->mac.rar_highwater) {
3618 /* already there so just add to the pool bits */
3619 ixgbe_set_vmdq(hw, rar, vmdq);
3620 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3621 /* stick it into first empty RAR slot we found */
3622 rar = first_empty_rar;
3623 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3624 } else if (rar == hw->mac.rar_highwater) {
3625 /* add it to the top of the list and inc the highwater mark */
3626 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3627 hw->mac.rar_highwater++;
3628 } else if (rar >= hw->mac.num_rar_entries) {
3629 return IXGBE_ERR_INVALID_MAC_ADDR;
3633 * If we found rar[0], make sure the default pool bit (we use pool 0)
3634 * remains cleared to be sure default pool packets will get delivered
3637 ixgbe_clear_vmdq(hw, rar, 0);
3643 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3644 * @hw: pointer to hardware struct
3645 * @rar: receive address register index to disassociate
3646 * @vmdq: VMDq pool index to remove from the rar
3648 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3650 u32 mpsar_lo, mpsar_hi;
3651 u32 rar_entries = hw->mac.num_rar_entries;
3653 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3655 /* Make sure we are using a valid rar index range */
3656 if (rar >= rar_entries) {
3657 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3658 "RAR index %d is out of range.\n", rar);
3659 return IXGBE_ERR_INVALID_ARGUMENT;
3662 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3663 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3665 if (IXGBE_REMOVED(hw->hw_addr))
3668 if (!mpsar_lo && !mpsar_hi)
3671 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3673 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3677 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3680 } else if (vmdq < 32) {
3681 mpsar_lo &= ~(1 << vmdq);
3682 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3684 mpsar_hi &= ~(1 << (vmdq - 32));
3685 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3688 /* was that the last pool using this rar? */
3689 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3690 hw->mac.ops.clear_rar(hw, rar);
3692 return IXGBE_SUCCESS;
3696 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3697 * @hw: pointer to hardware struct
3698 * @rar: receive address register index to associate with a VMDq index
3699 * @vmdq: VMDq pool index
3701 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3704 u32 rar_entries = hw->mac.num_rar_entries;
3706 DEBUGFUNC("ixgbe_set_vmdq_generic");
3708 /* Make sure we are using a valid rar index range */
3709 if (rar >= rar_entries) {
3710 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3711 "RAR index %d is out of range.\n", rar);
3712 return IXGBE_ERR_INVALID_ARGUMENT;
3716 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3718 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3720 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3721 mpsar |= 1 << (vmdq - 32);
3722 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3724 return IXGBE_SUCCESS;
3728 * This function should only be involved in the IOV mode.
3729 * In IOV mode, Default pool is next pool after the number of
3730 * VFs advertized and not 0.
3731 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3733 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3734 * @hw: pointer to hardware struct
3735 * @vmdq: VMDq pool index
3737 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3739 u32 rar = hw->mac.san_mac_rar_index;
3741 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3744 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3745 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3747 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3748 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3751 return IXGBE_SUCCESS;
3755 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3756 * @hw: pointer to hardware structure
3758 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3762 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3763 DEBUGOUT(" Clearing UTA\n");
3765 for (i = 0; i < 128; i++)
3766 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3768 return IXGBE_SUCCESS;
3772 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3773 * @hw: pointer to hardware structure
3774 * @vlan: VLAN id to write to VLAN filter
3776 * return the VLVF index where this VLAN id should be placed
3779 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3782 u32 first_empty_slot = 0;
3785 /* short cut the special case */
3790 * Search for the vlan id in the VLVF entries. Save off the first empty
3791 * slot found along the way
3793 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3794 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3795 if (!bits && !(first_empty_slot))
3796 first_empty_slot = regindex;
3797 else if ((bits & 0x0FFF) == vlan)
3802 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3803 * in the VLVF. Else use the first empty VLVF register for this
3806 if (regindex >= IXGBE_VLVF_ENTRIES) {
3807 if (first_empty_slot)
3808 regindex = first_empty_slot;
3810 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
3811 "No space in VLVF.\n");
3812 regindex = IXGBE_ERR_NO_SPACE;
3820 * ixgbe_set_vfta_generic - Set VLAN filter table
3821 * @hw: pointer to hardware structure
3822 * @vlan: VLAN id to write to VLAN filter
3823 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3824 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3826 * Turn on/off specified VLAN in the VLAN filter table.
3828 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3835 s32 ret_val = IXGBE_SUCCESS;
3836 bool vfta_changed = false;
3838 DEBUGFUNC("ixgbe_set_vfta_generic");
3841 return IXGBE_ERR_PARAM;
3844 * this is a 2 part operation - first the VFTA, then the
3845 * VLVF and VLVFB if VT Mode is set
3846 * We don't write the VFTA until we know the VLVF part succeeded.
3850 * The VFTA is a bitstring made up of 128 32-bit registers
3851 * that enable the particular VLAN id, much like the MTA:
3852 * bits[11-5]: which register
3853 * bits[4-0]: which bit in the register
3855 regindex = (vlan >> 5) & 0x7F;
3856 bitindex = vlan & 0x1F;
3857 targetbit = (1 << bitindex);
3858 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3861 if (!(vfta & targetbit)) {
3863 vfta_changed = true;
3866 if ((vfta & targetbit)) {
3868 vfta_changed = true;
3873 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3875 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3877 if (ret_val != IXGBE_SUCCESS)
3881 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3883 return IXGBE_SUCCESS;
3887 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3888 * @hw: pointer to hardware structure
3889 * @vlan: VLAN id to write to VLAN filter
3890 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3891 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3892 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3895 * Turn on/off specified bit in VLVF table.
3897 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3898 bool vlan_on, bool *vfta_changed)
3902 DEBUGFUNC("ixgbe_set_vlvf_generic");
3905 return IXGBE_ERR_PARAM;
3907 /* If VT Mode is set
3909 * make sure the vlan is in VLVF
3910 * set the vind bit in the matching VLVFB
3912 * clear the pool bit and possibly the vind
3914 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3915 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3919 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3924 /* set the pool bit */
3926 bits = IXGBE_READ_REG(hw,
3927 IXGBE_VLVFB(vlvf_index * 2));
3928 bits |= (1 << vind);
3930 IXGBE_VLVFB(vlvf_index * 2),
3933 bits = IXGBE_READ_REG(hw,
3934 IXGBE_VLVFB((vlvf_index * 2) + 1));
3935 bits |= (1 << (vind - 32));
3937 IXGBE_VLVFB((vlvf_index * 2) + 1),
3941 /* clear the pool bit */
3943 bits = IXGBE_READ_REG(hw,
3944 IXGBE_VLVFB(vlvf_index * 2));
3945 bits &= ~(1 << vind);
3947 IXGBE_VLVFB(vlvf_index * 2),
3949 bits |= IXGBE_READ_REG(hw,
3950 IXGBE_VLVFB((vlvf_index * 2) + 1));
3952 bits = IXGBE_READ_REG(hw,
3953 IXGBE_VLVFB((vlvf_index * 2) + 1));
3954 bits &= ~(1 << (vind - 32));
3956 IXGBE_VLVFB((vlvf_index * 2) + 1),
3958 bits |= IXGBE_READ_REG(hw,
3959 IXGBE_VLVFB(vlvf_index * 2));
3964 * If there are still bits set in the VLVFB registers
3965 * for the VLAN ID indicated we need to see if the
3966 * caller is requesting that we clear the VFTA entry bit.
3967 * If the caller has requested that we clear the VFTA
3968 * entry bit but there are still pools/VFs using this VLAN
3969 * ID entry then ignore the request. We're not worried
3970 * about the case where we're turning the VFTA VLAN ID
3971 * entry bit on, only when requested to turn it off as
3972 * there may be multiple pools and/or VFs using the
3973 * VLAN ID entry. In that case we cannot clear the
3974 * VFTA bit until all pools/VFs using that VLAN ID have also
3975 * been cleared. This will be indicated by "bits" being
3979 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3980 (IXGBE_VLVF_VIEN | vlan));
3981 if ((!vlan_on) && (vfta_changed != NULL)) {
3982 /* someone wants to clear the vfta entry
3983 * but some pools/VFs are still using it.
3985 *vfta_changed = false;
3988 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3991 return IXGBE_SUCCESS;
3995 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3996 * @hw: pointer to hardware structure
3998 * Clears the VLAN filer table, and the VMDq index associated with the filter
4000 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4004 DEBUGFUNC("ixgbe_clear_vfta_generic");
4006 for (offset = 0; offset < hw->mac.vft_size; offset++)
4007 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4009 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4010 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4011 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4012 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
4015 return IXGBE_SUCCESS;
4019 * ixgbe_check_mac_link_generic - Determine link and speed status
4020 * @hw: pointer to hardware structure
4021 * @speed: pointer to link speed
4022 * @link_up: true when link is up
4023 * @link_up_wait_to_complete: bool used to wait for link up or not
4025 * Reads the links register to determine if link is up and the current speed
4027 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4028 bool *link_up, bool link_up_wait_to_complete)
4030 u32 links_reg, links_orig;
4033 DEBUGFUNC("ixgbe_check_mac_link_generic");
4035 /* clear the old state */
4036 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4038 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4040 if (links_orig != links_reg) {
4041 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4042 links_orig, links_reg);
4045 if (link_up_wait_to_complete) {
4046 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
4047 if (links_reg & IXGBE_LINKS_UP) {
4054 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4057 if (links_reg & IXGBE_LINKS_UP)
4063 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4064 IXGBE_LINKS_SPEED_10G_82599)
4065 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4066 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4067 IXGBE_LINKS_SPEED_1G_82599)
4068 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4069 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4070 IXGBE_LINKS_SPEED_100_82599)
4071 *speed = IXGBE_LINK_SPEED_100_FULL;
4073 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4075 return IXGBE_SUCCESS;
4079 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4081 * @hw: pointer to hardware structure
4082 * @wwnn_prefix: the alternative WWNN prefix
4083 * @wwpn_prefix: the alternative WWPN prefix
4085 * This function will read the EEPROM from the alternative SAN MAC address
4086 * block to check the support for the alternative WWNN/WWPN prefix support.
4088 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4092 u16 alt_san_mac_blk_offset;
4094 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4096 /* clear output first */
4097 *wwnn_prefix = 0xFFFF;
4098 *wwpn_prefix = 0xFFFF;
4100 /* check if alternative SAN MAC is supported */
4101 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4102 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4103 goto wwn_prefix_err;
4105 if ((alt_san_mac_blk_offset == 0) ||
4106 (alt_san_mac_blk_offset == 0xFFFF))
4107 goto wwn_prefix_out;
4109 /* check capability in alternative san mac address block */
4110 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4111 if (hw->eeprom.ops.read(hw, offset, &caps))
4112 goto wwn_prefix_err;
4113 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4114 goto wwn_prefix_out;
4116 /* get the corresponding prefix for WWNN/WWPN */
4117 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4118 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4119 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4120 "eeprom read at offset %d failed", offset);
4123 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4124 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4125 goto wwn_prefix_err;
4128 return IXGBE_SUCCESS;
4131 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4132 "eeprom read at offset %d failed", offset);
4133 return IXGBE_SUCCESS;
4137 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4138 * @hw: pointer to hardware structure
4139 * @bs: the fcoe boot status
4141 * This function will read the FCOE boot status from the iSCSI FCOE block
4143 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4145 u16 offset, caps, flags;
4148 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4150 /* clear output first */
4151 *bs = ixgbe_fcoe_bootstatus_unavailable;
4153 /* check if FCOE IBA block is present */
4154 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4155 status = hw->eeprom.ops.read(hw, offset, &caps);
4156 if (status != IXGBE_SUCCESS)
4159 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4162 /* check if iSCSI FCOE block is populated */
4163 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4164 if (status != IXGBE_SUCCESS)
4167 if ((offset == 0) || (offset == 0xFFFF))
4170 /* read fcoe flags in iSCSI FCOE block */
4171 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4172 status = hw->eeprom.ops.read(hw, offset, &flags);
4173 if (status != IXGBE_SUCCESS)
4176 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4177 *bs = ixgbe_fcoe_bootstatus_enabled;
4179 *bs = ixgbe_fcoe_bootstatus_disabled;
4186 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4187 * @hw: pointer to hardware structure
4188 * @enable: enable or disable switch for anti-spoofing
4189 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
4192 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
4195 int pf_target_reg = pf >> 3;
4196 int pf_target_shift = pf % 8;
4199 if (hw->mac.type == ixgbe_mac_82598EB)
4203 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
4206 * PFVFSPOOF register array is size 8 with 8 bits assigned to
4207 * MAC anti-spoof enables in each register array element.
4209 for (j = 0; j < pf_target_reg; j++)
4210 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4213 * The PF should be allowed to spoof so that it can support
4214 * emulation mode NICs. Do not set the bits assigned to the PF
4216 pfvfspoof &= (1 << pf_target_shift) - 1;
4217 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4220 * Remaining pools belong to the PF so they do not need to have
4221 * anti-spoofing enabled.
4223 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
4224 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
4228 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4229 * @hw: pointer to hardware structure
4230 * @enable: enable or disable switch for VLAN anti-spoofing
4231 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4234 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4236 int vf_target_reg = vf >> 3;
4237 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4240 if (hw->mac.type == ixgbe_mac_82598EB)
4243 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4245 pfvfspoof |= (1 << vf_target_shift);
4247 pfvfspoof &= ~(1 << vf_target_shift);
4248 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4252 * ixgbe_get_device_caps_generic - Get additional device capabilities
4253 * @hw: pointer to hardware structure
4254 * @device_caps: the EEPROM word with the extra device capabilities
4256 * This function will read the EEPROM location for the device capabilities,
4257 * and return the word through device_caps.
4259 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4261 DEBUGFUNC("ixgbe_get_device_caps_generic");
4263 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4265 return IXGBE_SUCCESS;
4269 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4270 * @hw: pointer to hardware structure
4273 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4278 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4280 /* Enable relaxed ordering */
4281 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4282 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4283 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4284 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4287 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4288 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4289 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4290 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4291 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4297 * ixgbe_calculate_checksum - Calculate checksum for buffer
4298 * @buffer: pointer to EEPROM
4299 * @length: size of EEPROM to calculate a checksum for
4300 * Calculates the checksum for some buffer on a specified length. The
4301 * checksum calculated is returned.
4303 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4308 DEBUGFUNC("ixgbe_calculate_checksum");
4313 for (i = 0; i < length; i++)
4316 return (u8) (0 - sum);
4320 * ixgbe_host_interface_command - Issue command to manageability block
4321 * @hw: pointer to the HW structure
4322 * @buffer: contains the command to write and where the return status will
4324 * @length: length of buffer, must be multiple of 4 bytes
4326 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4327 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
4329 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4333 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4334 u8 buf_len, dword_len;
4336 s32 ret_val = IXGBE_SUCCESS;
4338 DEBUGFUNC("ixgbe_host_interface_command");
4340 if (length == 0 || length & 0x3 ||
4341 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4342 DEBUGOUT("Buffer length failure.\n");
4343 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4347 /* Check that the host interface is enabled. */
4348 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4349 if ((hicr & IXGBE_HICR_EN) == 0) {
4350 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4351 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4355 /* Calculate length in DWORDs */
4356 dword_len = length >> 2;
4359 * The device driver writes the relevant command block
4360 * into the ram area.
4362 for (i = 0; i < dword_len; i++)
4363 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4364 i, IXGBE_CPU_TO_LE32(buffer[i]));
4366 /* Setting this bit tells the ARC that a new command is pending. */
4367 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4369 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
4370 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4371 if (!(hicr & IXGBE_HICR_C))
4376 /* Check command successful completion. */
4377 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
4378 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
4379 DEBUGOUT("Command has failed with no status valid.\n");
4380 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4384 /* Calculate length in DWORDs */
4385 dword_len = hdr_size >> 2;
4387 /* first pull in the header so we know the buffer length */
4388 for (bi = 0; bi < dword_len; bi++) {
4389 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4390 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4393 /* If there is any thing in data position pull it in */
4394 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4398 if (length < (buf_len + hdr_size)) {
4399 DEBUGOUT("Buffer not large enough for reply message.\n");
4400 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4404 /* Calculate length in DWORDs, add 3 for odd lengths */
4405 dword_len = (buf_len + 3) >> 2;
4407 /* Pull in the rest of the buffer (bi is where we left off)*/
4408 for (; bi <= dword_len; bi++) {
4409 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4410 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4418 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4419 * @hw: pointer to the HW structure
4420 * @maj: driver version major number
4421 * @min: driver version minor number
4422 * @build: driver version build number
4423 * @sub: driver version sub build number
4425 * Sends driver version number to firmware through the manageability
4426 * block. On success return IXGBE_SUCCESS
4427 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4428 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4430 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4433 struct ixgbe_hic_drv_info fw_cmd;
4435 s32 ret_val = IXGBE_SUCCESS;
4437 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4439 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
4441 ret_val = IXGBE_ERR_SWFW_SYNC;
4445 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4446 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4447 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4448 fw_cmd.port_num = (u8)hw->bus.func;
4449 fw_cmd.ver_maj = maj;
4450 fw_cmd.ver_min = min;
4451 fw_cmd.ver_build = build;
4452 fw_cmd.ver_sub = sub;
4453 fw_cmd.hdr.checksum = 0;
4454 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4455 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4459 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4460 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4462 if (ret_val != IXGBE_SUCCESS)
4465 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4466 FW_CEM_RESP_STATUS_SUCCESS)
4467 ret_val = IXGBE_SUCCESS;
4469 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4474 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4480 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4481 * @hw: pointer to hardware structure
4482 * @num_pb: number of packet buffers to allocate
4483 * @headroom: reserve n KB of headroom
4484 * @strategy: packet buffer allocation strategy
4486 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4489 u32 pbsize = hw->mac.rx_pb_size;
4491 u32 rxpktsize, txpktsize, txpbthresh;
4493 /* Reserve headroom */
4499 /* Divide remaining packet buffer space amongst the number of packet
4500 * buffers requested using supplied strategy.
4503 case PBA_STRATEGY_WEIGHTED:
4504 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4505 * buffer with 5/8 of the packet buffer space.
4507 rxpktsize = (pbsize * 5) / (num_pb * 4);
4508 pbsize -= rxpktsize * (num_pb / 2);
4509 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4510 for (; i < (num_pb / 2); i++)
4511 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4512 /* Fall through to configure remaining packet buffers */
4513 case PBA_STRATEGY_EQUAL:
4514 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4515 for (; i < num_pb; i++)
4516 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4522 /* Only support an equally distributed Tx packet buffer strategy. */
4523 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4524 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4525 for (i = 0; i < num_pb; i++) {
4526 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4527 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4530 /* Clear unused TCs, if any, to zero buffer size*/
4531 for (; i < IXGBE_MAX_PB; i++) {
4532 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4533 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4534 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4539 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4540 * @hw: pointer to the hardware structure
4542 * The 82599 and x540 MACs can experience issues if TX work is still pending
4543 * when a reset occurs. This function prevents this by flushing the PCIe
4544 * buffers on the system.
4546 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4548 u32 gcr_ext, hlreg0;
4551 * If double reset is not requested then all transactions should
4552 * already be clear and as such there is no work to do
4554 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4558 * Set loopback enable to prevent any transmits from being sent
4559 * should the link come up. This assumes that the RXCTRL.RXEN bit
4560 * has already been cleared.
4562 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4563 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4565 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4566 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4567 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4568 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4570 /* Flush all writes and allow 20usec for all transactions to clear */
4571 IXGBE_WRITE_FLUSH(hw);
4574 /* restore previous register values */
4575 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4576 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4581 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4582 * @hw: pointer to hardware structure
4583 * @map: pointer to u8 arr for returning map
4585 * Read the rtrup2tc HW register and resolve its content into map
4587 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4591 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4592 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4593 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4594 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4598 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4603 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4604 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4605 if (hw->mac.type != ixgbe_mac_82598EB) {
4606 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4607 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4608 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4609 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4610 hw->mac.set_lben = true;
4612 hw->mac.set_lben = false;
4615 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4616 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4620 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4625 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4626 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4628 if (hw->mac.type != ixgbe_mac_82598EB) {
4629 if (hw->mac.set_lben) {
4630 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4631 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4632 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4633 hw->mac.set_lben = false;