1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
39 #ident "$Id: ixgbe_common.c,v 1.382 2013/11/22 01:02:01 jtkirshe Exp $"
41 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
42 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
44 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
46 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
48 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
49 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
51 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
53 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
54 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
56 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
57 u16 words, u16 *data);
58 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
64 * ixgbe_init_ops_generic - Inits function ptrs
65 * @hw: pointer to the hardware structure
67 * Initialize the function pointers.
69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
72 struct ixgbe_mac_info *mac = &hw->mac;
73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
75 DEBUGFUNC("ixgbe_init_ops_generic");
78 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
80 if (eec & IXGBE_EEC_PRES) {
81 eeprom->ops.read = &ixgbe_read_eerd_generic;
82 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
84 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
85 eeprom->ops.read_buffer =
86 &ixgbe_read_eeprom_buffer_bit_bang_generic;
88 eeprom->ops.write = &ixgbe_write_eeprom_generic;
89 eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
90 eeprom->ops.validate_checksum =
91 &ixgbe_validate_eeprom_checksum_generic;
92 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
93 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
96 mac->ops.init_hw = &ixgbe_init_hw_generic;
97 mac->ops.reset_hw = NULL;
98 mac->ops.start_hw = &ixgbe_start_hw_generic;
99 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
100 mac->ops.get_media_type = NULL;
101 mac->ops.get_supported_physical_layer = NULL;
102 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
103 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
104 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
105 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
106 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
107 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
108 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
111 mac->ops.led_on = &ixgbe_led_on_generic;
112 mac->ops.led_off = &ixgbe_led_off_generic;
113 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
114 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
116 /* RAR, Multicast, VLAN */
117 mac->ops.set_rar = &ixgbe_set_rar_generic;
118 mac->ops.clear_rar = &ixgbe_clear_rar_generic;
119 mac->ops.insert_mac_addr = NULL;
120 mac->ops.set_vmdq = NULL;
121 mac->ops.clear_vmdq = NULL;
122 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
123 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
124 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
125 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
126 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
127 mac->ops.clear_vfta = NULL;
128 mac->ops.set_vfta = NULL;
129 mac->ops.set_vlvf = NULL;
130 mac->ops.init_uta_tables = NULL;
131 mac->ops.enable_rx = &ixgbe_enable_rx_generic;
132 mac->ops.disable_rx = &ixgbe_disable_rx_generic;
135 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
138 mac->ops.get_link_capabilities = NULL;
139 mac->ops.setup_link = NULL;
140 mac->ops.check_link = NULL;
142 return IXGBE_SUCCESS;
146 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
148 * @hw: pointer to hardware structure
150 * This function returns true if the device supports flow control
151 * autonegotiation, and false if it does not.
154 s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
157 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
159 switch (hw->device_id) {
160 case IXGBE_DEV_ID_X540T:
161 case IXGBE_DEV_ID_X540T1:
162 case IXGBE_DEV_ID_82599_T3_LOM:
163 return IXGBE_SUCCESS;
165 return IXGBE_ERR_FC_NOT_SUPPORTED;
170 * ixgbe_setup_fc - Set up flow control
171 * @hw: pointer to hardware structure
173 * Called at init time to set up flow control.
175 STATIC s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
177 s32 ret_val = IXGBE_SUCCESS;
178 u32 reg = 0, reg_bp = 0;
180 bool got_lock = false;
182 DEBUGFUNC("ixgbe_setup_fc");
185 * Validate the requested mode. Strict IEEE mode does not allow
186 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
188 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
189 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
190 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
191 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
196 * 10gig parts do not have a word in the EEPROM to determine the
197 * default flow control setting, so we explicitly set it to full.
199 if (hw->fc.requested_mode == ixgbe_fc_default)
200 hw->fc.requested_mode = ixgbe_fc_full;
203 * Set up the 1G and 10G flow control advertisement registers so the
204 * HW will be able to do fc autoneg once the cable is plugged in. If
205 * we link at 10G, the 1G advertisement is harmless and vice versa.
207 switch (hw->phy.media_type) {
208 case ixgbe_media_type_fiber:
209 case ixgbe_media_type_backplane:
210 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
211 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
213 case ixgbe_media_type_copper:
214 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
215 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
222 * The possible values of fc.requested_mode are:
223 * 0: Flow control is completely disabled
224 * 1: Rx flow control is enabled (we can receive pause frames,
225 * but not send pause frames).
226 * 2: Tx flow control is enabled (we can send pause frames but
227 * we do not support receiving pause frames).
228 * 3: Both Rx and Tx flow control (symmetric) are enabled.
231 switch (hw->fc.requested_mode) {
233 /* Flow control completely disabled by software override. */
234 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
235 if (hw->phy.media_type == ixgbe_media_type_backplane)
236 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
237 IXGBE_AUTOC_ASM_PAUSE);
238 else if (hw->phy.media_type == ixgbe_media_type_copper)
239 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
241 case ixgbe_fc_tx_pause:
243 * Tx Flow control is enabled, and Rx Flow control is
244 * disabled by software override.
246 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
247 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
248 if (hw->phy.media_type == ixgbe_media_type_backplane) {
249 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
250 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
251 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
252 reg_cu |= IXGBE_TAF_ASM_PAUSE;
253 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
256 case ixgbe_fc_rx_pause:
258 * Rx Flow control is enabled and Tx Flow control is
259 * disabled by software override. Since there really
260 * isn't a way to advertise that we are capable of RX
261 * Pause ONLY, we will advertise that we support both
262 * symmetric and asymmetric Rx PAUSE, as such we fall
263 * through to the fc_full statement. Later, we will
264 * disable the adapter's ability to send PAUSE frames.
267 /* Flow control (both Rx and Tx) is enabled by SW override. */
268 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
269 if (hw->phy.media_type == ixgbe_media_type_backplane)
270 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
271 IXGBE_AUTOC_ASM_PAUSE;
272 else if (hw->phy.media_type == ixgbe_media_type_copper)
273 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
276 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
277 "Flow control param set incorrectly\n");
278 ret_val = IXGBE_ERR_CONFIG;
283 if (hw->mac.type < ixgbe_mac_X540) {
285 * Enable auto-negotiation between the MAC & PHY;
286 * the MAC will advertise clause 37 flow control.
288 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
289 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
291 /* Disable AN timeout */
292 if (hw->fc.strict_ieee)
293 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
295 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
296 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
300 * AUTOC restart handles negotiation of 1G and 10G on backplane
301 * and copper. There is no need to set the PCS1GCTL register.
304 if (hw->phy.media_type == ixgbe_media_type_backplane) {
305 reg_bp |= IXGBE_AUTOC_AN_RESTART;
306 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
307 * LESM is on, likewise reset_pipeline requries the lock as
308 * it also writes AUTOC.
310 if ((hw->mac.type == ixgbe_mac_82599EB) &&
311 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
312 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
313 IXGBE_GSSR_MAC_CSR_SM);
314 if (ret_val != IXGBE_SUCCESS) {
315 ret_val = IXGBE_ERR_SWFW_SYNC;
321 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
322 if (hw->mac.type == ixgbe_mac_82599EB)
323 ixgbe_reset_pipeline_82599(hw);
326 hw->mac.ops.release_swfw_sync(hw,
327 IXGBE_GSSR_MAC_CSR_SM);
328 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
329 (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
330 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
331 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
334 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
340 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
341 * @hw: pointer to hardware structure
343 * Starts the hardware by filling the bus info structure and media type, clears
344 * all on chip counters, initializes receive address registers, multicast
345 * table, VLAN filter table, calls routine to set up link and flow control
346 * settings, and leaves transmit and receive units disabled and uninitialized
348 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
353 DEBUGFUNC("ixgbe_start_hw_generic");
355 /* Set the media type */
356 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
358 /* PHY ops initialization must be done in reset_hw() */
360 /* Clear the VLAN filter table */
361 hw->mac.ops.clear_vfta(hw);
363 /* Clear statistics registers */
364 hw->mac.ops.clear_hw_cntrs(hw);
366 /* Set No Snoop Disable */
367 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
368 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
369 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
370 IXGBE_WRITE_FLUSH(hw);
372 /* Setup flow control */
373 ret_val = ixgbe_setup_fc(hw);
374 if (ret_val != IXGBE_SUCCESS)
377 /* Clear adapter stopped flag */
378 hw->adapter_stopped = false;
385 * ixgbe_start_hw_gen2 - Init sequence for common device family
386 * @hw: pointer to hw structure
388 * Performs the init sequence common to the second generation
390 * Devices in the second generation:
394 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
399 /* Clear the rate limiters */
400 for (i = 0; i < hw->mac.max_tx_queues; i++) {
401 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
402 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
404 IXGBE_WRITE_FLUSH(hw);
406 /* Disable relaxed ordering */
407 for (i = 0; i < hw->mac.max_tx_queues; i++) {
408 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
409 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
410 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
413 for (i = 0; i < hw->mac.max_rx_queues; i++) {
414 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
415 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
416 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
417 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
420 return IXGBE_SUCCESS;
424 * ixgbe_init_hw_generic - Generic hardware initialization
425 * @hw: pointer to hardware structure
427 * Initialize the hardware by resetting the hardware, filling the bus info
428 * structure and media type, clears all on chip counters, initializes receive
429 * address registers, multicast table, VLAN filter table, calls routine to set
430 * up link and flow control settings, and leaves transmit and receive units
431 * disabled and uninitialized
433 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
437 DEBUGFUNC("ixgbe_init_hw_generic");
439 /* Reset the hardware */
440 status = hw->mac.ops.reset_hw(hw);
442 if (status == IXGBE_SUCCESS) {
444 status = hw->mac.ops.start_hw(hw);
451 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
452 * @hw: pointer to hardware structure
454 * Clears all hardware statistics counters by reading them from the hardware
455 * Statistics counters are clear on read.
457 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
461 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
463 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
464 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
465 IXGBE_READ_REG(hw, IXGBE_ERRBC);
466 IXGBE_READ_REG(hw, IXGBE_MSPDC);
467 for (i = 0; i < 8; i++)
468 IXGBE_READ_REG(hw, IXGBE_MPC(i));
470 IXGBE_READ_REG(hw, IXGBE_MLFC);
471 IXGBE_READ_REG(hw, IXGBE_MRFC);
472 IXGBE_READ_REG(hw, IXGBE_RLEC);
473 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
474 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
475 if (hw->mac.type >= ixgbe_mac_82599EB) {
476 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
477 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
479 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
480 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
483 for (i = 0; i < 8; i++) {
484 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
485 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
486 if (hw->mac.type >= ixgbe_mac_82599EB) {
487 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
488 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
490 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
491 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
494 if (hw->mac.type >= ixgbe_mac_82599EB)
495 for (i = 0; i < 8; i++)
496 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
497 IXGBE_READ_REG(hw, IXGBE_PRC64);
498 IXGBE_READ_REG(hw, IXGBE_PRC127);
499 IXGBE_READ_REG(hw, IXGBE_PRC255);
500 IXGBE_READ_REG(hw, IXGBE_PRC511);
501 IXGBE_READ_REG(hw, IXGBE_PRC1023);
502 IXGBE_READ_REG(hw, IXGBE_PRC1522);
503 IXGBE_READ_REG(hw, IXGBE_GPRC);
504 IXGBE_READ_REG(hw, IXGBE_BPRC);
505 IXGBE_READ_REG(hw, IXGBE_MPRC);
506 IXGBE_READ_REG(hw, IXGBE_GPTC);
507 IXGBE_READ_REG(hw, IXGBE_GORCL);
508 IXGBE_READ_REG(hw, IXGBE_GORCH);
509 IXGBE_READ_REG(hw, IXGBE_GOTCL);
510 IXGBE_READ_REG(hw, IXGBE_GOTCH);
511 if (hw->mac.type == ixgbe_mac_82598EB)
512 for (i = 0; i < 8; i++)
513 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
514 IXGBE_READ_REG(hw, IXGBE_RUC);
515 IXGBE_READ_REG(hw, IXGBE_RFC);
516 IXGBE_READ_REG(hw, IXGBE_ROC);
517 IXGBE_READ_REG(hw, IXGBE_RJC);
518 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
519 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
520 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
521 IXGBE_READ_REG(hw, IXGBE_TORL);
522 IXGBE_READ_REG(hw, IXGBE_TORH);
523 IXGBE_READ_REG(hw, IXGBE_TPR);
524 IXGBE_READ_REG(hw, IXGBE_TPT);
525 IXGBE_READ_REG(hw, IXGBE_PTC64);
526 IXGBE_READ_REG(hw, IXGBE_PTC127);
527 IXGBE_READ_REG(hw, IXGBE_PTC255);
528 IXGBE_READ_REG(hw, IXGBE_PTC511);
529 IXGBE_READ_REG(hw, IXGBE_PTC1023);
530 IXGBE_READ_REG(hw, IXGBE_PTC1522);
531 IXGBE_READ_REG(hw, IXGBE_MPTC);
532 IXGBE_READ_REG(hw, IXGBE_BPTC);
533 for (i = 0; i < 16; i++) {
534 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
535 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
536 if (hw->mac.type >= ixgbe_mac_82599EB) {
537 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
538 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
539 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
540 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
541 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
543 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
544 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
548 if (hw->mac.type == ixgbe_mac_X540) {
550 ixgbe_identify_phy(hw);
551 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
552 IXGBE_MDIO_PCS_DEV_TYPE, &i);
553 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
554 IXGBE_MDIO_PCS_DEV_TYPE, &i);
555 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
556 IXGBE_MDIO_PCS_DEV_TYPE, &i);
557 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
558 IXGBE_MDIO_PCS_DEV_TYPE, &i);
561 return IXGBE_SUCCESS;
565 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
566 * @hw: pointer to hardware structure
567 * @pba_num: stores the part number string from the EEPROM
568 * @pba_num_size: part number string buffer length
570 * Reads the part number string from the EEPROM.
572 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
581 DEBUGFUNC("ixgbe_read_pba_string_generic");
583 if (pba_num == NULL) {
584 DEBUGOUT("PBA string buffer was null\n");
585 return IXGBE_ERR_INVALID_ARGUMENT;
588 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
590 DEBUGOUT("NVM Read Error\n");
594 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
596 DEBUGOUT("NVM Read Error\n");
601 * if data is not ptr guard the PBA must be in legacy format which
602 * means pba_ptr is actually our second data word for the PBA number
603 * and we can decode it into an ascii string
605 if (data != IXGBE_PBANUM_PTR_GUARD) {
606 DEBUGOUT("NVM PBA number is not stored as string\n");
608 /* we will need 11 characters to store the PBA */
609 if (pba_num_size < 11) {
610 DEBUGOUT("PBA string buffer too small\n");
611 return IXGBE_ERR_NO_SPACE;
614 /* extract hex string from data and pba_ptr */
615 pba_num[0] = (data >> 12) & 0xF;
616 pba_num[1] = (data >> 8) & 0xF;
617 pba_num[2] = (data >> 4) & 0xF;
618 pba_num[3] = data & 0xF;
619 pba_num[4] = (pba_ptr >> 12) & 0xF;
620 pba_num[5] = (pba_ptr >> 8) & 0xF;
623 pba_num[8] = (pba_ptr >> 4) & 0xF;
624 pba_num[9] = pba_ptr & 0xF;
626 /* put a null character on the end of our string */
629 /* switch all the data but the '-' to hex char */
630 for (offset = 0; offset < 10; offset++) {
631 if (pba_num[offset] < 0xA)
632 pba_num[offset] += '0';
633 else if (pba_num[offset] < 0x10)
634 pba_num[offset] += 'A' - 0xA;
637 return IXGBE_SUCCESS;
640 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
642 DEBUGOUT("NVM Read Error\n");
646 if (length == 0xFFFF || length == 0) {
647 DEBUGOUT("NVM PBA number section invalid length\n");
648 return IXGBE_ERR_PBA_SECTION;
651 /* check if pba_num buffer is big enough */
652 if (pba_num_size < (((u32)length * 2) - 1)) {
653 DEBUGOUT("PBA string buffer too small\n");
654 return IXGBE_ERR_NO_SPACE;
657 /* trim pba length from start of string */
661 for (offset = 0; offset < length; offset++) {
662 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
664 DEBUGOUT("NVM Read Error\n");
667 pba_num[offset * 2] = (u8)(data >> 8);
668 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
670 pba_num[offset * 2] = '\0';
672 return IXGBE_SUCCESS;
676 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
677 * @hw: pointer to hardware structure
678 * @pba_num: stores the part number from the EEPROM
680 * Reads the part number from the EEPROM.
682 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
687 DEBUGFUNC("ixgbe_read_pba_num_generic");
689 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
691 DEBUGOUT("NVM Read Error\n");
693 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
694 DEBUGOUT("NVM Not supported\n");
695 return IXGBE_NOT_IMPLEMENTED;
697 *pba_num = (u32)(data << 16);
699 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
701 DEBUGOUT("NVM Read Error\n");
706 return IXGBE_SUCCESS;
711 * @hw: pointer to the HW structure
712 * @eeprom_buf: optional pointer to EEPROM image
713 * @eeprom_buf_size: size of EEPROM image in words
714 * @max_pba_block_size: PBA block size limit
715 * @pba: pointer to output PBA structure
717 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
718 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
721 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
722 u32 eeprom_buf_size, u16 max_pba_block_size,
723 struct ixgbe_pba *pba)
729 return IXGBE_ERR_PARAM;
731 if (eeprom_buf == NULL) {
732 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
737 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
738 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
739 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
741 return IXGBE_ERR_PARAM;
745 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
746 if (pba->pba_block == NULL)
747 return IXGBE_ERR_PARAM;
749 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
755 if (pba_block_size > max_pba_block_size)
756 return IXGBE_ERR_PARAM;
758 if (eeprom_buf == NULL) {
759 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
765 if (eeprom_buf_size > (u32)(pba->word[1] +
766 pba->pba_block[0])) {
767 memcpy(pba->pba_block,
768 &eeprom_buf[pba->word[1]],
769 pba_block_size * sizeof(u16));
771 return IXGBE_ERR_PARAM;
776 return IXGBE_SUCCESS;
780 * ixgbe_write_pba_raw
781 * @hw: pointer to the HW structure
782 * @eeprom_buf: optional pointer to EEPROM image
783 * @eeprom_buf_size: size of EEPROM image in words
784 * @pba: pointer to PBA structure
786 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
787 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
790 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
791 u32 eeprom_buf_size, struct ixgbe_pba *pba)
796 return IXGBE_ERR_PARAM;
798 if (eeprom_buf == NULL) {
799 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
804 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
805 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
806 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
808 return IXGBE_ERR_PARAM;
812 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
813 if (pba->pba_block == NULL)
814 return IXGBE_ERR_PARAM;
816 if (eeprom_buf == NULL) {
817 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
823 if (eeprom_buf_size > (u32)(pba->word[1] +
824 pba->pba_block[0])) {
825 memcpy(&eeprom_buf[pba->word[1]],
827 pba->pba_block[0] * sizeof(u16));
829 return IXGBE_ERR_PARAM;
834 return IXGBE_SUCCESS;
838 * ixgbe_get_pba_block_size
839 * @hw: pointer to the HW structure
840 * @eeprom_buf: optional pointer to EEPROM image
841 * @eeprom_buf_size: size of EEPROM image in words
842 * @pba_data_size: pointer to output variable
844 * Returns the size of the PBA block in words. Function operates on EEPROM
845 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
849 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
850 u32 eeprom_buf_size, u16 *pba_block_size)
856 DEBUGFUNC("ixgbe_get_pba_block_size");
858 if (eeprom_buf == NULL) {
859 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
864 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
865 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
866 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
868 return IXGBE_ERR_PARAM;
872 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
873 if (eeprom_buf == NULL) {
874 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
879 if (eeprom_buf_size > pba_word[1])
880 length = eeprom_buf[pba_word[1] + 0];
882 return IXGBE_ERR_PARAM;
885 if (length == 0xFFFF || length == 0)
886 return IXGBE_ERR_PBA_SECTION;
888 /* PBA number in legacy format, there is no PBA Block. */
892 if (pba_block_size != NULL)
893 *pba_block_size = length;
895 return IXGBE_SUCCESS;
899 * ixgbe_get_mac_addr_generic - Generic get MAC address
900 * @hw: pointer to hardware structure
901 * @mac_addr: Adapter MAC address
903 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
904 * A reset of the adapter must be performed prior to calling this function
905 * in order for the MAC address to have been loaded from the EEPROM into RAR0
907 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
913 DEBUGFUNC("ixgbe_get_mac_addr_generic");
915 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
916 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
918 for (i = 0; i < 4; i++)
919 mac_addr[i] = (u8)(rar_low >> (i*8));
921 for (i = 0; i < 2; i++)
922 mac_addr[i+4] = (u8)(rar_high >> (i*8));
924 return IXGBE_SUCCESS;
928 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
929 * @hw: pointer to hardware structure
930 * @link_status: the link status returned by the PCI config space
932 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
934 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
936 struct ixgbe_mac_info *mac = &hw->mac;
938 hw->bus.type = ixgbe_bus_type_pci_express;
940 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
941 case IXGBE_PCI_LINK_WIDTH_1:
942 hw->bus.width = ixgbe_bus_width_pcie_x1;
944 case IXGBE_PCI_LINK_WIDTH_2:
945 hw->bus.width = ixgbe_bus_width_pcie_x2;
947 case IXGBE_PCI_LINK_WIDTH_4:
948 hw->bus.width = ixgbe_bus_width_pcie_x4;
950 case IXGBE_PCI_LINK_WIDTH_8:
951 hw->bus.width = ixgbe_bus_width_pcie_x8;
954 hw->bus.width = ixgbe_bus_width_unknown;
958 switch (link_status & IXGBE_PCI_LINK_SPEED) {
959 case IXGBE_PCI_LINK_SPEED_2500:
960 hw->bus.speed = ixgbe_bus_speed_2500;
962 case IXGBE_PCI_LINK_SPEED_5000:
963 hw->bus.speed = ixgbe_bus_speed_5000;
965 case IXGBE_PCI_LINK_SPEED_8000:
966 hw->bus.speed = ixgbe_bus_speed_8000;
969 hw->bus.speed = ixgbe_bus_speed_unknown;
973 mac->ops.set_lan_id(hw);
977 * ixgbe_get_bus_info_generic - Generic set PCI bus info
978 * @hw: pointer to hardware structure
980 * Gets the PCI bus info (speed, width, type) then calls helper function to
981 * store this data within the ixgbe_hw structure.
983 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
987 DEBUGFUNC("ixgbe_get_bus_info_generic");
989 /* Get the negotiated link width and speed from PCI config space */
990 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
992 ixgbe_set_pci_config_data_generic(hw, link_status);
994 return IXGBE_SUCCESS;
998 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
999 * @hw: pointer to the HW structure
1001 * Determines the LAN function id by reading memory-mapped registers
1002 * and swaps the port value if requested.
1004 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1006 struct ixgbe_bus_info *bus = &hw->bus;
1009 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1011 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1012 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1013 bus->lan_id = bus->func;
1015 /* check for a port swap */
1016 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
1017 if (reg & IXGBE_FACTPS_LFS)
1022 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1023 * @hw: pointer to hardware structure
1025 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1026 * disables transmit and receive units. The adapter_stopped flag is used by
1027 * the shared code and drivers to determine if the adapter is in a stopped
1028 * state and should not touch the hardware.
1030 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1035 DEBUGFUNC("ixgbe_stop_adapter_generic");
1038 * Set the adapter_stopped flag so other driver functions stop touching
1041 hw->adapter_stopped = true;
1043 /* Disable the receive unit */
1044 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
1046 /* Clear interrupt mask to stop interrupts from being generated */
1047 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1049 /* Clear any pending interrupts, flush previous writes */
1050 IXGBE_READ_REG(hw, IXGBE_EICR);
1052 /* Disable the transmit unit. Each queue must be disabled. */
1053 for (i = 0; i < hw->mac.max_tx_queues; i++)
1054 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1056 /* Disable the receive unit by stopping each queue */
1057 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1058 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1059 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1060 reg_val |= IXGBE_RXDCTL_SWFLSH;
1061 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1064 /* flush all queues disables */
1065 IXGBE_WRITE_FLUSH(hw);
1069 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
1070 * access and verify no pending requests
1072 return ixgbe_disable_pcie_master(hw);
1076 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1077 * @hw: pointer to hardware structure
1078 * @index: led number to turn on
1080 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1082 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1084 DEBUGFUNC("ixgbe_led_on_generic");
1086 /* To turn on the LED, set mode to ON. */
1087 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1088 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1089 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1090 IXGBE_WRITE_FLUSH(hw);
1092 return IXGBE_SUCCESS;
1096 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1097 * @hw: pointer to hardware structure
1098 * @index: led number to turn off
1100 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1102 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1104 DEBUGFUNC("ixgbe_led_off_generic");
1106 /* To turn off the LED, set mode to OFF. */
1107 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1108 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1109 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1110 IXGBE_WRITE_FLUSH(hw);
1112 return IXGBE_SUCCESS;
1116 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1117 * @hw: pointer to hardware structure
1119 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1120 * ixgbe_hw struct in order to set up EEPROM access.
1122 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1124 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1128 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1130 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1131 eeprom->type = ixgbe_eeprom_none;
1132 /* Set default semaphore delay to 10ms which is a well
1134 eeprom->semaphore_delay = 10;
1135 /* Clear EEPROM page size, it will be initialized as needed */
1136 eeprom->word_page_size = 0;
1139 * Check for EEPROM present first.
1140 * If not present leave as none
1142 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1143 if (eec & IXGBE_EEC_PRES) {
1144 eeprom->type = ixgbe_eeprom_spi;
1147 * SPI EEPROM is assumed here. This code would need to
1148 * change if a future EEPROM is not SPI.
1150 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1151 IXGBE_EEC_SIZE_SHIFT);
1152 eeprom->word_size = 1 << (eeprom_size +
1153 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1156 if (eec & IXGBE_EEC_ADDR_SIZE)
1157 eeprom->address_bits = 16;
1159 eeprom->address_bits = 8;
1160 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1161 "%d\n", eeprom->type, eeprom->word_size,
1162 eeprom->address_bits);
1165 return IXGBE_SUCCESS;
1169 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1170 * @hw: pointer to hardware structure
1171 * @offset: offset within the EEPROM to write
1172 * @words: number of word(s)
1173 * @data: 16 bit word(s) to write to EEPROM
1175 * Reads 16 bit word(s) from EEPROM through bit-bang method
1177 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1178 u16 words, u16 *data)
1180 s32 status = IXGBE_SUCCESS;
1183 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1185 hw->eeprom.ops.init_params(hw);
1188 status = IXGBE_ERR_INVALID_ARGUMENT;
1192 if (offset + words > hw->eeprom.word_size) {
1193 status = IXGBE_ERR_EEPROM;
1198 * The EEPROM page size cannot be queried from the chip. We do lazy
1199 * initialization. It is worth to do that when we write large buffer.
1201 if ((hw->eeprom.word_page_size == 0) &&
1202 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1203 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1206 * We cannot hold synchronization semaphores for too long
1207 * to avoid other entity starvation. However it is more efficient
1208 * to read in bursts than synchronizing access for each word.
1210 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1211 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1212 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1213 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1216 if (status != IXGBE_SUCCESS)
1225 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1226 * @hw: pointer to hardware structure
1227 * @offset: offset within the EEPROM to be written to
1228 * @words: number of word(s)
1229 * @data: 16 bit word(s) to be written to the EEPROM
1231 * If ixgbe_eeprom_update_checksum is not called after this function, the
1232 * EEPROM will most likely contain an invalid checksum.
1234 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1235 u16 words, u16 *data)
1241 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1243 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1245 /* Prepare the EEPROM for writing */
1246 status = ixgbe_acquire_eeprom(hw);
1248 if (status == IXGBE_SUCCESS) {
1249 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1250 ixgbe_release_eeprom(hw);
1251 status = IXGBE_ERR_EEPROM;
1255 if (status == IXGBE_SUCCESS) {
1256 for (i = 0; i < words; i++) {
1257 ixgbe_standby_eeprom(hw);
1259 /* Send the WRITE ENABLE command (8 bit opcode ) */
1260 ixgbe_shift_out_eeprom_bits(hw,
1261 IXGBE_EEPROM_WREN_OPCODE_SPI,
1262 IXGBE_EEPROM_OPCODE_BITS);
1264 ixgbe_standby_eeprom(hw);
1267 * Some SPI eeproms use the 8th address bit embedded
1270 if ((hw->eeprom.address_bits == 8) &&
1271 ((offset + i) >= 128))
1272 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1274 /* Send the Write command (8-bit opcode + addr) */
1275 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1276 IXGBE_EEPROM_OPCODE_BITS);
1277 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1278 hw->eeprom.address_bits);
1280 page_size = hw->eeprom.word_page_size;
1282 /* Send the data in burst via SPI*/
1285 word = (word >> 8) | (word << 8);
1286 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1291 /* do not wrap around page */
1292 if (((offset + i) & (page_size - 1)) ==
1295 } while (++i < words);
1297 ixgbe_standby_eeprom(hw);
1300 /* Done with writing - release the EEPROM */
1301 ixgbe_release_eeprom(hw);
1308 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1309 * @hw: pointer to hardware structure
1310 * @offset: offset within the EEPROM to be written to
1311 * @data: 16 bit word to be written to the EEPROM
1313 * If ixgbe_eeprom_update_checksum is not called after this function, the
1314 * EEPROM will most likely contain an invalid checksum.
1316 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1320 DEBUGFUNC("ixgbe_write_eeprom_generic");
1322 hw->eeprom.ops.init_params(hw);
1324 if (offset >= hw->eeprom.word_size) {
1325 status = IXGBE_ERR_EEPROM;
1329 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1336 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1337 * @hw: pointer to hardware structure
1338 * @offset: offset within the EEPROM to be read
1339 * @data: read 16 bit words(s) from EEPROM
1340 * @words: number of word(s)
1342 * Reads 16 bit word(s) from EEPROM through bit-bang method
1344 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1345 u16 words, u16 *data)
1347 s32 status = IXGBE_SUCCESS;
1350 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1352 hw->eeprom.ops.init_params(hw);
1355 status = IXGBE_ERR_INVALID_ARGUMENT;
1359 if (offset + words > hw->eeprom.word_size) {
1360 status = IXGBE_ERR_EEPROM;
1365 * We cannot hold synchronization semaphores for too long
1366 * to avoid other entity starvation. However it is more efficient
1367 * to read in bursts than synchronizing access for each word.
1369 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1370 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1371 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1373 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1376 if (status != IXGBE_SUCCESS)
1385 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1386 * @hw: pointer to hardware structure
1387 * @offset: offset within the EEPROM to be read
1388 * @words: number of word(s)
1389 * @data: read 16 bit word(s) from EEPROM
1391 * Reads 16 bit word(s) from EEPROM through bit-bang method
1393 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1394 u16 words, u16 *data)
1398 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1401 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1403 /* Prepare the EEPROM for reading */
1404 status = ixgbe_acquire_eeprom(hw);
1406 if (status == IXGBE_SUCCESS) {
1407 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1408 ixgbe_release_eeprom(hw);
1409 status = IXGBE_ERR_EEPROM;
1413 if (status == IXGBE_SUCCESS) {
1414 for (i = 0; i < words; i++) {
1415 ixgbe_standby_eeprom(hw);
1417 * Some SPI eeproms use the 8th address bit embedded
1420 if ((hw->eeprom.address_bits == 8) &&
1421 ((offset + i) >= 128))
1422 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1424 /* Send the READ command (opcode + addr) */
1425 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1426 IXGBE_EEPROM_OPCODE_BITS);
1427 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1428 hw->eeprom.address_bits);
1430 /* Read the data. */
1431 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1432 data[i] = (word_in >> 8) | (word_in << 8);
1435 /* End this read operation */
1436 ixgbe_release_eeprom(hw);
1443 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1444 * @hw: pointer to hardware structure
1445 * @offset: offset within the EEPROM to be read
1446 * @data: read 16 bit value from EEPROM
1448 * Reads 16 bit value from EEPROM through bit-bang method
1450 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1455 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1457 hw->eeprom.ops.init_params(hw);
1459 if (offset >= hw->eeprom.word_size) {
1460 status = IXGBE_ERR_EEPROM;
1464 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1471 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1472 * @hw: pointer to hardware structure
1473 * @offset: offset of word in the EEPROM to read
1474 * @words: number of word(s)
1475 * @data: 16 bit word(s) from the EEPROM
1477 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1479 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1480 u16 words, u16 *data)
1483 s32 status = IXGBE_SUCCESS;
1486 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1488 hw->eeprom.ops.init_params(hw);
1491 status = IXGBE_ERR_INVALID_ARGUMENT;
1492 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1496 if (offset >= hw->eeprom.word_size) {
1497 status = IXGBE_ERR_EEPROM;
1498 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1502 for (i = 0; i < words; i++) {
1503 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1504 IXGBE_EEPROM_RW_REG_START;
1506 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1507 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1509 if (status == IXGBE_SUCCESS) {
1510 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1511 IXGBE_EEPROM_RW_REG_DATA);
1513 DEBUGOUT("Eeprom read timed out\n");
1522 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1523 * @hw: pointer to hardware structure
1524 * @offset: offset within the EEPROM to be used as a scratch pad
1526 * Discover EEPROM page size by writing marching data at given offset.
1527 * This function is called only when we are writing a new large buffer
1528 * at given offset so the data would be overwritten anyway.
1530 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1533 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1534 s32 status = IXGBE_SUCCESS;
1537 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1539 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1542 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1543 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1544 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1545 hw->eeprom.word_page_size = 0;
1546 if (status != IXGBE_SUCCESS)
1549 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1550 if (status != IXGBE_SUCCESS)
1554 * When writing in burst more than the actual page size
1555 * EEPROM address wraps around current page.
1557 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1559 DEBUGOUT1("Detected EEPROM page size = %d words.",
1560 hw->eeprom.word_page_size);
1566 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1567 * @hw: pointer to hardware structure
1568 * @offset: offset of word in the EEPROM to read
1569 * @data: word read from the EEPROM
1571 * Reads a 16 bit word from the EEPROM using the EERD register.
1573 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1575 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1579 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1580 * @hw: pointer to hardware structure
1581 * @offset: offset of word in the EEPROM to write
1582 * @words: number of word(s)
1583 * @data: word(s) write to the EEPROM
1585 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1587 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1588 u16 words, u16 *data)
1591 s32 status = IXGBE_SUCCESS;
1594 DEBUGFUNC("ixgbe_write_eewr_generic");
1596 hw->eeprom.ops.init_params(hw);
1599 status = IXGBE_ERR_INVALID_ARGUMENT;
1600 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1604 if (offset >= hw->eeprom.word_size) {
1605 status = IXGBE_ERR_EEPROM;
1606 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1610 for (i = 0; i < words; i++) {
1611 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1612 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1613 IXGBE_EEPROM_RW_REG_START;
1615 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1616 if (status != IXGBE_SUCCESS) {
1617 DEBUGOUT("Eeprom write EEWR timed out\n");
1621 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1623 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1624 if (status != IXGBE_SUCCESS) {
1625 DEBUGOUT("Eeprom write EEWR timed out\n");
1635 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1636 * @hw: pointer to hardware structure
1637 * @offset: offset of word in the EEPROM to write
1638 * @data: word write to the EEPROM
1640 * Write a 16 bit word to the EEPROM using the EEWR register.
1642 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1644 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1648 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1649 * @hw: pointer to hardware structure
1650 * @ee_reg: EEPROM flag for polling
1652 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1653 * read or write is done respectively.
1655 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1659 s32 status = IXGBE_ERR_EEPROM;
1661 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1663 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1664 if (ee_reg == IXGBE_NVM_POLL_READ)
1665 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1667 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1669 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1670 status = IXGBE_SUCCESS;
1676 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1677 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1678 "EEPROM read/write done polling timed out");
1684 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1685 * @hw: pointer to hardware structure
1687 * Prepares EEPROM for access using bit-bang method. This function should
1688 * be called before issuing a command to the EEPROM.
1690 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1692 s32 status = IXGBE_SUCCESS;
1696 DEBUGFUNC("ixgbe_acquire_eeprom");
1698 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1700 status = IXGBE_ERR_SWFW_SYNC;
1702 if (status == IXGBE_SUCCESS) {
1703 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1705 /* Request EEPROM Access */
1706 eec |= IXGBE_EEC_REQ;
1707 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1709 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1710 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1711 if (eec & IXGBE_EEC_GNT)
1716 /* Release if grant not acquired */
1717 if (!(eec & IXGBE_EEC_GNT)) {
1718 eec &= ~IXGBE_EEC_REQ;
1719 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1720 DEBUGOUT("Could not acquire EEPROM grant\n");
1722 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1723 status = IXGBE_ERR_EEPROM;
1726 /* Setup EEPROM for Read/Write */
1727 if (status == IXGBE_SUCCESS) {
1728 /* Clear CS and SK */
1729 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1730 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1731 IXGBE_WRITE_FLUSH(hw);
1739 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1740 * @hw: pointer to hardware structure
1742 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1744 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1746 s32 status = IXGBE_ERR_EEPROM;
1751 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1754 /* Get SMBI software semaphore between device drivers first */
1755 for (i = 0; i < timeout; i++) {
1757 * If the SMBI bit is 0 when we read it, then the bit will be
1758 * set and we have the semaphore
1760 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1761 if (!(swsm & IXGBE_SWSM_SMBI)) {
1762 status = IXGBE_SUCCESS;
1769 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1772 * this release is particularly important because our attempts
1773 * above to get the semaphore may have succeeded, and if there
1774 * was a timeout, we should unconditionally clear the semaphore
1775 * bits to free the driver to make progress
1777 ixgbe_release_eeprom_semaphore(hw);
1782 * If the SMBI bit is 0 when we read it, then the bit will be
1783 * set and we have the semaphore
1785 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1786 if (!(swsm & IXGBE_SWSM_SMBI))
1787 status = IXGBE_SUCCESS;
1790 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1791 if (status == IXGBE_SUCCESS) {
1792 for (i = 0; i < timeout; i++) {
1793 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1795 /* Set the SW EEPROM semaphore bit to request access */
1796 swsm |= IXGBE_SWSM_SWESMBI;
1797 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1800 * If we set the bit successfully then we got the
1803 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1804 if (swsm & IXGBE_SWSM_SWESMBI)
1811 * Release semaphores and return error if SW EEPROM semaphore
1812 * was not granted because we don't have access to the EEPROM
1815 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1816 "SWESMBI Software EEPROM semaphore not granted.\n");
1817 ixgbe_release_eeprom_semaphore(hw);
1818 status = IXGBE_ERR_EEPROM;
1821 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1822 "Software semaphore SMBI between device drivers "
1830 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1831 * @hw: pointer to hardware structure
1833 * This function clears hardware semaphore bits.
1835 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1839 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1841 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1843 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1844 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1845 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1846 IXGBE_WRITE_FLUSH(hw);
1850 * ixgbe_ready_eeprom - Polls for EEPROM ready
1851 * @hw: pointer to hardware structure
1853 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1855 s32 status = IXGBE_SUCCESS;
1859 DEBUGFUNC("ixgbe_ready_eeprom");
1862 * Read "Status Register" repeatedly until the LSB is cleared. The
1863 * EEPROM will signal that the command has been completed by clearing
1864 * bit 0 of the internal status register. If it's not cleared within
1865 * 5 milliseconds, then error out.
1867 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1868 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1869 IXGBE_EEPROM_OPCODE_BITS);
1870 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1871 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1875 ixgbe_standby_eeprom(hw);
1879 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1880 * devices (and only 0-5mSec on 5V devices)
1882 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1883 DEBUGOUT("SPI EEPROM Status error\n");
1884 status = IXGBE_ERR_EEPROM;
1891 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1892 * @hw: pointer to hardware structure
1894 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1898 DEBUGFUNC("ixgbe_standby_eeprom");
1900 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1902 /* Toggle CS to flush commands */
1903 eec |= IXGBE_EEC_CS;
1904 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1905 IXGBE_WRITE_FLUSH(hw);
1907 eec &= ~IXGBE_EEC_CS;
1908 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1909 IXGBE_WRITE_FLUSH(hw);
1914 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1915 * @hw: pointer to hardware structure
1916 * @data: data to send to the EEPROM
1917 * @count: number of bits to shift out
1919 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1926 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1928 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1931 * Mask is used to shift "count" bits of "data" out to the EEPROM
1932 * one bit at a time. Determine the starting bit based on count
1934 mask = 0x01 << (count - 1);
1936 for (i = 0; i < count; i++) {
1938 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1939 * "1", and then raising and then lowering the clock (the SK
1940 * bit controls the clock input to the EEPROM). A "0" is
1941 * shifted out to the EEPROM by setting "DI" to "0" and then
1942 * raising and then lowering the clock.
1945 eec |= IXGBE_EEC_DI;
1947 eec &= ~IXGBE_EEC_DI;
1949 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1950 IXGBE_WRITE_FLUSH(hw);
1954 ixgbe_raise_eeprom_clk(hw, &eec);
1955 ixgbe_lower_eeprom_clk(hw, &eec);
1958 * Shift mask to signify next bit of data to shift in to the
1964 /* We leave the "DI" bit set to "0" when we leave this routine. */
1965 eec &= ~IXGBE_EEC_DI;
1966 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1967 IXGBE_WRITE_FLUSH(hw);
1971 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1972 * @hw: pointer to hardware structure
1974 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1980 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
1983 * In order to read a register from the EEPROM, we need to shift
1984 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1985 * the clock input to the EEPROM (setting the SK bit), and then reading
1986 * the value of the "DO" bit. During this "shifting in" process the
1987 * "DI" bit should always be clear.
1989 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1991 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1993 for (i = 0; i < count; i++) {
1995 ixgbe_raise_eeprom_clk(hw, &eec);
1997 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1999 eec &= ~(IXGBE_EEC_DI);
2000 if (eec & IXGBE_EEC_DO)
2003 ixgbe_lower_eeprom_clk(hw, &eec);
2010 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2011 * @hw: pointer to hardware structure
2012 * @eec: EEC register's current value
2014 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2016 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2019 * Raise the clock input to the EEPROM
2020 * (setting the SK bit), then delay
2022 *eec = *eec | IXGBE_EEC_SK;
2023 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2024 IXGBE_WRITE_FLUSH(hw);
2029 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2030 * @hw: pointer to hardware structure
2031 * @eecd: EECD's current value
2033 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2035 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2038 * Lower the clock input to the EEPROM (clearing the SK bit), then
2041 *eec = *eec & ~IXGBE_EEC_SK;
2042 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2043 IXGBE_WRITE_FLUSH(hw);
2048 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2049 * @hw: pointer to hardware structure
2051 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2055 DEBUGFUNC("ixgbe_release_eeprom");
2057 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2059 eec |= IXGBE_EEC_CS; /* Pull CS high */
2060 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2062 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2063 IXGBE_WRITE_FLUSH(hw);
2067 /* Stop requesting EEPROM access */
2068 eec &= ~IXGBE_EEC_REQ;
2069 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2071 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2073 /* Delay before attempt to obtain semaphore again to allow FW access */
2074 msec_delay(hw->eeprom.semaphore_delay);
2078 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2079 * @hw: pointer to hardware structure
2081 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2090 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2092 /* Include 0x0-0x3F in the checksum */
2093 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2094 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) {
2095 DEBUGOUT("EEPROM read failed\n");
2101 /* Include all data from pointers except for the fw pointer */
2102 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2103 hw->eeprom.ops.read(hw, i, &pointer);
2105 /* Make sure the pointer seems valid */
2106 if (pointer != 0xFFFF && pointer != 0) {
2107 hw->eeprom.ops.read(hw, pointer, &length);
2109 if (length != 0xFFFF && length != 0) {
2110 for (j = pointer+1; j <= pointer+length; j++) {
2111 hw->eeprom.ops.read(hw, j, &word);
2118 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2124 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2125 * @hw: pointer to hardware structure
2126 * @checksum_val: calculated checksum
2128 * Performs checksum calculation and validates the EEPROM checksum. If the
2129 * caller does not need checksum_val, the value can be NULL.
2131 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2136 u16 read_checksum = 0;
2138 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2141 * Read the first word from the EEPROM. If this times out or fails, do
2142 * not continue or we could be in for a very long wait while every
2145 status = hw->eeprom.ops.read(hw, 0, &checksum);
2147 if (status == IXGBE_SUCCESS) {
2148 checksum = hw->eeprom.ops.calc_checksum(hw);
2150 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2153 * Verify read checksum from EEPROM is the same as
2154 * calculated checksum
2156 if (read_checksum != checksum)
2157 status = IXGBE_ERR_EEPROM_CHECKSUM;
2159 /* If the user cares, return the calculated checksum */
2161 *checksum_val = checksum;
2163 DEBUGOUT("EEPROM read failed\n");
2170 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2171 * @hw: pointer to hardware structure
2173 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2178 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2181 * Read the first word from the EEPROM. If this times out or fails, do
2182 * not continue or we could be in for a very long wait while every
2185 status = hw->eeprom.ops.read(hw, 0, &checksum);
2187 if (status == IXGBE_SUCCESS) {
2188 checksum = hw->eeprom.ops.calc_checksum(hw);
2189 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
2192 DEBUGOUT("EEPROM read failed\n");
2199 * ixgbe_validate_mac_addr - Validate MAC address
2200 * @mac_addr: pointer to MAC address.
2202 * Tests a MAC address to ensure it is a valid Individual Address
2204 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2206 s32 status = IXGBE_SUCCESS;
2208 DEBUGFUNC("ixgbe_validate_mac_addr");
2210 /* Make sure it is not a multicast address */
2211 if (IXGBE_IS_MULTICAST(mac_addr)) {
2212 DEBUGOUT("MAC address is multicast\n");
2213 status = IXGBE_ERR_INVALID_MAC_ADDR;
2214 /* Not a broadcast address */
2215 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2216 DEBUGOUT("MAC address is broadcast\n");
2217 status = IXGBE_ERR_INVALID_MAC_ADDR;
2218 /* Reject the zero address */
2219 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2220 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2221 DEBUGOUT("MAC address is all zeros\n");
2222 status = IXGBE_ERR_INVALID_MAC_ADDR;
2228 * ixgbe_set_rar_generic - Set Rx address register
2229 * @hw: pointer to hardware structure
2230 * @index: Receive address register to write
2231 * @addr: Address to put into receive address register
2232 * @vmdq: VMDq "set" or "pool" index
2233 * @enable_addr: set flag that address is active
2235 * Puts an ethernet address into a receive address register.
2237 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2240 u32 rar_low, rar_high;
2241 u32 rar_entries = hw->mac.num_rar_entries;
2243 DEBUGFUNC("ixgbe_set_rar_generic");
2245 /* Make sure we are using a valid rar index range */
2246 if (index >= rar_entries) {
2247 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2248 "RAR index %d is out of range.\n", index);
2249 return IXGBE_ERR_INVALID_ARGUMENT;
2252 /* setup VMDq pool selection before this RAR gets enabled */
2253 hw->mac.ops.set_vmdq(hw, index, vmdq);
2256 * HW expects these in little endian so we reverse the byte
2257 * order from network order (big endian) to little endian
2259 rar_low = ((u32)addr[0] |
2260 ((u32)addr[1] << 8) |
2261 ((u32)addr[2] << 16) |
2262 ((u32)addr[3] << 24));
2264 * Some parts put the VMDq setting in the extra RAH bits,
2265 * so save everything except the lower 16 bits that hold part
2266 * of the address and the address valid bit.
2268 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2269 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2270 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2272 if (enable_addr != 0)
2273 rar_high |= IXGBE_RAH_AV;
2275 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2276 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2278 return IXGBE_SUCCESS;
2282 * ixgbe_clear_rar_generic - Remove Rx address register
2283 * @hw: pointer to hardware structure
2284 * @index: Receive address register to write
2286 * Clears an ethernet address from a receive address register.
2288 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2291 u32 rar_entries = hw->mac.num_rar_entries;
2293 DEBUGFUNC("ixgbe_clear_rar_generic");
2295 /* Make sure we are using a valid rar index range */
2296 if (index >= rar_entries) {
2297 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2298 "RAR index %d is out of range.\n", index);
2299 return IXGBE_ERR_INVALID_ARGUMENT;
2303 * Some parts put the VMDq setting in the extra RAH bits,
2304 * so save everything except the lower 16 bits that hold part
2305 * of the address and the address valid bit.
2307 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2308 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2310 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2311 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2313 /* clear VMDq pool/queue selection for this RAR */
2314 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2316 return IXGBE_SUCCESS;
2320 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2321 * @hw: pointer to hardware structure
2323 * Places the MAC address in receive address register 0 and clears the rest
2324 * of the receive address registers. Clears the multicast table. Assumes
2325 * the receiver is in reset when the routine is called.
2327 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2330 u32 rar_entries = hw->mac.num_rar_entries;
2332 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2335 * If the current mac address is valid, assume it is a software override
2336 * to the permanent address.
2337 * Otherwise, use the permanent address from the eeprom.
2339 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2340 IXGBE_ERR_INVALID_MAC_ADDR) {
2341 /* Get the MAC address from the RAR0 for later reference */
2342 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2344 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2345 hw->mac.addr[0], hw->mac.addr[1],
2347 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2348 hw->mac.addr[4], hw->mac.addr[5]);
2350 /* Setup the receive address. */
2351 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2352 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2353 hw->mac.addr[0], hw->mac.addr[1],
2355 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2356 hw->mac.addr[4], hw->mac.addr[5]);
2358 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2360 /* clear VMDq pool/queue selection for RAR 0 */
2361 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2363 hw->addr_ctrl.overflow_promisc = 0;
2365 hw->addr_ctrl.rar_used_count = 1;
2367 /* Zero out the other receive addresses. */
2368 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2369 for (i = 1; i < rar_entries; i++) {
2370 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2371 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2375 hw->addr_ctrl.mta_in_use = 0;
2376 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2378 DEBUGOUT(" Clearing MTA\n");
2379 for (i = 0; i < hw->mac.mcft_size; i++)
2380 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2382 ixgbe_init_uta_tables(hw);
2384 return IXGBE_SUCCESS;
2388 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2389 * @hw: pointer to hardware structure
2390 * @addr: new address
2392 * Adds it to unused receive address register or goes into promiscuous mode.
2394 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2396 u32 rar_entries = hw->mac.num_rar_entries;
2399 DEBUGFUNC("ixgbe_add_uc_addr");
2401 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2402 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2405 * Place this address in the RAR if there is room,
2406 * else put the controller into promiscuous mode
2408 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2409 rar = hw->addr_ctrl.rar_used_count;
2410 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2411 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2412 hw->addr_ctrl.rar_used_count++;
2414 hw->addr_ctrl.overflow_promisc++;
2417 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2421 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2422 * @hw: pointer to hardware structure
2423 * @addr_list: the list of new addresses
2424 * @addr_count: number of addresses
2425 * @next: iterator function to walk the address list
2427 * The given list replaces any existing list. Clears the secondary addrs from
2428 * receive address registers. Uses unused receive address registers for the
2429 * first secondary addresses, and falls back to promiscuous mode as needed.
2431 * Drivers using secondary unicast addresses must set user_set_promisc when
2432 * manually putting the device into promiscuous mode.
2434 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2435 u32 addr_count, ixgbe_mc_addr_itr next)
2439 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2444 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2447 * Clear accounting of old secondary address list,
2448 * don't count RAR[0]
2450 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2451 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2452 hw->addr_ctrl.overflow_promisc = 0;
2454 /* Zero out the other receive addresses */
2455 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2456 for (i = 0; i < uc_addr_in_use; i++) {
2457 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2458 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2461 /* Add the new addresses */
2462 for (i = 0; i < addr_count; i++) {
2463 DEBUGOUT(" Adding the secondary addresses:\n");
2464 addr = next(hw, &addr_list, &vmdq);
2465 ixgbe_add_uc_addr(hw, addr, vmdq);
2468 if (hw->addr_ctrl.overflow_promisc) {
2469 /* enable promisc if not already in overflow or set by user */
2470 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2471 DEBUGOUT(" Entering address overflow promisc mode\n");
2472 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2473 fctrl |= IXGBE_FCTRL_UPE;
2474 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2477 /* only disable if set by overflow, not by user */
2478 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2479 DEBUGOUT(" Leaving address overflow promisc mode\n");
2480 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2481 fctrl &= ~IXGBE_FCTRL_UPE;
2482 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2486 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2487 return IXGBE_SUCCESS;
2491 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2492 * @hw: pointer to hardware structure
2493 * @mc_addr: the multicast address
2495 * Extracts the 12 bits, from a multicast address, to determine which
2496 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2497 * incoming rx multicast addresses, to determine the bit-vector to check in
2498 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2499 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2500 * to mc_filter_type.
2502 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2506 DEBUGFUNC("ixgbe_mta_vector");
2508 switch (hw->mac.mc_filter_type) {
2509 case 0: /* use bits [47:36] of the address */
2510 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2512 case 1: /* use bits [46:35] of the address */
2513 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2515 case 2: /* use bits [45:34] of the address */
2516 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2518 case 3: /* use bits [43:32] of the address */
2519 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2521 default: /* Invalid mc_filter_type */
2522 DEBUGOUT("MC filter type param set incorrectly\n");
2527 /* vector can only be 12-bits or boundary will be exceeded */
2533 * ixgbe_set_mta - Set bit-vector in multicast table
2534 * @hw: pointer to hardware structure
2535 * @hash_value: Multicast address hash value
2537 * Sets the bit-vector in the multicast table.
2539 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2545 DEBUGFUNC("ixgbe_set_mta");
2547 hw->addr_ctrl.mta_in_use++;
2549 vector = ixgbe_mta_vector(hw, mc_addr);
2550 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2553 * The MTA is a register array of 128 32-bit registers. It is treated
2554 * like an array of 4096 bits. We want to set bit
2555 * BitArray[vector_value]. So we figure out what register the bit is
2556 * in, read it, OR in the new bit, then write back the new value. The
2557 * register is determined by the upper 7 bits of the vector value and
2558 * the bit within that register are determined by the lower 5 bits of
2561 vector_reg = (vector >> 5) & 0x7F;
2562 vector_bit = vector & 0x1F;
2563 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2567 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2568 * @hw: pointer to hardware structure
2569 * @mc_addr_list: the list of new multicast addresses
2570 * @mc_addr_count: number of addresses
2571 * @next: iterator function to walk the multicast address list
2572 * @clear: flag, when set clears the table beforehand
2574 * When the clear flag is set, the given list replaces any existing list.
2575 * Hashes the given addresses into the multicast table.
2577 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2578 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2584 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2587 * Set the new number of MC addresses that we are being requested to
2590 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2591 hw->addr_ctrl.mta_in_use = 0;
2593 /* Clear mta_shadow */
2595 DEBUGOUT(" Clearing MTA\n");
2596 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2599 /* Update mta_shadow */
2600 for (i = 0; i < mc_addr_count; i++) {
2601 DEBUGOUT(" Adding the multicast addresses:\n");
2602 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2606 for (i = 0; i < hw->mac.mcft_size; i++)
2607 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2608 hw->mac.mta_shadow[i]);
2610 if (hw->addr_ctrl.mta_in_use > 0)
2611 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2612 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2614 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2615 return IXGBE_SUCCESS;
2619 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2620 * @hw: pointer to hardware structure
2622 * Enables multicast address in RAR and the use of the multicast hash table.
2624 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2626 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2628 DEBUGFUNC("ixgbe_enable_mc_generic");
2630 if (a->mta_in_use > 0)
2631 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2632 hw->mac.mc_filter_type);
2634 return IXGBE_SUCCESS;
2638 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2639 * @hw: pointer to hardware structure
2641 * Disables multicast address in RAR and the use of the multicast hash table.
2643 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2645 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2647 DEBUGFUNC("ixgbe_disable_mc_generic");
2649 if (a->mta_in_use > 0)
2650 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2652 return IXGBE_SUCCESS;
2656 * ixgbe_fc_enable_generic - Enable flow control
2657 * @hw: pointer to hardware structure
2659 * Enable flow control according to the current settings.
2661 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2663 s32 ret_val = IXGBE_SUCCESS;
2664 u32 mflcn_reg, fccfg_reg;
2669 DEBUGFUNC("ixgbe_fc_enable_generic");
2671 /* Validate the water mark configuration */
2672 if (!hw->fc.pause_time) {
2673 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2677 /* Low water mark of zero causes XOFF floods */
2678 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2679 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2680 hw->fc.high_water[i]) {
2681 if (!hw->fc.low_water[i] ||
2682 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2683 DEBUGOUT("Invalid water mark configuration\n");
2684 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2690 /* Negotiate the fc mode to use */
2691 ixgbe_fc_autoneg(hw);
2693 /* Disable any previous flow control settings */
2694 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2695 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2697 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2698 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2701 * The possible values of fc.current_mode are:
2702 * 0: Flow control is completely disabled
2703 * 1: Rx flow control is enabled (we can receive pause frames,
2704 * but not send pause frames).
2705 * 2: Tx flow control is enabled (we can send pause frames but
2706 * we do not support receiving pause frames).
2707 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2710 switch (hw->fc.current_mode) {
2713 * Flow control is disabled by software override or autoneg.
2714 * The code below will actually disable it in the HW.
2717 case ixgbe_fc_rx_pause:
2719 * Rx Flow control is enabled and Tx Flow control is
2720 * disabled by software override. Since there really
2721 * isn't a way to advertise that we are capable of RX
2722 * Pause ONLY, we will advertise that we support both
2723 * symmetric and asymmetric Rx PAUSE. Later, we will
2724 * disable the adapter's ability to send PAUSE frames.
2726 mflcn_reg |= IXGBE_MFLCN_RFCE;
2728 case ixgbe_fc_tx_pause:
2730 * Tx Flow control is enabled, and Rx Flow control is
2731 * disabled by software override.
2733 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2736 /* Flow control (both Rx and Tx) is enabled by SW override. */
2737 mflcn_reg |= IXGBE_MFLCN_RFCE;
2738 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2741 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2742 "Flow control param set incorrectly\n");
2743 ret_val = IXGBE_ERR_CONFIG;
2748 /* Set 802.3x based flow control settings. */
2749 mflcn_reg |= IXGBE_MFLCN_DPF;
2750 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2751 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2754 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2755 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2756 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2757 hw->fc.high_water[i]) {
2758 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2759 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2760 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2762 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2764 * In order to prevent Tx hangs when the internal Tx
2765 * switch is enabled we must set the high water mark
2766 * to the maximum FCRTH value. This allows the Tx
2767 * switch to function even under heavy Rx workloads.
2769 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2772 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2775 /* Configure pause time (2 TCs per register) */
2776 reg = hw->fc.pause_time * 0x00010001;
2777 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2778 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2780 /* Configure flow control refresh threshold value */
2781 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2788 * ixgbe_negotiate_fc - Negotiate flow control
2789 * @hw: pointer to hardware structure
2790 * @adv_reg: flow control advertised settings
2791 * @lp_reg: link partner's flow control settings
2792 * @adv_sym: symmetric pause bit in advertisement
2793 * @adv_asm: asymmetric pause bit in advertisement
2794 * @lp_sym: symmetric pause bit in link partner advertisement
2795 * @lp_asm: asymmetric pause bit in link partner advertisement
2797 * Find the intersection between advertised settings and link partner's
2798 * advertised settings
2800 STATIC s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2801 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2803 if ((!(adv_reg)) || (!(lp_reg))) {
2804 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2805 "Local or link partner's advertised flow control "
2806 "settings are NULL. Local: %x, link partner: %x\n",
2808 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2811 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2813 * Now we need to check if the user selected Rx ONLY
2814 * of pause frames. In this case, we had to advertise
2815 * FULL flow control because we could not advertise RX
2816 * ONLY. Hence, we must now check to see if we need to
2817 * turn OFF the TRANSMISSION of PAUSE frames.
2819 if (hw->fc.requested_mode == ixgbe_fc_full) {
2820 hw->fc.current_mode = ixgbe_fc_full;
2821 DEBUGOUT("Flow Control = FULL.\n");
2823 hw->fc.current_mode = ixgbe_fc_rx_pause;
2824 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2826 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2827 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2828 hw->fc.current_mode = ixgbe_fc_tx_pause;
2829 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2830 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2831 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2832 hw->fc.current_mode = ixgbe_fc_rx_pause;
2833 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2835 hw->fc.current_mode = ixgbe_fc_none;
2836 DEBUGOUT("Flow Control = NONE.\n");
2838 return IXGBE_SUCCESS;
2842 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2843 * @hw: pointer to hardware structure
2845 * Enable flow control according on 1 gig fiber.
2847 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2849 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2850 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2853 * On multispeed fiber at 1g, bail out if
2854 * - link is up but AN did not complete, or if
2855 * - link is up and AN completed but timed out
2858 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2859 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2860 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2861 ERROR_REPORT1(IXGBE_ERROR_POLLING,
2862 "Auto-Negotiation did not complete or timed out");
2866 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2867 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2869 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2870 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2871 IXGBE_PCS1GANA_ASM_PAUSE,
2872 IXGBE_PCS1GANA_SYM_PAUSE,
2873 IXGBE_PCS1GANA_ASM_PAUSE);
2880 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2881 * @hw: pointer to hardware structure
2883 * Enable flow control according to IEEE clause 37.
2885 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2887 u32 links2, anlp1_reg, autoc_reg, links;
2888 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2891 * On backplane, bail out if
2892 * - backplane autoneg was not completed, or if
2893 * - we are 82599 and link partner is not AN enabled
2895 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2896 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2897 ERROR_REPORT1(IXGBE_ERROR_POLLING,
2898 "Auto-Negotiation did not complete");
2902 if (hw->mac.type == ixgbe_mac_82599EB) {
2903 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2904 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2905 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2906 "Link partner is not AN enabled");
2911 * Read the 10g AN autoc and LP ability registers and resolve
2912 * local flow control settings accordingly
2914 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2915 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2917 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2918 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2919 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2926 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2927 * @hw: pointer to hardware structure
2929 * Enable flow control according to IEEE clause 37.
2931 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2933 u16 technology_ability_reg = 0;
2934 u16 lp_technology_ability_reg = 0;
2936 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2937 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2938 &technology_ability_reg);
2939 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2940 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2941 &lp_technology_ability_reg);
2943 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2944 (u32)lp_technology_ability_reg,
2945 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2946 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2950 * ixgbe_fc_autoneg - Configure flow control
2951 * @hw: pointer to hardware structure
2953 * Compares our advertised flow control capabilities to those advertised by
2954 * our link partner, and determines the proper flow control mode to use.
2956 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2958 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2959 ixgbe_link_speed speed;
2962 DEBUGFUNC("ixgbe_fc_autoneg");
2965 * AN should have completed when the cable was plugged in.
2966 * Look for reasons to bail out. Bail out if:
2967 * - FC autoneg is disabled, or if
2970 if (hw->fc.disable_fc_autoneg) {
2971 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2972 "Flow control autoneg is disabled");
2976 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2978 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
2982 switch (hw->phy.media_type) {
2983 /* Autoneg flow control on fiber adapters */
2984 case ixgbe_media_type_fiber:
2985 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2986 ret_val = ixgbe_fc_autoneg_fiber(hw);
2989 /* Autoneg flow control on backplane adapters */
2990 case ixgbe_media_type_backplane:
2991 ret_val = ixgbe_fc_autoneg_backplane(hw);
2994 /* Autoneg flow control on copper adapters */
2995 case ixgbe_media_type_copper:
2996 if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)
2997 ret_val = ixgbe_fc_autoneg_copper(hw);
3005 if (ret_val == IXGBE_SUCCESS) {
3006 hw->fc.fc_was_autonegged = true;
3008 hw->fc.fc_was_autonegged = false;
3009 hw->fc.current_mode = hw->fc.requested_mode;
3014 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3015 * @hw: pointer to hardware structure
3017 * System-wide timeout range is encoded in PCIe Device Control2 register.
3019 * Add 10% to specified maximum and return the number of times to poll for
3020 * completion timeout, in units of 100 microsec. Never return less than
3021 * 800 = 80 millisec.
3023 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3028 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3029 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3032 case IXGBE_PCIDEVCTRL2_65_130ms:
3033 pollcnt = 1300; /* 130 millisec */
3035 case IXGBE_PCIDEVCTRL2_260_520ms:
3036 pollcnt = 5200; /* 520 millisec */
3038 case IXGBE_PCIDEVCTRL2_1_2s:
3039 pollcnt = 20000; /* 2 sec */
3041 case IXGBE_PCIDEVCTRL2_4_8s:
3042 pollcnt = 80000; /* 8 sec */
3044 case IXGBE_PCIDEVCTRL2_17_34s:
3045 pollcnt = 34000; /* 34 sec */
3047 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3048 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3049 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3050 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3052 pollcnt = 800; /* 80 millisec minimum */
3056 /* add 10% to spec maximum */
3057 return (pollcnt * 11) / 10;
3061 * ixgbe_disable_pcie_master - Disable PCI-express master access
3062 * @hw: pointer to hardware structure
3064 * Disables PCI-Express master access and verifies there are no pending
3065 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3066 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3067 * is returned signifying master requests disabled.
3069 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3071 s32 status = IXGBE_SUCCESS;
3075 DEBUGFUNC("ixgbe_disable_pcie_master");
3077 /* Always set this bit to ensure any future transactions are blocked */
3078 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3080 /* Exit if master requests are blocked */
3081 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3082 IXGBE_REMOVED(hw->hw_addr))
3085 /* Poll for master request bit to clear */
3086 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3088 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3093 * Two consecutive resets are required via CTRL.RST per datasheet
3094 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3095 * of this need. The first reset prevents new master requests from
3096 * being issued by our device. We then must wait 1usec or more for any
3097 * remaining completions from the PCIe bus to trickle in, and then reset
3098 * again to clear out any effects they may have had on our device.
3100 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3101 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3104 * Before proceeding, make sure that the PCIe block does not have
3105 * transactions pending.
3107 poll = ixgbe_pcie_timeout_poll(hw);
3108 for (i = 0; i < poll; i++) {
3110 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3111 if (IXGBE_REMOVED(hw->hw_addr))
3113 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3117 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3118 "PCIe transaction pending bit also did not clear.\n");
3119 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3126 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3127 * @hw: pointer to hardware structure
3128 * @mask: Mask to specify which semaphore to acquire
3130 * Acquires the SWFW semaphore through the GSSR register for the specified
3131 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3133 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
3137 u32 fwmask = mask << 5;
3140 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3144 * SW EEPROM semaphore bit is used for access to all
3145 * SW_FW_SYNC/GSSR bits (not just EEPROM)
3147 if (ixgbe_get_eeprom_semaphore(hw))
3148 return IXGBE_ERR_SWFW_SYNC;
3150 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3151 if (!(gssr & (fwmask | swmask)))
3155 * Firmware currently using resource (fwmask) or other software
3156 * thread currently using resource (swmask)
3158 ixgbe_release_eeprom_semaphore(hw);
3164 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3165 return IXGBE_ERR_SWFW_SYNC;
3169 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3171 ixgbe_release_eeprom_semaphore(hw);
3172 return IXGBE_SUCCESS;
3176 * ixgbe_release_swfw_sync - Release SWFW semaphore
3177 * @hw: pointer to hardware structure
3178 * @mask: Mask to specify which semaphore to release
3180 * Releases the SWFW semaphore through the GSSR register for the specified
3181 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3183 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
3188 DEBUGFUNC("ixgbe_release_swfw_sync");
3190 ixgbe_get_eeprom_semaphore(hw);
3192 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3194 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3196 ixgbe_release_eeprom_semaphore(hw);
3200 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3201 * @hw: pointer to hardware structure
3203 * Stops the receive data path and waits for the HW to internally empty
3204 * the Rx security block
3206 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3208 #define IXGBE_MAX_SECRX_POLL 40
3213 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3216 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3217 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3218 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3219 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3220 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3221 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3224 /* Use interrupt-safe sleep just in case */
3228 /* For informational purposes only */
3229 if (i >= IXGBE_MAX_SECRX_POLL)
3230 DEBUGOUT("Rx unit being enabled before security "
3231 "path fully disabled. Continuing with init.\n");
3233 return IXGBE_SUCCESS;
3237 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3238 * @hw: pointer to hardware structure
3240 * Enables the receive data path.
3242 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3246 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3248 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3249 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3250 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3251 IXGBE_WRITE_FLUSH(hw);
3253 return IXGBE_SUCCESS;
3257 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3258 * @hw: pointer to hardware structure
3259 * @regval: register value to write to RXCTRL
3261 * Enables the Rx DMA unit
3263 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3265 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3267 if (regval & IXGBE_RXCTRL_RXEN)
3268 ixgbe_enable_rx(hw);
3270 ixgbe_disable_rx(hw);
3272 return IXGBE_SUCCESS;
3276 * ixgbe_blink_led_start_generic - Blink LED based on index.
3277 * @hw: pointer to hardware structure
3278 * @index: led number to blink
3280 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3282 ixgbe_link_speed speed = 0;
3284 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3285 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3286 s32 ret_val = IXGBE_SUCCESS;
3288 DEBUGFUNC("ixgbe_blink_led_start_generic");
3291 * Link must be up to auto-blink the LEDs;
3292 * Force it if link is down.
3294 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3297 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
3300 bool got_lock = false;
3301 if ((hw->mac.type == ixgbe_mac_82599EB) &&
3302 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3303 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
3304 IXGBE_GSSR_MAC_CSR_SM);
3305 if (ret_val != IXGBE_SUCCESS) {
3306 ret_val = IXGBE_ERR_SWFW_SYNC;
3312 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3313 autoc_reg |= IXGBE_AUTOC_FLU;
3314 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3315 IXGBE_WRITE_FLUSH(hw);
3318 hw->mac.ops.release_swfw_sync(hw,
3319 IXGBE_GSSR_MAC_CSR_SM);
3323 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3324 led_reg |= IXGBE_LED_BLINK(index);
3325 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3326 IXGBE_WRITE_FLUSH(hw);
3333 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3334 * @hw: pointer to hardware structure
3335 * @index: led number to stop blinking
3337 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3339 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3340 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3341 s32 ret_val = IXGBE_SUCCESS;
3342 bool got_lock = false;
3344 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3345 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
3348 if ((hw->mac.type == ixgbe_mac_82599EB) &&
3349 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3350 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
3351 IXGBE_GSSR_MAC_CSR_SM);
3352 if (ret_val != IXGBE_SUCCESS) {
3353 ret_val = IXGBE_ERR_SWFW_SYNC;
3360 autoc_reg &= ~IXGBE_AUTOC_FLU;
3361 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3362 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3364 if (hw->mac.type == ixgbe_mac_82599EB)
3365 ixgbe_reset_pipeline_82599(hw);
3368 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3370 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3371 led_reg &= ~IXGBE_LED_BLINK(index);
3372 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3373 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3374 IXGBE_WRITE_FLUSH(hw);
3381 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3382 * @hw: pointer to hardware structure
3383 * @san_mac_offset: SAN MAC address offset
3385 * This function will read the EEPROM location for the SAN MAC address
3386 * pointer, and returns the value at that location. This is used in both
3387 * get and set mac_addr routines.
3389 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3390 u16 *san_mac_offset)
3394 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3397 * First read the EEPROM pointer to see if the MAC addresses are
3400 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3403 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3404 "eeprom at offset %d failed",
3405 IXGBE_SAN_MAC_ADDR_PTR);
3412 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3413 * @hw: pointer to hardware structure
3414 * @san_mac_addr: SAN MAC address
3416 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3417 * per-port, so set_lan_id() must be called before reading the addresses.
3418 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3419 * upon for non-SFP connections, so we must call it here.
3421 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3423 u16 san_mac_data, san_mac_offset;
3427 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3430 * First read the EEPROM pointer to see if the MAC addresses are
3431 * available. If they're not, no point in calling set_lan_id() here.
3433 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3434 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3435 goto san_mac_addr_out;
3437 /* make sure we know which port we need to program */
3438 hw->mac.ops.set_lan_id(hw);
3439 /* apply the port offset to the address offset */
3440 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3441 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3442 for (i = 0; i < 3; i++) {
3443 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3446 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3447 "eeprom read at offset %d failed",
3449 goto san_mac_addr_out;
3451 san_mac_addr[i * 2] = (u8)(san_mac_data);
3452 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3455 return IXGBE_SUCCESS;
3459 * No addresses available in this EEPROM. It's not an
3460 * error though, so just wipe the local address and return.
3462 for (i = 0; i < 6; i++)
3463 san_mac_addr[i] = 0xFF;
3464 return IXGBE_SUCCESS;
3468 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3469 * @hw: pointer to hardware structure
3470 * @san_mac_addr: SAN MAC address
3472 * Write a SAN MAC address to the EEPROM.
3474 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3477 u16 san_mac_data, san_mac_offset;
3480 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3482 /* Look for SAN mac address pointer. If not defined, return */
3483 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3484 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3485 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3487 /* Make sure we know which port we need to write */
3488 hw->mac.ops.set_lan_id(hw);
3489 /* Apply the port offset to the address offset */
3490 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3491 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3493 for (i = 0; i < 3; i++) {
3494 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3495 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3496 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3500 return IXGBE_SUCCESS;
3504 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3505 * @hw: pointer to hardware structure
3507 * Read PCIe configuration space, and get the MSI-X vector count from
3508 * the capabilities table.
3510 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3516 switch (hw->mac.type) {
3517 case ixgbe_mac_82598EB:
3518 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3519 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3521 case ixgbe_mac_82599EB:
3522 case ixgbe_mac_X540:
3523 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3524 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3530 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3531 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3532 if (IXGBE_REMOVED(hw->hw_addr))
3534 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3536 /* MSI-X count is zero-based in HW */
3539 if (msix_count > max_msix_count)
3540 msix_count = max_msix_count;
3546 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3547 * @hw: pointer to hardware structure
3548 * @addr: Address to put into receive address register
3549 * @vmdq: VMDq pool to assign
3551 * Puts an ethernet address into a receive address register, or
3552 * finds the rar that it is aleady in; adds to the pool list
3554 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3556 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3557 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3559 u32 rar_low, rar_high;
3560 u32 addr_low, addr_high;
3562 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3564 /* swap bytes for HW little endian */
3565 addr_low = addr[0] | (addr[1] << 8)
3568 addr_high = addr[4] | (addr[5] << 8);
3571 * Either find the mac_id in rar or find the first empty space.
3572 * rar_highwater points to just after the highest currently used
3573 * rar in order to shorten the search. It grows when we add a new
3576 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3577 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3579 if (((IXGBE_RAH_AV & rar_high) == 0)
3580 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3581 first_empty_rar = rar;
3582 } else if ((rar_high & 0xFFFF) == addr_high) {
3583 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3584 if (rar_low == addr_low)
3585 break; /* found it already in the rars */
3589 if (rar < hw->mac.rar_highwater) {
3590 /* already there so just add to the pool bits */
3591 ixgbe_set_vmdq(hw, rar, vmdq);
3592 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3593 /* stick it into first empty RAR slot we found */
3594 rar = first_empty_rar;
3595 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3596 } else if (rar == hw->mac.rar_highwater) {
3597 /* add it to the top of the list and inc the highwater mark */
3598 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3599 hw->mac.rar_highwater++;
3600 } else if (rar >= hw->mac.num_rar_entries) {
3601 return IXGBE_ERR_INVALID_MAC_ADDR;
3605 * If we found rar[0], make sure the default pool bit (we use pool 0)
3606 * remains cleared to be sure default pool packets will get delivered
3609 ixgbe_clear_vmdq(hw, rar, 0);
3615 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3616 * @hw: pointer to hardware struct
3617 * @rar: receive address register index to disassociate
3618 * @vmdq: VMDq pool index to remove from the rar
3620 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3622 u32 mpsar_lo, mpsar_hi;
3623 u32 rar_entries = hw->mac.num_rar_entries;
3625 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3627 /* Make sure we are using a valid rar index range */
3628 if (rar >= rar_entries) {
3629 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3630 "RAR index %d is out of range.\n", rar);
3631 return IXGBE_ERR_INVALID_ARGUMENT;
3634 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3635 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3637 if (IXGBE_REMOVED(hw->hw_addr))
3640 if (!mpsar_lo && !mpsar_hi)
3643 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3645 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3649 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3652 } else if (vmdq < 32) {
3653 mpsar_lo &= ~(1 << vmdq);
3654 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3656 mpsar_hi &= ~(1 << (vmdq - 32));
3657 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3660 /* was that the last pool using this rar? */
3661 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3662 hw->mac.ops.clear_rar(hw, rar);
3664 return IXGBE_SUCCESS;
3668 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3669 * @hw: pointer to hardware struct
3670 * @rar: receive address register index to associate with a VMDq index
3671 * @vmdq: VMDq pool index
3673 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3676 u32 rar_entries = hw->mac.num_rar_entries;
3678 DEBUGFUNC("ixgbe_set_vmdq_generic");
3680 /* Make sure we are using a valid rar index range */
3681 if (rar >= rar_entries) {
3682 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3683 "RAR index %d is out of range.\n", rar);
3684 return IXGBE_ERR_INVALID_ARGUMENT;
3688 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3690 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3692 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3693 mpsar |= 1 << (vmdq - 32);
3694 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3696 return IXGBE_SUCCESS;
3700 * This function should only be involved in the IOV mode.
3701 * In IOV mode, Default pool is next pool after the number of
3702 * VFs advertized and not 0.
3703 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3705 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3706 * @hw: pointer to hardware struct
3707 * @vmdq: VMDq pool index
3709 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3711 u32 rar = hw->mac.san_mac_rar_index;
3713 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3716 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3717 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3719 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3720 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3723 return IXGBE_SUCCESS;
3727 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3728 * @hw: pointer to hardware structure
3730 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3734 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3735 DEBUGOUT(" Clearing UTA\n");
3737 for (i = 0; i < 128; i++)
3738 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3740 return IXGBE_SUCCESS;
3744 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3745 * @hw: pointer to hardware structure
3746 * @vlan: VLAN id to write to VLAN filter
3748 * return the VLVF index where this VLAN id should be placed
3751 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3754 u32 first_empty_slot = 0;
3757 /* short cut the special case */
3762 * Search for the vlan id in the VLVF entries. Save off the first empty
3763 * slot found along the way
3765 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3766 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3767 if (!bits && !(first_empty_slot))
3768 first_empty_slot = regindex;
3769 else if ((bits & 0x0FFF) == vlan)
3774 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3775 * in the VLVF. Else use the first empty VLVF register for this
3778 if (regindex >= IXGBE_VLVF_ENTRIES) {
3779 if (first_empty_slot)
3780 regindex = first_empty_slot;
3782 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
3783 "No space in VLVF.\n");
3784 regindex = IXGBE_ERR_NO_SPACE;
3792 * ixgbe_set_vfta_generic - Set VLAN filter table
3793 * @hw: pointer to hardware structure
3794 * @vlan: VLAN id to write to VLAN filter
3795 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3796 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3798 * Turn on/off specified VLAN in the VLAN filter table.
3800 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3807 s32 ret_val = IXGBE_SUCCESS;
3808 bool vfta_changed = false;
3810 DEBUGFUNC("ixgbe_set_vfta_generic");
3813 return IXGBE_ERR_PARAM;
3816 * this is a 2 part operation - first the VFTA, then the
3817 * VLVF and VLVFB if VT Mode is set
3818 * We don't write the VFTA until we know the VLVF part succeeded.
3822 * The VFTA is a bitstring made up of 128 32-bit registers
3823 * that enable the particular VLAN id, much like the MTA:
3824 * bits[11-5]: which register
3825 * bits[4-0]: which bit in the register
3827 regindex = (vlan >> 5) & 0x7F;
3828 bitindex = vlan & 0x1F;
3829 targetbit = (1 << bitindex);
3830 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3833 if (!(vfta & targetbit)) {
3835 vfta_changed = true;
3838 if ((vfta & targetbit)) {
3840 vfta_changed = true;
3845 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3847 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3849 if (ret_val != IXGBE_SUCCESS)
3853 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3855 return IXGBE_SUCCESS;
3859 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3860 * @hw: pointer to hardware structure
3861 * @vlan: VLAN id to write to VLAN filter
3862 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3863 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3864 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3867 * Turn on/off specified bit in VLVF table.
3869 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3870 bool vlan_on, bool *vfta_changed)
3874 DEBUGFUNC("ixgbe_set_vlvf_generic");
3877 return IXGBE_ERR_PARAM;
3879 /* If VT Mode is set
3881 * make sure the vlan is in VLVF
3882 * set the vind bit in the matching VLVFB
3884 * clear the pool bit and possibly the vind
3886 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3887 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3891 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3896 /* set the pool bit */
3898 bits = IXGBE_READ_REG(hw,
3899 IXGBE_VLVFB(vlvf_index * 2));
3900 bits |= (1 << vind);
3902 IXGBE_VLVFB(vlvf_index * 2),
3905 bits = IXGBE_READ_REG(hw,
3906 IXGBE_VLVFB((vlvf_index * 2) + 1));
3907 bits |= (1 << (vind - 32));
3909 IXGBE_VLVFB((vlvf_index * 2) + 1),
3913 /* clear the pool bit */
3915 bits = IXGBE_READ_REG(hw,
3916 IXGBE_VLVFB(vlvf_index * 2));
3917 bits &= ~(1 << vind);
3919 IXGBE_VLVFB(vlvf_index * 2),
3921 bits |= IXGBE_READ_REG(hw,
3922 IXGBE_VLVFB((vlvf_index * 2) + 1));
3924 bits = IXGBE_READ_REG(hw,
3925 IXGBE_VLVFB((vlvf_index * 2) + 1));
3926 bits &= ~(1 << (vind - 32));
3928 IXGBE_VLVFB((vlvf_index * 2) + 1),
3930 bits |= IXGBE_READ_REG(hw,
3931 IXGBE_VLVFB(vlvf_index * 2));
3936 * If there are still bits set in the VLVFB registers
3937 * for the VLAN ID indicated we need to see if the
3938 * caller is requesting that we clear the VFTA entry bit.
3939 * If the caller has requested that we clear the VFTA
3940 * entry bit but there are still pools/VFs using this VLAN
3941 * ID entry then ignore the request. We're not worried
3942 * about the case where we're turning the VFTA VLAN ID
3943 * entry bit on, only when requested to turn it off as
3944 * there may be multiple pools and/or VFs using the
3945 * VLAN ID entry. In that case we cannot clear the
3946 * VFTA bit until all pools/VFs using that VLAN ID have also
3947 * been cleared. This will be indicated by "bits" being
3951 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3952 (IXGBE_VLVF_VIEN | vlan));
3953 if ((!vlan_on) && (vfta_changed != NULL)) {
3954 /* someone wants to clear the vfta entry
3955 * but some pools/VFs are still using it.
3957 *vfta_changed = false;
3960 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3963 return IXGBE_SUCCESS;
3967 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3968 * @hw: pointer to hardware structure
3970 * Clears the VLAN filer table, and the VMDq index associated with the filter
3972 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3976 DEBUGFUNC("ixgbe_clear_vfta_generic");
3978 for (offset = 0; offset < hw->mac.vft_size; offset++)
3979 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3981 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3982 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3983 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
3984 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
3987 return IXGBE_SUCCESS;
3991 * ixgbe_check_mac_link_generic - Determine link and speed status
3992 * @hw: pointer to hardware structure
3993 * @speed: pointer to link speed
3994 * @link_up: true when link is up
3995 * @link_up_wait_to_complete: bool used to wait for link up or not
3997 * Reads the links register to determine if link is up and the current speed
3999 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4000 bool *link_up, bool link_up_wait_to_complete)
4002 u32 links_reg, links_orig;
4005 DEBUGFUNC("ixgbe_check_mac_link_generic");
4007 /* clear the old state */
4008 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4010 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4012 if (links_orig != links_reg) {
4013 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4014 links_orig, links_reg);
4017 if (link_up_wait_to_complete) {
4018 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
4019 if (links_reg & IXGBE_LINKS_UP) {
4026 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4029 if (links_reg & IXGBE_LINKS_UP)
4035 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4036 IXGBE_LINKS_SPEED_10G_82599)
4037 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4038 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4039 IXGBE_LINKS_SPEED_1G_82599)
4040 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4041 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4042 IXGBE_LINKS_SPEED_100_82599)
4043 *speed = IXGBE_LINK_SPEED_100_FULL;
4045 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4047 return IXGBE_SUCCESS;
4051 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4053 * @hw: pointer to hardware structure
4054 * @wwnn_prefix: the alternative WWNN prefix
4055 * @wwpn_prefix: the alternative WWPN prefix
4057 * This function will read the EEPROM from the alternative SAN MAC address
4058 * block to check the support for the alternative WWNN/WWPN prefix support.
4060 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4064 u16 alt_san_mac_blk_offset;
4066 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4068 /* clear output first */
4069 *wwnn_prefix = 0xFFFF;
4070 *wwpn_prefix = 0xFFFF;
4072 /* check if alternative SAN MAC is supported */
4073 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4074 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4075 goto wwn_prefix_err;
4077 if ((alt_san_mac_blk_offset == 0) ||
4078 (alt_san_mac_blk_offset == 0xFFFF))
4079 goto wwn_prefix_out;
4081 /* check capability in alternative san mac address block */
4082 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4083 if (hw->eeprom.ops.read(hw, offset, &caps))
4084 goto wwn_prefix_err;
4085 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4086 goto wwn_prefix_out;
4088 /* get the corresponding prefix for WWNN/WWPN */
4089 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4090 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4091 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4092 "eeprom read at offset %d failed", offset);
4095 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4096 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4097 goto wwn_prefix_err;
4100 return IXGBE_SUCCESS;
4103 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4104 "eeprom read at offset %d failed", offset);
4105 return IXGBE_SUCCESS;
4109 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4110 * @hw: pointer to hardware structure
4111 * @bs: the fcoe boot status
4113 * This function will read the FCOE boot status from the iSCSI FCOE block
4115 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4117 u16 offset, caps, flags;
4120 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4122 /* clear output first */
4123 *bs = ixgbe_fcoe_bootstatus_unavailable;
4125 /* check if FCOE IBA block is present */
4126 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4127 status = hw->eeprom.ops.read(hw, offset, &caps);
4128 if (status != IXGBE_SUCCESS)
4131 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4134 /* check if iSCSI FCOE block is populated */
4135 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4136 if (status != IXGBE_SUCCESS)
4139 if ((offset == 0) || (offset == 0xFFFF))
4142 /* read fcoe flags in iSCSI FCOE block */
4143 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4144 status = hw->eeprom.ops.read(hw, offset, &flags);
4145 if (status != IXGBE_SUCCESS)
4148 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4149 *bs = ixgbe_fcoe_bootstatus_enabled;
4151 *bs = ixgbe_fcoe_bootstatus_disabled;
4158 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4159 * @hw: pointer to hardware structure
4160 * @enable: enable or disable switch for anti-spoofing
4161 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
4164 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
4167 int pf_target_reg = pf >> 3;
4168 int pf_target_shift = pf % 8;
4171 if (hw->mac.type == ixgbe_mac_82598EB)
4175 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
4178 * PFVFSPOOF register array is size 8 with 8 bits assigned to
4179 * MAC anti-spoof enables in each register array element.
4181 for (j = 0; j < pf_target_reg; j++)
4182 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4185 * The PF should be allowed to spoof so that it can support
4186 * emulation mode NICs. Do not set the bits assigned to the PF
4188 pfvfspoof &= (1 << pf_target_shift) - 1;
4189 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4192 * Remaining pools belong to the PF so they do not need to have
4193 * anti-spoofing enabled.
4195 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
4196 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
4200 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4201 * @hw: pointer to hardware structure
4202 * @enable: enable or disable switch for VLAN anti-spoofing
4203 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4206 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4208 int vf_target_reg = vf >> 3;
4209 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4212 if (hw->mac.type == ixgbe_mac_82598EB)
4215 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4217 pfvfspoof |= (1 << vf_target_shift);
4219 pfvfspoof &= ~(1 << vf_target_shift);
4220 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4224 * ixgbe_get_device_caps_generic - Get additional device capabilities
4225 * @hw: pointer to hardware structure
4226 * @device_caps: the EEPROM word with the extra device capabilities
4228 * This function will read the EEPROM location for the device capabilities,
4229 * and return the word through device_caps.
4231 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4233 DEBUGFUNC("ixgbe_get_device_caps_generic");
4235 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4237 return IXGBE_SUCCESS;
4241 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4242 * @hw: pointer to hardware structure
4245 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4250 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4252 /* Enable relaxed ordering */
4253 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4254 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4255 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4256 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4259 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4260 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4261 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4262 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4263 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4269 * ixgbe_calculate_checksum - Calculate checksum for buffer
4270 * @buffer: pointer to EEPROM
4271 * @length: size of EEPROM to calculate a checksum for
4272 * Calculates the checksum for some buffer on a specified length. The
4273 * checksum calculated is returned.
4275 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4280 DEBUGFUNC("ixgbe_calculate_checksum");
4285 for (i = 0; i < length; i++)
4288 return (u8) (0 - sum);
4292 * ixgbe_host_interface_command - Issue command to manageability block
4293 * @hw: pointer to the HW structure
4294 * @buffer: contains the command to write and where the return status will
4296 * @length: length of buffer, must be multiple of 4 bytes
4298 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4299 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
4301 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4305 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4306 u8 buf_len, dword_len;
4308 s32 ret_val = IXGBE_SUCCESS;
4310 DEBUGFUNC("ixgbe_host_interface_command");
4312 if (length == 0 || length & 0x3 ||
4313 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4314 DEBUGOUT("Buffer length failure.\n");
4315 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4319 /* Check that the host interface is enabled. */
4320 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4321 if ((hicr & IXGBE_HICR_EN) == 0) {
4322 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4323 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4327 /* Calculate length in DWORDs */
4328 dword_len = length >> 2;
4331 * The device driver writes the relevant command block
4332 * into the ram area.
4334 for (i = 0; i < dword_len; i++)
4335 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4336 i, IXGBE_CPU_TO_LE32(buffer[i]));
4338 /* Setting this bit tells the ARC that a new command is pending. */
4339 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4341 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
4342 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4343 if (!(hicr & IXGBE_HICR_C))
4348 /* Check command successful completion. */
4349 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
4350 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
4351 DEBUGOUT("Command has failed with no status valid.\n");
4352 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4356 /* Calculate length in DWORDs */
4357 dword_len = hdr_size >> 2;
4359 /* first pull in the header so we know the buffer length */
4360 for (bi = 0; bi < dword_len; bi++) {
4361 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4362 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4365 /* If there is any thing in data position pull it in */
4366 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4370 if (length < (buf_len + hdr_size)) {
4371 DEBUGOUT("Buffer not large enough for reply message.\n");
4372 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4376 /* Calculate length in DWORDs, add 3 for odd lengths */
4377 dword_len = (buf_len + 3) >> 2;
4379 /* Pull in the rest of the buffer (bi is where we left off)*/
4380 for (; bi <= dword_len; bi++) {
4381 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4382 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4390 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4391 * @hw: pointer to the HW structure
4392 * @maj: driver version major number
4393 * @min: driver version minor number
4394 * @build: driver version build number
4395 * @sub: driver version sub build number
4397 * Sends driver version number to firmware through the manageability
4398 * block. On success return IXGBE_SUCCESS
4399 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4400 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4402 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4405 struct ixgbe_hic_drv_info fw_cmd;
4407 s32 ret_val = IXGBE_SUCCESS;
4409 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4411 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
4413 ret_val = IXGBE_ERR_SWFW_SYNC;
4417 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4418 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4419 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4420 fw_cmd.port_num = (u8)hw->bus.func;
4421 fw_cmd.ver_maj = maj;
4422 fw_cmd.ver_min = min;
4423 fw_cmd.ver_build = build;
4424 fw_cmd.ver_sub = sub;
4425 fw_cmd.hdr.checksum = 0;
4426 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4427 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4431 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4432 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4434 if (ret_val != IXGBE_SUCCESS)
4437 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4438 FW_CEM_RESP_STATUS_SUCCESS)
4439 ret_val = IXGBE_SUCCESS;
4441 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4446 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4452 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4453 * @hw: pointer to hardware structure
4454 * @num_pb: number of packet buffers to allocate
4455 * @headroom: reserve n KB of headroom
4456 * @strategy: packet buffer allocation strategy
4458 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4461 u32 pbsize = hw->mac.rx_pb_size;
4463 u32 rxpktsize, txpktsize, txpbthresh;
4465 /* Reserve headroom */
4471 /* Divide remaining packet buffer space amongst the number of packet
4472 * buffers requested using supplied strategy.
4475 case PBA_STRATEGY_WEIGHTED:
4476 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4477 * buffer with 5/8 of the packet buffer space.
4479 rxpktsize = (pbsize * 5) / (num_pb * 4);
4480 pbsize -= rxpktsize * (num_pb / 2);
4481 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4482 for (; i < (num_pb / 2); i++)
4483 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4484 /* Fall through to configure remaining packet buffers */
4485 case PBA_STRATEGY_EQUAL:
4486 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4487 for (; i < num_pb; i++)
4488 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4494 /* Only support an equally distributed Tx packet buffer strategy. */
4495 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4496 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4497 for (i = 0; i < num_pb; i++) {
4498 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4499 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4502 /* Clear unused TCs, if any, to zero buffer size*/
4503 for (; i < IXGBE_MAX_PB; i++) {
4504 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4505 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4506 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4511 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4512 * @hw: pointer to the hardware structure
4514 * The 82599 and x540 MACs can experience issues if TX work is still pending
4515 * when a reset occurs. This function prevents this by flushing the PCIe
4516 * buffers on the system.
4518 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4520 u32 gcr_ext, hlreg0;
4523 * If double reset is not requested then all transactions should
4524 * already be clear and as such there is no work to do
4526 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4530 * Set loopback enable to prevent any transmits from being sent
4531 * should the link come up. This assumes that the RXCTRL.RXEN bit
4532 * has already been cleared.
4534 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4535 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4537 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4538 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4539 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4540 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4542 /* Flush all writes and allow 20usec for all transactions to clear */
4543 IXGBE_WRITE_FLUSH(hw);
4546 /* restore previous register values */
4547 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4548 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4553 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4554 * @hw: pointer to hardware structure
4555 * @map: pointer to u8 arr for returning map
4557 * Read the rtrup2tc HW register and resolve its content into map
4559 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4563 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4564 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4565 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4566 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4570 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4575 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4576 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4577 if (hw->mac.type != ixgbe_mac_82598EB) {
4578 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4579 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4580 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4581 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4582 hw->mac.set_lben = true;
4584 hw->mac.set_lben = false;
4587 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4588 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4592 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4597 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4598 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4600 if (hw->mac.type != ixgbe_mac_82598EB) {
4601 if (hw->mac.set_lben) {
4602 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4603 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4604 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4605 hw->mac.set_lben = false;