1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
39 #ident "$Id: ixgbe_common.c,v 1.382 2013/11/22 01:02:01 jtkirshe Exp $"
41 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
42 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
44 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
46 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
48 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
49 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
51 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
53 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
54 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
56 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
57 u16 words, u16 *data);
58 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
64 * ixgbe_init_ops_generic - Inits function ptrs
65 * @hw: pointer to the hardware structure
67 * Initialize the function pointers.
69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
72 struct ixgbe_mac_info *mac = &hw->mac;
73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
75 DEBUGFUNC("ixgbe_init_ops_generic");
78 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
80 if (eec & IXGBE_EEC_PRES) {
81 eeprom->ops.read = &ixgbe_read_eerd_generic;
82 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
84 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
85 eeprom->ops.read_buffer =
86 &ixgbe_read_eeprom_buffer_bit_bang_generic;
88 eeprom->ops.write = &ixgbe_write_eeprom_generic;
89 eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
90 eeprom->ops.validate_checksum =
91 &ixgbe_validate_eeprom_checksum_generic;
92 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
93 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
96 mac->ops.init_hw = &ixgbe_init_hw_generic;
97 mac->ops.reset_hw = NULL;
98 mac->ops.start_hw = &ixgbe_start_hw_generic;
99 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
100 mac->ops.get_media_type = NULL;
101 mac->ops.get_supported_physical_layer = NULL;
102 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
103 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
104 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
105 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
106 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
107 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
108 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
109 mac->ops.prot_autoc_read = &prot_autoc_read_generic;
110 mac->ops.prot_autoc_write = &prot_autoc_write_generic;
113 mac->ops.led_on = &ixgbe_led_on_generic;
114 mac->ops.led_off = &ixgbe_led_off_generic;
115 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
116 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
118 /* RAR, Multicast, VLAN */
119 mac->ops.set_rar = &ixgbe_set_rar_generic;
120 mac->ops.clear_rar = &ixgbe_clear_rar_generic;
121 mac->ops.insert_mac_addr = NULL;
122 mac->ops.set_vmdq = NULL;
123 mac->ops.clear_vmdq = NULL;
124 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
125 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
126 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
127 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
128 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
129 mac->ops.clear_vfta = NULL;
130 mac->ops.set_vfta = NULL;
131 mac->ops.set_vlvf = NULL;
132 mac->ops.init_uta_tables = NULL;
133 mac->ops.enable_rx = &ixgbe_enable_rx_generic;
134 mac->ops.disable_rx = &ixgbe_disable_rx_generic;
137 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
140 mac->ops.get_link_capabilities = NULL;
141 mac->ops.setup_link = NULL;
142 mac->ops.check_link = NULL;
143 mac->ops.dmac_config = NULL;
144 mac->ops.dmac_update_tcs = NULL;
145 mac->ops.dmac_config_tcs = NULL;
147 return IXGBE_SUCCESS;
151 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
153 * @hw: pointer to hardware structure
155 * This function returns true if the device supports flow control
156 * autonegotiation, and false if it does not.
159 bool ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
161 bool supported = false;
162 ixgbe_link_speed speed;
165 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
167 switch (hw->phy.media_type) {
168 case ixgbe_media_type_fiber:
169 hw->mac.ops.check_link(hw, &speed, &link_up, false);
170 /* if link is down, assume supported */
172 supported = speed == IXGBE_LINK_SPEED_1GB_FULL ?
177 case ixgbe_media_type_backplane:
180 case ixgbe_media_type_copper:
181 /* only some copper devices support flow control autoneg */
182 switch (hw->device_id) {
183 case IXGBE_DEV_ID_82599_T3_LOM:
184 case IXGBE_DEV_ID_X540T:
185 case IXGBE_DEV_ID_X540T1:
195 ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED,
196 "Device %x does not support flow control autoneg",
202 * ixgbe_setup_fc - Set up flow control
203 * @hw: pointer to hardware structure
205 * Called at init time to set up flow control.
207 STATIC s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
209 s32 ret_val = IXGBE_SUCCESS;
210 u32 reg = 0, reg_bp = 0;
214 DEBUGFUNC("ixgbe_setup_fc");
216 /* Validate the requested mode */
217 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
218 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
219 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
220 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
225 * 10gig parts do not have a word in the EEPROM to determine the
226 * default flow control setting, so we explicitly set it to full.
228 if (hw->fc.requested_mode == ixgbe_fc_default)
229 hw->fc.requested_mode = ixgbe_fc_full;
232 * Set up the 1G and 10G flow control advertisement registers so the
233 * HW will be able to do fc autoneg once the cable is plugged in. If
234 * we link at 10G, the 1G advertisement is harmless and vice versa.
236 switch (hw->phy.media_type) {
237 case ixgbe_media_type_backplane:
238 /* some MAC's need RMW protection on AUTOC */
239 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, ®_bp);
240 if (ret_val != IXGBE_SUCCESS)
243 /* only backplane uses autoc so fall though */
244 case ixgbe_media_type_fiber:
245 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
248 case ixgbe_media_type_copper:
249 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
250 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
257 * The possible values of fc.requested_mode are:
258 * 0: Flow control is completely disabled
259 * 1: Rx flow control is enabled (we can receive pause frames,
260 * but not send pause frames).
261 * 2: Tx flow control is enabled (we can send pause frames but
262 * we do not support receiving pause frames).
263 * 3: Both Rx and Tx flow control (symmetric) are enabled.
266 switch (hw->fc.requested_mode) {
268 /* Flow control completely disabled by software override. */
269 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
270 if (hw->phy.media_type == ixgbe_media_type_backplane)
271 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
272 IXGBE_AUTOC_ASM_PAUSE);
273 else if (hw->phy.media_type == ixgbe_media_type_copper)
274 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
276 case ixgbe_fc_tx_pause:
278 * Tx Flow control is enabled, and Rx Flow control is
279 * disabled by software override.
281 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
282 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
283 if (hw->phy.media_type == ixgbe_media_type_backplane) {
284 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
285 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
286 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
287 reg_cu |= IXGBE_TAF_ASM_PAUSE;
288 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
291 case ixgbe_fc_rx_pause:
293 * Rx Flow control is enabled and Tx Flow control is
294 * disabled by software override. Since there really
295 * isn't a way to advertise that we are capable of RX
296 * Pause ONLY, we will advertise that we support both
297 * symmetric and asymmetric Rx PAUSE, as such we fall
298 * through to the fc_full statement. Later, we will
299 * disable the adapter's ability to send PAUSE frames.
302 /* Flow control (both Rx and Tx) is enabled by SW override. */
303 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
304 if (hw->phy.media_type == ixgbe_media_type_backplane)
305 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
306 IXGBE_AUTOC_ASM_PAUSE;
307 else if (hw->phy.media_type == ixgbe_media_type_copper)
308 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
311 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
312 "Flow control param set incorrectly\n");
313 ret_val = IXGBE_ERR_CONFIG;
318 if (hw->mac.type < ixgbe_mac_X540) {
320 * Enable auto-negotiation between the MAC & PHY;
321 * the MAC will advertise clause 37 flow control.
323 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
324 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
326 /* Disable AN timeout */
327 if (hw->fc.strict_ieee)
328 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
330 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
331 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
335 * AUTOC restart handles negotiation of 1G and 10G on backplane
336 * and copper. There is no need to set the PCS1GCTL register.
339 if (hw->phy.media_type == ixgbe_media_type_backplane) {
340 reg_bp |= IXGBE_AUTOC_AN_RESTART;
341 ret_val = hw->mac.ops.prot_autoc_write(hw, reg_bp, locked);
344 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
345 (ixgbe_device_supports_autoneg_fc(hw))) {
346 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
347 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
350 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
356 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
357 * @hw: pointer to hardware structure
359 * Starts the hardware by filling the bus info structure and media type, clears
360 * all on chip counters, initializes receive address registers, multicast
361 * table, VLAN filter table, calls routine to set up link and flow control
362 * settings, and leaves transmit and receive units disabled and uninitialized
364 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
369 DEBUGFUNC("ixgbe_start_hw_generic");
371 /* Set the media type */
372 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
374 /* PHY ops initialization must be done in reset_hw() */
376 /* Clear the VLAN filter table */
377 hw->mac.ops.clear_vfta(hw);
379 /* Clear statistics registers */
380 hw->mac.ops.clear_hw_cntrs(hw);
382 /* Set No Snoop Disable */
383 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
384 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
385 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
386 IXGBE_WRITE_FLUSH(hw);
388 /* Setup flow control */
389 ret_val = ixgbe_setup_fc(hw);
390 if (ret_val != IXGBE_SUCCESS)
393 /* Clear adapter stopped flag */
394 hw->adapter_stopped = false;
401 * ixgbe_start_hw_gen2 - Init sequence for common device family
402 * @hw: pointer to hw structure
404 * Performs the init sequence common to the second generation
406 * Devices in the second generation:
410 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
415 /* Clear the rate limiters */
416 for (i = 0; i < hw->mac.max_tx_queues; i++) {
417 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
418 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
420 IXGBE_WRITE_FLUSH(hw);
422 /* Disable relaxed ordering */
423 for (i = 0; i < hw->mac.max_tx_queues; i++) {
424 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
425 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
426 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
429 for (i = 0; i < hw->mac.max_rx_queues; i++) {
430 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
431 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
432 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
433 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
436 return IXGBE_SUCCESS;
440 * ixgbe_init_hw_generic - Generic hardware initialization
441 * @hw: pointer to hardware structure
443 * Initialize the hardware by resetting the hardware, filling the bus info
444 * structure and media type, clears all on chip counters, initializes receive
445 * address registers, multicast table, VLAN filter table, calls routine to set
446 * up link and flow control settings, and leaves transmit and receive units
447 * disabled and uninitialized
449 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
453 DEBUGFUNC("ixgbe_init_hw_generic");
455 /* Reset the hardware */
456 status = hw->mac.ops.reset_hw(hw);
458 if (status == IXGBE_SUCCESS) {
460 status = hw->mac.ops.start_hw(hw);
467 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
468 * @hw: pointer to hardware structure
470 * Clears all hardware statistics counters by reading them from the hardware
471 * Statistics counters are clear on read.
473 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
477 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
479 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
480 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
481 IXGBE_READ_REG(hw, IXGBE_ERRBC);
482 IXGBE_READ_REG(hw, IXGBE_MSPDC);
483 for (i = 0; i < 8; i++)
484 IXGBE_READ_REG(hw, IXGBE_MPC(i));
486 IXGBE_READ_REG(hw, IXGBE_MLFC);
487 IXGBE_READ_REG(hw, IXGBE_MRFC);
488 IXGBE_READ_REG(hw, IXGBE_RLEC);
489 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
490 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
491 if (hw->mac.type >= ixgbe_mac_82599EB) {
492 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
493 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
495 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
496 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
499 for (i = 0; i < 8; i++) {
500 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
501 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
502 if (hw->mac.type >= ixgbe_mac_82599EB) {
503 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
504 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
506 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
507 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
510 if (hw->mac.type >= ixgbe_mac_82599EB)
511 for (i = 0; i < 8; i++)
512 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
513 IXGBE_READ_REG(hw, IXGBE_PRC64);
514 IXGBE_READ_REG(hw, IXGBE_PRC127);
515 IXGBE_READ_REG(hw, IXGBE_PRC255);
516 IXGBE_READ_REG(hw, IXGBE_PRC511);
517 IXGBE_READ_REG(hw, IXGBE_PRC1023);
518 IXGBE_READ_REG(hw, IXGBE_PRC1522);
519 IXGBE_READ_REG(hw, IXGBE_GPRC);
520 IXGBE_READ_REG(hw, IXGBE_BPRC);
521 IXGBE_READ_REG(hw, IXGBE_MPRC);
522 IXGBE_READ_REG(hw, IXGBE_GPTC);
523 IXGBE_READ_REG(hw, IXGBE_GORCL);
524 IXGBE_READ_REG(hw, IXGBE_GORCH);
525 IXGBE_READ_REG(hw, IXGBE_GOTCL);
526 IXGBE_READ_REG(hw, IXGBE_GOTCH);
527 if (hw->mac.type == ixgbe_mac_82598EB)
528 for (i = 0; i < 8; i++)
529 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
530 IXGBE_READ_REG(hw, IXGBE_RUC);
531 IXGBE_READ_REG(hw, IXGBE_RFC);
532 IXGBE_READ_REG(hw, IXGBE_ROC);
533 IXGBE_READ_REG(hw, IXGBE_RJC);
534 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
535 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
536 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
537 IXGBE_READ_REG(hw, IXGBE_TORL);
538 IXGBE_READ_REG(hw, IXGBE_TORH);
539 IXGBE_READ_REG(hw, IXGBE_TPR);
540 IXGBE_READ_REG(hw, IXGBE_TPT);
541 IXGBE_READ_REG(hw, IXGBE_PTC64);
542 IXGBE_READ_REG(hw, IXGBE_PTC127);
543 IXGBE_READ_REG(hw, IXGBE_PTC255);
544 IXGBE_READ_REG(hw, IXGBE_PTC511);
545 IXGBE_READ_REG(hw, IXGBE_PTC1023);
546 IXGBE_READ_REG(hw, IXGBE_PTC1522);
547 IXGBE_READ_REG(hw, IXGBE_MPTC);
548 IXGBE_READ_REG(hw, IXGBE_BPTC);
549 for (i = 0; i < 16; i++) {
550 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
551 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
552 if (hw->mac.type >= ixgbe_mac_82599EB) {
553 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
554 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
555 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
556 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
557 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
559 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
560 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
564 if (hw->mac.type == ixgbe_mac_X540) {
566 ixgbe_identify_phy(hw);
567 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
568 IXGBE_MDIO_PCS_DEV_TYPE, &i);
569 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
570 IXGBE_MDIO_PCS_DEV_TYPE, &i);
571 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
572 IXGBE_MDIO_PCS_DEV_TYPE, &i);
573 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
574 IXGBE_MDIO_PCS_DEV_TYPE, &i);
577 return IXGBE_SUCCESS;
581 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
582 * @hw: pointer to hardware structure
583 * @pba_num: stores the part number string from the EEPROM
584 * @pba_num_size: part number string buffer length
586 * Reads the part number string from the EEPROM.
588 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
597 DEBUGFUNC("ixgbe_read_pba_string_generic");
599 if (pba_num == NULL) {
600 DEBUGOUT("PBA string buffer was null\n");
601 return IXGBE_ERR_INVALID_ARGUMENT;
604 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
606 DEBUGOUT("NVM Read Error\n");
610 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
612 DEBUGOUT("NVM Read Error\n");
617 * if data is not ptr guard the PBA must be in legacy format which
618 * means pba_ptr is actually our second data word for the PBA number
619 * and we can decode it into an ascii string
621 if (data != IXGBE_PBANUM_PTR_GUARD) {
622 DEBUGOUT("NVM PBA number is not stored as string\n");
624 /* we will need 11 characters to store the PBA */
625 if (pba_num_size < 11) {
626 DEBUGOUT("PBA string buffer too small\n");
627 return IXGBE_ERR_NO_SPACE;
630 /* extract hex string from data and pba_ptr */
631 pba_num[0] = (data >> 12) & 0xF;
632 pba_num[1] = (data >> 8) & 0xF;
633 pba_num[2] = (data >> 4) & 0xF;
634 pba_num[3] = data & 0xF;
635 pba_num[4] = (pba_ptr >> 12) & 0xF;
636 pba_num[5] = (pba_ptr >> 8) & 0xF;
639 pba_num[8] = (pba_ptr >> 4) & 0xF;
640 pba_num[9] = pba_ptr & 0xF;
642 /* put a null character on the end of our string */
645 /* switch all the data but the '-' to hex char */
646 for (offset = 0; offset < 10; offset++) {
647 if (pba_num[offset] < 0xA)
648 pba_num[offset] += '0';
649 else if (pba_num[offset] < 0x10)
650 pba_num[offset] += 'A' - 0xA;
653 return IXGBE_SUCCESS;
656 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
658 DEBUGOUT("NVM Read Error\n");
662 if (length == 0xFFFF || length == 0) {
663 DEBUGOUT("NVM PBA number section invalid length\n");
664 return IXGBE_ERR_PBA_SECTION;
667 /* check if pba_num buffer is big enough */
668 if (pba_num_size < (((u32)length * 2) - 1)) {
669 DEBUGOUT("PBA string buffer too small\n");
670 return IXGBE_ERR_NO_SPACE;
673 /* trim pba length from start of string */
677 for (offset = 0; offset < length; offset++) {
678 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
680 DEBUGOUT("NVM Read Error\n");
683 pba_num[offset * 2] = (u8)(data >> 8);
684 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
686 pba_num[offset * 2] = '\0';
688 return IXGBE_SUCCESS;
692 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
693 * @hw: pointer to hardware structure
694 * @pba_num: stores the part number from the EEPROM
696 * Reads the part number from the EEPROM.
698 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
703 DEBUGFUNC("ixgbe_read_pba_num_generic");
705 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
707 DEBUGOUT("NVM Read Error\n");
709 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
710 DEBUGOUT("NVM Not supported\n");
711 return IXGBE_NOT_IMPLEMENTED;
713 *pba_num = (u32)(data << 16);
715 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
717 DEBUGOUT("NVM Read Error\n");
722 return IXGBE_SUCCESS;
727 * @hw: pointer to the HW structure
728 * @eeprom_buf: optional pointer to EEPROM image
729 * @eeprom_buf_size: size of EEPROM image in words
730 * @max_pba_block_size: PBA block size limit
731 * @pba: pointer to output PBA structure
733 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
734 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
737 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
738 u32 eeprom_buf_size, u16 max_pba_block_size,
739 struct ixgbe_pba *pba)
745 return IXGBE_ERR_PARAM;
747 if (eeprom_buf == NULL) {
748 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
753 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
754 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
755 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
757 return IXGBE_ERR_PARAM;
761 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
762 if (pba->pba_block == NULL)
763 return IXGBE_ERR_PARAM;
765 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
771 if (pba_block_size > max_pba_block_size)
772 return IXGBE_ERR_PARAM;
774 if (eeprom_buf == NULL) {
775 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
781 if (eeprom_buf_size > (u32)(pba->word[1] +
783 memcpy(pba->pba_block,
784 &eeprom_buf[pba->word[1]],
785 pba_block_size * sizeof(u16));
787 return IXGBE_ERR_PARAM;
792 return IXGBE_SUCCESS;
796 * ixgbe_write_pba_raw
797 * @hw: pointer to the HW structure
798 * @eeprom_buf: optional pointer to EEPROM image
799 * @eeprom_buf_size: size of EEPROM image in words
800 * @pba: pointer to PBA structure
802 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
803 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
806 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
807 u32 eeprom_buf_size, struct ixgbe_pba *pba)
812 return IXGBE_ERR_PARAM;
814 if (eeprom_buf == NULL) {
815 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
820 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
821 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
822 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
824 return IXGBE_ERR_PARAM;
828 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
829 if (pba->pba_block == NULL)
830 return IXGBE_ERR_PARAM;
832 if (eeprom_buf == NULL) {
833 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
839 if (eeprom_buf_size > (u32)(pba->word[1] +
840 pba->pba_block[0])) {
841 memcpy(&eeprom_buf[pba->word[1]],
843 pba->pba_block[0] * sizeof(u16));
845 return IXGBE_ERR_PARAM;
850 return IXGBE_SUCCESS;
854 * ixgbe_get_pba_block_size
855 * @hw: pointer to the HW structure
856 * @eeprom_buf: optional pointer to EEPROM image
857 * @eeprom_buf_size: size of EEPROM image in words
858 * @pba_data_size: pointer to output variable
860 * Returns the size of the PBA block in words. Function operates on EEPROM
861 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
865 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
866 u32 eeprom_buf_size, u16 *pba_block_size)
872 DEBUGFUNC("ixgbe_get_pba_block_size");
874 if (eeprom_buf == NULL) {
875 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
880 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
881 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
882 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
884 return IXGBE_ERR_PARAM;
888 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
889 if (eeprom_buf == NULL) {
890 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
895 if (eeprom_buf_size > pba_word[1])
896 length = eeprom_buf[pba_word[1] + 0];
898 return IXGBE_ERR_PARAM;
901 if (length == 0xFFFF || length == 0)
902 return IXGBE_ERR_PBA_SECTION;
904 /* PBA number in legacy format, there is no PBA Block. */
908 if (pba_block_size != NULL)
909 *pba_block_size = length;
911 return IXGBE_SUCCESS;
915 * ixgbe_get_mac_addr_generic - Generic get MAC address
916 * @hw: pointer to hardware structure
917 * @mac_addr: Adapter MAC address
919 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
920 * A reset of the adapter must be performed prior to calling this function
921 * in order for the MAC address to have been loaded from the EEPROM into RAR0
923 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
929 DEBUGFUNC("ixgbe_get_mac_addr_generic");
931 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
932 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
934 for (i = 0; i < 4; i++)
935 mac_addr[i] = (u8)(rar_low >> (i*8));
937 for (i = 0; i < 2; i++)
938 mac_addr[i+4] = (u8)(rar_high >> (i*8));
940 return IXGBE_SUCCESS;
944 * ixgbe_set_pci_config_data_generic - Generic store PCI bus info
945 * @hw: pointer to hardware structure
946 * @link_status: the link status returned by the PCI config space
948 * Stores the PCI bus info (speed, width, type) within the ixgbe_hw structure
950 void ixgbe_set_pci_config_data_generic(struct ixgbe_hw *hw, u16 link_status)
952 struct ixgbe_mac_info *mac = &hw->mac;
954 hw->bus.type = ixgbe_bus_type_pci_express;
956 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
957 case IXGBE_PCI_LINK_WIDTH_1:
958 hw->bus.width = ixgbe_bus_width_pcie_x1;
960 case IXGBE_PCI_LINK_WIDTH_2:
961 hw->bus.width = ixgbe_bus_width_pcie_x2;
963 case IXGBE_PCI_LINK_WIDTH_4:
964 hw->bus.width = ixgbe_bus_width_pcie_x4;
966 case IXGBE_PCI_LINK_WIDTH_8:
967 hw->bus.width = ixgbe_bus_width_pcie_x8;
970 hw->bus.width = ixgbe_bus_width_unknown;
974 switch (link_status & IXGBE_PCI_LINK_SPEED) {
975 case IXGBE_PCI_LINK_SPEED_2500:
976 hw->bus.speed = ixgbe_bus_speed_2500;
978 case IXGBE_PCI_LINK_SPEED_5000:
979 hw->bus.speed = ixgbe_bus_speed_5000;
981 case IXGBE_PCI_LINK_SPEED_8000:
982 hw->bus.speed = ixgbe_bus_speed_8000;
985 hw->bus.speed = ixgbe_bus_speed_unknown;
989 mac->ops.set_lan_id(hw);
993 * ixgbe_get_bus_info_generic - Generic set PCI bus info
994 * @hw: pointer to hardware structure
996 * Gets the PCI bus info (speed, width, type) then calls helper function to
997 * store this data within the ixgbe_hw structure.
999 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
1003 DEBUGFUNC("ixgbe_get_bus_info_generic");
1005 /* Get the negotiated link width and speed from PCI config space */
1006 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
1008 ixgbe_set_pci_config_data_generic(hw, link_status);
1010 return IXGBE_SUCCESS;
1014 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
1015 * @hw: pointer to the HW structure
1017 * Determines the LAN function id by reading memory-mapped registers
1018 * and swaps the port value if requested.
1020 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
1022 struct ixgbe_bus_info *bus = &hw->bus;
1025 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
1027 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
1028 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
1029 bus->lan_id = bus->func;
1031 /* check for a port swap */
1032 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
1033 if (reg & IXGBE_FACTPS_LFS)
1038 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1039 * @hw: pointer to hardware structure
1041 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1042 * disables transmit and receive units. The adapter_stopped flag is used by
1043 * the shared code and drivers to determine if the adapter is in a stopped
1044 * state and should not touch the hardware.
1046 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1051 DEBUGFUNC("ixgbe_stop_adapter_generic");
1054 * Set the adapter_stopped flag so other driver functions stop touching
1057 hw->adapter_stopped = true;
1059 /* Disable the receive unit */
1060 ixgbe_disable_rx(hw);
1062 /* Clear interrupt mask to stop interrupts from being generated */
1063 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1065 /* Clear any pending interrupts, flush previous writes */
1066 IXGBE_READ_REG(hw, IXGBE_EICR);
1068 /* Disable the transmit unit. Each queue must be disabled. */
1069 for (i = 0; i < hw->mac.max_tx_queues; i++)
1070 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1072 /* Disable the receive unit by stopping each queue */
1073 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1074 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1075 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1076 reg_val |= IXGBE_RXDCTL_SWFLSH;
1077 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1080 /* flush all queues disables */
1081 IXGBE_WRITE_FLUSH(hw);
1085 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
1086 * access and verify no pending requests
1088 return ixgbe_disable_pcie_master(hw);
1092 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1093 * @hw: pointer to hardware structure
1094 * @index: led number to turn on
1096 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1098 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1100 DEBUGFUNC("ixgbe_led_on_generic");
1102 /* To turn on the LED, set mode to ON. */
1103 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1104 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1105 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1106 IXGBE_WRITE_FLUSH(hw);
1108 return IXGBE_SUCCESS;
1112 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1113 * @hw: pointer to hardware structure
1114 * @index: led number to turn off
1116 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1118 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1120 DEBUGFUNC("ixgbe_led_off_generic");
1122 /* To turn off the LED, set mode to OFF. */
1123 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1124 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1125 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1126 IXGBE_WRITE_FLUSH(hw);
1128 return IXGBE_SUCCESS;
1132 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1133 * @hw: pointer to hardware structure
1135 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1136 * ixgbe_hw struct in order to set up EEPROM access.
1138 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1140 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1144 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1146 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1147 eeprom->type = ixgbe_eeprom_none;
1148 /* Set default semaphore delay to 10ms which is a well
1150 eeprom->semaphore_delay = 10;
1151 /* Clear EEPROM page size, it will be initialized as needed */
1152 eeprom->word_page_size = 0;
1155 * Check for EEPROM present first.
1156 * If not present leave as none
1158 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1159 if (eec & IXGBE_EEC_PRES) {
1160 eeprom->type = ixgbe_eeprom_spi;
1163 * SPI EEPROM is assumed here. This code would need to
1164 * change if a future EEPROM is not SPI.
1166 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1167 IXGBE_EEC_SIZE_SHIFT);
1168 eeprom->word_size = 1 << (eeprom_size +
1169 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1172 if (eec & IXGBE_EEC_ADDR_SIZE)
1173 eeprom->address_bits = 16;
1175 eeprom->address_bits = 8;
1176 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1177 "%d\n", eeprom->type, eeprom->word_size,
1178 eeprom->address_bits);
1181 return IXGBE_SUCCESS;
1185 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1186 * @hw: pointer to hardware structure
1187 * @offset: offset within the EEPROM to write
1188 * @words: number of word(s)
1189 * @data: 16 bit word(s) to write to EEPROM
1191 * Reads 16 bit word(s) from EEPROM through bit-bang method
1193 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1194 u16 words, u16 *data)
1196 s32 status = IXGBE_SUCCESS;
1199 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1201 hw->eeprom.ops.init_params(hw);
1204 status = IXGBE_ERR_INVALID_ARGUMENT;
1208 if (offset + words > hw->eeprom.word_size) {
1209 status = IXGBE_ERR_EEPROM;
1214 * The EEPROM page size cannot be queried from the chip. We do lazy
1215 * initialization. It is worth to do that when we write large buffer.
1217 if ((hw->eeprom.word_page_size == 0) &&
1218 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1219 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1222 * We cannot hold synchronization semaphores for too long
1223 * to avoid other entity starvation. However it is more efficient
1224 * to read in bursts than synchronizing access for each word.
1226 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1227 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1228 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1229 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1232 if (status != IXGBE_SUCCESS)
1241 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1242 * @hw: pointer to hardware structure
1243 * @offset: offset within the EEPROM to be written to
1244 * @words: number of word(s)
1245 * @data: 16 bit word(s) to be written to the EEPROM
1247 * If ixgbe_eeprom_update_checksum is not called after this function, the
1248 * EEPROM will most likely contain an invalid checksum.
1250 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1251 u16 words, u16 *data)
1257 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1259 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1261 /* Prepare the EEPROM for writing */
1262 status = ixgbe_acquire_eeprom(hw);
1264 if (status == IXGBE_SUCCESS) {
1265 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1266 ixgbe_release_eeprom(hw);
1267 status = IXGBE_ERR_EEPROM;
1271 if (status == IXGBE_SUCCESS) {
1272 for (i = 0; i < words; i++) {
1273 ixgbe_standby_eeprom(hw);
1275 /* Send the WRITE ENABLE command (8 bit opcode ) */
1276 ixgbe_shift_out_eeprom_bits(hw,
1277 IXGBE_EEPROM_WREN_OPCODE_SPI,
1278 IXGBE_EEPROM_OPCODE_BITS);
1280 ixgbe_standby_eeprom(hw);
1283 * Some SPI eeproms use the 8th address bit embedded
1286 if ((hw->eeprom.address_bits == 8) &&
1287 ((offset + i) >= 128))
1288 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1290 /* Send the Write command (8-bit opcode + addr) */
1291 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1292 IXGBE_EEPROM_OPCODE_BITS);
1293 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1294 hw->eeprom.address_bits);
1296 page_size = hw->eeprom.word_page_size;
1298 /* Send the data in burst via SPI*/
1301 word = (word >> 8) | (word << 8);
1302 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1307 /* do not wrap around page */
1308 if (((offset + i) & (page_size - 1)) ==
1311 } while (++i < words);
1313 ixgbe_standby_eeprom(hw);
1316 /* Done with writing - release the EEPROM */
1317 ixgbe_release_eeprom(hw);
1324 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1325 * @hw: pointer to hardware structure
1326 * @offset: offset within the EEPROM to be written to
1327 * @data: 16 bit word to be written to the EEPROM
1329 * If ixgbe_eeprom_update_checksum is not called after this function, the
1330 * EEPROM will most likely contain an invalid checksum.
1332 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1336 DEBUGFUNC("ixgbe_write_eeprom_generic");
1338 hw->eeprom.ops.init_params(hw);
1340 if (offset >= hw->eeprom.word_size) {
1341 status = IXGBE_ERR_EEPROM;
1345 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1352 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1353 * @hw: pointer to hardware structure
1354 * @offset: offset within the EEPROM to be read
1355 * @data: read 16 bit words(s) from EEPROM
1356 * @words: number of word(s)
1358 * Reads 16 bit word(s) from EEPROM through bit-bang method
1360 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1361 u16 words, u16 *data)
1363 s32 status = IXGBE_SUCCESS;
1366 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1368 hw->eeprom.ops.init_params(hw);
1371 status = IXGBE_ERR_INVALID_ARGUMENT;
1375 if (offset + words > hw->eeprom.word_size) {
1376 status = IXGBE_ERR_EEPROM;
1381 * We cannot hold synchronization semaphores for too long
1382 * to avoid other entity starvation. However it is more efficient
1383 * to read in bursts than synchronizing access for each word.
1385 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1386 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1387 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1389 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1392 if (status != IXGBE_SUCCESS)
1401 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1402 * @hw: pointer to hardware structure
1403 * @offset: offset within the EEPROM to be read
1404 * @words: number of word(s)
1405 * @data: read 16 bit word(s) from EEPROM
1407 * Reads 16 bit word(s) from EEPROM through bit-bang method
1409 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1410 u16 words, u16 *data)
1414 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1417 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1419 /* Prepare the EEPROM for reading */
1420 status = ixgbe_acquire_eeprom(hw);
1422 if (status == IXGBE_SUCCESS) {
1423 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1424 ixgbe_release_eeprom(hw);
1425 status = IXGBE_ERR_EEPROM;
1429 if (status == IXGBE_SUCCESS) {
1430 for (i = 0; i < words; i++) {
1431 ixgbe_standby_eeprom(hw);
1433 * Some SPI eeproms use the 8th address bit embedded
1436 if ((hw->eeprom.address_bits == 8) &&
1437 ((offset + i) >= 128))
1438 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1440 /* Send the READ command (opcode + addr) */
1441 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1442 IXGBE_EEPROM_OPCODE_BITS);
1443 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1444 hw->eeprom.address_bits);
1446 /* Read the data. */
1447 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1448 data[i] = (word_in >> 8) | (word_in << 8);
1451 /* End this read operation */
1452 ixgbe_release_eeprom(hw);
1459 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1460 * @hw: pointer to hardware structure
1461 * @offset: offset within the EEPROM to be read
1462 * @data: read 16 bit value from EEPROM
1464 * Reads 16 bit value from EEPROM through bit-bang method
1466 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1471 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1473 hw->eeprom.ops.init_params(hw);
1475 if (offset >= hw->eeprom.word_size) {
1476 status = IXGBE_ERR_EEPROM;
1480 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1487 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1488 * @hw: pointer to hardware structure
1489 * @offset: offset of word in the EEPROM to read
1490 * @words: number of word(s)
1491 * @data: 16 bit word(s) from the EEPROM
1493 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1495 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1496 u16 words, u16 *data)
1499 s32 status = IXGBE_SUCCESS;
1502 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1504 hw->eeprom.ops.init_params(hw);
1507 status = IXGBE_ERR_INVALID_ARGUMENT;
1508 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1512 if (offset >= hw->eeprom.word_size) {
1513 status = IXGBE_ERR_EEPROM;
1514 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1518 for (i = 0; i < words; i++) {
1519 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1520 IXGBE_EEPROM_RW_REG_START;
1522 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1523 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1525 if (status == IXGBE_SUCCESS) {
1526 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1527 IXGBE_EEPROM_RW_REG_DATA);
1529 DEBUGOUT("Eeprom read timed out\n");
1538 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1539 * @hw: pointer to hardware structure
1540 * @offset: offset within the EEPROM to be used as a scratch pad
1542 * Discover EEPROM page size by writing marching data at given offset.
1543 * This function is called only when we are writing a new large buffer
1544 * at given offset so the data would be overwritten anyway.
1546 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1549 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1550 s32 status = IXGBE_SUCCESS;
1553 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1555 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1558 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1559 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1560 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1561 hw->eeprom.word_page_size = 0;
1562 if (status != IXGBE_SUCCESS)
1565 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1566 if (status != IXGBE_SUCCESS)
1570 * When writing in burst more than the actual page size
1571 * EEPROM address wraps around current page.
1573 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1575 DEBUGOUT1("Detected EEPROM page size = %d words.",
1576 hw->eeprom.word_page_size);
1582 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1583 * @hw: pointer to hardware structure
1584 * @offset: offset of word in the EEPROM to read
1585 * @data: word read from the EEPROM
1587 * Reads a 16 bit word from the EEPROM using the EERD register.
1589 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1591 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1595 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1596 * @hw: pointer to hardware structure
1597 * @offset: offset of word in the EEPROM to write
1598 * @words: number of word(s)
1599 * @data: word(s) write to the EEPROM
1601 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1603 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1604 u16 words, u16 *data)
1607 s32 status = IXGBE_SUCCESS;
1610 DEBUGFUNC("ixgbe_write_eewr_generic");
1612 hw->eeprom.ops.init_params(hw);
1615 status = IXGBE_ERR_INVALID_ARGUMENT;
1616 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1620 if (offset >= hw->eeprom.word_size) {
1621 status = IXGBE_ERR_EEPROM;
1622 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1626 for (i = 0; i < words; i++) {
1627 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1628 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1629 IXGBE_EEPROM_RW_REG_START;
1631 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1632 if (status != IXGBE_SUCCESS) {
1633 DEBUGOUT("Eeprom write EEWR timed out\n");
1637 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1639 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1640 if (status != IXGBE_SUCCESS) {
1641 DEBUGOUT("Eeprom write EEWR timed out\n");
1651 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1652 * @hw: pointer to hardware structure
1653 * @offset: offset of word in the EEPROM to write
1654 * @data: word write to the EEPROM
1656 * Write a 16 bit word to the EEPROM using the EEWR register.
1658 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1660 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1664 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1665 * @hw: pointer to hardware structure
1666 * @ee_reg: EEPROM flag for polling
1668 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1669 * read or write is done respectively.
1671 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1675 s32 status = IXGBE_ERR_EEPROM;
1677 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1679 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1680 if (ee_reg == IXGBE_NVM_POLL_READ)
1681 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1683 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1685 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1686 status = IXGBE_SUCCESS;
1692 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1693 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1694 "EEPROM read/write done polling timed out");
1700 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1701 * @hw: pointer to hardware structure
1703 * Prepares EEPROM for access using bit-bang method. This function should
1704 * be called before issuing a command to the EEPROM.
1706 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1708 s32 status = IXGBE_SUCCESS;
1712 DEBUGFUNC("ixgbe_acquire_eeprom");
1714 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1716 status = IXGBE_ERR_SWFW_SYNC;
1718 if (status == IXGBE_SUCCESS) {
1719 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1721 /* Request EEPROM Access */
1722 eec |= IXGBE_EEC_REQ;
1723 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1725 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1726 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1727 if (eec & IXGBE_EEC_GNT)
1732 /* Release if grant not acquired */
1733 if (!(eec & IXGBE_EEC_GNT)) {
1734 eec &= ~IXGBE_EEC_REQ;
1735 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1736 DEBUGOUT("Could not acquire EEPROM grant\n");
1738 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1739 status = IXGBE_ERR_EEPROM;
1742 /* Setup EEPROM for Read/Write */
1743 if (status == IXGBE_SUCCESS) {
1744 /* Clear CS and SK */
1745 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1746 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1747 IXGBE_WRITE_FLUSH(hw);
1755 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1756 * @hw: pointer to hardware structure
1758 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1760 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1762 s32 status = IXGBE_ERR_EEPROM;
1767 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1770 /* Get SMBI software semaphore between device drivers first */
1771 for (i = 0; i < timeout; i++) {
1773 * If the SMBI bit is 0 when we read it, then the bit will be
1774 * set and we have the semaphore
1776 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1777 if (!(swsm & IXGBE_SWSM_SMBI)) {
1778 status = IXGBE_SUCCESS;
1785 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1788 * this release is particularly important because our attempts
1789 * above to get the semaphore may have succeeded, and if there
1790 * was a timeout, we should unconditionally clear the semaphore
1791 * bits to free the driver to make progress
1793 ixgbe_release_eeprom_semaphore(hw);
1798 * If the SMBI bit is 0 when we read it, then the bit will be
1799 * set and we have the semaphore
1801 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1802 if (!(swsm & IXGBE_SWSM_SMBI))
1803 status = IXGBE_SUCCESS;
1806 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1807 if (status == IXGBE_SUCCESS) {
1808 for (i = 0; i < timeout; i++) {
1809 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1811 /* Set the SW EEPROM semaphore bit to request access */
1812 swsm |= IXGBE_SWSM_SWESMBI;
1813 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1816 * If we set the bit successfully then we got the
1819 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1820 if (swsm & IXGBE_SWSM_SWESMBI)
1827 * Release semaphores and return error if SW EEPROM semaphore
1828 * was not granted because we don't have access to the EEPROM
1831 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1832 "SWESMBI Software EEPROM semaphore not granted.\n");
1833 ixgbe_release_eeprom_semaphore(hw);
1834 status = IXGBE_ERR_EEPROM;
1837 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1838 "Software semaphore SMBI between device drivers "
1846 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1847 * @hw: pointer to hardware structure
1849 * This function clears hardware semaphore bits.
1851 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1855 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1857 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1859 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1860 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1861 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1862 IXGBE_WRITE_FLUSH(hw);
1866 * ixgbe_ready_eeprom - Polls for EEPROM ready
1867 * @hw: pointer to hardware structure
1869 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1871 s32 status = IXGBE_SUCCESS;
1875 DEBUGFUNC("ixgbe_ready_eeprom");
1878 * Read "Status Register" repeatedly until the LSB is cleared. The
1879 * EEPROM will signal that the command has been completed by clearing
1880 * bit 0 of the internal status register. If it's not cleared within
1881 * 5 milliseconds, then error out.
1883 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1884 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1885 IXGBE_EEPROM_OPCODE_BITS);
1886 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1887 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1891 ixgbe_standby_eeprom(hw);
1895 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1896 * devices (and only 0-5mSec on 5V devices)
1898 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1899 DEBUGOUT("SPI EEPROM Status error\n");
1900 status = IXGBE_ERR_EEPROM;
1907 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1908 * @hw: pointer to hardware structure
1910 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1914 DEBUGFUNC("ixgbe_standby_eeprom");
1916 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1918 /* Toggle CS to flush commands */
1919 eec |= IXGBE_EEC_CS;
1920 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1921 IXGBE_WRITE_FLUSH(hw);
1923 eec &= ~IXGBE_EEC_CS;
1924 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1925 IXGBE_WRITE_FLUSH(hw);
1930 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1931 * @hw: pointer to hardware structure
1932 * @data: data to send to the EEPROM
1933 * @count: number of bits to shift out
1935 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1942 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1944 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1947 * Mask is used to shift "count" bits of "data" out to the EEPROM
1948 * one bit at a time. Determine the starting bit based on count
1950 mask = 0x01 << (count - 1);
1952 for (i = 0; i < count; i++) {
1954 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1955 * "1", and then raising and then lowering the clock (the SK
1956 * bit controls the clock input to the EEPROM). A "0" is
1957 * shifted out to the EEPROM by setting "DI" to "0" and then
1958 * raising and then lowering the clock.
1961 eec |= IXGBE_EEC_DI;
1963 eec &= ~IXGBE_EEC_DI;
1965 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1966 IXGBE_WRITE_FLUSH(hw);
1970 ixgbe_raise_eeprom_clk(hw, &eec);
1971 ixgbe_lower_eeprom_clk(hw, &eec);
1974 * Shift mask to signify next bit of data to shift in to the
1980 /* We leave the "DI" bit set to "0" when we leave this routine. */
1981 eec &= ~IXGBE_EEC_DI;
1982 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1983 IXGBE_WRITE_FLUSH(hw);
1987 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1988 * @hw: pointer to hardware structure
1990 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1996 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
1999 * In order to read a register from the EEPROM, we need to shift
2000 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
2001 * the clock input to the EEPROM (setting the SK bit), and then reading
2002 * the value of the "DO" bit. During this "shifting in" process the
2003 * "DI" bit should always be clear.
2005 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2007 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
2009 for (i = 0; i < count; i++) {
2011 ixgbe_raise_eeprom_clk(hw, &eec);
2013 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2015 eec &= ~(IXGBE_EEC_DI);
2016 if (eec & IXGBE_EEC_DO)
2019 ixgbe_lower_eeprom_clk(hw, &eec);
2026 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
2027 * @hw: pointer to hardware structure
2028 * @eec: EEC register's current value
2030 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2032 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2035 * Raise the clock input to the EEPROM
2036 * (setting the SK bit), then delay
2038 *eec = *eec | IXGBE_EEC_SK;
2039 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2040 IXGBE_WRITE_FLUSH(hw);
2045 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2046 * @hw: pointer to hardware structure
2047 * @eecd: EECD's current value
2049 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2051 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2054 * Lower the clock input to the EEPROM (clearing the SK bit), then
2057 *eec = *eec & ~IXGBE_EEC_SK;
2058 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2059 IXGBE_WRITE_FLUSH(hw);
2064 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2065 * @hw: pointer to hardware structure
2067 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2071 DEBUGFUNC("ixgbe_release_eeprom");
2073 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2075 eec |= IXGBE_EEC_CS; /* Pull CS high */
2076 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2078 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2079 IXGBE_WRITE_FLUSH(hw);
2083 /* Stop requesting EEPROM access */
2084 eec &= ~IXGBE_EEC_REQ;
2085 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2087 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2089 /* Delay before attempt to obtain semaphore again to allow FW access */
2090 msec_delay(hw->eeprom.semaphore_delay);
2094 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2095 * @hw: pointer to hardware structure
2097 * Returns a negative error code on error, or the 16-bit checksum
2099 s32 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2108 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2110 /* Include 0x0-0x3F in the checksum */
2111 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2112 if (hw->eeprom.ops.read(hw, i, &word)) {
2113 DEBUGOUT("EEPROM read failed\n");
2114 return IXGBE_ERR_EEPROM;
2119 /* Include all data from pointers except for the fw pointer */
2120 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2121 if (hw->eeprom.ops.read(hw, i, &pointer)) {
2122 DEBUGOUT("EEPROM read failed\n");
2123 return IXGBE_ERR_EEPROM;
2126 /* If the pointer seems invalid */
2127 if (pointer == 0xFFFF || pointer == 0)
2130 if (hw->eeprom.ops.read(hw, pointer, &length)) {
2131 DEBUGOUT("EEPROM read failed\n");
2132 return IXGBE_ERR_EEPROM;
2135 if (length == 0xFFFF || length == 0)
2138 for (j = pointer + 1; j <= pointer + length; j++) {
2139 if (hw->eeprom.ops.read(hw, j, &word)) {
2140 DEBUGOUT("EEPROM read failed\n");
2141 return IXGBE_ERR_EEPROM;
2147 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2149 return (s32)checksum;
2153 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2154 * @hw: pointer to hardware structure
2155 * @checksum_val: calculated checksum
2157 * Performs checksum calculation and validates the EEPROM checksum. If the
2158 * caller does not need checksum_val, the value can be NULL.
2160 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2165 u16 read_checksum = 0;
2167 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2169 /* Read the first word from the EEPROM. If this times out or fails, do
2170 * not continue or we could be in for a very long wait while every
2173 status = hw->eeprom.ops.read(hw, 0, &checksum);
2175 DEBUGOUT("EEPROM read failed\n");
2179 status = hw->eeprom.ops.calc_checksum(hw);
2183 checksum = (u16)(status & 0xffff);
2185 status = hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2187 DEBUGOUT("EEPROM read failed\n");
2191 /* Verify read checksum from EEPROM is the same as
2192 * calculated checksum
2194 if (read_checksum != checksum)
2195 status = IXGBE_ERR_EEPROM_CHECKSUM;
2197 /* If the user cares, return the calculated checksum */
2199 *checksum_val = checksum;
2205 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2206 * @hw: pointer to hardware structure
2208 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2213 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2215 /* Read the first word from the EEPROM. If this times out or fails, do
2216 * not continue or we could be in for a very long wait while every
2219 status = hw->eeprom.ops.read(hw, 0, &checksum);
2221 DEBUGOUT("EEPROM read failed\n");
2225 status = hw->eeprom.ops.calc_checksum(hw);
2229 checksum = (u16)(status & 0xffff);
2231 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM, checksum);
2237 * ixgbe_validate_mac_addr - Validate MAC address
2238 * @mac_addr: pointer to MAC address.
2240 * Tests a MAC address to ensure it is a valid Individual Address
2242 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2244 s32 status = IXGBE_SUCCESS;
2246 DEBUGFUNC("ixgbe_validate_mac_addr");
2248 /* Make sure it is not a multicast address */
2249 if (IXGBE_IS_MULTICAST(mac_addr)) {
2250 DEBUGOUT("MAC address is multicast\n");
2251 status = IXGBE_ERR_INVALID_MAC_ADDR;
2252 /* Not a broadcast address */
2253 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2254 DEBUGOUT("MAC address is broadcast\n");
2255 status = IXGBE_ERR_INVALID_MAC_ADDR;
2256 /* Reject the zero address */
2257 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2258 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2259 DEBUGOUT("MAC address is all zeros\n");
2260 status = IXGBE_ERR_INVALID_MAC_ADDR;
2266 * ixgbe_set_rar_generic - Set Rx address register
2267 * @hw: pointer to hardware structure
2268 * @index: Receive address register to write
2269 * @addr: Address to put into receive address register
2270 * @vmdq: VMDq "set" or "pool" index
2271 * @enable_addr: set flag that address is active
2273 * Puts an ethernet address into a receive address register.
2275 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2278 u32 rar_low, rar_high;
2279 u32 rar_entries = hw->mac.num_rar_entries;
2281 DEBUGFUNC("ixgbe_set_rar_generic");
2283 /* Make sure we are using a valid rar index range */
2284 if (index >= rar_entries) {
2285 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2286 "RAR index %d is out of range.\n", index);
2287 return IXGBE_ERR_INVALID_ARGUMENT;
2290 /* setup VMDq pool selection before this RAR gets enabled */
2291 hw->mac.ops.set_vmdq(hw, index, vmdq);
2294 * HW expects these in little endian so we reverse the byte
2295 * order from network order (big endian) to little endian
2297 rar_low = ((u32)addr[0] |
2298 ((u32)addr[1] << 8) |
2299 ((u32)addr[2] << 16) |
2300 ((u32)addr[3] << 24));
2302 * Some parts put the VMDq setting in the extra RAH bits,
2303 * so save everything except the lower 16 bits that hold part
2304 * of the address and the address valid bit.
2306 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2307 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2308 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2310 if (enable_addr != 0)
2311 rar_high |= IXGBE_RAH_AV;
2313 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2314 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2316 return IXGBE_SUCCESS;
2320 * ixgbe_clear_rar_generic - Remove Rx address register
2321 * @hw: pointer to hardware structure
2322 * @index: Receive address register to write
2324 * Clears an ethernet address from a receive address register.
2326 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2329 u32 rar_entries = hw->mac.num_rar_entries;
2331 DEBUGFUNC("ixgbe_clear_rar_generic");
2333 /* Make sure we are using a valid rar index range */
2334 if (index >= rar_entries) {
2335 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2336 "RAR index %d is out of range.\n", index);
2337 return IXGBE_ERR_INVALID_ARGUMENT;
2341 * Some parts put the VMDq setting in the extra RAH bits,
2342 * so save everything except the lower 16 bits that hold part
2343 * of the address and the address valid bit.
2345 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2346 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2348 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2349 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2351 /* clear VMDq pool/queue selection for this RAR */
2352 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2354 return IXGBE_SUCCESS;
2358 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2359 * @hw: pointer to hardware structure
2361 * Places the MAC address in receive address register 0 and clears the rest
2362 * of the receive address registers. Clears the multicast table. Assumes
2363 * the receiver is in reset when the routine is called.
2365 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2368 u32 rar_entries = hw->mac.num_rar_entries;
2370 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2373 * If the current mac address is valid, assume it is a software override
2374 * to the permanent address.
2375 * Otherwise, use the permanent address from the eeprom.
2377 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2378 IXGBE_ERR_INVALID_MAC_ADDR) {
2379 /* Get the MAC address from the RAR0 for later reference */
2380 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2382 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2383 hw->mac.addr[0], hw->mac.addr[1],
2385 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2386 hw->mac.addr[4], hw->mac.addr[5]);
2388 /* Setup the receive address. */
2389 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2390 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2391 hw->mac.addr[0], hw->mac.addr[1],
2393 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2394 hw->mac.addr[4], hw->mac.addr[5]);
2396 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2398 /* clear VMDq pool/queue selection for RAR 0 */
2399 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2401 hw->addr_ctrl.overflow_promisc = 0;
2403 hw->addr_ctrl.rar_used_count = 1;
2405 /* Zero out the other receive addresses. */
2406 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2407 for (i = 1; i < rar_entries; i++) {
2408 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2409 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2413 hw->addr_ctrl.mta_in_use = 0;
2414 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2416 DEBUGOUT(" Clearing MTA\n");
2417 for (i = 0; i < hw->mac.mcft_size; i++)
2418 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2420 ixgbe_init_uta_tables(hw);
2422 return IXGBE_SUCCESS;
2426 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2427 * @hw: pointer to hardware structure
2428 * @addr: new address
2430 * Adds it to unused receive address register or goes into promiscuous mode.
2432 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2434 u32 rar_entries = hw->mac.num_rar_entries;
2437 DEBUGFUNC("ixgbe_add_uc_addr");
2439 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2440 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2443 * Place this address in the RAR if there is room,
2444 * else put the controller into promiscuous mode
2446 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2447 rar = hw->addr_ctrl.rar_used_count;
2448 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2449 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2450 hw->addr_ctrl.rar_used_count++;
2452 hw->addr_ctrl.overflow_promisc++;
2455 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2459 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2460 * @hw: pointer to hardware structure
2461 * @addr_list: the list of new addresses
2462 * @addr_count: number of addresses
2463 * @next: iterator function to walk the address list
2465 * The given list replaces any existing list. Clears the secondary addrs from
2466 * receive address registers. Uses unused receive address registers for the
2467 * first secondary addresses, and falls back to promiscuous mode as needed.
2469 * Drivers using secondary unicast addresses must set user_set_promisc when
2470 * manually putting the device into promiscuous mode.
2472 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2473 u32 addr_count, ixgbe_mc_addr_itr next)
2477 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2482 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2485 * Clear accounting of old secondary address list,
2486 * don't count RAR[0]
2488 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2489 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2490 hw->addr_ctrl.overflow_promisc = 0;
2492 /* Zero out the other receive addresses */
2493 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2494 for (i = 0; i < uc_addr_in_use; i++) {
2495 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2496 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2499 /* Add the new addresses */
2500 for (i = 0; i < addr_count; i++) {
2501 DEBUGOUT(" Adding the secondary addresses:\n");
2502 addr = next(hw, &addr_list, &vmdq);
2503 ixgbe_add_uc_addr(hw, addr, vmdq);
2506 if (hw->addr_ctrl.overflow_promisc) {
2507 /* enable promisc if not already in overflow or set by user */
2508 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2509 DEBUGOUT(" Entering address overflow promisc mode\n");
2510 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2511 fctrl |= IXGBE_FCTRL_UPE;
2512 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2515 /* only disable if set by overflow, not by user */
2516 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2517 DEBUGOUT(" Leaving address overflow promisc mode\n");
2518 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2519 fctrl &= ~IXGBE_FCTRL_UPE;
2520 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2524 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2525 return IXGBE_SUCCESS;
2529 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2530 * @hw: pointer to hardware structure
2531 * @mc_addr: the multicast address
2533 * Extracts the 12 bits, from a multicast address, to determine which
2534 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2535 * incoming rx multicast addresses, to determine the bit-vector to check in
2536 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2537 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2538 * to mc_filter_type.
2540 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2544 DEBUGFUNC("ixgbe_mta_vector");
2546 switch (hw->mac.mc_filter_type) {
2547 case 0: /* use bits [47:36] of the address */
2548 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2550 case 1: /* use bits [46:35] of the address */
2551 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2553 case 2: /* use bits [45:34] of the address */
2554 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2556 case 3: /* use bits [43:32] of the address */
2557 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2559 default: /* Invalid mc_filter_type */
2560 DEBUGOUT("MC filter type param set incorrectly\n");
2565 /* vector can only be 12-bits or boundary will be exceeded */
2571 * ixgbe_set_mta - Set bit-vector in multicast table
2572 * @hw: pointer to hardware structure
2573 * @hash_value: Multicast address hash value
2575 * Sets the bit-vector in the multicast table.
2577 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2583 DEBUGFUNC("ixgbe_set_mta");
2585 hw->addr_ctrl.mta_in_use++;
2587 vector = ixgbe_mta_vector(hw, mc_addr);
2588 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2591 * The MTA is a register array of 128 32-bit registers. It is treated
2592 * like an array of 4096 bits. We want to set bit
2593 * BitArray[vector_value]. So we figure out what register the bit is
2594 * in, read it, OR in the new bit, then write back the new value. The
2595 * register is determined by the upper 7 bits of the vector value and
2596 * the bit within that register are determined by the lower 5 bits of
2599 vector_reg = (vector >> 5) & 0x7F;
2600 vector_bit = vector & 0x1F;
2601 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2605 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2606 * @hw: pointer to hardware structure
2607 * @mc_addr_list: the list of new multicast addresses
2608 * @mc_addr_count: number of addresses
2609 * @next: iterator function to walk the multicast address list
2610 * @clear: flag, when set clears the table beforehand
2612 * When the clear flag is set, the given list replaces any existing list.
2613 * Hashes the given addresses into the multicast table.
2615 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2616 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2622 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2625 * Set the new number of MC addresses that we are being requested to
2628 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2629 hw->addr_ctrl.mta_in_use = 0;
2631 /* Clear mta_shadow */
2633 DEBUGOUT(" Clearing MTA\n");
2634 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2637 /* Update mta_shadow */
2638 for (i = 0; i < mc_addr_count; i++) {
2639 DEBUGOUT(" Adding the multicast addresses:\n");
2640 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2644 for (i = 0; i < hw->mac.mcft_size; i++)
2645 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2646 hw->mac.mta_shadow[i]);
2648 if (hw->addr_ctrl.mta_in_use > 0)
2649 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2650 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2652 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2653 return IXGBE_SUCCESS;
2657 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2658 * @hw: pointer to hardware structure
2660 * Enables multicast address in RAR and the use of the multicast hash table.
2662 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2664 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2666 DEBUGFUNC("ixgbe_enable_mc_generic");
2668 if (a->mta_in_use > 0)
2669 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2670 hw->mac.mc_filter_type);
2672 return IXGBE_SUCCESS;
2676 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2677 * @hw: pointer to hardware structure
2679 * Disables multicast address in RAR and the use of the multicast hash table.
2681 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2683 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2685 DEBUGFUNC("ixgbe_disable_mc_generic");
2687 if (a->mta_in_use > 0)
2688 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2690 return IXGBE_SUCCESS;
2694 * ixgbe_fc_enable_generic - Enable flow control
2695 * @hw: pointer to hardware structure
2697 * Enable flow control according to the current settings.
2699 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2701 s32 ret_val = IXGBE_SUCCESS;
2702 u32 mflcn_reg, fccfg_reg;
2707 DEBUGFUNC("ixgbe_fc_enable_generic");
2709 /* Validate the water mark configuration */
2710 if (!hw->fc.pause_time) {
2711 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2715 /* Low water mark of zero causes XOFF floods */
2716 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2717 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2718 hw->fc.high_water[i]) {
2719 if (!hw->fc.low_water[i] ||
2720 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2721 DEBUGOUT("Invalid water mark configuration\n");
2722 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2728 /* Negotiate the fc mode to use */
2729 ixgbe_fc_autoneg(hw);
2731 /* Disable any previous flow control settings */
2732 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2733 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2735 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2736 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2739 * The possible values of fc.current_mode are:
2740 * 0: Flow control is completely disabled
2741 * 1: Rx flow control is enabled (we can receive pause frames,
2742 * but not send pause frames).
2743 * 2: Tx flow control is enabled (we can send pause frames but
2744 * we do not support receiving pause frames).
2745 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2748 switch (hw->fc.current_mode) {
2751 * Flow control is disabled by software override or autoneg.
2752 * The code below will actually disable it in the HW.
2755 case ixgbe_fc_rx_pause:
2757 * Rx Flow control is enabled and Tx Flow control is
2758 * disabled by software override. Since there really
2759 * isn't a way to advertise that we are capable of RX
2760 * Pause ONLY, we will advertise that we support both
2761 * symmetric and asymmetric Rx PAUSE. Later, we will
2762 * disable the adapter's ability to send PAUSE frames.
2764 mflcn_reg |= IXGBE_MFLCN_RFCE;
2766 case ixgbe_fc_tx_pause:
2768 * Tx Flow control is enabled, and Rx Flow control is
2769 * disabled by software override.
2771 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2774 /* Flow control (both Rx and Tx) is enabled by SW override. */
2775 mflcn_reg |= IXGBE_MFLCN_RFCE;
2776 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2779 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2780 "Flow control param set incorrectly\n");
2781 ret_val = IXGBE_ERR_CONFIG;
2786 /* Set 802.3x based flow control settings. */
2787 mflcn_reg |= IXGBE_MFLCN_DPF;
2788 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2789 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2792 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2793 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2794 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2795 hw->fc.high_water[i]) {
2796 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2797 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2798 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2800 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2802 * In order to prevent Tx hangs when the internal Tx
2803 * switch is enabled we must set the high water mark
2804 * to the Rx packet buffer size - 24KB. This allows
2805 * the Tx switch to function even under heavy Rx
2808 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 24576;
2811 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2814 /* Configure pause time (2 TCs per register) */
2815 reg = hw->fc.pause_time * 0x00010001;
2816 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2817 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2819 /* Configure flow control refresh threshold value */
2820 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2827 * ixgbe_negotiate_fc - Negotiate flow control
2828 * @hw: pointer to hardware structure
2829 * @adv_reg: flow control advertised settings
2830 * @lp_reg: link partner's flow control settings
2831 * @adv_sym: symmetric pause bit in advertisement
2832 * @adv_asm: asymmetric pause bit in advertisement
2833 * @lp_sym: symmetric pause bit in link partner advertisement
2834 * @lp_asm: asymmetric pause bit in link partner advertisement
2836 * Find the intersection between advertised settings and link partner's
2837 * advertised settings
2839 STATIC s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2840 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2842 if ((!(adv_reg)) || (!(lp_reg))) {
2843 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2844 "Local or link partner's advertised flow control "
2845 "settings are NULL. Local: %x, link partner: %x\n",
2847 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2850 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2852 * Now we need to check if the user selected Rx ONLY
2853 * of pause frames. In this case, we had to advertise
2854 * FULL flow control because we could not advertise RX
2855 * ONLY. Hence, we must now check to see if we need to
2856 * turn OFF the TRANSMISSION of PAUSE frames.
2858 if (hw->fc.requested_mode == ixgbe_fc_full) {
2859 hw->fc.current_mode = ixgbe_fc_full;
2860 DEBUGOUT("Flow Control = FULL.\n");
2862 hw->fc.current_mode = ixgbe_fc_rx_pause;
2863 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2865 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2866 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2867 hw->fc.current_mode = ixgbe_fc_tx_pause;
2868 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2869 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2870 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2871 hw->fc.current_mode = ixgbe_fc_rx_pause;
2872 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2874 hw->fc.current_mode = ixgbe_fc_none;
2875 DEBUGOUT("Flow Control = NONE.\n");
2877 return IXGBE_SUCCESS;
2881 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2882 * @hw: pointer to hardware structure
2884 * Enable flow control according on 1 gig fiber.
2886 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2888 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2889 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2892 * On multispeed fiber at 1g, bail out if
2893 * - link is up but AN did not complete, or if
2894 * - link is up and AN completed but timed out
2897 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2898 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2899 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2900 ERROR_REPORT1(IXGBE_ERROR_POLLING,
2901 "Auto-Negotiation did not complete or timed out");
2905 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2906 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2908 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2909 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2910 IXGBE_PCS1GANA_ASM_PAUSE,
2911 IXGBE_PCS1GANA_SYM_PAUSE,
2912 IXGBE_PCS1GANA_ASM_PAUSE);
2919 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2920 * @hw: pointer to hardware structure
2922 * Enable flow control according to IEEE clause 37.
2924 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2926 u32 links2, anlp1_reg, autoc_reg, links;
2927 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2930 * On backplane, bail out if
2931 * - backplane autoneg was not completed, or if
2932 * - we are 82599 and link partner is not AN enabled
2934 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2935 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2936 ERROR_REPORT1(IXGBE_ERROR_POLLING,
2937 "Auto-Negotiation did not complete");
2941 if (hw->mac.type == ixgbe_mac_82599EB) {
2942 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2943 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2944 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2945 "Link partner is not AN enabled");
2950 * Read the 10g AN autoc and LP ability registers and resolve
2951 * local flow control settings accordingly
2953 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2954 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2956 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2957 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2958 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2965 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2966 * @hw: pointer to hardware structure
2968 * Enable flow control according to IEEE clause 37.
2970 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2972 u16 technology_ability_reg = 0;
2973 u16 lp_technology_ability_reg = 0;
2975 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2976 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2977 &technology_ability_reg);
2978 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2979 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2980 &lp_technology_ability_reg);
2982 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2983 (u32)lp_technology_ability_reg,
2984 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2985 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2989 * ixgbe_fc_autoneg - Configure flow control
2990 * @hw: pointer to hardware structure
2992 * Compares our advertised flow control capabilities to those advertised by
2993 * our link partner, and determines the proper flow control mode to use.
2995 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2997 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2998 ixgbe_link_speed speed;
3001 DEBUGFUNC("ixgbe_fc_autoneg");
3004 * AN should have completed when the cable was plugged in.
3005 * Look for reasons to bail out. Bail out if:
3006 * - FC autoneg is disabled, or if
3009 if (hw->fc.disable_fc_autoneg) {
3010 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
3011 "Flow control autoneg is disabled");
3015 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3017 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
3021 switch (hw->phy.media_type) {
3022 /* Autoneg flow control on fiber adapters */
3023 case ixgbe_media_type_fiber:
3024 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
3025 ret_val = ixgbe_fc_autoneg_fiber(hw);
3028 /* Autoneg flow control on backplane adapters */
3029 case ixgbe_media_type_backplane:
3030 ret_val = ixgbe_fc_autoneg_backplane(hw);
3033 /* Autoneg flow control on copper adapters */
3034 case ixgbe_media_type_copper:
3035 if (ixgbe_device_supports_autoneg_fc(hw))
3036 ret_val = ixgbe_fc_autoneg_copper(hw);
3044 if (ret_val == IXGBE_SUCCESS) {
3045 hw->fc.fc_was_autonegged = true;
3047 hw->fc.fc_was_autonegged = false;
3048 hw->fc.current_mode = hw->fc.requested_mode;
3053 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
3054 * @hw: pointer to hardware structure
3056 * System-wide timeout range is encoded in PCIe Device Control2 register.
3058 * Add 10% to specified maximum and return the number of times to poll for
3059 * completion timeout, in units of 100 microsec. Never return less than
3060 * 800 = 80 millisec.
3062 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3067 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3068 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3071 case IXGBE_PCIDEVCTRL2_65_130ms:
3072 pollcnt = 1300; /* 130 millisec */
3074 case IXGBE_PCIDEVCTRL2_260_520ms:
3075 pollcnt = 5200; /* 520 millisec */
3077 case IXGBE_PCIDEVCTRL2_1_2s:
3078 pollcnt = 20000; /* 2 sec */
3080 case IXGBE_PCIDEVCTRL2_4_8s:
3081 pollcnt = 80000; /* 8 sec */
3083 case IXGBE_PCIDEVCTRL2_17_34s:
3084 pollcnt = 34000; /* 34 sec */
3086 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3087 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3088 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3089 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3091 pollcnt = 800; /* 80 millisec minimum */
3095 /* add 10% to spec maximum */
3096 return (pollcnt * 11) / 10;
3100 * ixgbe_disable_pcie_master - Disable PCI-express master access
3101 * @hw: pointer to hardware structure
3103 * Disables PCI-Express master access and verifies there are no pending
3104 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3105 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3106 * is returned signifying master requests disabled.
3108 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3110 s32 status = IXGBE_SUCCESS;
3114 DEBUGFUNC("ixgbe_disable_pcie_master");
3116 /* Always set this bit to ensure any future transactions are blocked */
3117 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3119 /* Exit if master requests are blocked */
3120 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3121 IXGBE_REMOVED(hw->hw_addr))
3124 /* Poll for master request bit to clear */
3125 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3127 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3132 * Two consecutive resets are required via CTRL.RST per datasheet
3133 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3134 * of this need. The first reset prevents new master requests from
3135 * being issued by our device. We then must wait 1usec or more for any
3136 * remaining completions from the PCIe bus to trickle in, and then reset
3137 * again to clear out any effects they may have had on our device.
3139 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3140 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3143 * Before proceeding, make sure that the PCIe block does not have
3144 * transactions pending.
3146 poll = ixgbe_pcie_timeout_poll(hw);
3147 for (i = 0; i < poll; i++) {
3149 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3150 if (IXGBE_REMOVED(hw->hw_addr))
3152 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3156 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3157 "PCIe transaction pending bit also did not clear.\n");
3158 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3165 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3166 * @hw: pointer to hardware structure
3167 * @mask: Mask to specify which semaphore to acquire
3169 * Acquires the SWFW semaphore through the GSSR register for the specified
3170 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3172 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
3176 u32 fwmask = mask << 5;
3180 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3182 for (i = 0; i < timeout; i++) {
3184 * SW NVM semaphore bit is used for access to all
3185 * SW_FW_SYNC bits (not just NVM)
3187 if (ixgbe_get_eeprom_semaphore(hw))
3188 return IXGBE_ERR_SWFW_SYNC;
3190 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3191 if (!(gssr & (fwmask | swmask))) {
3193 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3194 ixgbe_release_eeprom_semaphore(hw);
3195 return IXGBE_SUCCESS;
3197 /* Resource is currently in use by FW or SW */
3198 ixgbe_release_eeprom_semaphore(hw);
3203 /* If time expired clear the bits holding the lock and retry */
3204 if (gssr & (fwmask | swmask))
3205 ixgbe_release_swfw_sync(hw, gssr & (fwmask | swmask));
3208 return IXGBE_ERR_SWFW_SYNC;
3212 * ixgbe_release_swfw_sync - Release SWFW semaphore
3213 * @hw: pointer to hardware structure
3214 * @mask: Mask to specify which semaphore to release
3216 * Releases the SWFW semaphore through the GSSR register for the specified
3217 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3219 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
3224 DEBUGFUNC("ixgbe_release_swfw_sync");
3226 ixgbe_get_eeprom_semaphore(hw);
3228 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3230 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3232 ixgbe_release_eeprom_semaphore(hw);
3236 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3237 * @hw: pointer to hardware structure
3239 * Stops the receive data path and waits for the HW to internally empty
3240 * the Rx security block
3242 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3244 #define IXGBE_MAX_SECRX_POLL 40
3249 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3252 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3253 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3254 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3255 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3256 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3257 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3260 /* Use interrupt-safe sleep just in case */
3264 /* For informational purposes only */
3265 if (i >= IXGBE_MAX_SECRX_POLL)
3266 DEBUGOUT("Rx unit being enabled before security "
3267 "path fully disabled. Continuing with init.\n");
3269 return IXGBE_SUCCESS;
3273 * prot_autoc_read_generic - Hides MAC differences needed for AUTOC read
3274 * @hw: pointer to hardware structure
3275 * @reg_val: Value we read from AUTOC
3277 * The default case requires no protection so just to the register read.
3279 s32 prot_autoc_read_generic(struct ixgbe_hw *hw, bool *locked, u32 *reg_val)
3282 *reg_val = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3283 return IXGBE_SUCCESS;
3287 * prot_autoc_write_generic - Hides MAC differences needed for AUTOC write
3288 * @hw: pointer to hardware structure
3289 * @reg_val: value to write to AUTOC
3290 * @locked: bool to indicate whether the SW/FW lock was already taken by
3293 * The default case requires no protection so just to the register write.
3295 s32 prot_autoc_write_generic(struct ixgbe_hw *hw, u32 reg_val, bool locked)
3297 UNREFERENCED_1PARAMETER(locked);
3299 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_val);
3300 return IXGBE_SUCCESS;
3304 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3305 * @hw: pointer to hardware structure
3307 * Enables the receive data path.
3309 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3313 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3315 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3316 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3317 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3318 IXGBE_WRITE_FLUSH(hw);
3320 return IXGBE_SUCCESS;
3324 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3325 * @hw: pointer to hardware structure
3326 * @regval: register value to write to RXCTRL
3328 * Enables the Rx DMA unit
3330 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3332 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3334 if (regval & IXGBE_RXCTRL_RXEN)
3335 ixgbe_enable_rx(hw);
3337 ixgbe_disable_rx(hw);
3339 return IXGBE_SUCCESS;
3343 * ixgbe_blink_led_start_generic - Blink LED based on index.
3344 * @hw: pointer to hardware structure
3345 * @index: led number to blink
3347 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3349 ixgbe_link_speed speed = 0;
3352 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3353 s32 ret_val = IXGBE_SUCCESS;
3354 bool locked = false;
3356 DEBUGFUNC("ixgbe_blink_led_start_generic");
3359 * Link must be up to auto-blink the LEDs;
3360 * Force it if link is down.
3362 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3365 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3366 if (ret_val != IXGBE_SUCCESS)
3369 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3370 autoc_reg |= IXGBE_AUTOC_FLU;
3372 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3373 if (ret_val != IXGBE_SUCCESS)
3376 IXGBE_WRITE_FLUSH(hw);
3380 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3381 led_reg |= IXGBE_LED_BLINK(index);
3382 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3383 IXGBE_WRITE_FLUSH(hw);
3390 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3391 * @hw: pointer to hardware structure
3392 * @index: led number to stop blinking
3394 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3397 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3398 s32 ret_val = IXGBE_SUCCESS;
3399 bool locked = false;
3401 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3403 ret_val = hw->mac.ops.prot_autoc_read(hw, &locked, &autoc_reg);
3404 if (ret_val != IXGBE_SUCCESS)
3407 autoc_reg &= ~IXGBE_AUTOC_FLU;
3408 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3410 ret_val = hw->mac.ops.prot_autoc_write(hw, autoc_reg, locked);
3411 if (ret_val != IXGBE_SUCCESS)
3414 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3415 led_reg &= ~IXGBE_LED_BLINK(index);
3416 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3417 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3418 IXGBE_WRITE_FLUSH(hw);
3425 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3426 * @hw: pointer to hardware structure
3427 * @san_mac_offset: SAN MAC address offset
3429 * This function will read the EEPROM location for the SAN MAC address
3430 * pointer, and returns the value at that location. This is used in both
3431 * get and set mac_addr routines.
3433 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3434 u16 *san_mac_offset)
3438 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3441 * First read the EEPROM pointer to see if the MAC addresses are
3444 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3447 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3448 "eeprom at offset %d failed",
3449 IXGBE_SAN_MAC_ADDR_PTR);
3456 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3457 * @hw: pointer to hardware structure
3458 * @san_mac_addr: SAN MAC address
3460 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3461 * per-port, so set_lan_id() must be called before reading the addresses.
3462 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3463 * upon for non-SFP connections, so we must call it here.
3465 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3467 u16 san_mac_data, san_mac_offset;
3471 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3474 * First read the EEPROM pointer to see if the MAC addresses are
3475 * available. If they're not, no point in calling set_lan_id() here.
3477 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3478 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3479 goto san_mac_addr_out;
3481 /* make sure we know which port we need to program */
3482 hw->mac.ops.set_lan_id(hw);
3483 /* apply the port offset to the address offset */
3484 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3485 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3486 for (i = 0; i < 3; i++) {
3487 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3490 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3491 "eeprom read at offset %d failed",
3493 goto san_mac_addr_out;
3495 san_mac_addr[i * 2] = (u8)(san_mac_data);
3496 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3499 return IXGBE_SUCCESS;
3503 * No addresses available in this EEPROM. It's not an
3504 * error though, so just wipe the local address and return.
3506 for (i = 0; i < 6; i++)
3507 san_mac_addr[i] = 0xFF;
3508 return IXGBE_SUCCESS;
3512 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3513 * @hw: pointer to hardware structure
3514 * @san_mac_addr: SAN MAC address
3516 * Write a SAN MAC address to the EEPROM.
3518 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3521 u16 san_mac_data, san_mac_offset;
3524 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3526 /* Look for SAN mac address pointer. If not defined, return */
3527 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3528 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3529 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3531 /* Make sure we know which port we need to write */
3532 hw->mac.ops.set_lan_id(hw);
3533 /* Apply the port offset to the address offset */
3534 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3535 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3537 for (i = 0; i < 3; i++) {
3538 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3539 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3540 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3544 return IXGBE_SUCCESS;
3548 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3549 * @hw: pointer to hardware structure
3551 * Read PCIe configuration space, and get the MSI-X vector count from
3552 * the capabilities table.
3554 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3560 switch (hw->mac.type) {
3561 case ixgbe_mac_82598EB:
3562 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3563 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3565 case ixgbe_mac_82599EB:
3566 case ixgbe_mac_X540:
3567 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3568 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3574 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3575 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3576 if (IXGBE_REMOVED(hw->hw_addr))
3578 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3580 /* MSI-X count is zero-based in HW */
3583 if (msix_count > max_msix_count)
3584 msix_count = max_msix_count;
3590 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3591 * @hw: pointer to hardware structure
3592 * @addr: Address to put into receive address register
3593 * @vmdq: VMDq pool to assign
3595 * Puts an ethernet address into a receive address register, or
3596 * finds the rar that it is aleady in; adds to the pool list
3598 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3600 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3601 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3603 u32 rar_low, rar_high;
3604 u32 addr_low, addr_high;
3606 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3608 /* swap bytes for HW little endian */
3609 addr_low = addr[0] | (addr[1] << 8)
3612 addr_high = addr[4] | (addr[5] << 8);
3615 * Either find the mac_id in rar or find the first empty space.
3616 * rar_highwater points to just after the highest currently used
3617 * rar in order to shorten the search. It grows when we add a new
3620 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3621 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3623 if (((IXGBE_RAH_AV & rar_high) == 0)
3624 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3625 first_empty_rar = rar;
3626 } else if ((rar_high & 0xFFFF) == addr_high) {
3627 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3628 if (rar_low == addr_low)
3629 break; /* found it already in the rars */
3633 if (rar < hw->mac.rar_highwater) {
3634 /* already there so just add to the pool bits */
3635 ixgbe_set_vmdq(hw, rar, vmdq);
3636 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3637 /* stick it into first empty RAR slot we found */
3638 rar = first_empty_rar;
3639 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3640 } else if (rar == hw->mac.rar_highwater) {
3641 /* add it to the top of the list and inc the highwater mark */
3642 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3643 hw->mac.rar_highwater++;
3644 } else if (rar >= hw->mac.num_rar_entries) {
3645 return IXGBE_ERR_INVALID_MAC_ADDR;
3649 * If we found rar[0], make sure the default pool bit (we use pool 0)
3650 * remains cleared to be sure default pool packets will get delivered
3653 ixgbe_clear_vmdq(hw, rar, 0);
3659 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3660 * @hw: pointer to hardware struct
3661 * @rar: receive address register index to disassociate
3662 * @vmdq: VMDq pool index to remove from the rar
3664 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3666 u32 mpsar_lo, mpsar_hi;
3667 u32 rar_entries = hw->mac.num_rar_entries;
3669 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3671 /* Make sure we are using a valid rar index range */
3672 if (rar >= rar_entries) {
3673 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3674 "RAR index %d is out of range.\n", rar);
3675 return IXGBE_ERR_INVALID_ARGUMENT;
3678 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3679 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3681 if (IXGBE_REMOVED(hw->hw_addr))
3684 if (!mpsar_lo && !mpsar_hi)
3687 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3689 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3693 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3696 } else if (vmdq < 32) {
3697 mpsar_lo &= ~(1 << vmdq);
3698 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3700 mpsar_hi &= ~(1 << (vmdq - 32));
3701 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3704 /* was that the last pool using this rar? */
3705 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3706 hw->mac.ops.clear_rar(hw, rar);
3708 return IXGBE_SUCCESS;
3712 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3713 * @hw: pointer to hardware struct
3714 * @rar: receive address register index to associate with a VMDq index
3715 * @vmdq: VMDq pool index
3717 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3720 u32 rar_entries = hw->mac.num_rar_entries;
3722 DEBUGFUNC("ixgbe_set_vmdq_generic");
3724 /* Make sure we are using a valid rar index range */
3725 if (rar >= rar_entries) {
3726 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3727 "RAR index %d is out of range.\n", rar);
3728 return IXGBE_ERR_INVALID_ARGUMENT;
3732 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3734 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3736 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3737 mpsar |= 1 << (vmdq - 32);
3738 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3740 return IXGBE_SUCCESS;
3744 * This function should only be involved in the IOV mode.
3745 * In IOV mode, Default pool is next pool after the number of
3746 * VFs advertized and not 0.
3747 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3749 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3750 * @hw: pointer to hardware struct
3751 * @vmdq: VMDq pool index
3753 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3755 u32 rar = hw->mac.san_mac_rar_index;
3757 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3760 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3761 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3763 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3764 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3767 return IXGBE_SUCCESS;
3771 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3772 * @hw: pointer to hardware structure
3774 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3778 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3779 DEBUGOUT(" Clearing UTA\n");
3781 for (i = 0; i < 128; i++)
3782 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3784 return IXGBE_SUCCESS;
3788 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3789 * @hw: pointer to hardware structure
3790 * @vlan: VLAN id to write to VLAN filter
3792 * return the VLVF index where this VLAN id should be placed
3795 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3798 u32 first_empty_slot = 0;
3801 /* short cut the special case */
3806 * Search for the vlan id in the VLVF entries. Save off the first empty
3807 * slot found along the way
3809 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3810 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3811 if (!bits && !(first_empty_slot))
3812 first_empty_slot = regindex;
3813 else if ((bits & 0x0FFF) == vlan)
3818 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3819 * in the VLVF. Else use the first empty VLVF register for this
3822 if (regindex >= IXGBE_VLVF_ENTRIES) {
3823 if (first_empty_slot)
3824 regindex = first_empty_slot;
3826 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
3827 "No space in VLVF.\n");
3828 regindex = IXGBE_ERR_NO_SPACE;
3836 * ixgbe_set_vfta_generic - Set VLAN filter table
3837 * @hw: pointer to hardware structure
3838 * @vlan: VLAN id to write to VLAN filter
3839 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3840 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3842 * Turn on/off specified VLAN in the VLAN filter table.
3844 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3851 s32 ret_val = IXGBE_SUCCESS;
3852 bool vfta_changed = false;
3854 DEBUGFUNC("ixgbe_set_vfta_generic");
3857 return IXGBE_ERR_PARAM;
3860 * this is a 2 part operation - first the VFTA, then the
3861 * VLVF and VLVFB if VT Mode is set
3862 * We don't write the VFTA until we know the VLVF part succeeded.
3866 * The VFTA is a bitstring made up of 128 32-bit registers
3867 * that enable the particular VLAN id, much like the MTA:
3868 * bits[11-5]: which register
3869 * bits[4-0]: which bit in the register
3871 regindex = (vlan >> 5) & 0x7F;
3872 bitindex = vlan & 0x1F;
3873 targetbit = (1 << bitindex);
3874 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3877 if (!(vfta & targetbit)) {
3879 vfta_changed = true;
3882 if ((vfta & targetbit)) {
3884 vfta_changed = true;
3889 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3891 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3893 if (ret_val != IXGBE_SUCCESS)
3897 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3899 return IXGBE_SUCCESS;
3903 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3904 * @hw: pointer to hardware structure
3905 * @vlan: VLAN id to write to VLAN filter
3906 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3907 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3908 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3911 * Turn on/off specified bit in VLVF table.
3913 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3914 bool vlan_on, bool *vfta_changed)
3918 DEBUGFUNC("ixgbe_set_vlvf_generic");
3921 return IXGBE_ERR_PARAM;
3923 /* If VT Mode is set
3925 * make sure the vlan is in VLVF
3926 * set the vind bit in the matching VLVFB
3928 * clear the pool bit and possibly the vind
3930 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3931 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3935 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3940 /* set the pool bit */
3942 bits = IXGBE_READ_REG(hw,
3943 IXGBE_VLVFB(vlvf_index * 2));
3944 bits |= (1 << vind);
3946 IXGBE_VLVFB(vlvf_index * 2),
3949 bits = IXGBE_READ_REG(hw,
3950 IXGBE_VLVFB((vlvf_index * 2) + 1));
3951 bits |= (1 << (vind - 32));
3953 IXGBE_VLVFB((vlvf_index * 2) + 1),
3957 /* clear the pool bit */
3959 bits = IXGBE_READ_REG(hw,
3960 IXGBE_VLVFB(vlvf_index * 2));
3961 bits &= ~(1 << vind);
3963 IXGBE_VLVFB(vlvf_index * 2),
3965 bits |= IXGBE_READ_REG(hw,
3966 IXGBE_VLVFB((vlvf_index * 2) + 1));
3968 bits = IXGBE_READ_REG(hw,
3969 IXGBE_VLVFB((vlvf_index * 2) + 1));
3970 bits &= ~(1 << (vind - 32));
3972 IXGBE_VLVFB((vlvf_index * 2) + 1),
3974 bits |= IXGBE_READ_REG(hw,
3975 IXGBE_VLVFB(vlvf_index * 2));
3980 * If there are still bits set in the VLVFB registers
3981 * for the VLAN ID indicated we need to see if the
3982 * caller is requesting that we clear the VFTA entry bit.
3983 * If the caller has requested that we clear the VFTA
3984 * entry bit but there are still pools/VFs using this VLAN
3985 * ID entry then ignore the request. We're not worried
3986 * about the case where we're turning the VFTA VLAN ID
3987 * entry bit on, only when requested to turn it off as
3988 * there may be multiple pools and/or VFs using the
3989 * VLAN ID entry. In that case we cannot clear the
3990 * VFTA bit until all pools/VFs using that VLAN ID have also
3991 * been cleared. This will be indicated by "bits" being
3995 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3996 (IXGBE_VLVF_VIEN | vlan));
3997 if ((!vlan_on) && (vfta_changed != NULL)) {
3998 /* someone wants to clear the vfta entry
3999 * but some pools/VFs are still using it.
4001 *vfta_changed = false;
4004 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
4007 return IXGBE_SUCCESS;
4011 * ixgbe_clear_vfta_generic - Clear VLAN filter table
4012 * @hw: pointer to hardware structure
4014 * Clears the VLAN filer table, and the VMDq index associated with the filter
4016 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
4020 DEBUGFUNC("ixgbe_clear_vfta_generic");
4022 for (offset = 0; offset < hw->mac.vft_size; offset++)
4023 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
4025 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
4026 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
4027 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
4028 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
4031 return IXGBE_SUCCESS;
4035 * ixgbe_check_mac_link_generic - Determine link and speed status
4036 * @hw: pointer to hardware structure
4037 * @speed: pointer to link speed
4038 * @link_up: true when link is up
4039 * @link_up_wait_to_complete: bool used to wait for link up or not
4041 * Reads the links register to determine if link is up and the current speed
4043 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
4044 bool *link_up, bool link_up_wait_to_complete)
4046 u32 links_reg, links_orig;
4049 DEBUGFUNC("ixgbe_check_mac_link_generic");
4051 /* clear the old state */
4052 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
4054 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4056 if (links_orig != links_reg) {
4057 DEBUGOUT2("LINKS changed from %08X to %08X\n",
4058 links_orig, links_reg);
4061 if (link_up_wait_to_complete) {
4062 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
4063 if (links_reg & IXGBE_LINKS_UP) {
4070 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4073 if (links_reg & IXGBE_LINKS_UP)
4079 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4080 IXGBE_LINKS_SPEED_10G_82599)
4081 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4082 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4083 IXGBE_LINKS_SPEED_1G_82599)
4084 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4085 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4086 IXGBE_LINKS_SPEED_100_82599)
4087 *speed = IXGBE_LINK_SPEED_100_FULL;
4089 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4091 return IXGBE_SUCCESS;
4095 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4097 * @hw: pointer to hardware structure
4098 * @wwnn_prefix: the alternative WWNN prefix
4099 * @wwpn_prefix: the alternative WWPN prefix
4101 * This function will read the EEPROM from the alternative SAN MAC address
4102 * block to check the support for the alternative WWNN/WWPN prefix support.
4104 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4108 u16 alt_san_mac_blk_offset;
4110 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4112 /* clear output first */
4113 *wwnn_prefix = 0xFFFF;
4114 *wwpn_prefix = 0xFFFF;
4116 /* check if alternative SAN MAC is supported */
4117 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4118 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4119 goto wwn_prefix_err;
4121 if ((alt_san_mac_blk_offset == 0) ||
4122 (alt_san_mac_blk_offset == 0xFFFF))
4123 goto wwn_prefix_out;
4125 /* check capability in alternative san mac address block */
4126 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4127 if (hw->eeprom.ops.read(hw, offset, &caps))
4128 goto wwn_prefix_err;
4129 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4130 goto wwn_prefix_out;
4132 /* get the corresponding prefix for WWNN/WWPN */
4133 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4134 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4135 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4136 "eeprom read at offset %d failed", offset);
4139 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4140 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4141 goto wwn_prefix_err;
4144 return IXGBE_SUCCESS;
4147 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4148 "eeprom read at offset %d failed", offset);
4149 return IXGBE_SUCCESS;
4153 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4154 * @hw: pointer to hardware structure
4155 * @bs: the fcoe boot status
4157 * This function will read the FCOE boot status from the iSCSI FCOE block
4159 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4161 u16 offset, caps, flags;
4164 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4166 /* clear output first */
4167 *bs = ixgbe_fcoe_bootstatus_unavailable;
4169 /* check if FCOE IBA block is present */
4170 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4171 status = hw->eeprom.ops.read(hw, offset, &caps);
4172 if (status != IXGBE_SUCCESS)
4175 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4178 /* check if iSCSI FCOE block is populated */
4179 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4180 if (status != IXGBE_SUCCESS)
4183 if ((offset == 0) || (offset == 0xFFFF))
4186 /* read fcoe flags in iSCSI FCOE block */
4187 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4188 status = hw->eeprom.ops.read(hw, offset, &flags);
4189 if (status != IXGBE_SUCCESS)
4192 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4193 *bs = ixgbe_fcoe_bootstatus_enabled;
4195 *bs = ixgbe_fcoe_bootstatus_disabled;
4202 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4203 * @hw: pointer to hardware structure
4204 * @enable: enable or disable switch for anti-spoofing
4205 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
4208 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
4211 int pf_target_reg = pf >> 3;
4212 int pf_target_shift = pf % 8;
4215 if (hw->mac.type == ixgbe_mac_82598EB)
4219 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
4222 * PFVFSPOOF register array is size 8 with 8 bits assigned to
4223 * MAC anti-spoof enables in each register array element.
4225 for (j = 0; j < pf_target_reg; j++)
4226 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4229 * The PF should be allowed to spoof so that it can support
4230 * emulation mode NICs. Do not set the bits assigned to the PF
4232 pfvfspoof &= (1 << pf_target_shift) - 1;
4233 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4236 * Remaining pools belong to the PF so they do not need to have
4237 * anti-spoofing enabled.
4239 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
4240 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
4244 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4245 * @hw: pointer to hardware structure
4246 * @enable: enable or disable switch for VLAN anti-spoofing
4247 * @vf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4250 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4252 int vf_target_reg = vf >> 3;
4253 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4256 if (hw->mac.type == ixgbe_mac_82598EB)
4259 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4261 pfvfspoof |= (1 << vf_target_shift);
4263 pfvfspoof &= ~(1 << vf_target_shift);
4264 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4268 * ixgbe_get_device_caps_generic - Get additional device capabilities
4269 * @hw: pointer to hardware structure
4270 * @device_caps: the EEPROM word with the extra device capabilities
4272 * This function will read the EEPROM location for the device capabilities,
4273 * and return the word through device_caps.
4275 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4277 DEBUGFUNC("ixgbe_get_device_caps_generic");
4279 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4281 return IXGBE_SUCCESS;
4285 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4286 * @hw: pointer to hardware structure
4289 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4294 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4296 /* Enable relaxed ordering */
4297 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4298 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4299 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4300 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4303 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4304 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4305 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4306 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4307 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4313 * ixgbe_calculate_checksum - Calculate checksum for buffer
4314 * @buffer: pointer to EEPROM
4315 * @length: size of EEPROM to calculate a checksum for
4316 * Calculates the checksum for some buffer on a specified length. The
4317 * checksum calculated is returned.
4319 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4324 DEBUGFUNC("ixgbe_calculate_checksum");
4329 for (i = 0; i < length; i++)
4332 return (u8) (0 - sum);
4336 * ixgbe_host_interface_command - Issue command to manageability block
4337 * @hw: pointer to the HW structure
4338 * @buffer: contains the command to write and where the return status will
4340 * @length: length of buffer, must be multiple of 4 bytes
4341 * @return_data: read and return data from the buffer (true) or not (false)
4342 * Needed because FW structures are big endian and decoding of
4343 * these fields can be 8 bit or 16 bit based on command. Decoding
4344 * is not easily understood without making a table of commands.
4345 * So we will leave this up to the caller to read back the data
4348 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4349 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
4351 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4352 u32 length, bool return_data)
4354 u32 hicr, i, bi, fwsts;
4355 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4359 DEBUGFUNC("ixgbe_host_interface_command");
4361 if (length == 0 || length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4362 DEBUGOUT1("Buffer length failure buffersize=%d.\n", length);
4363 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4365 /* Set bit 9 of FWSTS clearing FW reset indication */
4366 fwsts = IXGBE_READ_REG(hw, IXGBE_FWSTS);
4367 IXGBE_WRITE_REG(hw, IXGBE_FWSTS, fwsts | IXGBE_FWSTS_FWRI);
4369 /* Check that the host interface is enabled. */
4370 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4371 if ((hicr & IXGBE_HICR_EN) == 0) {
4372 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4373 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4376 /* Calculate length in DWORDs. We must be DWORD aligned */
4377 if ((length % (sizeof(u32))) != 0) {
4378 DEBUGOUT("Buffer length failure, not aligned to dword");
4379 return IXGBE_ERR_INVALID_ARGUMENT;
4382 dword_len = length >> 2;
4384 /* The device driver writes the relevant command block
4385 * into the ram area.
4387 for (i = 0; i < dword_len; i++)
4388 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4389 i, IXGBE_CPU_TO_LE32(buffer[i]));
4391 /* Setting this bit tells the ARC that a new command is pending. */
4392 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4394 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
4395 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4396 if (!(hicr & IXGBE_HICR_C))
4401 /* Check command completion */
4402 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
4403 !(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV)) {
4404 ERROR_REPORT1(IXGBE_ERROR_CAUTION,
4405 "Command has failed with no status valid.\n");
4406 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4412 /* Calculate length in DWORDs */
4413 dword_len = hdr_size >> 2;
4415 /* first pull in the header so we know the buffer length */
4416 for (bi = 0; bi < dword_len; bi++) {
4417 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4418 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4421 /* If there is any thing in data position pull it in */
4422 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4426 if (length < buf_len + hdr_size) {
4427 DEBUGOUT("Buffer not large enough for reply message.\n");
4428 return IXGBE_ERR_HOST_INTERFACE_COMMAND;
4431 /* Calculate length in DWORDs, add 3 for odd lengths */
4432 dword_len = (buf_len + 3) >> 2;
4434 /* Pull in the rest of the buffer (bi is where we left off) */
4435 for (; bi <= dword_len; bi++) {
4436 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4437 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4444 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4445 * @hw: pointer to the HW structure
4446 * @maj: driver version major number
4447 * @min: driver version minor number
4448 * @build: driver version build number
4449 * @sub: driver version sub build number
4451 * Sends driver version number to firmware through the manageability
4452 * block. On success return IXGBE_SUCCESS
4453 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4454 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4456 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4459 struct ixgbe_hic_drv_info fw_cmd;
4461 s32 ret_val = IXGBE_SUCCESS;
4463 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4465 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
4467 ret_val = IXGBE_ERR_SWFW_SYNC;
4471 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4472 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4473 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4474 fw_cmd.port_num = (u8)hw->bus.func;
4475 fw_cmd.ver_maj = maj;
4476 fw_cmd.ver_min = min;
4477 fw_cmd.ver_build = build;
4478 fw_cmd.ver_sub = sub;
4479 fw_cmd.hdr.checksum = 0;
4480 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4481 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4485 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4486 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4487 sizeof(fw_cmd), true);
4488 if (ret_val != IXGBE_SUCCESS)
4491 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4492 FW_CEM_RESP_STATUS_SUCCESS)
4493 ret_val = IXGBE_SUCCESS;
4495 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4500 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4506 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4507 * @hw: pointer to hardware structure
4508 * @num_pb: number of packet buffers to allocate
4509 * @headroom: reserve n KB of headroom
4510 * @strategy: packet buffer allocation strategy
4512 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4515 u32 pbsize = hw->mac.rx_pb_size;
4517 u32 rxpktsize, txpktsize, txpbthresh;
4519 /* Reserve headroom */
4525 /* Divide remaining packet buffer space amongst the number of packet
4526 * buffers requested using supplied strategy.
4529 case PBA_STRATEGY_WEIGHTED:
4530 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4531 * buffer with 5/8 of the packet buffer space.
4533 rxpktsize = (pbsize * 5) / (num_pb * 4);
4534 pbsize -= rxpktsize * (num_pb / 2);
4535 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4536 for (; i < (num_pb / 2); i++)
4537 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4538 /* Fall through to configure remaining packet buffers */
4539 case PBA_STRATEGY_EQUAL:
4540 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4541 for (; i < num_pb; i++)
4542 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4548 /* Only support an equally distributed Tx packet buffer strategy. */
4549 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4550 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4551 for (i = 0; i < num_pb; i++) {
4552 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4553 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4556 /* Clear unused TCs, if any, to zero buffer size*/
4557 for (; i < IXGBE_MAX_PB; i++) {
4558 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4559 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4560 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4565 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4566 * @hw: pointer to the hardware structure
4568 * The 82599 and x540 MACs can experience issues if TX work is still pending
4569 * when a reset occurs. This function prevents this by flushing the PCIe
4570 * buffers on the system.
4572 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4574 u32 gcr_ext, hlreg0;
4577 * If double reset is not requested then all transactions should
4578 * already be clear and as such there is no work to do
4580 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4584 * Set loopback enable to prevent any transmits from being sent
4585 * should the link come up. This assumes that the RXCTRL.RXEN bit
4586 * has already been cleared.
4588 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4589 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4591 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4592 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4593 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4594 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4596 /* Flush all writes and allow 20usec for all transactions to clear */
4597 IXGBE_WRITE_FLUSH(hw);
4600 /* restore previous register values */
4601 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4602 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4607 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4608 * @hw: pointer to hardware structure
4609 * @map: pointer to u8 arr for returning map
4611 * Read the rtrup2tc HW register and resolve its content into map
4613 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4617 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4618 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4619 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4620 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));
4624 void ixgbe_disable_rx_generic(struct ixgbe_hw *hw)
4629 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4630 if (rxctrl & IXGBE_RXCTRL_RXEN) {
4631 if (hw->mac.type != ixgbe_mac_82598EB) {
4632 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4633 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) {
4634 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN;
4635 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4636 hw->mac.set_lben = true;
4638 hw->mac.set_lben = false;
4641 rxctrl &= ~IXGBE_RXCTRL_RXEN;
4642 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl);
4646 void ixgbe_enable_rx_generic(struct ixgbe_hw *hw)
4651 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4652 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, (rxctrl | IXGBE_RXCTRL_RXEN));
4654 if (hw->mac.type != ixgbe_mac_82598EB) {
4655 if (hw->mac.set_lben) {
4656 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC);
4657 pfdtxgswc |= IXGBE_PFDTXGSWC_VT_LBEN;
4658 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc);
4659 hw->mac.set_lben = false;
4665 * ixgbe_mng_enabled - Is the manageability engine enabled?
4666 * @hw: pointer to hardware structure
4668 * Returns true if the manageability engine is enabled.
4670 bool ixgbe_mng_enabled(struct ixgbe_hw *hw)
4672 u32 fwsm, manc, factps;
4674 fwsm = IXGBE_READ_REG(hw, IXGBE_FWSM);
4675 if ((fwsm & IXGBE_FWSM_MODE_MASK) != IXGBE_FWSM_FW_MODE_PT)
4678 manc = IXGBE_READ_REG(hw, IXGBE_MANC);
4679 if (!(manc & IXGBE_MANC_RCV_TCO_EN))
4682 if (hw->mac.type <= ixgbe_mac_X540) {
4683 factps = IXGBE_READ_REG(hw, IXGBE_FACTPS);
4684 if (factps & IXGBE_FACTPS_MNGCG)