1 /*******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_common.h"
35 #include "ixgbe_phy.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82599.h"
38 #include "ixgbe_api.h"
39 #ident "$Id: ixgbe_common.c,v 1.382 2013/11/22 01:02:01 jtkirshe Exp $"
41 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw);
42 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw);
43 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw);
44 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw);
45 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw);
46 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
48 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count);
49 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
50 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec);
51 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw);
53 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr);
54 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
56 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
57 u16 words, u16 *data);
58 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
59 u16 words, u16 *data);
60 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
64 * ixgbe_init_ops_generic - Inits function ptrs
65 * @hw: pointer to the hardware structure
67 * Initialize the function pointers.
69 s32 ixgbe_init_ops_generic(struct ixgbe_hw *hw)
71 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
72 struct ixgbe_mac_info *mac = &hw->mac;
73 u32 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
75 DEBUGFUNC("ixgbe_init_ops_generic");
78 eeprom->ops.init_params = &ixgbe_init_eeprom_params_generic;
79 /* If EEPROM is valid (bit 8 = 1), use EERD otherwise use bit bang */
80 if (eec & IXGBE_EEC_PRES) {
81 eeprom->ops.read = &ixgbe_read_eerd_generic;
82 eeprom->ops.read_buffer = &ixgbe_read_eerd_buffer_generic;
84 eeprom->ops.read = &ixgbe_read_eeprom_bit_bang_generic;
85 eeprom->ops.read_buffer =
86 &ixgbe_read_eeprom_buffer_bit_bang_generic;
88 eeprom->ops.write = &ixgbe_write_eeprom_generic;
89 eeprom->ops.write_buffer = &ixgbe_write_eeprom_buffer_bit_bang_generic;
90 eeprom->ops.validate_checksum =
91 &ixgbe_validate_eeprom_checksum_generic;
92 eeprom->ops.update_checksum = &ixgbe_update_eeprom_checksum_generic;
93 eeprom->ops.calc_checksum = &ixgbe_calc_eeprom_checksum_generic;
96 mac->ops.init_hw = &ixgbe_init_hw_generic;
97 mac->ops.reset_hw = NULL;
98 mac->ops.start_hw = &ixgbe_start_hw_generic;
99 mac->ops.clear_hw_cntrs = &ixgbe_clear_hw_cntrs_generic;
100 mac->ops.get_media_type = NULL;
101 mac->ops.get_supported_physical_layer = NULL;
102 mac->ops.enable_rx_dma = &ixgbe_enable_rx_dma_generic;
103 mac->ops.get_mac_addr = &ixgbe_get_mac_addr_generic;
104 mac->ops.stop_adapter = &ixgbe_stop_adapter_generic;
105 mac->ops.get_bus_info = &ixgbe_get_bus_info_generic;
106 mac->ops.set_lan_id = &ixgbe_set_lan_id_multi_port_pcie;
107 mac->ops.acquire_swfw_sync = &ixgbe_acquire_swfw_sync;
108 mac->ops.release_swfw_sync = &ixgbe_release_swfw_sync;
111 mac->ops.led_on = &ixgbe_led_on_generic;
112 mac->ops.led_off = &ixgbe_led_off_generic;
113 mac->ops.blink_led_start = &ixgbe_blink_led_start_generic;
114 mac->ops.blink_led_stop = &ixgbe_blink_led_stop_generic;
116 /* RAR, Multicast, VLAN */
117 mac->ops.set_rar = &ixgbe_set_rar_generic;
118 mac->ops.clear_rar = &ixgbe_clear_rar_generic;
119 mac->ops.insert_mac_addr = NULL;
120 mac->ops.set_vmdq = NULL;
121 mac->ops.clear_vmdq = NULL;
122 mac->ops.init_rx_addrs = &ixgbe_init_rx_addrs_generic;
123 mac->ops.update_uc_addr_list = &ixgbe_update_uc_addr_list_generic;
124 mac->ops.update_mc_addr_list = &ixgbe_update_mc_addr_list_generic;
125 mac->ops.enable_mc = &ixgbe_enable_mc_generic;
126 mac->ops.disable_mc = &ixgbe_disable_mc_generic;
127 mac->ops.clear_vfta = NULL;
128 mac->ops.set_vfta = NULL;
129 mac->ops.set_vlvf = NULL;
130 mac->ops.init_uta_tables = NULL;
133 mac->ops.fc_enable = &ixgbe_fc_enable_generic;
136 mac->ops.get_link_capabilities = NULL;
137 mac->ops.setup_link = NULL;
138 mac->ops.check_link = NULL;
140 return IXGBE_SUCCESS;
144 * ixgbe_device_supports_autoneg_fc - Check if device supports autonegotiation
146 * @hw: pointer to hardware structure
148 * This function returns true if the device supports flow control
149 * autonegotiation, and false if it does not.
152 s32 ixgbe_device_supports_autoneg_fc(struct ixgbe_hw *hw)
155 DEBUGFUNC("ixgbe_device_supports_autoneg_fc");
157 switch (hw->device_id) {
158 case IXGBE_DEV_ID_X540T:
159 case IXGBE_DEV_ID_X540T1:
160 case IXGBE_DEV_ID_82599_T3_LOM:
161 return IXGBE_SUCCESS;
163 return IXGBE_ERR_FC_NOT_SUPPORTED;
168 * ixgbe_setup_fc - Set up flow control
169 * @hw: pointer to hardware structure
171 * Called at init time to set up flow control.
173 STATIC s32 ixgbe_setup_fc(struct ixgbe_hw *hw)
175 s32 ret_val = IXGBE_SUCCESS;
176 u32 reg = 0, reg_bp = 0;
178 bool got_lock = false;
180 DEBUGFUNC("ixgbe_setup_fc");
183 * Validate the requested mode. Strict IEEE mode does not allow
184 * ixgbe_fc_rx_pause because it will cause us to fail at UNH.
186 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) {
187 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
188 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n");
189 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
194 * 10gig parts do not have a word in the EEPROM to determine the
195 * default flow control setting, so we explicitly set it to full.
197 if (hw->fc.requested_mode == ixgbe_fc_default)
198 hw->fc.requested_mode = ixgbe_fc_full;
201 * Set up the 1G and 10G flow control advertisement registers so the
202 * HW will be able to do fc autoneg once the cable is plugged in. If
203 * we link at 10G, the 1G advertisement is harmless and vice versa.
205 switch (hw->phy.media_type) {
206 case ixgbe_media_type_fiber:
207 case ixgbe_media_type_backplane:
208 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
209 reg_bp = IXGBE_READ_REG(hw, IXGBE_AUTOC);
211 case ixgbe_media_type_copper:
212 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
213 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®_cu);
220 * The possible values of fc.requested_mode are:
221 * 0: Flow control is completely disabled
222 * 1: Rx flow control is enabled (we can receive pause frames,
223 * but not send pause frames).
224 * 2: Tx flow control is enabled (we can send pause frames but
225 * we do not support receiving pause frames).
226 * 3: Both Rx and Tx flow control (symmetric) are enabled.
229 switch (hw->fc.requested_mode) {
231 /* Flow control completely disabled by software override. */
232 reg &= ~(IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE);
233 if (hw->phy.media_type == ixgbe_media_type_backplane)
234 reg_bp &= ~(IXGBE_AUTOC_SYM_PAUSE |
235 IXGBE_AUTOC_ASM_PAUSE);
236 else if (hw->phy.media_type == ixgbe_media_type_copper)
237 reg_cu &= ~(IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE);
239 case ixgbe_fc_tx_pause:
241 * Tx Flow control is enabled, and Rx Flow control is
242 * disabled by software override.
244 reg |= IXGBE_PCS1GANA_ASM_PAUSE;
245 reg &= ~IXGBE_PCS1GANA_SYM_PAUSE;
246 if (hw->phy.media_type == ixgbe_media_type_backplane) {
247 reg_bp |= IXGBE_AUTOC_ASM_PAUSE;
248 reg_bp &= ~IXGBE_AUTOC_SYM_PAUSE;
249 } else if (hw->phy.media_type == ixgbe_media_type_copper) {
250 reg_cu |= IXGBE_TAF_ASM_PAUSE;
251 reg_cu &= ~IXGBE_TAF_SYM_PAUSE;
254 case ixgbe_fc_rx_pause:
256 * Rx Flow control is enabled and Tx Flow control is
257 * disabled by software override. Since there really
258 * isn't a way to advertise that we are capable of RX
259 * Pause ONLY, we will advertise that we support both
260 * symmetric and asymmetric Rx PAUSE, as such we fall
261 * through to the fc_full statement. Later, we will
262 * disable the adapter's ability to send PAUSE frames.
265 /* Flow control (both Rx and Tx) is enabled by SW override. */
266 reg |= IXGBE_PCS1GANA_SYM_PAUSE | IXGBE_PCS1GANA_ASM_PAUSE;
267 if (hw->phy.media_type == ixgbe_media_type_backplane)
268 reg_bp |= IXGBE_AUTOC_SYM_PAUSE |
269 IXGBE_AUTOC_ASM_PAUSE;
270 else if (hw->phy.media_type == ixgbe_media_type_copper)
271 reg_cu |= IXGBE_TAF_SYM_PAUSE | IXGBE_TAF_ASM_PAUSE;
274 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
275 "Flow control param set incorrectly\n");
276 ret_val = IXGBE_ERR_CONFIG;
281 if (hw->mac.type < ixgbe_mac_X540) {
283 * Enable auto-negotiation between the MAC & PHY;
284 * the MAC will advertise clause 37 flow control.
286 IXGBE_WRITE_REG(hw, IXGBE_PCS1GANA, reg);
287 reg = IXGBE_READ_REG(hw, IXGBE_PCS1GLCTL);
289 /* Disable AN timeout */
290 if (hw->fc.strict_ieee)
291 reg &= ~IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN;
293 IXGBE_WRITE_REG(hw, IXGBE_PCS1GLCTL, reg);
294 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
298 * AUTOC restart handles negotiation of 1G and 10G on backplane
299 * and copper. There is no need to set the PCS1GCTL register.
302 if (hw->phy.media_type == ixgbe_media_type_backplane) {
303 reg_bp |= IXGBE_AUTOC_AN_RESTART;
304 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
305 * LESM is on, likewise reset_pipeline requries the lock as
306 * it also writes AUTOC.
308 if ((hw->mac.type == ixgbe_mac_82599EB) &&
309 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
310 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
311 IXGBE_GSSR_MAC_CSR_SM);
312 if (ret_val != IXGBE_SUCCESS) {
313 ret_val = IXGBE_ERR_SWFW_SYNC;
319 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, reg_bp);
320 if (hw->mac.type == ixgbe_mac_82599EB)
321 ixgbe_reset_pipeline_82599(hw);
324 hw->mac.ops.release_swfw_sync(hw,
325 IXGBE_GSSR_MAC_CSR_SM);
326 } else if ((hw->phy.media_type == ixgbe_media_type_copper) &&
327 (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)) {
328 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
329 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg_cu);
332 DEBUGOUT1("Set up FC; PCS1GLCTL = 0x%08X\n", reg);
338 * ixgbe_start_hw_generic - Prepare hardware for Tx/Rx
339 * @hw: pointer to hardware structure
341 * Starts the hardware by filling the bus info structure and media type, clears
342 * all on chip counters, initializes receive address registers, multicast
343 * table, VLAN filter table, calls routine to set up link and flow control
344 * settings, and leaves transmit and receive units disabled and uninitialized
346 s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
351 DEBUGFUNC("ixgbe_start_hw_generic");
353 /* Set the media type */
354 hw->phy.media_type = hw->mac.ops.get_media_type(hw);
356 /* PHY ops initialization must be done in reset_hw() */
358 /* Clear the VLAN filter table */
359 hw->mac.ops.clear_vfta(hw);
361 /* Clear statistics registers */
362 hw->mac.ops.clear_hw_cntrs(hw);
364 /* Set No Snoop Disable */
365 ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
366 ctrl_ext |= IXGBE_CTRL_EXT_NS_DIS;
367 IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
368 IXGBE_WRITE_FLUSH(hw);
370 /* Setup flow control */
371 ret_val = ixgbe_setup_fc(hw);
372 if (ret_val != IXGBE_SUCCESS)
375 /* Clear adapter stopped flag */
376 hw->adapter_stopped = false;
383 * ixgbe_start_hw_gen2 - Init sequence for common device family
384 * @hw: pointer to hw structure
386 * Performs the init sequence common to the second generation
388 * Devices in the second generation:
392 s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
397 /* Clear the rate limiters */
398 for (i = 0; i < hw->mac.max_tx_queues; i++) {
399 IXGBE_WRITE_REG(hw, IXGBE_RTTDQSEL, i);
400 IXGBE_WRITE_REG(hw, IXGBE_RTTBCNRC, 0);
402 IXGBE_WRITE_FLUSH(hw);
404 /* Disable relaxed ordering */
405 for (i = 0; i < hw->mac.max_tx_queues; i++) {
406 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
407 regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
408 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
411 for (i = 0; i < hw->mac.max_rx_queues; i++) {
412 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
413 regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
414 IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
415 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
418 return IXGBE_SUCCESS;
422 * ixgbe_init_hw_generic - Generic hardware initialization
423 * @hw: pointer to hardware structure
425 * Initialize the hardware by resetting the hardware, filling the bus info
426 * structure and media type, clears all on chip counters, initializes receive
427 * address registers, multicast table, VLAN filter table, calls routine to set
428 * up link and flow control settings, and leaves transmit and receive units
429 * disabled and uninitialized
431 s32 ixgbe_init_hw_generic(struct ixgbe_hw *hw)
435 DEBUGFUNC("ixgbe_init_hw_generic");
437 /* Reset the hardware */
438 status = hw->mac.ops.reset_hw(hw);
440 if (status == IXGBE_SUCCESS) {
442 status = hw->mac.ops.start_hw(hw);
449 * ixgbe_clear_hw_cntrs_generic - Generic clear hardware counters
450 * @hw: pointer to hardware structure
452 * Clears all hardware statistics counters by reading them from the hardware
453 * Statistics counters are clear on read.
455 s32 ixgbe_clear_hw_cntrs_generic(struct ixgbe_hw *hw)
459 DEBUGFUNC("ixgbe_clear_hw_cntrs_generic");
461 IXGBE_READ_REG(hw, IXGBE_CRCERRS);
462 IXGBE_READ_REG(hw, IXGBE_ILLERRC);
463 IXGBE_READ_REG(hw, IXGBE_ERRBC);
464 IXGBE_READ_REG(hw, IXGBE_MSPDC);
465 for (i = 0; i < 8; i++)
466 IXGBE_READ_REG(hw, IXGBE_MPC(i));
468 IXGBE_READ_REG(hw, IXGBE_MLFC);
469 IXGBE_READ_REG(hw, IXGBE_MRFC);
470 IXGBE_READ_REG(hw, IXGBE_RLEC);
471 IXGBE_READ_REG(hw, IXGBE_LXONTXC);
472 IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
473 if (hw->mac.type >= ixgbe_mac_82599EB) {
474 IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
475 IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
477 IXGBE_READ_REG(hw, IXGBE_LXONRXC);
478 IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
481 for (i = 0; i < 8; i++) {
482 IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
483 IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
484 if (hw->mac.type >= ixgbe_mac_82599EB) {
485 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
486 IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
488 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
489 IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
492 if (hw->mac.type >= ixgbe_mac_82599EB)
493 for (i = 0; i < 8; i++)
494 IXGBE_READ_REG(hw, IXGBE_PXON2OFFCNT(i));
495 IXGBE_READ_REG(hw, IXGBE_PRC64);
496 IXGBE_READ_REG(hw, IXGBE_PRC127);
497 IXGBE_READ_REG(hw, IXGBE_PRC255);
498 IXGBE_READ_REG(hw, IXGBE_PRC511);
499 IXGBE_READ_REG(hw, IXGBE_PRC1023);
500 IXGBE_READ_REG(hw, IXGBE_PRC1522);
501 IXGBE_READ_REG(hw, IXGBE_GPRC);
502 IXGBE_READ_REG(hw, IXGBE_BPRC);
503 IXGBE_READ_REG(hw, IXGBE_MPRC);
504 IXGBE_READ_REG(hw, IXGBE_GPTC);
505 IXGBE_READ_REG(hw, IXGBE_GORCL);
506 IXGBE_READ_REG(hw, IXGBE_GORCH);
507 IXGBE_READ_REG(hw, IXGBE_GOTCL);
508 IXGBE_READ_REG(hw, IXGBE_GOTCH);
509 if (hw->mac.type == ixgbe_mac_82598EB)
510 for (i = 0; i < 8; i++)
511 IXGBE_READ_REG(hw, IXGBE_RNBC(i));
512 IXGBE_READ_REG(hw, IXGBE_RUC);
513 IXGBE_READ_REG(hw, IXGBE_RFC);
514 IXGBE_READ_REG(hw, IXGBE_ROC);
515 IXGBE_READ_REG(hw, IXGBE_RJC);
516 IXGBE_READ_REG(hw, IXGBE_MNGPRC);
517 IXGBE_READ_REG(hw, IXGBE_MNGPDC);
518 IXGBE_READ_REG(hw, IXGBE_MNGPTC);
519 IXGBE_READ_REG(hw, IXGBE_TORL);
520 IXGBE_READ_REG(hw, IXGBE_TORH);
521 IXGBE_READ_REG(hw, IXGBE_TPR);
522 IXGBE_READ_REG(hw, IXGBE_TPT);
523 IXGBE_READ_REG(hw, IXGBE_PTC64);
524 IXGBE_READ_REG(hw, IXGBE_PTC127);
525 IXGBE_READ_REG(hw, IXGBE_PTC255);
526 IXGBE_READ_REG(hw, IXGBE_PTC511);
527 IXGBE_READ_REG(hw, IXGBE_PTC1023);
528 IXGBE_READ_REG(hw, IXGBE_PTC1522);
529 IXGBE_READ_REG(hw, IXGBE_MPTC);
530 IXGBE_READ_REG(hw, IXGBE_BPTC);
531 for (i = 0; i < 16; i++) {
532 IXGBE_READ_REG(hw, IXGBE_QPRC(i));
533 IXGBE_READ_REG(hw, IXGBE_QPTC(i));
534 if (hw->mac.type >= ixgbe_mac_82599EB) {
535 IXGBE_READ_REG(hw, IXGBE_QBRC_L(i));
536 IXGBE_READ_REG(hw, IXGBE_QBRC_H(i));
537 IXGBE_READ_REG(hw, IXGBE_QBTC_L(i));
538 IXGBE_READ_REG(hw, IXGBE_QBTC_H(i));
539 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
541 IXGBE_READ_REG(hw, IXGBE_QBRC(i));
542 IXGBE_READ_REG(hw, IXGBE_QBTC(i));
546 if (hw->mac.type == ixgbe_mac_X540) {
548 ixgbe_identify_phy(hw);
549 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECL,
550 IXGBE_MDIO_PCS_DEV_TYPE, &i);
551 hw->phy.ops.read_reg(hw, IXGBE_PCRC8ECH,
552 IXGBE_MDIO_PCS_DEV_TYPE, &i);
553 hw->phy.ops.read_reg(hw, IXGBE_LDPCECL,
554 IXGBE_MDIO_PCS_DEV_TYPE, &i);
555 hw->phy.ops.read_reg(hw, IXGBE_LDPCECH,
556 IXGBE_MDIO_PCS_DEV_TYPE, &i);
559 return IXGBE_SUCCESS;
563 * ixgbe_read_pba_string_generic - Reads part number string from EEPROM
564 * @hw: pointer to hardware structure
565 * @pba_num: stores the part number string from the EEPROM
566 * @pba_num_size: part number string buffer length
568 * Reads the part number string from the EEPROM.
570 s32 ixgbe_read_pba_string_generic(struct ixgbe_hw *hw, u8 *pba_num,
579 DEBUGFUNC("ixgbe_read_pba_string_generic");
581 if (pba_num == NULL) {
582 DEBUGOUT("PBA string buffer was null\n");
583 return IXGBE_ERR_INVALID_ARGUMENT;
586 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
588 DEBUGOUT("NVM Read Error\n");
592 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &pba_ptr);
594 DEBUGOUT("NVM Read Error\n");
599 * if data is not ptr guard the PBA must be in legacy format which
600 * means pba_ptr is actually our second data word for the PBA number
601 * and we can decode it into an ascii string
603 if (data != IXGBE_PBANUM_PTR_GUARD) {
604 DEBUGOUT("NVM PBA number is not stored as string\n");
606 /* we will need 11 characters to store the PBA */
607 if (pba_num_size < 11) {
608 DEBUGOUT("PBA string buffer too small\n");
609 return IXGBE_ERR_NO_SPACE;
612 /* extract hex string from data and pba_ptr */
613 pba_num[0] = (data >> 12) & 0xF;
614 pba_num[1] = (data >> 8) & 0xF;
615 pba_num[2] = (data >> 4) & 0xF;
616 pba_num[3] = data & 0xF;
617 pba_num[4] = (pba_ptr >> 12) & 0xF;
618 pba_num[5] = (pba_ptr >> 8) & 0xF;
621 pba_num[8] = (pba_ptr >> 4) & 0xF;
622 pba_num[9] = pba_ptr & 0xF;
624 /* put a null character on the end of our string */
627 /* switch all the data but the '-' to hex char */
628 for (offset = 0; offset < 10; offset++) {
629 if (pba_num[offset] < 0xA)
630 pba_num[offset] += '0';
631 else if (pba_num[offset] < 0x10)
632 pba_num[offset] += 'A' - 0xA;
635 return IXGBE_SUCCESS;
638 ret_val = hw->eeprom.ops.read(hw, pba_ptr, &length);
640 DEBUGOUT("NVM Read Error\n");
644 if (length == 0xFFFF || length == 0) {
645 DEBUGOUT("NVM PBA number section invalid length\n");
646 return IXGBE_ERR_PBA_SECTION;
649 /* check if pba_num buffer is big enough */
650 if (pba_num_size < (((u32)length * 2) - 1)) {
651 DEBUGOUT("PBA string buffer too small\n");
652 return IXGBE_ERR_NO_SPACE;
655 /* trim pba length from start of string */
659 for (offset = 0; offset < length; offset++) {
660 ret_val = hw->eeprom.ops.read(hw, pba_ptr + offset, &data);
662 DEBUGOUT("NVM Read Error\n");
665 pba_num[offset * 2] = (u8)(data >> 8);
666 pba_num[(offset * 2) + 1] = (u8)(data & 0xFF);
668 pba_num[offset * 2] = '\0';
670 return IXGBE_SUCCESS;
674 * ixgbe_read_pba_num_generic - Reads part number from EEPROM
675 * @hw: pointer to hardware structure
676 * @pba_num: stores the part number from the EEPROM
678 * Reads the part number from the EEPROM.
680 s32 ixgbe_read_pba_num_generic(struct ixgbe_hw *hw, u32 *pba_num)
685 DEBUGFUNC("ixgbe_read_pba_num_generic");
687 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM0_PTR, &data);
689 DEBUGOUT("NVM Read Error\n");
691 } else if (data == IXGBE_PBANUM_PTR_GUARD) {
692 DEBUGOUT("NVM Not supported\n");
693 return IXGBE_NOT_IMPLEMENTED;
695 *pba_num = (u32)(data << 16);
697 ret_val = hw->eeprom.ops.read(hw, IXGBE_PBANUM1_PTR, &data);
699 DEBUGOUT("NVM Read Error\n");
704 return IXGBE_SUCCESS;
709 * @hw: pointer to the HW structure
710 * @eeprom_buf: optional pointer to EEPROM image
711 * @eeprom_buf_size: size of EEPROM image in words
712 * @max_pba_block_size: PBA block size limit
713 * @pba: pointer to output PBA structure
715 * Reads PBA from EEPROM image when eeprom_buf is not NULL.
716 * Reads PBA from physical EEPROM device when eeprom_buf is NULL.
719 s32 ixgbe_read_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
720 u32 eeprom_buf_size, u16 max_pba_block_size,
721 struct ixgbe_pba *pba)
727 return IXGBE_ERR_PARAM;
729 if (eeprom_buf == NULL) {
730 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
735 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
736 pba->word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
737 pba->word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
739 return IXGBE_ERR_PARAM;
743 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
744 if (pba->pba_block == NULL)
745 return IXGBE_ERR_PARAM;
747 ret_val = ixgbe_get_pba_block_size(hw, eeprom_buf,
753 if (pba_block_size > max_pba_block_size)
754 return IXGBE_ERR_PARAM;
756 if (eeprom_buf == NULL) {
757 ret_val = hw->eeprom.ops.read_buffer(hw, pba->word[1],
763 if (eeprom_buf_size > (u32)(pba->word[1] +
764 pba->pba_block[0])) {
765 memcpy(pba->pba_block,
766 &eeprom_buf[pba->word[1]],
767 pba_block_size * sizeof(u16));
769 return IXGBE_ERR_PARAM;
774 return IXGBE_SUCCESS;
778 * ixgbe_write_pba_raw
779 * @hw: pointer to the HW structure
780 * @eeprom_buf: optional pointer to EEPROM image
781 * @eeprom_buf_size: size of EEPROM image in words
782 * @pba: pointer to PBA structure
784 * Writes PBA to EEPROM image when eeprom_buf is not NULL.
785 * Writes PBA to physical EEPROM device when eeprom_buf is NULL.
788 s32 ixgbe_write_pba_raw(struct ixgbe_hw *hw, u16 *eeprom_buf,
789 u32 eeprom_buf_size, struct ixgbe_pba *pba)
794 return IXGBE_ERR_PARAM;
796 if (eeprom_buf == NULL) {
797 ret_val = hw->eeprom.ops.write_buffer(hw, IXGBE_PBANUM0_PTR, 2,
802 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
803 eeprom_buf[IXGBE_PBANUM0_PTR] = pba->word[0];
804 eeprom_buf[IXGBE_PBANUM1_PTR] = pba->word[1];
806 return IXGBE_ERR_PARAM;
810 if (pba->word[0] == IXGBE_PBANUM_PTR_GUARD) {
811 if (pba->pba_block == NULL)
812 return IXGBE_ERR_PARAM;
814 if (eeprom_buf == NULL) {
815 ret_val = hw->eeprom.ops.write_buffer(hw, pba->word[1],
821 if (eeprom_buf_size > (u32)(pba->word[1] +
822 pba->pba_block[0])) {
823 memcpy(&eeprom_buf[pba->word[1]],
825 pba->pba_block[0] * sizeof(u16));
827 return IXGBE_ERR_PARAM;
832 return IXGBE_SUCCESS;
836 * ixgbe_get_pba_block_size
837 * @hw: pointer to the HW structure
838 * @eeprom_buf: optional pointer to EEPROM image
839 * @eeprom_buf_size: size of EEPROM image in words
840 * @pba_data_size: pointer to output variable
842 * Returns the size of the PBA block in words. Function operates on EEPROM
843 * image if the eeprom_buf pointer is not NULL otherwise it accesses physical
847 s32 ixgbe_get_pba_block_size(struct ixgbe_hw *hw, u16 *eeprom_buf,
848 u32 eeprom_buf_size, u16 *pba_block_size)
854 DEBUGFUNC("ixgbe_get_pba_block_size");
856 if (eeprom_buf == NULL) {
857 ret_val = hw->eeprom.ops.read_buffer(hw, IXGBE_PBANUM0_PTR, 2,
862 if (eeprom_buf_size > IXGBE_PBANUM1_PTR) {
863 pba_word[0] = eeprom_buf[IXGBE_PBANUM0_PTR];
864 pba_word[1] = eeprom_buf[IXGBE_PBANUM1_PTR];
866 return IXGBE_ERR_PARAM;
870 if (pba_word[0] == IXGBE_PBANUM_PTR_GUARD) {
871 if (eeprom_buf == NULL) {
872 ret_val = hw->eeprom.ops.read(hw, pba_word[1] + 0,
877 if (eeprom_buf_size > pba_word[1])
878 length = eeprom_buf[pba_word[1] + 0];
880 return IXGBE_ERR_PARAM;
883 if (length == 0xFFFF || length == 0)
884 return IXGBE_ERR_PBA_SECTION;
886 /* PBA number in legacy format, there is no PBA Block. */
890 if (pba_block_size != NULL)
891 *pba_block_size = length;
893 return IXGBE_SUCCESS;
897 * ixgbe_get_mac_addr_generic - Generic get MAC address
898 * @hw: pointer to hardware structure
899 * @mac_addr: Adapter MAC address
901 * Reads the adapter's MAC address from first Receive Address Register (RAR0)
902 * A reset of the adapter must be performed prior to calling this function
903 * in order for the MAC address to have been loaded from the EEPROM into RAR0
905 s32 ixgbe_get_mac_addr_generic(struct ixgbe_hw *hw, u8 *mac_addr)
911 DEBUGFUNC("ixgbe_get_mac_addr_generic");
913 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(0));
914 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(0));
916 for (i = 0; i < 4; i++)
917 mac_addr[i] = (u8)(rar_low >> (i*8));
919 for (i = 0; i < 2; i++)
920 mac_addr[i+4] = (u8)(rar_high >> (i*8));
922 return IXGBE_SUCCESS;
926 * ixgbe_get_bus_info_generic - Generic set PCI bus info
927 * @hw: pointer to hardware structure
929 * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure
931 s32 ixgbe_get_bus_info_generic(struct ixgbe_hw *hw)
933 struct ixgbe_mac_info *mac = &hw->mac;
936 DEBUGFUNC("ixgbe_get_bus_info_generic");
938 hw->bus.type = ixgbe_bus_type_pci_express;
940 /* Get the negotiated link width and speed from PCI config space */
941 link_status = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_LINK_STATUS);
943 switch (link_status & IXGBE_PCI_LINK_WIDTH) {
944 case IXGBE_PCI_LINK_WIDTH_1:
945 hw->bus.width = ixgbe_bus_width_pcie_x1;
947 case IXGBE_PCI_LINK_WIDTH_2:
948 hw->bus.width = ixgbe_bus_width_pcie_x2;
950 case IXGBE_PCI_LINK_WIDTH_4:
951 hw->bus.width = ixgbe_bus_width_pcie_x4;
953 case IXGBE_PCI_LINK_WIDTH_8:
954 hw->bus.width = ixgbe_bus_width_pcie_x8;
957 hw->bus.width = ixgbe_bus_width_unknown;
961 switch (link_status & IXGBE_PCI_LINK_SPEED) {
962 case IXGBE_PCI_LINK_SPEED_2500:
963 hw->bus.speed = ixgbe_bus_speed_2500;
965 case IXGBE_PCI_LINK_SPEED_5000:
966 hw->bus.speed = ixgbe_bus_speed_5000;
968 case IXGBE_PCI_LINK_SPEED_8000:
969 hw->bus.speed = ixgbe_bus_speed_8000;
972 hw->bus.speed = ixgbe_bus_speed_unknown;
976 mac->ops.set_lan_id(hw);
978 return IXGBE_SUCCESS;
982 * ixgbe_set_lan_id_multi_port_pcie - Set LAN id for PCIe multiple port devices
983 * @hw: pointer to the HW structure
985 * Determines the LAN function id by reading memory-mapped registers
986 * and swaps the port value if requested.
988 void ixgbe_set_lan_id_multi_port_pcie(struct ixgbe_hw *hw)
990 struct ixgbe_bus_info *bus = &hw->bus;
993 DEBUGFUNC("ixgbe_set_lan_id_multi_port_pcie");
995 reg = IXGBE_READ_REG(hw, IXGBE_STATUS);
996 bus->func = (reg & IXGBE_STATUS_LAN_ID) >> IXGBE_STATUS_LAN_ID_SHIFT;
997 bus->lan_id = bus->func;
999 /* check for a port swap */
1000 reg = IXGBE_READ_REG(hw, IXGBE_FACTPS);
1001 if (reg & IXGBE_FACTPS_LFS)
1006 * ixgbe_stop_adapter_generic - Generic stop Tx/Rx units
1007 * @hw: pointer to hardware structure
1009 * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts,
1010 * disables transmit and receive units. The adapter_stopped flag is used by
1011 * the shared code and drivers to determine if the adapter is in a stopped
1012 * state and should not touch the hardware.
1014 s32 ixgbe_stop_adapter_generic(struct ixgbe_hw *hw)
1019 DEBUGFUNC("ixgbe_stop_adapter_generic");
1022 * Set the adapter_stopped flag so other driver functions stop touching
1025 hw->adapter_stopped = true;
1027 /* Disable the receive unit */
1028 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, 0);
1030 /* Clear interrupt mask to stop interrupts from being generated */
1031 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1033 /* Clear any pending interrupts, flush previous writes */
1034 IXGBE_READ_REG(hw, IXGBE_EICR);
1036 /* Disable the transmit unit. Each queue must be disabled. */
1037 for (i = 0; i < hw->mac.max_tx_queues; i++)
1038 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(i), IXGBE_TXDCTL_SWFLSH);
1040 /* Disable the receive unit by stopping each queue */
1041 for (i = 0; i < hw->mac.max_rx_queues; i++) {
1042 reg_val = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
1043 reg_val &= ~IXGBE_RXDCTL_ENABLE;
1044 reg_val |= IXGBE_RXDCTL_SWFLSH;
1045 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(i), reg_val);
1048 /* flush all queues disables */
1049 IXGBE_WRITE_FLUSH(hw);
1053 * Prevent the PCI-E bus from from hanging by disabling PCI-E master
1054 * access and verify no pending requests
1056 return ixgbe_disable_pcie_master(hw);
1060 * ixgbe_led_on_generic - Turns on the software controllable LEDs.
1061 * @hw: pointer to hardware structure
1062 * @index: led number to turn on
1064 s32 ixgbe_led_on_generic(struct ixgbe_hw *hw, u32 index)
1066 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1068 DEBUGFUNC("ixgbe_led_on_generic");
1070 /* To turn on the LED, set mode to ON. */
1071 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1072 led_reg |= IXGBE_LED_ON << IXGBE_LED_MODE_SHIFT(index);
1073 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1074 IXGBE_WRITE_FLUSH(hw);
1076 return IXGBE_SUCCESS;
1080 * ixgbe_led_off_generic - Turns off the software controllable LEDs.
1081 * @hw: pointer to hardware structure
1082 * @index: led number to turn off
1084 s32 ixgbe_led_off_generic(struct ixgbe_hw *hw, u32 index)
1086 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
1088 DEBUGFUNC("ixgbe_led_off_generic");
1090 /* To turn off the LED, set mode to OFF. */
1091 led_reg &= ~IXGBE_LED_MODE_MASK(index);
1092 led_reg |= IXGBE_LED_OFF << IXGBE_LED_MODE_SHIFT(index);
1093 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
1094 IXGBE_WRITE_FLUSH(hw);
1096 return IXGBE_SUCCESS;
1100 * ixgbe_init_eeprom_params_generic - Initialize EEPROM params
1101 * @hw: pointer to hardware structure
1103 * Initializes the EEPROM parameters ixgbe_eeprom_info within the
1104 * ixgbe_hw struct in order to set up EEPROM access.
1106 s32 ixgbe_init_eeprom_params_generic(struct ixgbe_hw *hw)
1108 struct ixgbe_eeprom_info *eeprom = &hw->eeprom;
1112 DEBUGFUNC("ixgbe_init_eeprom_params_generic");
1114 if (eeprom->type == ixgbe_eeprom_uninitialized) {
1115 eeprom->type = ixgbe_eeprom_none;
1116 /* Set default semaphore delay to 10ms which is a well
1118 eeprom->semaphore_delay = 10;
1119 /* Clear EEPROM page size, it will be initialized as needed */
1120 eeprom->word_page_size = 0;
1123 * Check for EEPROM present first.
1124 * If not present leave as none
1126 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1127 if (eec & IXGBE_EEC_PRES) {
1128 eeprom->type = ixgbe_eeprom_spi;
1131 * SPI EEPROM is assumed here. This code would need to
1132 * change if a future EEPROM is not SPI.
1134 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >>
1135 IXGBE_EEC_SIZE_SHIFT);
1136 eeprom->word_size = 1 << (eeprom_size +
1137 IXGBE_EEPROM_WORD_SIZE_SHIFT);
1140 if (eec & IXGBE_EEC_ADDR_SIZE)
1141 eeprom->address_bits = 16;
1143 eeprom->address_bits = 8;
1144 DEBUGOUT3("Eeprom params: type = %d, size = %d, address bits: "
1145 "%d\n", eeprom->type, eeprom->word_size,
1146 eeprom->address_bits);
1149 return IXGBE_SUCCESS;
1153 * ixgbe_write_eeprom_buffer_bit_bang_generic - Write EEPROM using bit-bang
1154 * @hw: pointer to hardware structure
1155 * @offset: offset within the EEPROM to write
1156 * @words: number of word(s)
1157 * @data: 16 bit word(s) to write to EEPROM
1159 * Reads 16 bit word(s) from EEPROM through bit-bang method
1161 s32 ixgbe_write_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1162 u16 words, u16 *data)
1164 s32 status = IXGBE_SUCCESS;
1167 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang_generic");
1169 hw->eeprom.ops.init_params(hw);
1172 status = IXGBE_ERR_INVALID_ARGUMENT;
1176 if (offset + words > hw->eeprom.word_size) {
1177 status = IXGBE_ERR_EEPROM;
1182 * The EEPROM page size cannot be queried from the chip. We do lazy
1183 * initialization. It is worth to do that when we write large buffer.
1185 if ((hw->eeprom.word_page_size == 0) &&
1186 (words > IXGBE_EEPROM_PAGE_SIZE_MAX))
1187 ixgbe_detect_eeprom_page_size_generic(hw, offset);
1190 * We cannot hold synchronization semaphores for too long
1191 * to avoid other entity starvation. However it is more efficient
1192 * to read in bursts than synchronizing access for each word.
1194 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1195 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1196 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1197 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset + i,
1200 if (status != IXGBE_SUCCESS)
1209 * ixgbe_write_eeprom_buffer_bit_bang - Writes 16 bit word(s) to EEPROM
1210 * @hw: pointer to hardware structure
1211 * @offset: offset within the EEPROM to be written to
1212 * @words: number of word(s)
1213 * @data: 16 bit word(s) to be written to the EEPROM
1215 * If ixgbe_eeprom_update_checksum is not called after this function, the
1216 * EEPROM will most likely contain an invalid checksum.
1218 STATIC s32 ixgbe_write_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1219 u16 words, u16 *data)
1225 u8 write_opcode = IXGBE_EEPROM_WRITE_OPCODE_SPI;
1227 DEBUGFUNC("ixgbe_write_eeprom_buffer_bit_bang");
1229 /* Prepare the EEPROM for writing */
1230 status = ixgbe_acquire_eeprom(hw);
1232 if (status == IXGBE_SUCCESS) {
1233 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1234 ixgbe_release_eeprom(hw);
1235 status = IXGBE_ERR_EEPROM;
1239 if (status == IXGBE_SUCCESS) {
1240 for (i = 0; i < words; i++) {
1241 ixgbe_standby_eeprom(hw);
1243 /* Send the WRITE ENABLE command (8 bit opcode ) */
1244 ixgbe_shift_out_eeprom_bits(hw,
1245 IXGBE_EEPROM_WREN_OPCODE_SPI,
1246 IXGBE_EEPROM_OPCODE_BITS);
1248 ixgbe_standby_eeprom(hw);
1251 * Some SPI eeproms use the 8th address bit embedded
1254 if ((hw->eeprom.address_bits == 8) &&
1255 ((offset + i) >= 128))
1256 write_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1258 /* Send the Write command (8-bit opcode + addr) */
1259 ixgbe_shift_out_eeprom_bits(hw, write_opcode,
1260 IXGBE_EEPROM_OPCODE_BITS);
1261 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1262 hw->eeprom.address_bits);
1264 page_size = hw->eeprom.word_page_size;
1266 /* Send the data in burst via SPI*/
1269 word = (word >> 8) | (word << 8);
1270 ixgbe_shift_out_eeprom_bits(hw, word, 16);
1275 /* do not wrap around page */
1276 if (((offset + i) & (page_size - 1)) ==
1279 } while (++i < words);
1281 ixgbe_standby_eeprom(hw);
1284 /* Done with writing - release the EEPROM */
1285 ixgbe_release_eeprom(hw);
1292 * ixgbe_write_eeprom_generic - Writes 16 bit value to EEPROM
1293 * @hw: pointer to hardware structure
1294 * @offset: offset within the EEPROM to be written to
1295 * @data: 16 bit word to be written to the EEPROM
1297 * If ixgbe_eeprom_update_checksum is not called after this function, the
1298 * EEPROM will most likely contain an invalid checksum.
1300 s32 ixgbe_write_eeprom_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1304 DEBUGFUNC("ixgbe_write_eeprom_generic");
1306 hw->eeprom.ops.init_params(hw);
1308 if (offset >= hw->eeprom.word_size) {
1309 status = IXGBE_ERR_EEPROM;
1313 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset, 1, &data);
1320 * ixgbe_read_eeprom_buffer_bit_bang_generic - Read EEPROM using bit-bang
1321 * @hw: pointer to hardware structure
1322 * @offset: offset within the EEPROM to be read
1323 * @data: read 16 bit words(s) from EEPROM
1324 * @words: number of word(s)
1326 * Reads 16 bit word(s) from EEPROM through bit-bang method
1328 s32 ixgbe_read_eeprom_buffer_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1329 u16 words, u16 *data)
1331 s32 status = IXGBE_SUCCESS;
1334 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang_generic");
1336 hw->eeprom.ops.init_params(hw);
1339 status = IXGBE_ERR_INVALID_ARGUMENT;
1343 if (offset + words > hw->eeprom.word_size) {
1344 status = IXGBE_ERR_EEPROM;
1349 * We cannot hold synchronization semaphores for too long
1350 * to avoid other entity starvation. However it is more efficient
1351 * to read in bursts than synchronizing access for each word.
1353 for (i = 0; i < words; i += IXGBE_EEPROM_RD_BUFFER_MAX_COUNT) {
1354 count = (words - i) / IXGBE_EEPROM_RD_BUFFER_MAX_COUNT > 0 ?
1355 IXGBE_EEPROM_RD_BUFFER_MAX_COUNT : (words - i);
1357 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset + i,
1360 if (status != IXGBE_SUCCESS)
1369 * ixgbe_read_eeprom_buffer_bit_bang - Read EEPROM using bit-bang
1370 * @hw: pointer to hardware structure
1371 * @offset: offset within the EEPROM to be read
1372 * @words: number of word(s)
1373 * @data: read 16 bit word(s) from EEPROM
1375 * Reads 16 bit word(s) from EEPROM through bit-bang method
1377 STATIC s32 ixgbe_read_eeprom_buffer_bit_bang(struct ixgbe_hw *hw, u16 offset,
1378 u16 words, u16 *data)
1382 u8 read_opcode = IXGBE_EEPROM_READ_OPCODE_SPI;
1385 DEBUGFUNC("ixgbe_read_eeprom_buffer_bit_bang");
1387 /* Prepare the EEPROM for reading */
1388 status = ixgbe_acquire_eeprom(hw);
1390 if (status == IXGBE_SUCCESS) {
1391 if (ixgbe_ready_eeprom(hw) != IXGBE_SUCCESS) {
1392 ixgbe_release_eeprom(hw);
1393 status = IXGBE_ERR_EEPROM;
1397 if (status == IXGBE_SUCCESS) {
1398 for (i = 0; i < words; i++) {
1399 ixgbe_standby_eeprom(hw);
1401 * Some SPI eeproms use the 8th address bit embedded
1404 if ((hw->eeprom.address_bits == 8) &&
1405 ((offset + i) >= 128))
1406 read_opcode |= IXGBE_EEPROM_A8_OPCODE_SPI;
1408 /* Send the READ command (opcode + addr) */
1409 ixgbe_shift_out_eeprom_bits(hw, read_opcode,
1410 IXGBE_EEPROM_OPCODE_BITS);
1411 ixgbe_shift_out_eeprom_bits(hw, (u16)((offset + i) * 2),
1412 hw->eeprom.address_bits);
1414 /* Read the data. */
1415 word_in = ixgbe_shift_in_eeprom_bits(hw, 16);
1416 data[i] = (word_in >> 8) | (word_in << 8);
1419 /* End this read operation */
1420 ixgbe_release_eeprom(hw);
1427 * ixgbe_read_eeprom_bit_bang_generic - Read EEPROM word using bit-bang
1428 * @hw: pointer to hardware structure
1429 * @offset: offset within the EEPROM to be read
1430 * @data: read 16 bit value from EEPROM
1432 * Reads 16 bit value from EEPROM through bit-bang method
1434 s32 ixgbe_read_eeprom_bit_bang_generic(struct ixgbe_hw *hw, u16 offset,
1439 DEBUGFUNC("ixgbe_read_eeprom_bit_bang_generic");
1441 hw->eeprom.ops.init_params(hw);
1443 if (offset >= hw->eeprom.word_size) {
1444 status = IXGBE_ERR_EEPROM;
1448 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1455 * ixgbe_read_eerd_buffer_generic - Read EEPROM word(s) using EERD
1456 * @hw: pointer to hardware structure
1457 * @offset: offset of word in the EEPROM to read
1458 * @words: number of word(s)
1459 * @data: 16 bit word(s) from the EEPROM
1461 * Reads a 16 bit word(s) from the EEPROM using the EERD register.
1463 s32 ixgbe_read_eerd_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1464 u16 words, u16 *data)
1467 s32 status = IXGBE_SUCCESS;
1470 DEBUGFUNC("ixgbe_read_eerd_buffer_generic");
1472 hw->eeprom.ops.init_params(hw);
1475 status = IXGBE_ERR_INVALID_ARGUMENT;
1476 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1480 if (offset >= hw->eeprom.word_size) {
1481 status = IXGBE_ERR_EEPROM;
1482 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1486 for (i = 0; i < words; i++) {
1487 eerd = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1488 IXGBE_EEPROM_RW_REG_START;
1490 IXGBE_WRITE_REG(hw, IXGBE_EERD, eerd);
1491 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_READ);
1493 if (status == IXGBE_SUCCESS) {
1494 data[i] = (IXGBE_READ_REG(hw, IXGBE_EERD) >>
1495 IXGBE_EEPROM_RW_REG_DATA);
1497 DEBUGOUT("Eeprom read timed out\n");
1506 * ixgbe_detect_eeprom_page_size_generic - Detect EEPROM page size
1507 * @hw: pointer to hardware structure
1508 * @offset: offset within the EEPROM to be used as a scratch pad
1510 * Discover EEPROM page size by writing marching data at given offset.
1511 * This function is called only when we are writing a new large buffer
1512 * at given offset so the data would be overwritten anyway.
1514 STATIC s32 ixgbe_detect_eeprom_page_size_generic(struct ixgbe_hw *hw,
1517 u16 data[IXGBE_EEPROM_PAGE_SIZE_MAX];
1518 s32 status = IXGBE_SUCCESS;
1521 DEBUGFUNC("ixgbe_detect_eeprom_page_size_generic");
1523 for (i = 0; i < IXGBE_EEPROM_PAGE_SIZE_MAX; i++)
1526 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX;
1527 status = ixgbe_write_eeprom_buffer_bit_bang(hw, offset,
1528 IXGBE_EEPROM_PAGE_SIZE_MAX, data);
1529 hw->eeprom.word_page_size = 0;
1530 if (status != IXGBE_SUCCESS)
1533 status = ixgbe_read_eeprom_buffer_bit_bang(hw, offset, 1, data);
1534 if (status != IXGBE_SUCCESS)
1538 * When writing in burst more than the actual page size
1539 * EEPROM address wraps around current page.
1541 hw->eeprom.word_page_size = IXGBE_EEPROM_PAGE_SIZE_MAX - data[0];
1543 DEBUGOUT1("Detected EEPROM page size = %d words.",
1544 hw->eeprom.word_page_size);
1550 * ixgbe_read_eerd_generic - Read EEPROM word using EERD
1551 * @hw: pointer to hardware structure
1552 * @offset: offset of word in the EEPROM to read
1553 * @data: word read from the EEPROM
1555 * Reads a 16 bit word from the EEPROM using the EERD register.
1557 s32 ixgbe_read_eerd_generic(struct ixgbe_hw *hw, u16 offset, u16 *data)
1559 return ixgbe_read_eerd_buffer_generic(hw, offset, 1, data);
1563 * ixgbe_write_eewr_buffer_generic - Write EEPROM word(s) using EEWR
1564 * @hw: pointer to hardware structure
1565 * @offset: offset of word in the EEPROM to write
1566 * @words: number of word(s)
1567 * @data: word(s) write to the EEPROM
1569 * Write a 16 bit word(s) to the EEPROM using the EEWR register.
1571 s32 ixgbe_write_eewr_buffer_generic(struct ixgbe_hw *hw, u16 offset,
1572 u16 words, u16 *data)
1575 s32 status = IXGBE_SUCCESS;
1578 DEBUGFUNC("ixgbe_write_eewr_generic");
1580 hw->eeprom.ops.init_params(hw);
1583 status = IXGBE_ERR_INVALID_ARGUMENT;
1584 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM words");
1588 if (offset >= hw->eeprom.word_size) {
1589 status = IXGBE_ERR_EEPROM;
1590 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, "Invalid EEPROM offset");
1594 for (i = 0; i < words; i++) {
1595 eewr = ((offset + i) << IXGBE_EEPROM_RW_ADDR_SHIFT) |
1596 (data[i] << IXGBE_EEPROM_RW_REG_DATA) |
1597 IXGBE_EEPROM_RW_REG_START;
1599 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1600 if (status != IXGBE_SUCCESS) {
1601 DEBUGOUT("Eeprom write EEWR timed out\n");
1605 IXGBE_WRITE_REG(hw, IXGBE_EEWR, eewr);
1607 status = ixgbe_poll_eerd_eewr_done(hw, IXGBE_NVM_POLL_WRITE);
1608 if (status != IXGBE_SUCCESS) {
1609 DEBUGOUT("Eeprom write EEWR timed out\n");
1619 * ixgbe_write_eewr_generic - Write EEPROM word using EEWR
1620 * @hw: pointer to hardware structure
1621 * @offset: offset of word in the EEPROM to write
1622 * @data: word write to the EEPROM
1624 * Write a 16 bit word to the EEPROM using the EEWR register.
1626 s32 ixgbe_write_eewr_generic(struct ixgbe_hw *hw, u16 offset, u16 data)
1628 return ixgbe_write_eewr_buffer_generic(hw, offset, 1, &data);
1632 * ixgbe_poll_eerd_eewr_done - Poll EERD read or EEWR write status
1633 * @hw: pointer to hardware structure
1634 * @ee_reg: EEPROM flag for polling
1636 * Polls the status bit (bit 1) of the EERD or EEWR to determine when the
1637 * read or write is done respectively.
1639 s32 ixgbe_poll_eerd_eewr_done(struct ixgbe_hw *hw, u32 ee_reg)
1643 s32 status = IXGBE_ERR_EEPROM;
1645 DEBUGFUNC("ixgbe_poll_eerd_eewr_done");
1647 for (i = 0; i < IXGBE_EERD_EEWR_ATTEMPTS; i++) {
1648 if (ee_reg == IXGBE_NVM_POLL_READ)
1649 reg = IXGBE_READ_REG(hw, IXGBE_EERD);
1651 reg = IXGBE_READ_REG(hw, IXGBE_EEWR);
1653 if (reg & IXGBE_EEPROM_RW_REG_DONE) {
1654 status = IXGBE_SUCCESS;
1660 if (i == IXGBE_EERD_EEWR_ATTEMPTS)
1661 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1662 "EEPROM read/write done polling timed out");
1668 * ixgbe_acquire_eeprom - Acquire EEPROM using bit-bang
1669 * @hw: pointer to hardware structure
1671 * Prepares EEPROM for access using bit-bang method. This function should
1672 * be called before issuing a command to the EEPROM.
1674 STATIC s32 ixgbe_acquire_eeprom(struct ixgbe_hw *hw)
1676 s32 status = IXGBE_SUCCESS;
1680 DEBUGFUNC("ixgbe_acquire_eeprom");
1682 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)
1684 status = IXGBE_ERR_SWFW_SYNC;
1686 if (status == IXGBE_SUCCESS) {
1687 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1689 /* Request EEPROM Access */
1690 eec |= IXGBE_EEC_REQ;
1691 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1693 for (i = 0; i < IXGBE_EEPROM_GRANT_ATTEMPTS; i++) {
1694 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1695 if (eec & IXGBE_EEC_GNT)
1700 /* Release if grant not acquired */
1701 if (!(eec & IXGBE_EEC_GNT)) {
1702 eec &= ~IXGBE_EEC_REQ;
1703 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1704 DEBUGOUT("Could not acquire EEPROM grant\n");
1706 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
1707 status = IXGBE_ERR_EEPROM;
1710 /* Setup EEPROM for Read/Write */
1711 if (status == IXGBE_SUCCESS) {
1712 /* Clear CS and SK */
1713 eec &= ~(IXGBE_EEC_CS | IXGBE_EEC_SK);
1714 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1715 IXGBE_WRITE_FLUSH(hw);
1723 * ixgbe_get_eeprom_semaphore - Get hardware semaphore
1724 * @hw: pointer to hardware structure
1726 * Sets the hardware semaphores so EEPROM access can occur for bit-bang method
1728 STATIC s32 ixgbe_get_eeprom_semaphore(struct ixgbe_hw *hw)
1730 s32 status = IXGBE_ERR_EEPROM;
1735 DEBUGFUNC("ixgbe_get_eeprom_semaphore");
1738 /* Get SMBI software semaphore between device drivers first */
1739 for (i = 0; i < timeout; i++) {
1741 * If the SMBI bit is 0 when we read it, then the bit will be
1742 * set and we have the semaphore
1744 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1745 if (!(swsm & IXGBE_SWSM_SMBI)) {
1746 status = IXGBE_SUCCESS;
1753 DEBUGOUT("Driver can't access the Eeprom - SMBI Semaphore "
1756 * this release is particularly important because our attempts
1757 * above to get the semaphore may have succeeded, and if there
1758 * was a timeout, we should unconditionally clear the semaphore
1759 * bits to free the driver to make progress
1761 ixgbe_release_eeprom_semaphore(hw);
1766 * If the SMBI bit is 0 when we read it, then the bit will be
1767 * set and we have the semaphore
1769 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1770 if (!(swsm & IXGBE_SWSM_SMBI))
1771 status = IXGBE_SUCCESS;
1774 /* Now get the semaphore between SW/FW through the SWESMBI bit */
1775 if (status == IXGBE_SUCCESS) {
1776 for (i = 0; i < timeout; i++) {
1777 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1779 /* Set the SW EEPROM semaphore bit to request access */
1780 swsm |= IXGBE_SWSM_SWESMBI;
1781 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1784 * If we set the bit successfully then we got the
1787 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1788 if (swsm & IXGBE_SWSM_SWESMBI)
1795 * Release semaphores and return error if SW EEPROM semaphore
1796 * was not granted because we don't have access to the EEPROM
1799 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1800 "SWESMBI Software EEPROM semaphore not granted.\n");
1801 ixgbe_release_eeprom_semaphore(hw);
1802 status = IXGBE_ERR_EEPROM;
1805 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1806 "Software semaphore SMBI between device drivers "
1814 * ixgbe_release_eeprom_semaphore - Release hardware semaphore
1815 * @hw: pointer to hardware structure
1817 * This function clears hardware semaphore bits.
1819 STATIC void ixgbe_release_eeprom_semaphore(struct ixgbe_hw *hw)
1823 DEBUGFUNC("ixgbe_release_eeprom_semaphore");
1825 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM);
1827 /* Release both semaphores by writing 0 to the bits SWESMBI and SMBI */
1828 swsm &= ~(IXGBE_SWSM_SWESMBI | IXGBE_SWSM_SMBI);
1829 IXGBE_WRITE_REG(hw, IXGBE_SWSM, swsm);
1830 IXGBE_WRITE_FLUSH(hw);
1834 * ixgbe_ready_eeprom - Polls for EEPROM ready
1835 * @hw: pointer to hardware structure
1837 STATIC s32 ixgbe_ready_eeprom(struct ixgbe_hw *hw)
1839 s32 status = IXGBE_SUCCESS;
1843 DEBUGFUNC("ixgbe_ready_eeprom");
1846 * Read "Status Register" repeatedly until the LSB is cleared. The
1847 * EEPROM will signal that the command has been completed by clearing
1848 * bit 0 of the internal status register. If it's not cleared within
1849 * 5 milliseconds, then error out.
1851 for (i = 0; i < IXGBE_EEPROM_MAX_RETRY_SPI; i += 5) {
1852 ixgbe_shift_out_eeprom_bits(hw, IXGBE_EEPROM_RDSR_OPCODE_SPI,
1853 IXGBE_EEPROM_OPCODE_BITS);
1854 spi_stat_reg = (u8)ixgbe_shift_in_eeprom_bits(hw, 8);
1855 if (!(spi_stat_reg & IXGBE_EEPROM_STATUS_RDY_SPI))
1859 ixgbe_standby_eeprom(hw);
1863 * On some parts, SPI write time could vary from 0-20mSec on 3.3V
1864 * devices (and only 0-5mSec on 5V devices)
1866 if (i >= IXGBE_EEPROM_MAX_RETRY_SPI) {
1867 DEBUGOUT("SPI EEPROM Status error\n");
1868 status = IXGBE_ERR_EEPROM;
1875 * ixgbe_standby_eeprom - Returns EEPROM to a "standby" state
1876 * @hw: pointer to hardware structure
1878 STATIC void ixgbe_standby_eeprom(struct ixgbe_hw *hw)
1882 DEBUGFUNC("ixgbe_standby_eeprom");
1884 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1886 /* Toggle CS to flush commands */
1887 eec |= IXGBE_EEC_CS;
1888 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1889 IXGBE_WRITE_FLUSH(hw);
1891 eec &= ~IXGBE_EEC_CS;
1892 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1893 IXGBE_WRITE_FLUSH(hw);
1898 * ixgbe_shift_out_eeprom_bits - Shift data bits out to the EEPROM.
1899 * @hw: pointer to hardware structure
1900 * @data: data to send to the EEPROM
1901 * @count: number of bits to shift out
1903 STATIC void ixgbe_shift_out_eeprom_bits(struct ixgbe_hw *hw, u16 data,
1910 DEBUGFUNC("ixgbe_shift_out_eeprom_bits");
1912 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1915 * Mask is used to shift "count" bits of "data" out to the EEPROM
1916 * one bit at a time. Determine the starting bit based on count
1918 mask = 0x01 << (count - 1);
1920 for (i = 0; i < count; i++) {
1922 * A "1" is shifted out to the EEPROM by setting bit "DI" to a
1923 * "1", and then raising and then lowering the clock (the SK
1924 * bit controls the clock input to the EEPROM). A "0" is
1925 * shifted out to the EEPROM by setting "DI" to "0" and then
1926 * raising and then lowering the clock.
1929 eec |= IXGBE_EEC_DI;
1931 eec &= ~IXGBE_EEC_DI;
1933 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1934 IXGBE_WRITE_FLUSH(hw);
1938 ixgbe_raise_eeprom_clk(hw, &eec);
1939 ixgbe_lower_eeprom_clk(hw, &eec);
1942 * Shift mask to signify next bit of data to shift in to the
1948 /* We leave the "DI" bit set to "0" when we leave this routine. */
1949 eec &= ~IXGBE_EEC_DI;
1950 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
1951 IXGBE_WRITE_FLUSH(hw);
1955 * ixgbe_shift_in_eeprom_bits - Shift data bits in from the EEPROM
1956 * @hw: pointer to hardware structure
1958 STATIC u16 ixgbe_shift_in_eeprom_bits(struct ixgbe_hw *hw, u16 count)
1964 DEBUGFUNC("ixgbe_shift_in_eeprom_bits");
1967 * In order to read a register from the EEPROM, we need to shift
1968 * 'count' bits in from the EEPROM. Bits are "shifted in" by raising
1969 * the clock input to the EEPROM (setting the SK bit), and then reading
1970 * the value of the "DO" bit. During this "shifting in" process the
1971 * "DI" bit should always be clear.
1973 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1975 eec &= ~(IXGBE_EEC_DO | IXGBE_EEC_DI);
1977 for (i = 0; i < count; i++) {
1979 ixgbe_raise_eeprom_clk(hw, &eec);
1981 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
1983 eec &= ~(IXGBE_EEC_DI);
1984 if (eec & IXGBE_EEC_DO)
1987 ixgbe_lower_eeprom_clk(hw, &eec);
1994 * ixgbe_raise_eeprom_clk - Raises the EEPROM's clock input.
1995 * @hw: pointer to hardware structure
1996 * @eec: EEC register's current value
1998 STATIC void ixgbe_raise_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2000 DEBUGFUNC("ixgbe_raise_eeprom_clk");
2003 * Raise the clock input to the EEPROM
2004 * (setting the SK bit), then delay
2006 *eec = *eec | IXGBE_EEC_SK;
2007 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2008 IXGBE_WRITE_FLUSH(hw);
2013 * ixgbe_lower_eeprom_clk - Lowers the EEPROM's clock input.
2014 * @hw: pointer to hardware structure
2015 * @eecd: EECD's current value
2017 STATIC void ixgbe_lower_eeprom_clk(struct ixgbe_hw *hw, u32 *eec)
2019 DEBUGFUNC("ixgbe_lower_eeprom_clk");
2022 * Lower the clock input to the EEPROM (clearing the SK bit), then
2025 *eec = *eec & ~IXGBE_EEC_SK;
2026 IXGBE_WRITE_REG(hw, IXGBE_EEC, *eec);
2027 IXGBE_WRITE_FLUSH(hw);
2032 * ixgbe_release_eeprom - Release EEPROM, release semaphores
2033 * @hw: pointer to hardware structure
2035 STATIC void ixgbe_release_eeprom(struct ixgbe_hw *hw)
2039 DEBUGFUNC("ixgbe_release_eeprom");
2041 eec = IXGBE_READ_REG(hw, IXGBE_EEC);
2043 eec |= IXGBE_EEC_CS; /* Pull CS high */
2044 eec &= ~IXGBE_EEC_SK; /* Lower SCK */
2046 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2047 IXGBE_WRITE_FLUSH(hw);
2051 /* Stop requesting EEPROM access */
2052 eec &= ~IXGBE_EEC_REQ;
2053 IXGBE_WRITE_REG(hw, IXGBE_EEC, eec);
2055 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM);
2057 /* Delay before attempt to obtain semaphore again to allow FW access */
2058 msec_delay(hw->eeprom.semaphore_delay);
2062 * ixgbe_calc_eeprom_checksum_generic - Calculates and returns the checksum
2063 * @hw: pointer to hardware structure
2065 u16 ixgbe_calc_eeprom_checksum_generic(struct ixgbe_hw *hw)
2074 DEBUGFUNC("ixgbe_calc_eeprom_checksum_generic");
2076 /* Include 0x0-0x3F in the checksum */
2077 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) {
2078 if (hw->eeprom.ops.read(hw, i, &word) != IXGBE_SUCCESS) {
2079 DEBUGOUT("EEPROM read failed\n");
2085 /* Include all data from pointers except for the fw pointer */
2086 for (i = IXGBE_PCIE_ANALOG_PTR; i < IXGBE_FW_PTR; i++) {
2087 hw->eeprom.ops.read(hw, i, &pointer);
2089 /* Make sure the pointer seems valid */
2090 if (pointer != 0xFFFF && pointer != 0) {
2091 hw->eeprom.ops.read(hw, pointer, &length);
2093 if (length != 0xFFFF && length != 0) {
2094 for (j = pointer+1; j <= pointer+length; j++) {
2095 hw->eeprom.ops.read(hw, j, &word);
2102 checksum = (u16)IXGBE_EEPROM_SUM - checksum;
2108 * ixgbe_validate_eeprom_checksum_generic - Validate EEPROM checksum
2109 * @hw: pointer to hardware structure
2110 * @checksum_val: calculated checksum
2112 * Performs checksum calculation and validates the EEPROM checksum. If the
2113 * caller does not need checksum_val, the value can be NULL.
2115 s32 ixgbe_validate_eeprom_checksum_generic(struct ixgbe_hw *hw,
2120 u16 read_checksum = 0;
2122 DEBUGFUNC("ixgbe_validate_eeprom_checksum_generic");
2125 * Read the first word from the EEPROM. If this times out or fails, do
2126 * not continue or we could be in for a very long wait while every
2129 status = hw->eeprom.ops.read(hw, 0, &checksum);
2131 if (status == IXGBE_SUCCESS) {
2132 checksum = hw->eeprom.ops.calc_checksum(hw);
2134 hw->eeprom.ops.read(hw, IXGBE_EEPROM_CHECKSUM, &read_checksum);
2137 * Verify read checksum from EEPROM is the same as
2138 * calculated checksum
2140 if (read_checksum != checksum)
2141 status = IXGBE_ERR_EEPROM_CHECKSUM;
2143 /* If the user cares, return the calculated checksum */
2145 *checksum_val = checksum;
2147 DEBUGOUT("EEPROM read failed\n");
2154 * ixgbe_update_eeprom_checksum_generic - Updates the EEPROM checksum
2155 * @hw: pointer to hardware structure
2157 s32 ixgbe_update_eeprom_checksum_generic(struct ixgbe_hw *hw)
2162 DEBUGFUNC("ixgbe_update_eeprom_checksum_generic");
2165 * Read the first word from the EEPROM. If this times out or fails, do
2166 * not continue or we could be in for a very long wait while every
2169 status = hw->eeprom.ops.read(hw, 0, &checksum);
2171 if (status == IXGBE_SUCCESS) {
2172 checksum = hw->eeprom.ops.calc_checksum(hw);
2173 status = hw->eeprom.ops.write(hw, IXGBE_EEPROM_CHECKSUM,
2176 DEBUGOUT("EEPROM read failed\n");
2183 * ixgbe_validate_mac_addr - Validate MAC address
2184 * @mac_addr: pointer to MAC address.
2186 * Tests a MAC address to ensure it is a valid Individual Address
2188 s32 ixgbe_validate_mac_addr(u8 *mac_addr)
2190 s32 status = IXGBE_SUCCESS;
2192 DEBUGFUNC("ixgbe_validate_mac_addr");
2194 /* Make sure it is not a multicast address */
2195 if (IXGBE_IS_MULTICAST(mac_addr)) {
2196 DEBUGOUT("MAC address is multicast\n");
2197 status = IXGBE_ERR_INVALID_MAC_ADDR;
2198 /* Not a broadcast address */
2199 } else if (IXGBE_IS_BROADCAST(mac_addr)) {
2200 DEBUGOUT("MAC address is broadcast\n");
2201 status = IXGBE_ERR_INVALID_MAC_ADDR;
2202 /* Reject the zero address */
2203 } else if (mac_addr[0] == 0 && mac_addr[1] == 0 && mac_addr[2] == 0 &&
2204 mac_addr[3] == 0 && mac_addr[4] == 0 && mac_addr[5] == 0) {
2205 DEBUGOUT("MAC address is all zeros\n");
2206 status = IXGBE_ERR_INVALID_MAC_ADDR;
2212 * ixgbe_set_rar_generic - Set Rx address register
2213 * @hw: pointer to hardware structure
2214 * @index: Receive address register to write
2215 * @addr: Address to put into receive address register
2216 * @vmdq: VMDq "set" or "pool" index
2217 * @enable_addr: set flag that address is active
2219 * Puts an ethernet address into a receive address register.
2221 s32 ixgbe_set_rar_generic(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq,
2224 u32 rar_low, rar_high;
2225 u32 rar_entries = hw->mac.num_rar_entries;
2227 DEBUGFUNC("ixgbe_set_rar_generic");
2229 /* Make sure we are using a valid rar index range */
2230 if (index >= rar_entries) {
2231 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2232 "RAR index %d is out of range.\n", index);
2233 return IXGBE_ERR_INVALID_ARGUMENT;
2236 /* setup VMDq pool selection before this RAR gets enabled */
2237 hw->mac.ops.set_vmdq(hw, index, vmdq);
2240 * HW expects these in little endian so we reverse the byte
2241 * order from network order (big endian) to little endian
2243 rar_low = ((u32)addr[0] |
2244 ((u32)addr[1] << 8) |
2245 ((u32)addr[2] << 16) |
2246 ((u32)addr[3] << 24));
2248 * Some parts put the VMDq setting in the extra RAH bits,
2249 * so save everything except the lower 16 bits that hold part
2250 * of the address and the address valid bit.
2252 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2253 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2254 rar_high |= ((u32)addr[4] | ((u32)addr[5] << 8));
2256 if (enable_addr != 0)
2257 rar_high |= IXGBE_RAH_AV;
2259 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), rar_low);
2260 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2262 return IXGBE_SUCCESS;
2266 * ixgbe_clear_rar_generic - Remove Rx address register
2267 * @hw: pointer to hardware structure
2268 * @index: Receive address register to write
2270 * Clears an ethernet address from a receive address register.
2272 s32 ixgbe_clear_rar_generic(struct ixgbe_hw *hw, u32 index)
2275 u32 rar_entries = hw->mac.num_rar_entries;
2277 DEBUGFUNC("ixgbe_clear_rar_generic");
2279 /* Make sure we are using a valid rar index range */
2280 if (index >= rar_entries) {
2281 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
2282 "RAR index %d is out of range.\n", index);
2283 return IXGBE_ERR_INVALID_ARGUMENT;
2287 * Some parts put the VMDq setting in the extra RAH bits,
2288 * so save everything except the lower 16 bits that hold part
2289 * of the address and the address valid bit.
2291 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(index));
2292 rar_high &= ~(0x0000FFFF | IXGBE_RAH_AV);
2294 IXGBE_WRITE_REG(hw, IXGBE_RAL(index), 0);
2295 IXGBE_WRITE_REG(hw, IXGBE_RAH(index), rar_high);
2297 /* clear VMDq pool/queue selection for this RAR */
2298 hw->mac.ops.clear_vmdq(hw, index, IXGBE_CLEAR_VMDQ_ALL);
2300 return IXGBE_SUCCESS;
2304 * ixgbe_init_rx_addrs_generic - Initializes receive address filters.
2305 * @hw: pointer to hardware structure
2307 * Places the MAC address in receive address register 0 and clears the rest
2308 * of the receive address registers. Clears the multicast table. Assumes
2309 * the receiver is in reset when the routine is called.
2311 s32 ixgbe_init_rx_addrs_generic(struct ixgbe_hw *hw)
2314 u32 rar_entries = hw->mac.num_rar_entries;
2316 DEBUGFUNC("ixgbe_init_rx_addrs_generic");
2319 * If the current mac address is valid, assume it is a software override
2320 * to the permanent address.
2321 * Otherwise, use the permanent address from the eeprom.
2323 if (ixgbe_validate_mac_addr(hw->mac.addr) ==
2324 IXGBE_ERR_INVALID_MAC_ADDR) {
2325 /* Get the MAC address from the RAR0 for later reference */
2326 hw->mac.ops.get_mac_addr(hw, hw->mac.addr);
2328 DEBUGOUT3(" Keeping Current RAR0 Addr =%.2X %.2X %.2X ",
2329 hw->mac.addr[0], hw->mac.addr[1],
2331 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2332 hw->mac.addr[4], hw->mac.addr[5]);
2334 /* Setup the receive address. */
2335 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
2336 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
2337 hw->mac.addr[0], hw->mac.addr[1],
2339 DEBUGOUT3("%.2X %.2X %.2X\n", hw->mac.addr[3],
2340 hw->mac.addr[4], hw->mac.addr[5]);
2342 hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2344 /* clear VMDq pool/queue selection for RAR 0 */
2345 hw->mac.ops.clear_vmdq(hw, 0, IXGBE_CLEAR_VMDQ_ALL);
2347 hw->addr_ctrl.overflow_promisc = 0;
2349 hw->addr_ctrl.rar_used_count = 1;
2351 /* Zero out the other receive addresses. */
2352 DEBUGOUT1("Clearing RAR[1-%d]\n", rar_entries - 1);
2353 for (i = 1; i < rar_entries; i++) {
2354 IXGBE_WRITE_REG(hw, IXGBE_RAL(i), 0);
2355 IXGBE_WRITE_REG(hw, IXGBE_RAH(i), 0);
2359 hw->addr_ctrl.mta_in_use = 0;
2360 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2362 DEBUGOUT(" Clearing MTA\n");
2363 for (i = 0; i < hw->mac.mcft_size; i++)
2364 IXGBE_WRITE_REG(hw, IXGBE_MTA(i), 0);
2366 ixgbe_init_uta_tables(hw);
2368 return IXGBE_SUCCESS;
2372 * ixgbe_add_uc_addr - Adds a secondary unicast address.
2373 * @hw: pointer to hardware structure
2374 * @addr: new address
2376 * Adds it to unused receive address register or goes into promiscuous mode.
2378 void ixgbe_add_uc_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
2380 u32 rar_entries = hw->mac.num_rar_entries;
2383 DEBUGFUNC("ixgbe_add_uc_addr");
2385 DEBUGOUT6(" UC Addr = %.2X %.2X %.2X %.2X %.2X %.2X\n",
2386 addr[0], addr[1], addr[2], addr[3], addr[4], addr[5]);
2389 * Place this address in the RAR if there is room,
2390 * else put the controller into promiscuous mode
2392 if (hw->addr_ctrl.rar_used_count < rar_entries) {
2393 rar = hw->addr_ctrl.rar_used_count;
2394 hw->mac.ops.set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
2395 DEBUGOUT1("Added a secondary address to RAR[%d]\n", rar);
2396 hw->addr_ctrl.rar_used_count++;
2398 hw->addr_ctrl.overflow_promisc++;
2401 DEBUGOUT("ixgbe_add_uc_addr Complete\n");
2405 * ixgbe_update_uc_addr_list_generic - Updates MAC list of secondary addresses
2406 * @hw: pointer to hardware structure
2407 * @addr_list: the list of new addresses
2408 * @addr_count: number of addresses
2409 * @next: iterator function to walk the address list
2411 * The given list replaces any existing list. Clears the secondary addrs from
2412 * receive address registers. Uses unused receive address registers for the
2413 * first secondary addresses, and falls back to promiscuous mode as needed.
2415 * Drivers using secondary unicast addresses must set user_set_promisc when
2416 * manually putting the device into promiscuous mode.
2418 s32 ixgbe_update_uc_addr_list_generic(struct ixgbe_hw *hw, u8 *addr_list,
2419 u32 addr_count, ixgbe_mc_addr_itr next)
2423 u32 old_promisc_setting = hw->addr_ctrl.overflow_promisc;
2428 DEBUGFUNC("ixgbe_update_uc_addr_list_generic");
2431 * Clear accounting of old secondary address list,
2432 * don't count RAR[0]
2434 uc_addr_in_use = hw->addr_ctrl.rar_used_count - 1;
2435 hw->addr_ctrl.rar_used_count -= uc_addr_in_use;
2436 hw->addr_ctrl.overflow_promisc = 0;
2438 /* Zero out the other receive addresses */
2439 DEBUGOUT1("Clearing RAR[1-%d]\n", uc_addr_in_use+1);
2440 for (i = 0; i < uc_addr_in_use; i++) {
2441 IXGBE_WRITE_REG(hw, IXGBE_RAL(1+i), 0);
2442 IXGBE_WRITE_REG(hw, IXGBE_RAH(1+i), 0);
2445 /* Add the new addresses */
2446 for (i = 0; i < addr_count; i++) {
2447 DEBUGOUT(" Adding the secondary addresses:\n");
2448 addr = next(hw, &addr_list, &vmdq);
2449 ixgbe_add_uc_addr(hw, addr, vmdq);
2452 if (hw->addr_ctrl.overflow_promisc) {
2453 /* enable promisc if not already in overflow or set by user */
2454 if (!old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2455 DEBUGOUT(" Entering address overflow promisc mode\n");
2456 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2457 fctrl |= IXGBE_FCTRL_UPE;
2458 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2461 /* only disable if set by overflow, not by user */
2462 if (old_promisc_setting && !hw->addr_ctrl.user_set_promisc) {
2463 DEBUGOUT(" Leaving address overflow promisc mode\n");
2464 fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2465 fctrl &= ~IXGBE_FCTRL_UPE;
2466 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2470 DEBUGOUT("ixgbe_update_uc_addr_list_generic Complete\n");
2471 return IXGBE_SUCCESS;
2475 * ixgbe_mta_vector - Determines bit-vector in multicast table to set
2476 * @hw: pointer to hardware structure
2477 * @mc_addr: the multicast address
2479 * Extracts the 12 bits, from a multicast address, to determine which
2480 * bit-vector to set in the multicast table. The hardware uses 12 bits, from
2481 * incoming rx multicast addresses, to determine the bit-vector to check in
2482 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set
2483 * by the MO field of the MCSTCTRL. The MO field is set during initialization
2484 * to mc_filter_type.
2486 STATIC s32 ixgbe_mta_vector(struct ixgbe_hw *hw, u8 *mc_addr)
2490 DEBUGFUNC("ixgbe_mta_vector");
2492 switch (hw->mac.mc_filter_type) {
2493 case 0: /* use bits [47:36] of the address */
2494 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4));
2496 case 1: /* use bits [46:35] of the address */
2497 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5));
2499 case 2: /* use bits [45:34] of the address */
2500 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6));
2502 case 3: /* use bits [43:32] of the address */
2503 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8));
2505 default: /* Invalid mc_filter_type */
2506 DEBUGOUT("MC filter type param set incorrectly\n");
2511 /* vector can only be 12-bits or boundary will be exceeded */
2517 * ixgbe_set_mta - Set bit-vector in multicast table
2518 * @hw: pointer to hardware structure
2519 * @hash_value: Multicast address hash value
2521 * Sets the bit-vector in the multicast table.
2523 void ixgbe_set_mta(struct ixgbe_hw *hw, u8 *mc_addr)
2529 DEBUGFUNC("ixgbe_set_mta");
2531 hw->addr_ctrl.mta_in_use++;
2533 vector = ixgbe_mta_vector(hw, mc_addr);
2534 DEBUGOUT1(" bit-vector = 0x%03X\n", vector);
2537 * The MTA is a register array of 128 32-bit registers. It is treated
2538 * like an array of 4096 bits. We want to set bit
2539 * BitArray[vector_value]. So we figure out what register the bit is
2540 * in, read it, OR in the new bit, then write back the new value. The
2541 * register is determined by the upper 7 bits of the vector value and
2542 * the bit within that register are determined by the lower 5 bits of
2545 vector_reg = (vector >> 5) & 0x7F;
2546 vector_bit = vector & 0x1F;
2547 hw->mac.mta_shadow[vector_reg] |= (1 << vector_bit);
2551 * ixgbe_update_mc_addr_list_generic - Updates MAC list of multicast addresses
2552 * @hw: pointer to hardware structure
2553 * @mc_addr_list: the list of new multicast addresses
2554 * @mc_addr_count: number of addresses
2555 * @next: iterator function to walk the multicast address list
2556 * @clear: flag, when set clears the table beforehand
2558 * When the clear flag is set, the given list replaces any existing list.
2559 * Hashes the given addresses into the multicast table.
2561 s32 ixgbe_update_mc_addr_list_generic(struct ixgbe_hw *hw, u8 *mc_addr_list,
2562 u32 mc_addr_count, ixgbe_mc_addr_itr next,
2568 DEBUGFUNC("ixgbe_update_mc_addr_list_generic");
2571 * Set the new number of MC addresses that we are being requested to
2574 hw->addr_ctrl.num_mc_addrs = mc_addr_count;
2575 hw->addr_ctrl.mta_in_use = 0;
2577 /* Clear mta_shadow */
2579 DEBUGOUT(" Clearing MTA\n");
2580 memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
2583 /* Update mta_shadow */
2584 for (i = 0; i < mc_addr_count; i++) {
2585 DEBUGOUT(" Adding the multicast addresses:\n");
2586 ixgbe_set_mta(hw, next(hw, &mc_addr_list, &vmdq));
2590 for (i = 0; i < hw->mac.mcft_size; i++)
2591 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_MTA(0), i,
2592 hw->mac.mta_shadow[i]);
2594 if (hw->addr_ctrl.mta_in_use > 0)
2595 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL,
2596 IXGBE_MCSTCTRL_MFE | hw->mac.mc_filter_type);
2598 DEBUGOUT("ixgbe_update_mc_addr_list_generic Complete\n");
2599 return IXGBE_SUCCESS;
2603 * ixgbe_enable_mc_generic - Enable multicast address in RAR
2604 * @hw: pointer to hardware structure
2606 * Enables multicast address in RAR and the use of the multicast hash table.
2608 s32 ixgbe_enable_mc_generic(struct ixgbe_hw *hw)
2610 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2612 DEBUGFUNC("ixgbe_enable_mc_generic");
2614 if (a->mta_in_use > 0)
2615 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, IXGBE_MCSTCTRL_MFE |
2616 hw->mac.mc_filter_type);
2618 return IXGBE_SUCCESS;
2622 * ixgbe_disable_mc_generic - Disable multicast address in RAR
2623 * @hw: pointer to hardware structure
2625 * Disables multicast address in RAR and the use of the multicast hash table.
2627 s32 ixgbe_disable_mc_generic(struct ixgbe_hw *hw)
2629 struct ixgbe_addr_filter_info *a = &hw->addr_ctrl;
2631 DEBUGFUNC("ixgbe_disable_mc_generic");
2633 if (a->mta_in_use > 0)
2634 IXGBE_WRITE_REG(hw, IXGBE_MCSTCTRL, hw->mac.mc_filter_type);
2636 return IXGBE_SUCCESS;
2640 * ixgbe_fc_enable_generic - Enable flow control
2641 * @hw: pointer to hardware structure
2643 * Enable flow control according to the current settings.
2645 s32 ixgbe_fc_enable_generic(struct ixgbe_hw *hw)
2647 s32 ret_val = IXGBE_SUCCESS;
2648 u32 mflcn_reg, fccfg_reg;
2653 DEBUGFUNC("ixgbe_fc_enable_generic");
2655 /* Validate the water mark configuration */
2656 if (!hw->fc.pause_time) {
2657 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2661 /* Low water mark of zero causes XOFF floods */
2662 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2663 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2664 hw->fc.high_water[i]) {
2665 if (!hw->fc.low_water[i] ||
2666 hw->fc.low_water[i] >= hw->fc.high_water[i]) {
2667 DEBUGOUT("Invalid water mark configuration\n");
2668 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS;
2674 /* Negotiate the fc mode to use */
2675 ixgbe_fc_autoneg(hw);
2677 /* Disable any previous flow control settings */
2678 mflcn_reg = IXGBE_READ_REG(hw, IXGBE_MFLCN);
2679 mflcn_reg &= ~(IXGBE_MFLCN_RPFCE_MASK | IXGBE_MFLCN_RFCE);
2681 fccfg_reg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
2682 fccfg_reg &= ~(IXGBE_FCCFG_TFCE_802_3X | IXGBE_FCCFG_TFCE_PRIORITY);
2685 * The possible values of fc.current_mode are:
2686 * 0: Flow control is completely disabled
2687 * 1: Rx flow control is enabled (we can receive pause frames,
2688 * but not send pause frames).
2689 * 2: Tx flow control is enabled (we can send pause frames but
2690 * we do not support receiving pause frames).
2691 * 3: Both Rx and Tx flow control (symmetric) are enabled.
2694 switch (hw->fc.current_mode) {
2697 * Flow control is disabled by software override or autoneg.
2698 * The code below will actually disable it in the HW.
2701 case ixgbe_fc_rx_pause:
2703 * Rx Flow control is enabled and Tx Flow control is
2704 * disabled by software override. Since there really
2705 * isn't a way to advertise that we are capable of RX
2706 * Pause ONLY, we will advertise that we support both
2707 * symmetric and asymmetric Rx PAUSE. Later, we will
2708 * disable the adapter's ability to send PAUSE frames.
2710 mflcn_reg |= IXGBE_MFLCN_RFCE;
2712 case ixgbe_fc_tx_pause:
2714 * Tx Flow control is enabled, and Rx Flow control is
2715 * disabled by software override.
2717 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2720 /* Flow control (both Rx and Tx) is enabled by SW override. */
2721 mflcn_reg |= IXGBE_MFLCN_RFCE;
2722 fccfg_reg |= IXGBE_FCCFG_TFCE_802_3X;
2725 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT,
2726 "Flow control param set incorrectly\n");
2727 ret_val = IXGBE_ERR_CONFIG;
2732 /* Set 802.3x based flow control settings. */
2733 mflcn_reg |= IXGBE_MFLCN_DPF;
2734 IXGBE_WRITE_REG(hw, IXGBE_MFLCN, mflcn_reg);
2735 IXGBE_WRITE_REG(hw, IXGBE_FCCFG, fccfg_reg);
2738 /* Set up and enable Rx high/low water mark thresholds, enable XON. */
2739 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
2740 if ((hw->fc.current_mode & ixgbe_fc_tx_pause) &&
2741 hw->fc.high_water[i]) {
2742 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
2743 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), fcrtl);
2744 fcrth = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
2746 IXGBE_WRITE_REG(hw, IXGBE_FCRTL_82599(i), 0);
2748 * In order to prevent Tx hangs when the internal Tx
2749 * switch is enabled we must set the high water mark
2750 * to the maximum FCRTH value. This allows the Tx
2751 * switch to function even under heavy Rx workloads.
2753 fcrth = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(i)) - 32;
2756 IXGBE_WRITE_REG(hw, IXGBE_FCRTH_82599(i), fcrth);
2759 /* Configure pause time (2 TCs per register) */
2760 reg = hw->fc.pause_time * 0x00010001;
2761 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
2762 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
2764 /* Configure flow control refresh threshold value */
2765 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
2772 * ixgbe_negotiate_fc - Negotiate flow control
2773 * @hw: pointer to hardware structure
2774 * @adv_reg: flow control advertised settings
2775 * @lp_reg: link partner's flow control settings
2776 * @adv_sym: symmetric pause bit in advertisement
2777 * @adv_asm: asymmetric pause bit in advertisement
2778 * @lp_sym: symmetric pause bit in link partner advertisement
2779 * @lp_asm: asymmetric pause bit in link partner advertisement
2781 * Find the intersection between advertised settings and link partner's
2782 * advertised settings
2784 STATIC s32 ixgbe_negotiate_fc(struct ixgbe_hw *hw, u32 adv_reg, u32 lp_reg,
2785 u32 adv_sym, u32 adv_asm, u32 lp_sym, u32 lp_asm)
2787 if ((!(adv_reg)) || (!(lp_reg))) {
2788 ERROR_REPORT3(IXGBE_ERROR_UNSUPPORTED,
2789 "Local or link partner's advertised flow control "
2790 "settings are NULL. Local: %x, link partner: %x\n",
2792 return IXGBE_ERR_FC_NOT_NEGOTIATED;
2795 if ((adv_reg & adv_sym) && (lp_reg & lp_sym)) {
2797 * Now we need to check if the user selected Rx ONLY
2798 * of pause frames. In this case, we had to advertise
2799 * FULL flow control because we could not advertise RX
2800 * ONLY. Hence, we must now check to see if we need to
2801 * turn OFF the TRANSMISSION of PAUSE frames.
2803 if (hw->fc.requested_mode == ixgbe_fc_full) {
2804 hw->fc.current_mode = ixgbe_fc_full;
2805 DEBUGOUT("Flow Control = FULL.\n");
2807 hw->fc.current_mode = ixgbe_fc_rx_pause;
2808 DEBUGOUT("Flow Control=RX PAUSE frames only\n");
2810 } else if (!(adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2811 (lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2812 hw->fc.current_mode = ixgbe_fc_tx_pause;
2813 DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2814 } else if ((adv_reg & adv_sym) && (adv_reg & adv_asm) &&
2815 !(lp_reg & lp_sym) && (lp_reg & lp_asm)) {
2816 hw->fc.current_mode = ixgbe_fc_rx_pause;
2817 DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2819 hw->fc.current_mode = ixgbe_fc_none;
2820 DEBUGOUT("Flow Control = NONE.\n");
2822 return IXGBE_SUCCESS;
2826 * ixgbe_fc_autoneg_fiber - Enable flow control on 1 gig fiber
2827 * @hw: pointer to hardware structure
2829 * Enable flow control according on 1 gig fiber.
2831 STATIC s32 ixgbe_fc_autoneg_fiber(struct ixgbe_hw *hw)
2833 u32 pcs_anadv_reg, pcs_lpab_reg, linkstat;
2834 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2837 * On multispeed fiber at 1g, bail out if
2838 * - link is up but AN did not complete, or if
2839 * - link is up and AN completed but timed out
2842 linkstat = IXGBE_READ_REG(hw, IXGBE_PCS1GLSTA);
2843 if ((!!(linkstat & IXGBE_PCS1GLSTA_AN_COMPLETE) == 0) ||
2844 (!!(linkstat & IXGBE_PCS1GLSTA_AN_TIMED_OUT) == 1)) {
2845 ERROR_REPORT1(IXGBE_ERROR_POLLING,
2846 "Auto-Negotiation did not complete or timed out");
2850 pcs_anadv_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANA);
2851 pcs_lpab_reg = IXGBE_READ_REG(hw, IXGBE_PCS1GANLP);
2853 ret_val = ixgbe_negotiate_fc(hw, pcs_anadv_reg,
2854 pcs_lpab_reg, IXGBE_PCS1GANA_SYM_PAUSE,
2855 IXGBE_PCS1GANA_ASM_PAUSE,
2856 IXGBE_PCS1GANA_SYM_PAUSE,
2857 IXGBE_PCS1GANA_ASM_PAUSE);
2864 * ixgbe_fc_autoneg_backplane - Enable flow control IEEE clause 37
2865 * @hw: pointer to hardware structure
2867 * Enable flow control according to IEEE clause 37.
2869 STATIC s32 ixgbe_fc_autoneg_backplane(struct ixgbe_hw *hw)
2871 u32 links2, anlp1_reg, autoc_reg, links;
2872 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2875 * On backplane, bail out if
2876 * - backplane autoneg was not completed, or if
2877 * - we are 82599 and link partner is not AN enabled
2879 links = IXGBE_READ_REG(hw, IXGBE_LINKS);
2880 if ((links & IXGBE_LINKS_KX_AN_COMP) == 0) {
2881 ERROR_REPORT1(IXGBE_ERROR_POLLING,
2882 "Auto-Negotiation did not complete");
2886 if (hw->mac.type == ixgbe_mac_82599EB) {
2887 links2 = IXGBE_READ_REG(hw, IXGBE_LINKS2);
2888 if ((links2 & IXGBE_LINKS2_AN_SUPPORTED) == 0) {
2889 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2890 "Link partner is not AN enabled");
2895 * Read the 10g AN autoc and LP ability registers and resolve
2896 * local flow control settings accordingly
2898 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
2899 anlp1_reg = IXGBE_READ_REG(hw, IXGBE_ANLP1);
2901 ret_val = ixgbe_negotiate_fc(hw, autoc_reg,
2902 anlp1_reg, IXGBE_AUTOC_SYM_PAUSE, IXGBE_AUTOC_ASM_PAUSE,
2903 IXGBE_ANLP1_SYM_PAUSE, IXGBE_ANLP1_ASM_PAUSE);
2910 * ixgbe_fc_autoneg_copper - Enable flow control IEEE clause 37
2911 * @hw: pointer to hardware structure
2913 * Enable flow control according to IEEE clause 37.
2915 STATIC s32 ixgbe_fc_autoneg_copper(struct ixgbe_hw *hw)
2917 u16 technology_ability_reg = 0;
2918 u16 lp_technology_ability_reg = 0;
2920 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_ADVT,
2921 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2922 &technology_ability_reg);
2923 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_LP,
2924 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
2925 &lp_technology_ability_reg);
2927 return ixgbe_negotiate_fc(hw, (u32)technology_ability_reg,
2928 (u32)lp_technology_ability_reg,
2929 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE,
2930 IXGBE_TAF_SYM_PAUSE, IXGBE_TAF_ASM_PAUSE);
2934 * ixgbe_fc_autoneg - Configure flow control
2935 * @hw: pointer to hardware structure
2937 * Compares our advertised flow control capabilities to those advertised by
2938 * our link partner, and determines the proper flow control mode to use.
2940 void ixgbe_fc_autoneg(struct ixgbe_hw *hw)
2942 s32 ret_val = IXGBE_ERR_FC_NOT_NEGOTIATED;
2943 ixgbe_link_speed speed;
2946 DEBUGFUNC("ixgbe_fc_autoneg");
2949 * AN should have completed when the cable was plugged in.
2950 * Look for reasons to bail out. Bail out if:
2951 * - FC autoneg is disabled, or if
2954 if (hw->fc.disable_fc_autoneg) {
2955 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED,
2956 "Flow control autoneg is disabled");
2960 hw->mac.ops.check_link(hw, &speed, &link_up, false);
2962 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, "The link is down");
2966 switch (hw->phy.media_type) {
2967 /* Autoneg flow control on fiber adapters */
2968 case ixgbe_media_type_fiber:
2969 if (speed == IXGBE_LINK_SPEED_1GB_FULL)
2970 ret_val = ixgbe_fc_autoneg_fiber(hw);
2973 /* Autoneg flow control on backplane adapters */
2974 case ixgbe_media_type_backplane:
2975 ret_val = ixgbe_fc_autoneg_backplane(hw);
2978 /* Autoneg flow control on copper adapters */
2979 case ixgbe_media_type_copper:
2980 if (ixgbe_device_supports_autoneg_fc(hw) == IXGBE_SUCCESS)
2981 ret_val = ixgbe_fc_autoneg_copper(hw);
2989 if (ret_val == IXGBE_SUCCESS) {
2990 hw->fc.fc_was_autonegged = true;
2992 hw->fc.fc_was_autonegged = false;
2993 hw->fc.current_mode = hw->fc.requested_mode;
2998 * ixgbe_pcie_timeout_poll - Return number of times to poll for completion
2999 * @hw: pointer to hardware structure
3001 * System-wide timeout range is encoded in PCIe Device Control2 register.
3003 * Add 10% to specified maximum and return the number of times to poll for
3004 * completion timeout, in units of 100 microsec. Never return less than
3005 * 800 = 80 millisec.
3007 STATIC u32 ixgbe_pcie_timeout_poll(struct ixgbe_hw *hw)
3012 devctl2 = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_CONTROL2);
3013 devctl2 &= IXGBE_PCIDEVCTRL2_TIMEO_MASK;
3016 case IXGBE_PCIDEVCTRL2_65_130ms:
3017 pollcnt = 1300; /* 130 millisec */
3019 case IXGBE_PCIDEVCTRL2_260_520ms:
3020 pollcnt = 5200; /* 520 millisec */
3022 case IXGBE_PCIDEVCTRL2_1_2s:
3023 pollcnt = 20000; /* 2 sec */
3025 case IXGBE_PCIDEVCTRL2_4_8s:
3026 pollcnt = 80000; /* 8 sec */
3028 case IXGBE_PCIDEVCTRL2_17_34s:
3029 pollcnt = 34000; /* 34 sec */
3031 case IXGBE_PCIDEVCTRL2_50_100us: /* 100 microsecs */
3032 case IXGBE_PCIDEVCTRL2_1_2ms: /* 2 millisecs */
3033 case IXGBE_PCIDEVCTRL2_16_32ms: /* 32 millisec */
3034 case IXGBE_PCIDEVCTRL2_16_32ms_def: /* 32 millisec default */
3036 pollcnt = 800; /* 80 millisec minimum */
3040 /* add 10% to spec maximum */
3041 return (pollcnt * 11) / 10;
3045 * ixgbe_disable_pcie_master - Disable PCI-express master access
3046 * @hw: pointer to hardware structure
3048 * Disables PCI-Express master access and verifies there are no pending
3049 * requests. IXGBE_ERR_MASTER_REQUESTS_PENDING is returned if master disable
3050 * bit hasn't caused the master requests to be disabled, else IXGBE_SUCCESS
3051 * is returned signifying master requests disabled.
3053 s32 ixgbe_disable_pcie_master(struct ixgbe_hw *hw)
3055 s32 status = IXGBE_SUCCESS;
3059 DEBUGFUNC("ixgbe_disable_pcie_master");
3061 /* Always set this bit to ensure any future transactions are blocked */
3062 IXGBE_WRITE_REG(hw, IXGBE_CTRL, IXGBE_CTRL_GIO_DIS);
3064 /* Exit if master requests are blocked */
3065 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO) ||
3066 IXGBE_REMOVED(hw->hw_addr))
3069 /* Poll for master request bit to clear */
3070 for (i = 0; i < IXGBE_PCI_MASTER_DISABLE_TIMEOUT; i++) {
3072 if (!(IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_GIO))
3077 * Two consecutive resets are required via CTRL.RST per datasheet
3078 * 5.2.5.3.2 Master Disable. We set a flag to inform the reset routine
3079 * of this need. The first reset prevents new master requests from
3080 * being issued by our device. We then must wait 1usec or more for any
3081 * remaining completions from the PCIe bus to trickle in, and then reset
3082 * again to clear out any effects they may have had on our device.
3084 DEBUGOUT("GIO Master Disable bit didn't clear - requesting resets\n");
3085 hw->mac.flags |= IXGBE_FLAGS_DOUBLE_RESET_REQUIRED;
3088 * Before proceeding, make sure that the PCIe block does not have
3089 * transactions pending.
3091 poll = ixgbe_pcie_timeout_poll(hw);
3092 for (i = 0; i < poll; i++) {
3094 value = IXGBE_READ_PCIE_WORD(hw, IXGBE_PCI_DEVICE_STATUS);
3095 if (IXGBE_REMOVED(hw->hw_addr))
3097 if (!(value & IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING))
3101 ERROR_REPORT1(IXGBE_ERROR_POLLING,
3102 "PCIe transaction pending bit also did not clear.\n");
3103 status = IXGBE_ERR_MASTER_REQUESTS_PENDING;
3110 * ixgbe_acquire_swfw_sync - Acquire SWFW semaphore
3111 * @hw: pointer to hardware structure
3112 * @mask: Mask to specify which semaphore to acquire
3114 * Acquires the SWFW semaphore through the GSSR register for the specified
3115 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3117 s32 ixgbe_acquire_swfw_sync(struct ixgbe_hw *hw, u16 mask)
3121 u32 fwmask = mask << 5;
3124 DEBUGFUNC("ixgbe_acquire_swfw_sync");
3128 * SW EEPROM semaphore bit is used for access to all
3129 * SW_FW_SYNC/GSSR bits (not just EEPROM)
3131 if (ixgbe_get_eeprom_semaphore(hw))
3132 return IXGBE_ERR_SWFW_SYNC;
3134 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3135 if (!(gssr & (fwmask | swmask)))
3139 * Firmware currently using resource (fwmask) or other software
3140 * thread currently using resource (swmask)
3142 ixgbe_release_eeprom_semaphore(hw);
3148 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3149 return IXGBE_ERR_SWFW_SYNC;
3153 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3155 ixgbe_release_eeprom_semaphore(hw);
3156 return IXGBE_SUCCESS;
3160 * ixgbe_release_swfw_sync - Release SWFW semaphore
3161 * @hw: pointer to hardware structure
3162 * @mask: Mask to specify which semaphore to release
3164 * Releases the SWFW semaphore through the GSSR register for the specified
3165 * function (CSR, PHY0, PHY1, EEPROM, Flash)
3167 void ixgbe_release_swfw_sync(struct ixgbe_hw *hw, u16 mask)
3172 DEBUGFUNC("ixgbe_release_swfw_sync");
3174 ixgbe_get_eeprom_semaphore(hw);
3176 gssr = IXGBE_READ_REG(hw, IXGBE_GSSR);
3178 IXGBE_WRITE_REG(hw, IXGBE_GSSR, gssr);
3180 ixgbe_release_eeprom_semaphore(hw);
3184 * ixgbe_disable_sec_rx_path_generic - Stops the receive data path
3185 * @hw: pointer to hardware structure
3187 * Stops the receive data path and waits for the HW to internally empty
3188 * the Rx security block
3190 s32 ixgbe_disable_sec_rx_path_generic(struct ixgbe_hw *hw)
3192 #define IXGBE_MAX_SECRX_POLL 40
3197 DEBUGFUNC("ixgbe_disable_sec_rx_path_generic");
3200 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3201 secrxreg |= IXGBE_SECRXCTRL_RX_DIS;
3202 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3203 for (i = 0; i < IXGBE_MAX_SECRX_POLL; i++) {
3204 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXSTAT);
3205 if (secrxreg & IXGBE_SECRXSTAT_SECRX_RDY)
3208 /* Use interrupt-safe sleep just in case */
3212 /* For informational purposes only */
3213 if (i >= IXGBE_MAX_SECRX_POLL)
3214 DEBUGOUT("Rx unit being enabled before security "
3215 "path fully disabled. Continuing with init.\n");
3217 return IXGBE_SUCCESS;
3221 * ixgbe_enable_sec_rx_path_generic - Enables the receive data path
3222 * @hw: pointer to hardware structure
3224 * Enables the receive data path.
3226 s32 ixgbe_enable_sec_rx_path_generic(struct ixgbe_hw *hw)
3230 DEBUGFUNC("ixgbe_enable_sec_rx_path_generic");
3232 secrxreg = IXGBE_READ_REG(hw, IXGBE_SECRXCTRL);
3233 secrxreg &= ~IXGBE_SECRXCTRL_RX_DIS;
3234 IXGBE_WRITE_REG(hw, IXGBE_SECRXCTRL, secrxreg);
3235 IXGBE_WRITE_FLUSH(hw);
3237 return IXGBE_SUCCESS;
3241 * ixgbe_enable_rx_dma_generic - Enable the Rx DMA unit
3242 * @hw: pointer to hardware structure
3243 * @regval: register value to write to RXCTRL
3245 * Enables the Rx DMA unit
3247 s32 ixgbe_enable_rx_dma_generic(struct ixgbe_hw *hw, u32 regval)
3249 DEBUGFUNC("ixgbe_enable_rx_dma_generic");
3251 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, regval);
3253 return IXGBE_SUCCESS;
3257 * ixgbe_blink_led_start_generic - Blink LED based on index.
3258 * @hw: pointer to hardware structure
3259 * @index: led number to blink
3261 s32 ixgbe_blink_led_start_generic(struct ixgbe_hw *hw, u32 index)
3263 ixgbe_link_speed speed = 0;
3265 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3266 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3267 s32 ret_val = IXGBE_SUCCESS;
3269 DEBUGFUNC("ixgbe_blink_led_start_generic");
3272 * Link must be up to auto-blink the LEDs;
3273 * Force it if link is down.
3275 hw->mac.ops.check_link(hw, &speed, &link_up, false);
3278 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
3281 bool got_lock = false;
3282 if ((hw->mac.type == ixgbe_mac_82599EB) &&
3283 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3284 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
3285 IXGBE_GSSR_MAC_CSR_SM);
3286 if (ret_val != IXGBE_SUCCESS) {
3287 ret_val = IXGBE_ERR_SWFW_SYNC;
3293 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3294 autoc_reg |= IXGBE_AUTOC_FLU;
3295 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3296 IXGBE_WRITE_FLUSH(hw);
3299 hw->mac.ops.release_swfw_sync(hw,
3300 IXGBE_GSSR_MAC_CSR_SM);
3304 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3305 led_reg |= IXGBE_LED_BLINK(index);
3306 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3307 IXGBE_WRITE_FLUSH(hw);
3314 * ixgbe_blink_led_stop_generic - Stop blinking LED based on index.
3315 * @hw: pointer to hardware structure
3316 * @index: led number to stop blinking
3318 s32 ixgbe_blink_led_stop_generic(struct ixgbe_hw *hw, u32 index)
3320 u32 autoc_reg = IXGBE_READ_REG(hw, IXGBE_AUTOC);
3321 u32 led_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL);
3322 s32 ret_val = IXGBE_SUCCESS;
3323 bool got_lock = false;
3325 DEBUGFUNC("ixgbe_blink_led_stop_generic");
3326 /* Need the SW/FW semaphore around AUTOC writes if 82599 and
3329 if ((hw->mac.type == ixgbe_mac_82599EB) &&
3330 ixgbe_verify_lesm_fw_enabled_82599(hw)) {
3331 ret_val = hw->mac.ops.acquire_swfw_sync(hw,
3332 IXGBE_GSSR_MAC_CSR_SM);
3333 if (ret_val != IXGBE_SUCCESS) {
3334 ret_val = IXGBE_ERR_SWFW_SYNC;
3341 autoc_reg &= ~IXGBE_AUTOC_FLU;
3342 autoc_reg |= IXGBE_AUTOC_AN_RESTART;
3343 IXGBE_WRITE_REG(hw, IXGBE_AUTOC, autoc_reg);
3345 if (hw->mac.type == ixgbe_mac_82599EB)
3346 ixgbe_reset_pipeline_82599(hw);
3349 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_MAC_CSR_SM);
3351 led_reg &= ~IXGBE_LED_MODE_MASK(index);
3352 led_reg &= ~IXGBE_LED_BLINK(index);
3353 led_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index);
3354 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, led_reg);
3355 IXGBE_WRITE_FLUSH(hw);
3362 * ixgbe_get_san_mac_addr_offset - Get SAN MAC address offset from the EEPROM
3363 * @hw: pointer to hardware structure
3364 * @san_mac_offset: SAN MAC address offset
3366 * This function will read the EEPROM location for the SAN MAC address
3367 * pointer, and returns the value at that location. This is used in both
3368 * get and set mac_addr routines.
3370 STATIC s32 ixgbe_get_san_mac_addr_offset(struct ixgbe_hw *hw,
3371 u16 *san_mac_offset)
3375 DEBUGFUNC("ixgbe_get_san_mac_addr_offset");
3378 * First read the EEPROM pointer to see if the MAC addresses are
3381 ret_val = hw->eeprom.ops.read(hw, IXGBE_SAN_MAC_ADDR_PTR,
3384 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3385 "eeprom at offset %d failed",
3386 IXGBE_SAN_MAC_ADDR_PTR);
3393 * ixgbe_get_san_mac_addr_generic - SAN MAC address retrieval from the EEPROM
3394 * @hw: pointer to hardware structure
3395 * @san_mac_addr: SAN MAC address
3397 * Reads the SAN MAC address from the EEPROM, if it's available. This is
3398 * per-port, so set_lan_id() must be called before reading the addresses.
3399 * set_lan_id() is called by identify_sfp(), but this cannot be relied
3400 * upon for non-SFP connections, so we must call it here.
3402 s32 ixgbe_get_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3404 u16 san_mac_data, san_mac_offset;
3408 DEBUGFUNC("ixgbe_get_san_mac_addr_generic");
3411 * First read the EEPROM pointer to see if the MAC addresses are
3412 * available. If they're not, no point in calling set_lan_id() here.
3414 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3415 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3416 goto san_mac_addr_out;
3418 /* make sure we know which port we need to program */
3419 hw->mac.ops.set_lan_id(hw);
3420 /* apply the port offset to the address offset */
3421 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3422 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3423 for (i = 0; i < 3; i++) {
3424 ret_val = hw->eeprom.ops.read(hw, san_mac_offset,
3427 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
3428 "eeprom read at offset %d failed",
3430 goto san_mac_addr_out;
3432 san_mac_addr[i * 2] = (u8)(san_mac_data);
3433 san_mac_addr[i * 2 + 1] = (u8)(san_mac_data >> 8);
3436 return IXGBE_SUCCESS;
3440 * No addresses available in this EEPROM. It's not an
3441 * error though, so just wipe the local address and return.
3443 for (i = 0; i < 6; i++)
3444 san_mac_addr[i] = 0xFF;
3445 return IXGBE_SUCCESS;
3449 * ixgbe_set_san_mac_addr_generic - Write the SAN MAC address to the EEPROM
3450 * @hw: pointer to hardware structure
3451 * @san_mac_addr: SAN MAC address
3453 * Write a SAN MAC address to the EEPROM.
3455 s32 ixgbe_set_san_mac_addr_generic(struct ixgbe_hw *hw, u8 *san_mac_addr)
3458 u16 san_mac_data, san_mac_offset;
3461 DEBUGFUNC("ixgbe_set_san_mac_addr_generic");
3463 /* Look for SAN mac address pointer. If not defined, return */
3464 ret_val = ixgbe_get_san_mac_addr_offset(hw, &san_mac_offset);
3465 if (ret_val || san_mac_offset == 0 || san_mac_offset == 0xFFFF)
3466 return IXGBE_ERR_NO_SAN_ADDR_PTR;
3468 /* Make sure we know which port we need to write */
3469 hw->mac.ops.set_lan_id(hw);
3470 /* Apply the port offset to the address offset */
3471 (hw->bus.func) ? (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT1_OFFSET) :
3472 (san_mac_offset += IXGBE_SAN_MAC_ADDR_PORT0_OFFSET);
3474 for (i = 0; i < 3; i++) {
3475 san_mac_data = (u16)((u16)(san_mac_addr[i * 2 + 1]) << 8);
3476 san_mac_data |= (u16)(san_mac_addr[i * 2]);
3477 hw->eeprom.ops.write(hw, san_mac_offset, san_mac_data);
3481 return IXGBE_SUCCESS;
3485 * ixgbe_get_pcie_msix_count_generic - Gets MSI-X vector count
3486 * @hw: pointer to hardware structure
3488 * Read PCIe configuration space, and get the MSI-X vector count from
3489 * the capabilities table.
3491 u16 ixgbe_get_pcie_msix_count_generic(struct ixgbe_hw *hw)
3497 switch (hw->mac.type) {
3498 case ixgbe_mac_82598EB:
3499 pcie_offset = IXGBE_PCIE_MSIX_82598_CAPS;
3500 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82598;
3502 case ixgbe_mac_82599EB:
3503 case ixgbe_mac_X540:
3504 pcie_offset = IXGBE_PCIE_MSIX_82599_CAPS;
3505 max_msix_count = IXGBE_MAX_MSIX_VECTORS_82599;
3511 DEBUGFUNC("ixgbe_get_pcie_msix_count_generic");
3512 msix_count = IXGBE_READ_PCIE_WORD(hw, pcie_offset);
3513 if (IXGBE_REMOVED(hw->hw_addr))
3515 msix_count &= IXGBE_PCIE_MSIX_TBL_SZ_MASK;
3517 /* MSI-X count is zero-based in HW */
3520 if (msix_count > max_msix_count)
3521 msix_count = max_msix_count;
3527 * ixgbe_insert_mac_addr_generic - Find a RAR for this mac address
3528 * @hw: pointer to hardware structure
3529 * @addr: Address to put into receive address register
3530 * @vmdq: VMDq pool to assign
3532 * Puts an ethernet address into a receive address register, or
3533 * finds the rar that it is aleady in; adds to the pool list
3535 s32 ixgbe_insert_mac_addr_generic(struct ixgbe_hw *hw, u8 *addr, u32 vmdq)
3537 static const u32 NO_EMPTY_RAR_FOUND = 0xFFFFFFFF;
3538 u32 first_empty_rar = NO_EMPTY_RAR_FOUND;
3540 u32 rar_low, rar_high;
3541 u32 addr_low, addr_high;
3543 DEBUGFUNC("ixgbe_insert_mac_addr_generic");
3545 /* swap bytes for HW little endian */
3546 addr_low = addr[0] | (addr[1] << 8)
3549 addr_high = addr[4] | (addr[5] << 8);
3552 * Either find the mac_id in rar or find the first empty space.
3553 * rar_highwater points to just after the highest currently used
3554 * rar in order to shorten the search. It grows when we add a new
3557 for (rar = 0; rar < hw->mac.rar_highwater; rar++) {
3558 rar_high = IXGBE_READ_REG(hw, IXGBE_RAH(rar));
3560 if (((IXGBE_RAH_AV & rar_high) == 0)
3561 && first_empty_rar == NO_EMPTY_RAR_FOUND) {
3562 first_empty_rar = rar;
3563 } else if ((rar_high & 0xFFFF) == addr_high) {
3564 rar_low = IXGBE_READ_REG(hw, IXGBE_RAL(rar));
3565 if (rar_low == addr_low)
3566 break; /* found it already in the rars */
3570 if (rar < hw->mac.rar_highwater) {
3571 /* already there so just add to the pool bits */
3572 ixgbe_set_vmdq(hw, rar, vmdq);
3573 } else if (first_empty_rar != NO_EMPTY_RAR_FOUND) {
3574 /* stick it into first empty RAR slot we found */
3575 rar = first_empty_rar;
3576 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3577 } else if (rar == hw->mac.rar_highwater) {
3578 /* add it to the top of the list and inc the highwater mark */
3579 ixgbe_set_rar(hw, rar, addr, vmdq, IXGBE_RAH_AV);
3580 hw->mac.rar_highwater++;
3581 } else if (rar >= hw->mac.num_rar_entries) {
3582 return IXGBE_ERR_INVALID_MAC_ADDR;
3586 * If we found rar[0], make sure the default pool bit (we use pool 0)
3587 * remains cleared to be sure default pool packets will get delivered
3590 ixgbe_clear_vmdq(hw, rar, 0);
3596 * ixgbe_clear_vmdq_generic - Disassociate a VMDq pool index from a rx address
3597 * @hw: pointer to hardware struct
3598 * @rar: receive address register index to disassociate
3599 * @vmdq: VMDq pool index to remove from the rar
3601 s32 ixgbe_clear_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3603 u32 mpsar_lo, mpsar_hi;
3604 u32 rar_entries = hw->mac.num_rar_entries;
3606 DEBUGFUNC("ixgbe_clear_vmdq_generic");
3608 /* Make sure we are using a valid rar index range */
3609 if (rar >= rar_entries) {
3610 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3611 "RAR index %d is out of range.\n", rar);
3612 return IXGBE_ERR_INVALID_ARGUMENT;
3615 mpsar_lo = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3616 mpsar_hi = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3618 if (IXGBE_REMOVED(hw->hw_addr))
3621 if (!mpsar_lo && !mpsar_hi)
3624 if (vmdq == IXGBE_CLEAR_VMDQ_ALL) {
3626 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3630 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3633 } else if (vmdq < 32) {
3634 mpsar_lo &= ~(1 << vmdq);
3635 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar_lo);
3637 mpsar_hi &= ~(1 << (vmdq - 32));
3638 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar_hi);
3641 /* was that the last pool using this rar? */
3642 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0)
3643 hw->mac.ops.clear_rar(hw, rar);
3645 return IXGBE_SUCCESS;
3649 * ixgbe_set_vmdq_generic - Associate a VMDq pool index with a rx address
3650 * @hw: pointer to hardware struct
3651 * @rar: receive address register index to associate with a VMDq index
3652 * @vmdq: VMDq pool index
3654 s32 ixgbe_set_vmdq_generic(struct ixgbe_hw *hw, u32 rar, u32 vmdq)
3657 u32 rar_entries = hw->mac.num_rar_entries;
3659 DEBUGFUNC("ixgbe_set_vmdq_generic");
3661 /* Make sure we are using a valid rar index range */
3662 if (rar >= rar_entries) {
3663 ERROR_REPORT2(IXGBE_ERROR_ARGUMENT,
3664 "RAR index %d is out of range.\n", rar);
3665 return IXGBE_ERR_INVALID_ARGUMENT;
3669 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_LO(rar));
3671 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), mpsar);
3673 mpsar = IXGBE_READ_REG(hw, IXGBE_MPSAR_HI(rar));
3674 mpsar |= 1 << (vmdq - 32);
3675 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), mpsar);
3677 return IXGBE_SUCCESS;
3681 * This function should only be involved in the IOV mode.
3682 * In IOV mode, Default pool is next pool after the number of
3683 * VFs advertized and not 0.
3684 * MPSAR table needs to be updated for SAN_MAC RAR [hw->mac.san_mac_rar_index]
3686 * ixgbe_set_vmdq_san_mac - Associate default VMDq pool index with a rx address
3687 * @hw: pointer to hardware struct
3688 * @vmdq: VMDq pool index
3690 s32 ixgbe_set_vmdq_san_mac_generic(struct ixgbe_hw *hw, u32 vmdq)
3692 u32 rar = hw->mac.san_mac_rar_index;
3694 DEBUGFUNC("ixgbe_set_vmdq_san_mac");
3697 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 1 << vmdq);
3698 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 0);
3700 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_LO(rar), 0);
3701 IXGBE_WRITE_REG(hw, IXGBE_MPSAR_HI(rar), 1 << (vmdq - 32));
3704 return IXGBE_SUCCESS;
3708 * ixgbe_init_uta_tables_generic - Initialize the Unicast Table Array
3709 * @hw: pointer to hardware structure
3711 s32 ixgbe_init_uta_tables_generic(struct ixgbe_hw *hw)
3715 DEBUGFUNC("ixgbe_init_uta_tables_generic");
3716 DEBUGOUT(" Clearing UTA\n");
3718 for (i = 0; i < 128; i++)
3719 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), 0);
3721 return IXGBE_SUCCESS;
3725 * ixgbe_find_vlvf_slot - find the vlanid or the first empty slot
3726 * @hw: pointer to hardware structure
3727 * @vlan: VLAN id to write to VLAN filter
3729 * return the VLVF index where this VLAN id should be placed
3732 s32 ixgbe_find_vlvf_slot(struct ixgbe_hw *hw, u32 vlan)
3735 u32 first_empty_slot = 0;
3738 /* short cut the special case */
3743 * Search for the vlan id in the VLVF entries. Save off the first empty
3744 * slot found along the way
3746 for (regindex = 1; regindex < IXGBE_VLVF_ENTRIES; regindex++) {
3747 bits = IXGBE_READ_REG(hw, IXGBE_VLVF(regindex));
3748 if (!bits && !(first_empty_slot))
3749 first_empty_slot = regindex;
3750 else if ((bits & 0x0FFF) == vlan)
3755 * If regindex is less than IXGBE_VLVF_ENTRIES, then we found the vlan
3756 * in the VLVF. Else use the first empty VLVF register for this
3759 if (regindex >= IXGBE_VLVF_ENTRIES) {
3760 if (first_empty_slot)
3761 regindex = first_empty_slot;
3763 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
3764 "No space in VLVF.\n");
3765 regindex = IXGBE_ERR_NO_SPACE;
3773 * ixgbe_set_vfta_generic - Set VLAN filter table
3774 * @hw: pointer to hardware structure
3775 * @vlan: VLAN id to write to VLAN filter
3776 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3777 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3779 * Turn on/off specified VLAN in the VLAN filter table.
3781 s32 ixgbe_set_vfta_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3788 s32 ret_val = IXGBE_SUCCESS;
3789 bool vfta_changed = false;
3791 DEBUGFUNC("ixgbe_set_vfta_generic");
3794 return IXGBE_ERR_PARAM;
3797 * this is a 2 part operation - first the VFTA, then the
3798 * VLVF and VLVFB if VT Mode is set
3799 * We don't write the VFTA until we know the VLVF part succeeded.
3803 * The VFTA is a bitstring made up of 128 32-bit registers
3804 * that enable the particular VLAN id, much like the MTA:
3805 * bits[11-5]: which register
3806 * bits[4-0]: which bit in the register
3808 regindex = (vlan >> 5) & 0x7F;
3809 bitindex = vlan & 0x1F;
3810 targetbit = (1 << bitindex);
3811 vfta = IXGBE_READ_REG(hw, IXGBE_VFTA(regindex));
3814 if (!(vfta & targetbit)) {
3816 vfta_changed = true;
3819 if ((vfta & targetbit)) {
3821 vfta_changed = true;
3826 * Call ixgbe_set_vlvf_generic to set VLVFB and VLVF
3828 ret_val = ixgbe_set_vlvf_generic(hw, vlan, vind, vlan_on,
3830 if (ret_val != IXGBE_SUCCESS)
3834 IXGBE_WRITE_REG(hw, IXGBE_VFTA(regindex), vfta);
3836 return IXGBE_SUCCESS;
3840 * ixgbe_set_vlvf_generic - Set VLAN Pool Filter
3841 * @hw: pointer to hardware structure
3842 * @vlan: VLAN id to write to VLAN filter
3843 * @vind: VMDq output index that maps queue to VLAN id in VFVFB
3844 * @vlan_on: boolean flag to turn on/off VLAN in VFVF
3845 * @vfta_changed: pointer to boolean flag which indicates whether VFTA
3848 * Turn on/off specified bit in VLVF table.
3850 s32 ixgbe_set_vlvf_generic(struct ixgbe_hw *hw, u32 vlan, u32 vind,
3851 bool vlan_on, bool *vfta_changed)
3855 DEBUGFUNC("ixgbe_set_vlvf_generic");
3858 return IXGBE_ERR_PARAM;
3860 /* If VT Mode is set
3862 * make sure the vlan is in VLVF
3863 * set the vind bit in the matching VLVFB
3865 * clear the pool bit and possibly the vind
3867 vt = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3868 if (vt & IXGBE_VT_CTL_VT_ENABLE) {
3872 vlvf_index = ixgbe_find_vlvf_slot(hw, vlan);
3877 /* set the pool bit */
3879 bits = IXGBE_READ_REG(hw,
3880 IXGBE_VLVFB(vlvf_index * 2));
3881 bits |= (1 << vind);
3883 IXGBE_VLVFB(vlvf_index * 2),
3886 bits = IXGBE_READ_REG(hw,
3887 IXGBE_VLVFB((vlvf_index * 2) + 1));
3888 bits |= (1 << (vind - 32));
3890 IXGBE_VLVFB((vlvf_index * 2) + 1),
3894 /* clear the pool bit */
3896 bits = IXGBE_READ_REG(hw,
3897 IXGBE_VLVFB(vlvf_index * 2));
3898 bits &= ~(1 << vind);
3900 IXGBE_VLVFB(vlvf_index * 2),
3902 bits |= IXGBE_READ_REG(hw,
3903 IXGBE_VLVFB((vlvf_index * 2) + 1));
3905 bits = IXGBE_READ_REG(hw,
3906 IXGBE_VLVFB((vlvf_index * 2) + 1));
3907 bits &= ~(1 << (vind - 32));
3909 IXGBE_VLVFB((vlvf_index * 2) + 1),
3911 bits |= IXGBE_READ_REG(hw,
3912 IXGBE_VLVFB(vlvf_index * 2));
3917 * If there are still bits set in the VLVFB registers
3918 * for the VLAN ID indicated we need to see if the
3919 * caller is requesting that we clear the VFTA entry bit.
3920 * If the caller has requested that we clear the VFTA
3921 * entry bit but there are still pools/VFs using this VLAN
3922 * ID entry then ignore the request. We're not worried
3923 * about the case where we're turning the VFTA VLAN ID
3924 * entry bit on, only when requested to turn it off as
3925 * there may be multiple pools and/or VFs using the
3926 * VLAN ID entry. In that case we cannot clear the
3927 * VFTA bit until all pools/VFs using that VLAN ID have also
3928 * been cleared. This will be indicated by "bits" being
3932 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index),
3933 (IXGBE_VLVF_VIEN | vlan));
3934 if ((!vlan_on) && (vfta_changed != NULL)) {
3935 /* someone wants to clear the vfta entry
3936 * but some pools/VFs are still using it.
3938 *vfta_changed = false;
3941 IXGBE_WRITE_REG(hw, IXGBE_VLVF(vlvf_index), 0);
3944 return IXGBE_SUCCESS;
3948 * ixgbe_clear_vfta_generic - Clear VLAN filter table
3949 * @hw: pointer to hardware structure
3951 * Clears the VLAN filer table, and the VMDq index associated with the filter
3953 s32 ixgbe_clear_vfta_generic(struct ixgbe_hw *hw)
3957 DEBUGFUNC("ixgbe_clear_vfta_generic");
3959 for (offset = 0; offset < hw->mac.vft_size; offset++)
3960 IXGBE_WRITE_REG(hw, IXGBE_VFTA(offset), 0);
3962 for (offset = 0; offset < IXGBE_VLVF_ENTRIES; offset++) {
3963 IXGBE_WRITE_REG(hw, IXGBE_VLVF(offset), 0);
3964 IXGBE_WRITE_REG(hw, IXGBE_VLVFB(offset * 2), 0);
3965 IXGBE_WRITE_REG(hw, IXGBE_VLVFB((offset * 2) + 1), 0);
3968 return IXGBE_SUCCESS;
3972 * ixgbe_check_mac_link_generic - Determine link and speed status
3973 * @hw: pointer to hardware structure
3974 * @speed: pointer to link speed
3975 * @link_up: true when link is up
3976 * @link_up_wait_to_complete: bool used to wait for link up or not
3978 * Reads the links register to determine if link is up and the current speed
3980 s32 ixgbe_check_mac_link_generic(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
3981 bool *link_up, bool link_up_wait_to_complete)
3983 u32 links_reg, links_orig;
3986 DEBUGFUNC("ixgbe_check_mac_link_generic");
3988 /* clear the old state */
3989 links_orig = IXGBE_READ_REG(hw, IXGBE_LINKS);
3991 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
3993 if (links_orig != links_reg) {
3994 DEBUGOUT2("LINKS changed from %08X to %08X\n",
3995 links_orig, links_reg);
3998 if (link_up_wait_to_complete) {
3999 for (i = 0; i < IXGBE_LINK_UP_TIME; i++) {
4000 if (links_reg & IXGBE_LINKS_UP) {
4007 links_reg = IXGBE_READ_REG(hw, IXGBE_LINKS);
4010 if (links_reg & IXGBE_LINKS_UP)
4016 if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4017 IXGBE_LINKS_SPEED_10G_82599)
4018 *speed = IXGBE_LINK_SPEED_10GB_FULL;
4019 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4020 IXGBE_LINKS_SPEED_1G_82599)
4021 *speed = IXGBE_LINK_SPEED_1GB_FULL;
4022 else if ((links_reg & IXGBE_LINKS_SPEED_82599) ==
4023 IXGBE_LINKS_SPEED_100_82599)
4024 *speed = IXGBE_LINK_SPEED_100_FULL;
4026 *speed = IXGBE_LINK_SPEED_UNKNOWN;
4028 return IXGBE_SUCCESS;
4032 * ixgbe_get_wwn_prefix_generic - Get alternative WWNN/WWPN prefix from
4034 * @hw: pointer to hardware structure
4035 * @wwnn_prefix: the alternative WWNN prefix
4036 * @wwpn_prefix: the alternative WWPN prefix
4038 * This function will read the EEPROM from the alternative SAN MAC address
4039 * block to check the support for the alternative WWNN/WWPN prefix support.
4041 s32 ixgbe_get_wwn_prefix_generic(struct ixgbe_hw *hw, u16 *wwnn_prefix,
4045 u16 alt_san_mac_blk_offset;
4047 DEBUGFUNC("ixgbe_get_wwn_prefix_generic");
4049 /* clear output first */
4050 *wwnn_prefix = 0xFFFF;
4051 *wwpn_prefix = 0xFFFF;
4053 /* check if alternative SAN MAC is supported */
4054 offset = IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR;
4055 if (hw->eeprom.ops.read(hw, offset, &alt_san_mac_blk_offset))
4056 goto wwn_prefix_err;
4058 if ((alt_san_mac_blk_offset == 0) ||
4059 (alt_san_mac_blk_offset == 0xFFFF))
4060 goto wwn_prefix_out;
4062 /* check capability in alternative san mac address block */
4063 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET;
4064 if (hw->eeprom.ops.read(hw, offset, &caps))
4065 goto wwn_prefix_err;
4066 if (!(caps & IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN))
4067 goto wwn_prefix_out;
4069 /* get the corresponding prefix for WWNN/WWPN */
4070 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET;
4071 if (hw->eeprom.ops.read(hw, offset, wwnn_prefix)) {
4072 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4073 "eeprom read at offset %d failed", offset);
4076 offset = alt_san_mac_blk_offset + IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET;
4077 if (hw->eeprom.ops.read(hw, offset, wwpn_prefix))
4078 goto wwn_prefix_err;
4081 return IXGBE_SUCCESS;
4084 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
4085 "eeprom read at offset %d failed", offset);
4086 return IXGBE_SUCCESS;
4090 * ixgbe_get_fcoe_boot_status_generic - Get FCOE boot status from EEPROM
4091 * @hw: pointer to hardware structure
4092 * @bs: the fcoe boot status
4094 * This function will read the FCOE boot status from the iSCSI FCOE block
4096 s32 ixgbe_get_fcoe_boot_status_generic(struct ixgbe_hw *hw, u16 *bs)
4098 u16 offset, caps, flags;
4101 DEBUGFUNC("ixgbe_get_fcoe_boot_status_generic");
4103 /* clear output first */
4104 *bs = ixgbe_fcoe_bootstatus_unavailable;
4106 /* check if FCOE IBA block is present */
4107 offset = IXGBE_FCOE_IBA_CAPS_BLK_PTR;
4108 status = hw->eeprom.ops.read(hw, offset, &caps);
4109 if (status != IXGBE_SUCCESS)
4112 if (!(caps & IXGBE_FCOE_IBA_CAPS_FCOE))
4115 /* check if iSCSI FCOE block is populated */
4116 status = hw->eeprom.ops.read(hw, IXGBE_ISCSI_FCOE_BLK_PTR, &offset);
4117 if (status != IXGBE_SUCCESS)
4120 if ((offset == 0) || (offset == 0xFFFF))
4123 /* read fcoe flags in iSCSI FCOE block */
4124 offset = offset + IXGBE_ISCSI_FCOE_FLAGS_OFFSET;
4125 status = hw->eeprom.ops.read(hw, offset, &flags);
4126 if (status != IXGBE_SUCCESS)
4129 if (flags & IXGBE_ISCSI_FCOE_FLAGS_ENABLE)
4130 *bs = ixgbe_fcoe_bootstatus_enabled;
4132 *bs = ixgbe_fcoe_bootstatus_disabled;
4139 * ixgbe_set_mac_anti_spoofing - Enable/Disable MAC anti-spoofing
4140 * @hw: pointer to hardware structure
4141 * @enable: enable or disable switch for anti-spoofing
4142 * @pf: Physical Function pool - do not enable anti-spoofing for the PF
4145 void ixgbe_set_mac_anti_spoofing(struct ixgbe_hw *hw, bool enable, int pf)
4148 int pf_target_reg = pf >> 3;
4149 int pf_target_shift = pf % 8;
4152 if (hw->mac.type == ixgbe_mac_82598EB)
4156 pfvfspoof = IXGBE_SPOOF_MACAS_MASK;
4159 * PFVFSPOOF register array is size 8 with 8 bits assigned to
4160 * MAC anti-spoof enables in each register array element.
4162 for (j = 0; j < pf_target_reg; j++)
4163 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4166 * The PF should be allowed to spoof so that it can support
4167 * emulation mode NICs. Do not set the bits assigned to the PF
4169 pfvfspoof &= (1 << pf_target_shift) - 1;
4170 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), pfvfspoof);
4173 * Remaining pools belong to the PF so they do not need to have
4174 * anti-spoofing enabled.
4176 for (j++; j < IXGBE_PFVFSPOOF_REG_COUNT; j++)
4177 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(j), 0);
4181 * ixgbe_set_vlan_anti_spoofing - Enable/Disable VLAN anti-spoofing
4182 * @hw: pointer to hardware structure
4183 * @enable: enable or disable switch for VLAN anti-spoofing
4184 * @pf: Virtual Function pool - VF Pool to set for VLAN anti-spoofing
4187 void ixgbe_set_vlan_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf)
4189 int vf_target_reg = vf >> 3;
4190 int vf_target_shift = vf % 8 + IXGBE_SPOOF_VLANAS_SHIFT;
4193 if (hw->mac.type == ixgbe_mac_82598EB)
4196 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg));
4198 pfvfspoof |= (1 << vf_target_shift);
4200 pfvfspoof &= ~(1 << vf_target_shift);
4201 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof);
4205 * ixgbe_get_device_caps_generic - Get additional device capabilities
4206 * @hw: pointer to hardware structure
4207 * @device_caps: the EEPROM word with the extra device capabilities
4209 * This function will read the EEPROM location for the device capabilities,
4210 * and return the word through device_caps.
4212 s32 ixgbe_get_device_caps_generic(struct ixgbe_hw *hw, u16 *device_caps)
4214 DEBUGFUNC("ixgbe_get_device_caps_generic");
4216 hw->eeprom.ops.read(hw, IXGBE_DEVICE_CAPS, device_caps);
4218 return IXGBE_SUCCESS;
4222 * ixgbe_enable_relaxed_ordering_gen2 - Enable relaxed ordering
4223 * @hw: pointer to hardware structure
4226 void ixgbe_enable_relaxed_ordering_gen2(struct ixgbe_hw *hw)
4231 DEBUGFUNC("ixgbe_enable_relaxed_ordering_gen2");
4233 /* Enable relaxed ordering */
4234 for (i = 0; i < hw->mac.max_tx_queues; i++) {
4235 regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
4236 regval |= IXGBE_DCA_TXCTRL_DESC_WRO_EN;
4237 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
4240 for (i = 0; i < hw->mac.max_rx_queues; i++) {
4241 regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
4242 regval |= IXGBE_DCA_RXCTRL_DATA_WRO_EN |
4243 IXGBE_DCA_RXCTRL_HEAD_WRO_EN;
4244 IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
4250 * ixgbe_calculate_checksum - Calculate checksum for buffer
4251 * @buffer: pointer to EEPROM
4252 * @length: size of EEPROM to calculate a checksum for
4253 * Calculates the checksum for some buffer on a specified length. The
4254 * checksum calculated is returned.
4256 u8 ixgbe_calculate_checksum(u8 *buffer, u32 length)
4261 DEBUGFUNC("ixgbe_calculate_checksum");
4266 for (i = 0; i < length; i++)
4269 return (u8) (0 - sum);
4273 * ixgbe_host_interface_command - Issue command to manageability block
4274 * @hw: pointer to the HW structure
4275 * @buffer: contains the command to write and where the return status will
4277 * @length: length of buffer, must be multiple of 4 bytes
4279 * Communicates with the manageability block. On success return IXGBE_SUCCESS
4280 * else return IXGBE_ERR_HOST_INTERFACE_COMMAND.
4282 s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
4286 u32 hdr_size = sizeof(struct ixgbe_hic_hdr);
4287 u8 buf_len, dword_len;
4289 s32 ret_val = IXGBE_SUCCESS;
4291 DEBUGFUNC("ixgbe_host_interface_command");
4293 if (length == 0 || length & 0x3 ||
4294 length > IXGBE_HI_MAX_BLOCK_BYTE_LENGTH) {
4295 DEBUGOUT("Buffer length failure.\n");
4296 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4300 /* Check that the host interface is enabled. */
4301 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4302 if ((hicr & IXGBE_HICR_EN) == 0) {
4303 DEBUGOUT("IXGBE_HOST_EN bit disabled.\n");
4304 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4308 /* Calculate length in DWORDs */
4309 dword_len = length >> 2;
4312 * The device driver writes the relevant command block
4313 * into the ram area.
4315 for (i = 0; i < dword_len; i++)
4316 IXGBE_WRITE_REG_ARRAY(hw, IXGBE_FLEX_MNG,
4317 i, IXGBE_CPU_TO_LE32(buffer[i]));
4319 /* Setting this bit tells the ARC that a new command is pending. */
4320 IXGBE_WRITE_REG(hw, IXGBE_HICR, hicr | IXGBE_HICR_C);
4322 for (i = 0; i < IXGBE_HI_COMMAND_TIMEOUT; i++) {
4323 hicr = IXGBE_READ_REG(hw, IXGBE_HICR);
4324 if (!(hicr & IXGBE_HICR_C))
4329 /* Check command successful completion. */
4330 if (i == IXGBE_HI_COMMAND_TIMEOUT ||
4331 (!(IXGBE_READ_REG(hw, IXGBE_HICR) & IXGBE_HICR_SV))) {
4332 DEBUGOUT("Command has failed with no status valid.\n");
4333 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4337 /* Calculate length in DWORDs */
4338 dword_len = hdr_size >> 2;
4340 /* first pull in the header so we know the buffer length */
4341 for (bi = 0; bi < dword_len; bi++) {
4342 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4343 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4346 /* If there is any thing in data position pull it in */
4347 buf_len = ((struct ixgbe_hic_hdr *)buffer)->buf_len;
4351 if (length < (buf_len + hdr_size)) {
4352 DEBUGOUT("Buffer not large enough for reply message.\n");
4353 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4357 /* Calculate length in DWORDs, add 3 for odd lengths */
4358 dword_len = (buf_len + 3) >> 2;
4360 /* Pull in the rest of the buffer (bi is where we left off)*/
4361 for (; bi <= dword_len; bi++) {
4362 buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, bi);
4363 IXGBE_LE32_TO_CPUS(&buffer[bi]);
4371 * ixgbe_set_fw_drv_ver_generic - Sends driver version to firmware
4372 * @hw: pointer to the HW structure
4373 * @maj: driver version major number
4374 * @min: driver version minor number
4375 * @build: driver version build number
4376 * @sub: driver version sub build number
4378 * Sends driver version number to firmware through the manageability
4379 * block. On success return IXGBE_SUCCESS
4380 * else returns IXGBE_ERR_SWFW_SYNC when encountering an error acquiring
4381 * semaphore or IXGBE_ERR_HOST_INTERFACE_COMMAND when command fails.
4383 s32 ixgbe_set_fw_drv_ver_generic(struct ixgbe_hw *hw, u8 maj, u8 min,
4386 struct ixgbe_hic_drv_info fw_cmd;
4388 s32 ret_val = IXGBE_SUCCESS;
4390 DEBUGFUNC("ixgbe_set_fw_drv_ver_generic");
4392 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM)
4394 ret_val = IXGBE_ERR_SWFW_SYNC;
4398 fw_cmd.hdr.cmd = FW_CEM_CMD_DRIVER_INFO;
4399 fw_cmd.hdr.buf_len = FW_CEM_CMD_DRIVER_INFO_LEN;
4400 fw_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED;
4401 fw_cmd.port_num = (u8)hw->bus.func;
4402 fw_cmd.ver_maj = maj;
4403 fw_cmd.ver_min = min;
4404 fw_cmd.ver_build = build;
4405 fw_cmd.ver_sub = sub;
4406 fw_cmd.hdr.checksum = 0;
4407 fw_cmd.hdr.checksum = ixgbe_calculate_checksum((u8 *)&fw_cmd,
4408 (FW_CEM_HDR_LEN + fw_cmd.hdr.buf_len));
4412 for (i = 0; i <= FW_CEM_MAX_RETRIES; i++) {
4413 ret_val = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd,
4415 if (ret_val != IXGBE_SUCCESS)
4418 if (fw_cmd.hdr.cmd_or_resp.ret_status ==
4419 FW_CEM_RESP_STATUS_SUCCESS)
4420 ret_val = IXGBE_SUCCESS;
4422 ret_val = IXGBE_ERR_HOST_INTERFACE_COMMAND;
4427 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_SW_MNG_SM);
4433 * ixgbe_set_rxpba_generic - Initialize Rx packet buffer
4434 * @hw: pointer to hardware structure
4435 * @num_pb: number of packet buffers to allocate
4436 * @headroom: reserve n KB of headroom
4437 * @strategy: packet buffer allocation strategy
4439 void ixgbe_set_rxpba_generic(struct ixgbe_hw *hw, int num_pb, u32 headroom,
4442 u32 pbsize = hw->mac.rx_pb_size;
4444 u32 rxpktsize, txpktsize, txpbthresh;
4446 /* Reserve headroom */
4452 /* Divide remaining packet buffer space amongst the number of packet
4453 * buffers requested using supplied strategy.
4456 case PBA_STRATEGY_WEIGHTED:
4457 /* ixgbe_dcb_pba_80_48 strategy weight first half of packet
4458 * buffer with 5/8 of the packet buffer space.
4460 rxpktsize = (pbsize * 5) / (num_pb * 4);
4461 pbsize -= rxpktsize * (num_pb / 2);
4462 rxpktsize <<= IXGBE_RXPBSIZE_SHIFT;
4463 for (; i < (num_pb / 2); i++)
4464 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4465 /* Fall through to configure remaining packet buffers */
4466 case PBA_STRATEGY_EQUAL:
4467 rxpktsize = (pbsize / (num_pb - i)) << IXGBE_RXPBSIZE_SHIFT;
4468 for (; i < num_pb; i++)
4469 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), rxpktsize);
4475 /* Only support an equally distributed Tx packet buffer strategy. */
4476 txpktsize = IXGBE_TXPBSIZE_MAX / num_pb;
4477 txpbthresh = (txpktsize / 1024) - IXGBE_TXPKT_SIZE_MAX;
4478 for (i = 0; i < num_pb; i++) {
4479 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), txpktsize);
4480 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), txpbthresh);
4483 /* Clear unused TCs, if any, to zero buffer size*/
4484 for (; i < IXGBE_MAX_PB; i++) {
4485 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(i), 0);
4486 IXGBE_WRITE_REG(hw, IXGBE_TXPBSIZE(i), 0);
4487 IXGBE_WRITE_REG(hw, IXGBE_TXPBTHRESH(i), 0);
4492 * ixgbe_clear_tx_pending - Clear pending TX work from the PCIe fifo
4493 * @hw: pointer to the hardware structure
4495 * The 82599 and x540 MACs can experience issues if TX work is still pending
4496 * when a reset occurs. This function prevents this by flushing the PCIe
4497 * buffers on the system.
4499 void ixgbe_clear_tx_pending(struct ixgbe_hw *hw)
4501 u32 gcr_ext, hlreg0;
4504 * If double reset is not requested then all transactions should
4505 * already be clear and as such there is no work to do
4507 if (!(hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED))
4511 * Set loopback enable to prevent any transmits from being sent
4512 * should the link come up. This assumes that the RXCTRL.RXEN bit
4513 * has already been cleared.
4515 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
4516 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0 | IXGBE_HLREG0_LPBK);
4518 /* initiate cleaning flow for buffers in the PCIe transaction layer */
4519 gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
4520 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT,
4521 gcr_ext | IXGBE_GCR_EXT_BUFFERS_CLEAR);
4523 /* Flush all writes and allow 20usec for all transactions to clear */
4524 IXGBE_WRITE_FLUSH(hw);
4527 /* restore previous register values */
4528 IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
4529 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
4534 * ixgbe_dcb_get_rtrup2tc_generic - read rtrup2tc reg
4535 * @hw: pointer to hardware structure
4536 * @map: pointer to u8 arr for returning map
4538 * Read the rtrup2tc HW register and resolve its content into map
4540 void ixgbe_dcb_get_rtrup2tc_generic(struct ixgbe_hw *hw, u8 *map)
4544 reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
4545 for (i = 0; i < IXGBE_DCB_MAX_USER_PRIORITY; i++)
4546 map[i] = IXGBE_RTRUP2TC_UP_MASK &
4547 (reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT));