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35 #include "ixgbe_type.h"
36 #include "ixgbe_dcb.h"
37 #include "ixgbe_dcb_82598.h"
38 #ident "$Id: ixgbe_dcb_82598.c,v 1.29 2012/03/30 06:45:33 jtkirshe Exp $"
41 * ixgbe_dcb_get_tc_stats_82598 - Return status data for each traffic class
42 * @hw: pointer to hardware structure
43 * @stats: pointer to statistics structure
44 * @tc_count: Number of elements in bwg_array.
46 * This function returns the status data for each of the Traffic Classes in use.
48 s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *hw,
49 struct ixgbe_hw_stats *stats,
54 DEBUGFUNC("dcb_get_tc_stats");
56 if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
57 return IXGBE_ERR_PARAM;
59 /* Statistics pertaining to each traffic class */
60 for (tc = 0; tc < tc_count; tc++) {
61 /* Transmitted Packets */
62 stats->qptc[tc] += IXGBE_READ_REG(hw, IXGBE_QPTC(tc));
63 /* Transmitted Bytes */
64 stats->qbtc[tc] += IXGBE_READ_REG(hw, IXGBE_QBTC(tc));
65 /* Received Packets */
66 stats->qprc[tc] += IXGBE_READ_REG(hw, IXGBE_QPRC(tc));
68 stats->qbrc[tc] += IXGBE_READ_REG(hw, IXGBE_QBRC(tc));
71 /* Can we get rid of these?? Consequently, getting rid
72 * of the tc_stats structure.
74 tc_stats_array[up]->in_overflow_discards = 0;
75 tc_stats_array[up]->out_overflow_discards = 0;
83 * ixgbe_dcb_get_pfc_stats_82598 - Returns CBFC status data
84 * @hw: pointer to hardware structure
85 * @stats: pointer to statistics structure
86 * @tc_count: Number of elements in bwg_array.
88 * This function returns the CBFC status data for each of the Traffic Classes.
90 s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *hw,
91 struct ixgbe_hw_stats *stats,
96 DEBUGFUNC("dcb_get_pfc_stats");
98 if (tc_count > IXGBE_DCB_MAX_TRAFFIC_CLASS)
99 return IXGBE_ERR_PARAM;
101 for (tc = 0; tc < tc_count; tc++) {
102 /* Priority XOFF Transmitted */
103 stats->pxofftxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(tc));
104 /* Priority XOFF Received */
105 stats->pxoffrxc[tc] += IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(tc));
108 return IXGBE_SUCCESS;
112 * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
113 * @hw: pointer to hardware structure
114 * @dcb_config: pointer to ixgbe_dcb_config structure
116 * Configure Rx Data Arbiter and credits for each traffic class.
118 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *hw, u16 *refill,
122 u32 credit_refill = 0;
126 reg = IXGBE_READ_REG(hw, IXGBE_RUPPBMR) | IXGBE_RUPPBMR_MQA;
127 IXGBE_WRITE_REG(hw, IXGBE_RUPPBMR, reg);
129 reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
131 reg &= ~IXGBE_RMCS_ARBDIS;
132 /* Enable Receive Recycle within the BWG */
133 reg |= IXGBE_RMCS_RRM;
134 /* Enable Deficit Fixed Priority arbitration*/
135 reg |= IXGBE_RMCS_DFP;
137 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
139 /* Configure traffic class credits and priority */
140 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
141 credit_refill = refill[i];
144 reg = credit_refill | (credit_max << IXGBE_RT2CR_MCL_SHIFT);
146 if (tsa[i] == ixgbe_dcb_tsa_strict)
147 reg |= IXGBE_RT2CR_LSP;
149 IXGBE_WRITE_REG(hw, IXGBE_RT2CR(i), reg);
152 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
153 reg |= IXGBE_RDRXCTL_RDMTS_1_2;
154 reg |= IXGBE_RDRXCTL_MPBEN;
155 reg |= IXGBE_RDRXCTL_MCEN;
156 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg);
158 reg = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
159 /* Make sure there is enough descriptors before arbitration */
160 reg &= ~IXGBE_RXCTRL_DMBYPS;
161 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, reg);
163 return IXGBE_SUCCESS;
167 * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
168 * @hw: pointer to hardware structure
169 * @dcb_config: pointer to ixgbe_dcb_config structure
171 * Configure Tx Descriptor Arbiter and credits for each traffic class.
173 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *hw,
174 u16 *refill, u16 *max, u8 *bwg_id,
177 u32 reg, max_credits;
180 reg = IXGBE_READ_REG(hw, IXGBE_DPMCS);
183 reg &= ~IXGBE_DPMCS_ARBDIS;
184 reg |= IXGBE_DPMCS_TSOEF;
186 /* Configure Max TSO packet size 34KB including payload and headers */
187 reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);
189 IXGBE_WRITE_REG(hw, IXGBE_DPMCS, reg);
191 /* Configure traffic class credits and priority */
192 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
193 max_credits = max[i];
194 reg = max_credits << IXGBE_TDTQ2TCCR_MCL_SHIFT;
196 reg |= (u32)(bwg_id[i]) << IXGBE_TDTQ2TCCR_BWG_SHIFT;
198 if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
199 reg |= IXGBE_TDTQ2TCCR_GSP;
201 if (tsa[i] == ixgbe_dcb_tsa_strict)
202 reg |= IXGBE_TDTQ2TCCR_LSP;
204 IXGBE_WRITE_REG(hw, IXGBE_TDTQ2TCCR(i), reg);
207 return IXGBE_SUCCESS;
211 * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
212 * @hw: pointer to hardware structure
213 * @dcb_config: pointer to ixgbe_dcb_config structure
215 * Configure Tx Data Arbiter and credits for each traffic class.
217 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *hw,
218 u16 *refill, u16 *max, u8 *bwg_id,
224 reg = IXGBE_READ_REG(hw, IXGBE_PDPMCS);
225 /* Enable Data Plane Arbiter */
226 reg &= ~IXGBE_PDPMCS_ARBDIS;
227 /* Enable DFP and Transmit Recycle Mode */
228 reg |= (IXGBE_PDPMCS_TPPAC | IXGBE_PDPMCS_TRM);
230 IXGBE_WRITE_REG(hw, IXGBE_PDPMCS, reg);
232 /* Configure traffic class credits and priority */
233 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
235 reg |= (u32)(max[i]) << IXGBE_TDPT2TCCR_MCL_SHIFT;
236 reg |= (u32)(bwg_id[i]) << IXGBE_TDPT2TCCR_BWG_SHIFT;
238 if (tsa[i] == ixgbe_dcb_tsa_group_strict_cee)
239 reg |= IXGBE_TDPT2TCCR_GSP;
241 if (tsa[i] == ixgbe_dcb_tsa_strict)
242 reg |= IXGBE_TDPT2TCCR_LSP;
244 IXGBE_WRITE_REG(hw, IXGBE_TDPT2TCCR(i), reg);
247 /* Enable Tx packet buffer division */
248 reg = IXGBE_READ_REG(hw, IXGBE_DTXCTL);
249 reg |= IXGBE_DTXCTL_ENDBUBD;
250 IXGBE_WRITE_REG(hw, IXGBE_DTXCTL, reg);
252 return IXGBE_SUCCESS;
256 * ixgbe_dcb_config_pfc_82598 - Config priority flow control
257 * @hw: pointer to hardware structure
258 * @dcb_config: pointer to ixgbe_dcb_config structure
260 * Configure Priority Flow Control for each traffic class.
262 s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *hw, u8 pfc_en)
267 /* Enable Transmit Priority Flow Control */
268 reg = IXGBE_READ_REG(hw, IXGBE_RMCS);
269 reg &= ~IXGBE_RMCS_TFCE_802_3X;
270 reg |= IXGBE_RMCS_TFCE_PRIORITY;
271 IXGBE_WRITE_REG(hw, IXGBE_RMCS, reg);
273 /* Enable Receive Priority Flow Control */
274 reg = IXGBE_READ_REG(hw, IXGBE_FCTRL);
275 reg &= ~(IXGBE_FCTRL_RPFCE | IXGBE_FCTRL_RFCE);
278 reg |= IXGBE_FCTRL_RPFCE;
280 IXGBE_WRITE_REG(hw, IXGBE_FCTRL, reg);
282 /* Configure PFC Tx thresholds per TC */
283 for (i = 0; i < IXGBE_DCB_MAX_TRAFFIC_CLASS; i++) {
284 if (!(pfc_en & (1 << i))) {
285 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);
286 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);
290 fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;
291 reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;
292 IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), fcrtl);
293 IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), reg);
296 /* Configure pause time */
297 reg = hw->fc.pause_time | (hw->fc.pause_time << 16);
298 for (i = 0; i < (IXGBE_DCB_MAX_TRAFFIC_CLASS / 2); i++)
299 IXGBE_WRITE_REG(hw, IXGBE_FCTTV(i), reg);
301 /* Configure flow control refresh threshold value */
302 IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);
304 return IXGBE_SUCCESS;
308 * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
309 * @hw: pointer to hardware structure
311 * Configure queue statistics registers, all queues belonging to same traffic
312 * class uses a single set of queue statistics counters.
314 s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *hw)
320 /* Receive Queues stats setting - 8 queues per statistics reg */
321 for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {
322 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i));
323 reg |= ((0x1010101) * j);
324 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i), reg);
325 reg = IXGBE_READ_REG(hw, IXGBE_RQSMR(i + 1));
326 reg |= ((0x1010101) * j);
327 IXGBE_WRITE_REG(hw, IXGBE_RQSMR(i + 1), reg);
329 /* Transmit Queues stats setting - 4 queues per statistics reg*/
330 for (i = 0; i < 8; i++) {
331 reg = IXGBE_READ_REG(hw, IXGBE_TQSMR(i));
332 reg |= ((0x1010101) * i);
333 IXGBE_WRITE_REG(hw, IXGBE_TQSMR(i), reg);
336 return IXGBE_SUCCESS;
340 * ixgbe_dcb_hw_config_82598 - Config and enable DCB
341 * @hw: pointer to hardware structure
342 * @dcb_config: pointer to ixgbe_dcb_config structure
344 * Configure dcb settings and enable dcb mode.
346 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *hw, int link_speed,
347 u16 *refill, u16 *max, u8 *bwg_id,
350 UNREFERENCED_1PARAMETER(link_speed);
352 ixgbe_dcb_config_rx_arbiter_82598(hw, refill, max, tsa);
353 ixgbe_dcb_config_tx_desc_arbiter_82598(hw, refill, max, bwg_id,
355 ixgbe_dcb_config_tx_data_arbiter_82598(hw, refill, max, bwg_id,
357 ixgbe_dcb_config_tc_stats_82598(hw);
360 return IXGBE_SUCCESS;