1 /******************************************************************************
3 Copyright (c) 2001-2012, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
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10 this list of conditions and the following disclaimer.
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13 notice, this list of conditions and the following disclaimer in the
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18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
42 #include <rte_common.h>
43 #include <rte_debug.h>
44 #include <rte_cycles.h>
46 #include <rte_byteorder.h>
48 #include "../ixgbe_logs.h"
50 #define ASSERT(x) if(!(x)) rte_panic("IXGBE: x")
52 #define DELAY(x) rte_delay_us(x)
53 #define usec_delay(x) DELAY(x)
54 #define msec_delay(x) DELAY(1000*(x))
56 #define DEBUGFUNC(F) DEBUGOUT(F);
57 #define DEBUGOUT(S, args...) PMD_DRV_LOG(DEBUG, S, ##args)
58 #define DEBUGOUT1(S, args...) DEBUGOUT(S, ##args)
59 #define DEBUGOUT2(S, args...) DEBUGOUT(S, ##args)
60 #define DEBUGOUT3(S, args...) DEBUGOUT(S, ##args)
61 #define DEBUGOUT6(S, args...) DEBUGOUT(S, ##args)
62 #define DEBUGOUT7(S, args...) DEBUGOUT(S, ##args)
69 #define min(a,b) RTE_MIN(a,b)
71 #define EWARN(hw, S, args...) DEBUGOUT1(S, ##args)
73 /* Bunch of defines for shared code bogosity */
74 #define UNREFERENCED_PARAMETER(_p)
75 #define UNREFERENCED_1PARAMETER(_p)
76 #define UNREFERENCED_2PARAMETER(_p, _q)
77 #define UNREFERENCED_3PARAMETER(_p, _q, _r)
78 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s)
81 #define IXGBE_NTOHL(_i) rte_be_to_cpu_32(_i)
82 #define IXGBE_NTOHS(_i) rte_be_to_cpu_16(_i)
83 #define IXGBE_CPU_TO_LE32(_i) rte_cpu_to_le_32(_i)
84 #define IXGBE_LE32_TO_CPUS(_i) rte_le_to_cpu_32(_i)
95 #define wmb() rte_wmb()
96 #define rmb() rte_rmb()
98 #define prefetch(x) rte_prefetch0(x)
100 #define IXGBE_PCI_REG(reg) (*((volatile uint32_t *)(reg)))
102 static inline uint32_t ixgbe_read_addr(volatile void* addr)
104 return IXGBE_PCI_REG(addr);
107 #define IXGBE_PCI_REG_WRITE(reg, value) do { \
108 IXGBE_PCI_REG((reg)) = (value); \
111 #define IXGBE_PCI_REG_ADDR(hw, reg) \
112 ((volatile uint32_t *)((char *)(hw)->hw_addr + (reg)))
114 #define IXGBE_PCI_REG_ARRAY_ADDR(hw, reg, index) \
115 IXGBE_PCI_REG_ADDR((hw), (reg) + ((index) << 2))
117 /* Not implemented !! */
118 #define IXGBE_READ_PCIE_WORD(hw, reg) 0
119 #define IXGBE_WRITE_PCIE_WORD(hw, reg, value) do { } while(0)
121 #define IXGBE_WRITE_FLUSH(a) IXGBE_READ_REG(a, IXGBE_STATUS)
123 #define IXGBE_READ_REG(hw, reg) \
124 ixgbe_read_addr(IXGBE_PCI_REG_ADDR((hw), (reg)))
126 #define IXGBE_WRITE_REG(hw, reg, value) \
127 IXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ADDR((hw), (reg)), (value))
129 #define IXGBE_READ_REG_ARRAY(hw, reg, index) \
130 IXGBE_PCI_REG(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index)))
132 #define IXGBE_WRITE_REG_ARRAY(hw, reg, index, value) \
133 IXGBE_PCI_REG_WRITE(IXGBE_PCI_REG_ARRAY_ADDR((hw), (reg), (index)), (value))
135 #endif /* _IXGBE_OS_H_ */