lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37 #ident "$Id: ixgbe_phy.c,v 1.139 2012/05/24 23:36:12 jtkirshe Exp $"
  38
  39 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  40 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  41 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  42 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  43 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  44 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  45 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  46 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  48 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  49 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl);
  50 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  51                                           u8 *sff8472_data);
  52
  53 /**
  54  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
  55  *  @hw: pointer to the hardware structure
  56  *
  57  *  Initialize the function pointers.
  58  **/
  59 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
  60 {
  61         struct ixgbe_phy_info *phy = &hw->phy;
  62
  63         DEBUGFUNC("ixgbe_init_phy_ops_generic");
  64
  65         /* PHY */
  66         phy->ops.identify = &ixgbe_identify_phy_generic;
  67         phy->ops.reset = &ixgbe_reset_phy_generic;
  68         phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
  69         phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
  70         phy->ops.read_reg_mdi = &ixgbe_read_phy_reg_mdi;
  71         phy->ops.write_reg_mdi = &ixgbe_write_phy_reg_mdi;
  72         phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
  73         phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
  74         phy->ops.check_link = NULL;
  75         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
  76         phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
  77         phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
  78         phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic;
  79         phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
  80         phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
  81         phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
  82         phy->ops.identify_sfp = &ixgbe_identify_module_generic;
  83         phy->sfp_type = ixgbe_sfp_type_unknown;
  84         phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
  85         return IXGBE_SUCCESS;
  86 }
  87
  88 /**
  89  *  ixgbe_identify_phy_generic - Get physical layer module
  90  *  @hw: pointer to hardware structure
  91  *
  92  *  Determines the physical layer module found on the current adapter.
  93  **/
  94 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  95 {
  96         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  97         u32 phy_addr;
  98         u16 ext_ability = 0;
  99
 100         DEBUGFUNC("ixgbe_identify_phy_generic");
 101
 102         if (hw->phy.type == ixgbe_phy_unknown) {
 103                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 104                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 105                                 hw->phy.addr = phy_addr;
 106                                 ixgbe_get_phy_id(hw);
 107                                 hw->phy.type =
 108                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 109
 110                                 if (hw->phy.type == ixgbe_phy_unknown) {
 111                                         hw->phy.ops.read_reg(hw,
 112                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 113                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 114                                                   &ext_ability);
 115                                         if (ext_ability &
 116                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 117                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 118                                                 hw->phy.type =
 119                                                          ixgbe_phy_cu_unknown;
 120                                         else
 121                                                 hw->phy.type =
 122                                                          ixgbe_phy_generic;
 123                                 }
 124
 125                                 status = IXGBE_SUCCESS;
 126                                 break;
 127                         }
 128                 }
 129
 130                 /* Certain media types do not have a phy so an address will not
 131                  * be found and the code will take this path.  Caller has to
 132                  * decide if it is an error or not.
 133                  */
 134                 if (status != IXGBE_SUCCESS) {
 135                         hw->phy.addr = 0;
 136                 }
 137         } else {
 138                 status = IXGBE_SUCCESS;
 139         }
 140
 141         return status;
 142 }
 143
 144 /**
 145  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 146  * @hw: pointer to the hardware structure
 147  *
 148  * This function checks the MMNGC.MNG_VETO bit to see if there are
 149  * any constraints on link from manageability.  For MAC's that don't
 150  * have this bit just return faluse since the link can not be blocked
 151  * via this method.
 152  **/
 153 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 154 {
 155         u32 mmngc;
 156
 157         DEBUGFUNC("ixgbe_check_reset_blocked");
 158
 159         /* If we don't have this bit, it can't be blocking */
 160         if (hw->mac.type == ixgbe_mac_82598EB)
 161                 return false;
 162
 163         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 164         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 165                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 166                               "MNG_VETO bit detected.\n");
 167                 return true;
 168         }
 169
 170         return false;
 171 }
 172
 173 /**
 174  *  ixgbe_validate_phy_addr - Determines phy address is valid
 175  *  @hw: pointer to hardware structure
 176  *
 177  **/
 178 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 179 {
 180         u16 phy_id = 0;
 181         bool valid = false;
 182
 183         DEBUGFUNC("ixgbe_validate_phy_addr");
 184
 185         hw->phy.addr = phy_addr;
 186         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 187                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 188
 189         if (phy_id != 0xFFFF && phy_id != 0x0)
 190                 valid = true;
 191
 192         return valid;
 193 }
 194
 195 /**
 196  *  ixgbe_get_phy_id - Get the phy type
 197  *  @hw: pointer to hardware structure
 198  *
 199  **/
 200 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 201 {
 202         u32 status;
 203         u16 phy_id_high = 0;
 204         u16 phy_id_low = 0;
 205
 206         DEBUGFUNC("ixgbe_get_phy_id");
 207
 208         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 209                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 210                                       &phy_id_high);
 211
 212         if (status == IXGBE_SUCCESS) {
 213                 hw->phy.id = (u32)(phy_id_high << 16);
 214                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 215                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 216                                               &phy_id_low);
 217                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 218                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 219         }
 220         return status;
 221 }
 222
 223 /**
 224  *  ixgbe_get_phy_type_from_id - Get the phy type
 225  *  @hw: pointer to hardware structure
 226  *
 227  **/
 228 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 229 {
 230         enum ixgbe_phy_type phy_type;
 231
 232         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 233
 234         switch (phy_id) {
 235         case TN1010_PHY_ID:
 236                 phy_type = ixgbe_phy_tn;
 237                 break;
 238         case X540_PHY_ID:
 239                 phy_type = ixgbe_phy_aq;
 240                 break;
 241         case QT2022_PHY_ID:
 242                 phy_type = ixgbe_phy_qt;
 243                 break;
 244         case ATH_PHY_ID:
 245                 phy_type = ixgbe_phy_nl;
 246                 break;
 247         default:
 248                 phy_type = ixgbe_phy_unknown;
 249                 break;
 250         }
 251
 252         DEBUGOUT1("phy type found is %d\n", phy_type);
 253         return phy_type;
 254 }
 255
 256 /**
 257  *  ixgbe_reset_phy_generic - Performs a PHY reset
 258  *  @hw: pointer to hardware structure
 259  **/
 260 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 261 {
 262         u32 i;
 263         u16 ctrl = 0;
 264         s32 status = IXGBE_SUCCESS;
 265
 266         DEBUGFUNC("ixgbe_reset_phy_generic");
 267
 268         if (hw->phy.type == ixgbe_phy_unknown)
 269                 status = ixgbe_identify_phy_generic(hw);
 270
 271         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 272                 goto out;
 273
 274         /* Don't reset PHY if it's shut down due to overtemp. */
 275         if (!hw->phy.reset_if_overtemp &&
 276             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 277                 goto out;
 278
 279         /* Blocked by MNG FW so bail */
 280         if (ixgbe_check_reset_blocked(hw))
 281                 goto out;
 282
 283         /*
 284          * Perform soft PHY reset to the PHY_XS.
 285          * This will cause a soft reset to the PHY
 286          */
 287         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 288                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 289                               IXGBE_MDIO_PHY_XS_RESET);
 290
 291         /*
 292          * Poll for reset bit to self-clear indicating reset is complete.
 293          * Some PHYs could take up to 3 seconds to complete and need about
 294          * 1.7 usec delay after the reset is complete.
 295          */
 296         for (i = 0; i < 30; i++) {
 297                 msec_delay(100);
 298                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 299                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 300                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 301                         usec_delay(2);
 302                         break;
 303                 }
 304         }
 305
 306         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 307                 status = IXGBE_ERR_RESET_FAILED;
 308                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 309                              "PHY reset polling failed to complete.\n");
 310         }
 311
 312 out:
 313         return status;
 314 }
 315
 316 /**
 317  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 318  *  the SWFW lock
 319  *  @hw: pointer to hardware structure
 320  *  @reg_addr: 32 bit address of PHY register to read
 321  *  @phy_data: Pointer to read data from PHY register
 322  **/
 323 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 324                        u16 *phy_data)
 325 {
 326         u32 i, data, command;
 327
 328         /* Setup and write the address cycle command */
 329         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 330                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 331                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 332                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 333
 334         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 335
 336         /*
 337          * Check every 10 usec to see if the address cycle completed.
 338          * The MDI Command bit will clear when the operation is
 339          * complete
 340          */
 341         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 342                 usec_delay(10);
 343
 344                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 345                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 346                                 break;
 347         }
 348
 349
 350         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 351                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 352                 return IXGBE_ERR_PHY;
 353         }
 354
 355         /*
 356          * Address cycle complete, setup and write the read
 357          * command
 358          */
 359         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 360                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 361                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 362                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 363
 364         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 365
 366         /*
 367          * Check every 10 usec to see if the address cycle
 368          * completed. The MDI Command bit will clear when the
 369          * operation is complete
 370          */
 371         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 372                 usec_delay(10);
 373
 374                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 375                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 376                         break;
 377         }
 378
 379         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 380                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 381                 return IXGBE_ERR_PHY;
 382         }
 383
 384         /*
 385          * Read operation is complete.  Get the data
 386          * from MSRWD
 387          */
 388         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 389         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 390         *phy_data = (u16)(data);
 391
 392         return IXGBE_SUCCESS;
 393 }
 394
 395 /**
 396  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 397  *  using the SWFW lock - this function is needed in most cases
 398  *  @hw: pointer to hardware structure
 399  *  @reg_addr: 32 bit address of PHY register to read
 400  *  @phy_data: Pointer to read data from PHY register
 401  **/
 402 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 403                                u32 device_type, u16 *phy_data)
 404 {
 405         s32 status;
 406         u16 gssr;
 407
 408         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 409
 410         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 411                 gssr = IXGBE_GSSR_PHY1_SM;
 412         else
 413                 gssr = IXGBE_GSSR_PHY0_SM;
 414
 415         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 416                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 417                                                 phy_data);
 418                 hw->mac.ops.release_swfw_sync(hw, gssr);
 419         } else {
 420                 status = IXGBE_ERR_SWFW_SYNC;
 421         }
 422
 423         return status;
 424 }
 425
 426 /**
 427  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 428  *  without SWFW lock
 429  *  @hw: pointer to hardware structure
 430  *  @reg_addr: 32 bit PHY register to write
 431  *  @device_type: 5 bit device type
 432  *  @phy_data: Data to write to the PHY register
 433  **/
 434 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 435                                 u32 device_type, u16 phy_data)
 436 {
 437         u32 i, command;
 438
 439         /* Put the data in the MDI single read and write data register*/
 440         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 441
 442         /* Setup and write the address cycle command */
 443         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 444                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 445                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 446                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 447
 448         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 449
 450         /*
 451          * Check every 10 usec to see if the address cycle completed.
 452          * The MDI Command bit will clear when the operation is
 453          * complete
 454          */
 455         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 456                 usec_delay(10);
 457
 458                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 459                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 460                         break;
 461         }
 462
 463         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 464                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 465                 return IXGBE_ERR_PHY;
 466         }
 467
 468         /*
 469          * Address cycle complete, setup and write the write
 470          * command
 471          */
 472         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 473                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 474                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 475                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 476
 477         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 478
 479         /*
 480          * Check every 10 usec to see if the address cycle
 481          * completed. The MDI Command bit will clear when the
 482          * operation is complete
 483          */
 484         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 485                 usec_delay(10);
 486
 487                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 488                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 489                         break;
 490         }
 491
 492         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 493                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 494                 return IXGBE_ERR_PHY;
 495         }
 496
 497         return IXGBE_SUCCESS;
 498 }
 499
 500 /**
 501  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 502  *  using SWFW lock- this function is needed in most cases
 503  *  @hw: pointer to hardware structure
 504  *  @reg_addr: 32 bit PHY register to write
 505  *  @device_type: 5 bit device type
 506  *  @phy_data: Data to write to the PHY register
 507  **/
 508 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 509                                 u32 device_type, u16 phy_data)
 510 {
 511         s32 status;
 512         u16 gssr;
 513
 514         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 515
 516         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 517                 gssr = IXGBE_GSSR_PHY1_SM;
 518         else
 519                 gssr = IXGBE_GSSR_PHY0_SM;
 520
 521         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 522                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 523                                                  phy_data);
 524                 hw->mac.ops.release_swfw_sync(hw, gssr);
 525         } else {
 526                 status = IXGBE_ERR_SWFW_SYNC;
 527         }
 528
 529         return status;
 530 }
 531
 532 /**
 533  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 534  *  @hw: pointer to hardware structure
 535  *
 536  *  Restart autonegotiation and PHY and waits for completion.
 537  **/
 538 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 539 {
 540         s32 status = IXGBE_SUCCESS;
 541         u32 time_out;
 542         u32 max_time_out = 10;
 543         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 544         bool autoneg = false;
 545         ixgbe_link_speed speed;
 546
 547         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 548
 549         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 550
 551         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 552                 /* Set or unset auto-negotiation 10G advertisement */
 553                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 554                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 555                                      &autoneg_reg);
 556
 557                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 558                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 559                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 560
 561                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 562                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 563                                       autoneg_reg);
 564         }
 565
 566         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 567                 /* Set or unset auto-negotiation 1G advertisement */
 568                 hw->phy.ops.read_reg(hw,
 569                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 570                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 571                                      &autoneg_reg);
 572
 573                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 574                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 575                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 576
 577                 hw->phy.ops.write_reg(hw,
 578                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 579                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 580                                       autoneg_reg);
 581         }
 582
 583         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 584                 /* Set or unset auto-negotiation 100M advertisement */
 585                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 586                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 587                                      &autoneg_reg);
 588
 589                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 590                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 591                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 592                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 593
 594                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 595                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 596                                       autoneg_reg);
 597         }
 598
 599         /* Blocked by MNG FW so don't reset PHY */
 600         if (ixgbe_check_reset_blocked(hw))
 601                 return status;
 602
 603         /* Restart PHY autonegotiation and wait for completion */
 604         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 605                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 606
 607         autoneg_reg |= IXGBE_MII_RESTART;
 608
 609         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 610                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 611
 612         /* Wait for autonegotiation to finish */
 613         for (time_out = 0; time_out < max_time_out; time_out++) {
 614                 usec_delay(10);
 615                 /* Restart PHY autonegotiation and wait for completion */
 616                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 617                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 618                                               &autoneg_reg);
 619
 620                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 621                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
 622                         break;
 623         }
 624
 625         if (time_out == max_time_out) {
 626                 status = IXGBE_ERR_LINK_SETUP;
 627                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 628                              "PHY autonegotiation time out");
 629         }
 630
 631         return status;
 632 }
 633
 634 /**
 635  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 636  *  @hw: pointer to hardware structure
 637  *  @speed: new link speed
 638  **/
 639 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 640                                        ixgbe_link_speed speed,
 641                                        bool autoneg_wait_to_complete)
 642 {
 643         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 644
 645         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 646
 647         /*
 648          * Clear autoneg_advertised and set new values based on input link
 649          * speed.
 650          */
 651         hw->phy.autoneg_advertised = 0;
 652
 653         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 654                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 655
 656         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 657                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 658
 659         if (speed & IXGBE_LINK_SPEED_100_FULL)
 660                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 661
 662         /* Setup link based on the new speed settings */
 663         hw->phy.ops.setup_link(hw);
 664
 665         return IXGBE_SUCCESS;
 666 }
 667
 668 /**
 669  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 670  *  @hw: pointer to hardware structure
 671  *  @speed: pointer to link speed
 672  *  @autoneg: boolean auto-negotiation value
 673  *
 674  *  Determines the link capabilities by reading the AUTOC register.
 675  **/
 676 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 677                                                ixgbe_link_speed *speed,
 678                                                bool *autoneg)
 679 {
 680         s32 status;
 681         u16 speed_ability;
 682
 683         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 684
 685         *speed = 0;
 686         *autoneg = true;
 687
 688         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 689                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 690                                       &speed_ability);
 691
 692         if (status == IXGBE_SUCCESS) {
 693                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 694                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 695                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 696                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 697                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 698                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 699         }
 700
 701         return status;
 702 }
 703
 704 /**
 705  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 706  *  @hw: pointer to hardware structure
 707  *
 708  *  Reads the VS1 register to determine if link is up and the current speed for
 709  *  the PHY.
 710  **/
 711 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 712                              bool *link_up)
 713 {
 714         s32 status = IXGBE_SUCCESS;
 715         u32 time_out;
 716         u32 max_time_out = 10;
 717         u16 phy_link = 0;
 718         u16 phy_speed = 0;
 719         u16 phy_data = 0;
 720
 721         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 722
 723         /* Initialize speed and link to default case */
 724         *link_up = false;
 725         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 726
 727         /*
 728          * Check current speed and link status of the PHY register.
 729          * This is a vendor specific register and may have to
 730          * be changed for other copper PHYs.
 731          */
 732         for (time_out = 0; time_out < max_time_out; time_out++) {
 733                 usec_delay(10);
 734                 status = hw->phy.ops.read_reg(hw,
 735                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 736                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 737                                         &phy_data);
 738                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 739                 phy_speed = phy_data &
 740                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 741                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 742                         *link_up = true;
 743                         if (phy_speed ==
 744                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 745                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 746                         break;
 747                 }
 748         }
 749
 750         return status;
 751 }
 752
 753 /**
 754  *      ixgbe_setup_phy_link_tnx - Set and restart autoneg
 755  *      @hw: pointer to hardware structure
 756  *
 757  *      Restart autonegotiation and PHY and waits for completion.
 758  **/
 759 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 760 {
 761         s32 status = IXGBE_SUCCESS;
 762         u32 time_out;
 763         u32 max_time_out = 10;
 764         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 765         bool autoneg = false;
 766         ixgbe_link_speed speed;
 767
 768         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
 769
 770         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 771
 772         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 773                 /* Set or unset auto-negotiation 10G advertisement */
 774                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 775                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 776                                      &autoneg_reg);
 777
 778                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 779                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 780                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 781
 782                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 783                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 784                                       autoneg_reg);
 785         }
 786
 787         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 788                 /* Set or unset auto-negotiation 1G advertisement */
 789                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 790                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 791                                      &autoneg_reg);
 792
 793                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 794                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 795                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 796
 797                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 798                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 799                                       autoneg_reg);
 800         }
 801
 802         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 803                 /* Set or unset auto-negotiation 100M advertisement */
 804                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 805                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 806                                      &autoneg_reg);
 807
 808                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
 809                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 810                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 811
 812                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 813                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 814                                       autoneg_reg);
 815         }
 816
 817         /* Blocked by MNG FW so don't reset PHY */
 818         if (ixgbe_check_reset_blocked(hw))
 819                 return status;
 820
 821         /* Restart PHY autonegotiation and wait for completion */
 822         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 823                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 824
 825         autoneg_reg |= IXGBE_MII_RESTART;
 826
 827         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 828                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 829
 830         /* Wait for autonegotiation to finish */
 831         for (time_out = 0; time_out < max_time_out; time_out++) {
 832                 usec_delay(10);
 833                 /* Restart PHY autonegotiation and wait for completion */
 834                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 835                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 836                                               &autoneg_reg);
 837
 838                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 839                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
 840                         break;
 841         }
 842
 843         if (time_out == max_time_out) {
 844                 status = IXGBE_ERR_LINK_SETUP;
 845                 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
 846         }
 847
 848         return status;
 849 }
 850
 851 /**
 852  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 853  *  @hw: pointer to hardware structure
 854  *  @firmware_version: pointer to the PHY Firmware Version
 855  **/
 856 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 857                                        u16 *firmware_version)
 858 {
 859         s32 status;
 860
 861         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
 862
 863         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 864                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 865                                       firmware_version);
 866
 867         return status;
 868 }
 869
 870 /**
 871  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 872  *  @hw: pointer to hardware structure
 873  *  @firmware_version: pointer to the PHY Firmware Version
 874  **/
 875 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 876                                            u16 *firmware_version)
 877 {
 878         s32 status;
 879
 880         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
 881
 882         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 883                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 884                                       firmware_version);
 885
 886         return status;
 887 }
 888
 889 /**
 890  *  ixgbe_reset_phy_nl - Performs a PHY reset
 891  *  @hw: pointer to hardware structure
 892  **/
 893 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 894 {
 895         u16 phy_offset, control, eword, edata, block_crc;
 896         bool end_data = false;
 897         u16 list_offset, data_offset;
 898         u16 phy_data = 0;
 899         s32 ret_val = IXGBE_SUCCESS;
 900         u32 i;
 901
 902         DEBUGFUNC("ixgbe_reset_phy_nl");
 903
 904         /* Blocked by MNG FW so bail */
 905         if (ixgbe_check_reset_blocked(hw))
 906                 goto out;
 907
 908         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 909                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 910
 911         /* reset the PHY and poll for completion */
 912         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 913                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 914                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
 915
 916         for (i = 0; i < 100; i++) {
 917                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 918                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 919                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
 920                         break;
 921                 msec_delay(10);
 922         }
 923
 924         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
 925                 DEBUGOUT("PHY reset did not complete.\n");
 926                 ret_val = IXGBE_ERR_PHY;
 927                 goto out;
 928         }
 929
 930         /* Get init offsets */
 931         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 932                                                       &data_offset);
 933         if (ret_val != IXGBE_SUCCESS)
 934                 goto out;
 935
 936         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 937         data_offset++;
 938         while (!end_data) {
 939                 /*
 940                  * Read control word from PHY init contents offset
 941                  */
 942                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 943                 if (ret_val)
 944                         goto err_eeprom;
 945                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 946                            IXGBE_CONTROL_SHIFT_NL;
 947                 edata = eword & IXGBE_DATA_MASK_NL;
 948                 switch (control) {
 949                 case IXGBE_DELAY_NL:
 950                         data_offset++;
 951                         DEBUGOUT1("DELAY: %d MS\n", edata);
 952                         msec_delay(edata);
 953                         break;
 954                 case IXGBE_DATA_NL:
 955                         DEBUGOUT("DATA:\n");
 956                         data_offset++;
 957                         ret_val = hw->eeprom.ops.read(hw, data_offset,
 958                                                       &phy_offset);
 959                         if (ret_val)
 960                                 goto err_eeprom;
 961                         data_offset++;
 962                         for (i = 0; i < edata; i++) {
 963                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
 964                                                               &eword);
 965                                 if (ret_val)
 966                                         goto err_eeprom;
 967                                 hw->phy.ops.write_reg(hw, phy_offset,
 968                                                       IXGBE_TWINAX_DEV, eword);
 969                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
 970                                           phy_offset);
 971                                 data_offset++;
 972                                 phy_offset++;
 973                         }
 974                         break;
 975                 case IXGBE_CONTROL_NL:
 976                         data_offset++;
 977                         DEBUGOUT("CONTROL:\n");
 978                         if (edata == IXGBE_CONTROL_EOL_NL) {
 979                                 DEBUGOUT("EOL\n");
 980                                 end_data = true;
 981                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 982                                 DEBUGOUT("SOL\n");
 983                         } else {
 984                                 DEBUGOUT("Bad control value\n");
 985                                 ret_val = IXGBE_ERR_PHY;
 986                                 goto out;
 987                         }
 988                         break;
 989                 default:
 990                         DEBUGOUT("Bad control type\n");
 991                         ret_val = IXGBE_ERR_PHY;
 992                         goto out;
 993                 }
 994         }
 995
 996 out:
 997         return ret_val;
 998
 999 err_eeprom:
1000         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1001                       "eeprom read at offset %d failed", data_offset);
1002         return IXGBE_ERR_PHY;
1003 }
1004
1005 /**
1006  *  ixgbe_identify_module_generic - Identifies module type
1007  *  @hw: pointer to hardware structure
1008  *
1009  *  Determines HW type and calls appropriate function.
1010  **/
1011 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1012 {
1013         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1014
1015         DEBUGFUNC("ixgbe_identify_module_generic");
1016
1017         switch (hw->mac.ops.get_media_type(hw)) {
1018         case ixgbe_media_type_fiber:
1019                 status = ixgbe_identify_sfp_module_generic(hw);
1020                 break;
1021
1022
1023         default:
1024                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1025                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1026                 break;
1027         }
1028
1029         return status;
1030 }
1031
1032 /**
1033  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1034  *  @hw: pointer to hardware structure
1035  *
1036  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1037  **/
1038 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1039 {
1040         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1041         u32 vendor_oui = 0;
1042         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1043         u8 identifier = 0;
1044         u8 comp_codes_1g = 0;
1045         u8 comp_codes_10g = 0;
1046         u8 oui_bytes[3] = {0, 0, 0};
1047         u8 cable_tech = 0;
1048         u8 cable_spec = 0;
1049         u16 enforce_sfp = 0;
1050
1051         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1052
1053         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1054                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1055                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1056                 goto out;
1057         }
1058
1059         status = hw->phy.ops.read_i2c_eeprom(hw,
1060                                              IXGBE_SFF_IDENTIFIER,
1061                                              &identifier);
1062
1063         if (status != IXGBE_SUCCESS)
1064                 goto err_read_i2c_eeprom;
1065
1066         /* LAN ID is needed for sfp_type determination */
1067         hw->mac.ops.set_lan_id(hw);
1068
1069         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1070                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1071                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1072         } else {
1073                 status = hw->phy.ops.read_i2c_eeprom(hw,
1074                                                      IXGBE_SFF_1GBE_COMP_CODES,
1075                                                      &comp_codes_1g);
1076
1077                 if (status != IXGBE_SUCCESS)
1078                         goto err_read_i2c_eeprom;
1079
1080                 status = hw->phy.ops.read_i2c_eeprom(hw,
1081                                                      IXGBE_SFF_10GBE_COMP_CODES,
1082                                                      &comp_codes_10g);
1083
1084                 if (status != IXGBE_SUCCESS)
1085                         goto err_read_i2c_eeprom;
1086                 status = hw->phy.ops.read_i2c_eeprom(hw,
1087                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1088                                                      &cable_tech);
1089
1090                 if (status != IXGBE_SUCCESS)
1091                         goto err_read_i2c_eeprom;
1092
1093                  /* ID Module
1094                   * =========
1095                   * 0   SFP_DA_CU
1096                   * 1   SFP_SR
1097                   * 2   SFP_LR
1098                   * 3   SFP_DA_CORE0 - 82599-specific
1099                   * 4   SFP_DA_CORE1 - 82599-specific
1100                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1101                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1102                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1103                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1104                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1105                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1106                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1107                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1108                   */
1109                 if (hw->mac.type == ixgbe_mac_82598EB) {
1110                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1111                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1112                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1113                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1114                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1115                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1116                         else
1117                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1118                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1119                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1120                                 if (hw->bus.lan_id == 0)
1121                                         hw->phy.sfp_type =
1122                                                      ixgbe_sfp_type_da_cu_core0;
1123                                 else
1124                                         hw->phy.sfp_type =
1125                                                      ixgbe_sfp_type_da_cu_core1;
1126                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1127                                 hw->phy.ops.read_i2c_eeprom(
1128                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1129                                                 &cable_spec);
1130                                 if (cable_spec &
1131                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1132                                         if (hw->bus.lan_id == 0)
1133                                                 hw->phy.sfp_type =
1134                                                 ixgbe_sfp_type_da_act_lmt_core0;
1135                                         else
1136                                                 hw->phy.sfp_type =
1137                                                 ixgbe_sfp_type_da_act_lmt_core1;
1138                                 } else {
1139                                         hw->phy.sfp_type =
1140                                                         ixgbe_sfp_type_unknown;
1141                                 }
1142                         } else if (comp_codes_10g &
1143                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1144                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1145                                 if (hw->bus.lan_id == 0)
1146                                         hw->phy.sfp_type =
1147                                                       ixgbe_sfp_type_srlr_core0;
1148                                 else
1149                                         hw->phy.sfp_type =
1150                                                       ixgbe_sfp_type_srlr_core1;
1151 #ifdef SUPPORT_10GBASE_ER
1152                         } else if (comp_codes_10g &
1153                                    IXGBE_SFF_10GBASEER_CAPABLE) {
1154                                 if (hw->bus.lan_id == 0)
1155                                         hw->phy.sfp_type =
1156                                                         ixgbe_sfp_type_er_core0;
1157                                 else
1158                                         hw->phy.sfp_type =
1159                                                         ixgbe_sfp_type_er_core1;
1160 #endif /* SUPPORT_10GBASE_ER */
1161                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1162                                 if (hw->bus.lan_id == 0)
1163                                         hw->phy.sfp_type =
1164                                                 ixgbe_sfp_type_1g_cu_core0;
1165                                 else
1166                                         hw->phy.sfp_type =
1167                                                 ixgbe_sfp_type_1g_cu_core1;
1168                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1169                                 if (hw->bus.lan_id == 0)
1170                                         hw->phy.sfp_type =
1171                                                 ixgbe_sfp_type_1g_sx_core0;
1172                                 else
1173                                         hw->phy.sfp_type =
1174                                                 ixgbe_sfp_type_1g_sx_core1;
1175 #ifdef SUPPORT_1000BASE_LX
1176                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1177                                 if (hw->bus.lan_id == 0)
1178                                         hw->phy.sfp_type =
1179                                                 ixgbe_sfp_type_1g_lx_core0;
1180                                 else
1181                                         hw->phy.sfp_type =
1182                                                 ixgbe_sfp_type_1g_lx_core1;
1183 #endif /* SUPPORT_1000BASE_LX */
1184                         } else {
1185                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1186                         }
1187                 }
1188
1189                 if (hw->phy.sfp_type != stored_sfp_type)
1190                         hw->phy.sfp_setup_needed = true;
1191
1192                 /* Determine if the SFP+ PHY is dual speed or not. */
1193                 hw->phy.multispeed_fiber = false;
1194                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1195                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1196                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1197                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1198                         hw->phy.multispeed_fiber = true;
1199
1200                 /* Determine PHY vendor */
1201                 if (hw->phy.type != ixgbe_phy_nl) {
1202                         hw->phy.id = identifier;
1203                         status = hw->phy.ops.read_i2c_eeprom(hw,
1204                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1205                                                     &oui_bytes[0]);
1206
1207                         if (status != IXGBE_SUCCESS)
1208                                 goto err_read_i2c_eeprom;
1209
1210                         status = hw->phy.ops.read_i2c_eeprom(hw,
1211                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1212                                                     &oui_bytes[1]);
1213
1214                         if (status != IXGBE_SUCCESS)
1215                                 goto err_read_i2c_eeprom;
1216
1217                         status = hw->phy.ops.read_i2c_eeprom(hw,
1218                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1219                                                     &oui_bytes[2]);
1220
1221                         if (status != IXGBE_SUCCESS)
1222                                 goto err_read_i2c_eeprom;
1223
1224                         vendor_oui =
1225                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1226                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1227                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1228
1229                         switch (vendor_oui) {
1230                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1231                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1232                                         hw->phy.type =
1233                                                     ixgbe_phy_sfp_passive_tyco;
1234                                 break;
1235                         case IXGBE_SFF_VENDOR_OUI_FTL:
1236                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1237                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1238                                 else
1239                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1240                                 break;
1241                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1242                                 hw->phy.type = ixgbe_phy_sfp_avago;
1243                                 break;
1244                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1245                                 hw->phy.type = ixgbe_phy_sfp_intel;
1246                                 break;
1247                         default:
1248                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1249                                         hw->phy.type =
1250                                                  ixgbe_phy_sfp_passive_unknown;
1251                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1252                                         hw->phy.type =
1253                                                 ixgbe_phy_sfp_active_unknown;
1254                                 else
1255                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1256                                 break;
1257                         }
1258                 }
1259
1260                 /* Allow any DA cable vendor */
1261                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1262                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1263                         status = IXGBE_SUCCESS;
1264                         goto out;
1265                 }
1266
1267                 /* Verify supported 1G SFP modules */
1268                 if (comp_codes_10g == 0 &&
1269                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1270                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1271 #ifdef SUPPORT_1000BASE_LX
1272                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1273                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1274 #endif
1275                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1276                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1277                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1278                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1279                         goto out;
1280                 }
1281
1282                 /* Anything else 82598-based is supported */
1283                 if (hw->mac.type == ixgbe_mac_82598EB) {
1284                         status = IXGBE_SUCCESS;
1285                         goto out;
1286                 }
1287
1288                 ixgbe_get_device_caps(hw, &enforce_sfp);
1289                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1290                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1291                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1292 #ifdef SUPPORT_1000BASE_LX
1293                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1294                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1295 #endif
1296 #ifdef SUPPORT_10GBASE_ER
1297                       hw->phy.sfp_type == ixgbe_sfp_type_er_core0 ||
1298                       hw->phy.sfp_type == ixgbe_sfp_type_er_core1 ||
1299 #endif
1300                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1301                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1302                         /* Make sure we're a supported PHY type */
1303                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1304                                 status = IXGBE_SUCCESS;
1305                         } else {
1306                                 if (hw->allow_unsupported_sfp == true) {
1307                                         EWARN(hw, "WARNING: Intel (R) Network "
1308                                               "Connections are quality tested "
1309                                               "using Intel (R) Ethernet Optics."
1310                                               " Using untested modules is not "
1311                                               "supported and may cause unstable"
1312                                               " operation or damage to the "
1313                                               "module or the adapter. Intel "
1314                                               "Corporation is not responsible "
1315                                               "for any harm caused by using "
1316                                               "untested modules.\n", status);
1317                                         status = IXGBE_SUCCESS;
1318                                 } else {
1319                                         DEBUGOUT("SFP+ module not supported\n");
1320                                         hw->phy.type =
1321                                                 ixgbe_phy_sfp_unsupported;
1322                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1323                                 }
1324                         }
1325                 } else {
1326                         status = IXGBE_SUCCESS;
1327                 }
1328         }
1329
1330 out:
1331         return status;
1332
1333 err_read_i2c_eeprom:
1334         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1335         if (hw->phy.type != ixgbe_phy_nl) {
1336                 hw->phy.id = 0;
1337                 hw->phy.type = ixgbe_phy_unknown;
1338         }
1339         return IXGBE_ERR_SFP_NOT_PRESENT;
1340 }
1341
1342
1343
1344 /**
1345  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1346  *  @hw: pointer to hardware structure
1347  *  @list_offset: offset to the SFP ID list
1348  *  @data_offset: offset to the SFP data block
1349  *
1350  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1351  *  so it returns the offsets to the phy init sequence block.
1352  **/
1353 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1354                                         u16 *list_offset,
1355                                         u16 *data_offset)
1356 {
1357         u16 sfp_id;
1358         u16 sfp_type = hw->phy.sfp_type;
1359
1360         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1361
1362         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1363                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1364
1365         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1366                 return IXGBE_ERR_SFP_NOT_PRESENT;
1367
1368         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1369             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1370                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1371
1372         /*
1373          * Limiting active cables and 1G Phys must be initialized as
1374          * SR modules
1375          */
1376         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1377 #ifdef SUPPORT_10GBASE_ER
1378             sfp_type == ixgbe_sfp_type_er_core0 ||
1379 #endif /* SUPPORT_10GBASE_ER */
1380 #ifdef SUPPORT_1000BASE_LX
1381             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1382 #endif /* SUPPORT_1000BASE_LX */
1383             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1384             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1385                 sfp_type = ixgbe_sfp_type_srlr_core0;
1386         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1387 #ifdef SUPPORT_10GBASE_ER
1388                  sfp_type == ixgbe_sfp_type_er_core1 ||
1389 #endif /* SUPPORT_10GBASE_ER */
1390 #ifdef SUPPORT_1000BASE_LX
1391                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1392 #endif /* SUPPORT_1000BASE_LX */
1393                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1394                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1395                 sfp_type = ixgbe_sfp_type_srlr_core1;
1396
1397         /* Read offset to PHY init contents */
1398         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1399                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1400                               "eeprom read at offset %d failed",
1401                               IXGBE_PHY_INIT_OFFSET_NL);
1402                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1403         }
1404
1405         if ((!*list_offset) || (*list_offset == 0xFFFF))
1406                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1407
1408         /* Shift offset to first ID word */
1409         (*list_offset)++;
1410
1411         /*
1412          * Find the matching SFP ID in the EEPROM
1413          * and program the init sequence
1414          */
1415         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1416                 goto err_phy;
1417
1418         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1419                 if (sfp_id == sfp_type) {
1420                         (*list_offset)++;
1421                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1422                                 goto err_phy;
1423                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1424                                 DEBUGOUT("SFP+ module not supported\n");
1425                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1426                         } else {
1427                                 break;
1428                         }
1429                 } else {
1430                         (*list_offset) += 2;
1431                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1432                                 goto err_phy;
1433                 }
1434         }
1435
1436         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1437                 DEBUGOUT("No matching SFP+ module found\n");
1438                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1439         }
1440
1441         return IXGBE_SUCCESS;
1442
1443 err_phy:
1444         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1445                       "eeprom read at offset %d failed", *list_offset);
1446         return IXGBE_ERR_PHY;
1447 }
1448
1449 /**
1450  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1451  *  @hw: pointer to hardware structure
1452  *  @byte_offset: EEPROM byte offset to read
1453  *  @eeprom_data: value read
1454  *
1455  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1456  **/
1457 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1458                                   u8 *eeprom_data)
1459 {
1460         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1461
1462         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1463                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1464                                          eeprom_data);
1465 }
1466
1467 /**
1468  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1469  *  @hw: pointer to hardware structure
1470  *  @byte_offset: byte offset at address 0xA2
1471  *  @eeprom_data: value read
1472  *
1473  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1474  **/
1475 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1476                                           u8 *sff8472_data)
1477 {
1478         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1479                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1480                                          sff8472_data);
1481 }
1482
1483 /**
1484  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1485  *  @hw: pointer to hardware structure
1486  *  @byte_offset: EEPROM byte offset to write
1487  *  @eeprom_data: value to write
1488  *
1489  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1490  **/
1491 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1492                                    u8 eeprom_data)
1493 {
1494         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1495
1496         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1497                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1498                                           eeprom_data);
1499 }
1500
1501 /**
1502  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1503  *  @hw: pointer to hardware structure
1504  *  @byte_offset: byte offset to read
1505  *  @data: value read
1506  *
1507  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1508  *  a specified device address.
1509  **/
1510 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1511                                 u8 dev_addr, u8 *data)
1512 {
1513         s32 status = IXGBE_SUCCESS;
1514         u32 max_retry = 10;
1515         u32 retry = 0;
1516         u16 swfw_mask = 0;
1517         bool nack = 1;
1518         *data = 0;
1519
1520         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1521
1522         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1523                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1524         else
1525                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1526
1527         do {
1528                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1529                     != IXGBE_SUCCESS) {
1530                         status = IXGBE_ERR_SWFW_SYNC;
1531                         goto read_byte_out;
1532                 }
1533
1534                 ixgbe_i2c_start(hw);
1535
1536                 /* Device Address and write indication */
1537                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1538                 if (status != IXGBE_SUCCESS)
1539                         goto fail;
1540
1541                 status = ixgbe_get_i2c_ack(hw);
1542                 if (status != IXGBE_SUCCESS)
1543                         goto fail;
1544
1545                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1546                 if (status != IXGBE_SUCCESS)
1547                         goto fail;
1548
1549                 status = ixgbe_get_i2c_ack(hw);
1550                 if (status != IXGBE_SUCCESS)
1551                         goto fail;
1552
1553                 ixgbe_i2c_start(hw);
1554
1555                 /* Device Address and read indication */
1556                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1557                 if (status != IXGBE_SUCCESS)
1558                         goto fail;
1559
1560                 status = ixgbe_get_i2c_ack(hw);
1561                 if (status != IXGBE_SUCCESS)
1562                         goto fail;
1563
1564                 status = ixgbe_clock_in_i2c_byte(hw, data);
1565                 if (status != IXGBE_SUCCESS)
1566                         goto fail;
1567
1568                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1569                 if (status != IXGBE_SUCCESS)
1570                         goto fail;
1571
1572                 ixgbe_i2c_stop(hw);
1573                 break;
1574
1575 fail:
1576                 ixgbe_i2c_bus_clear(hw);
1577                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1578                 msec_delay(100);
1579                 retry++;
1580                 if (retry < max_retry)
1581                         DEBUGOUT("I2C byte read error - Retrying.\n");
1582                 else
1583                         DEBUGOUT("I2C byte read error.\n");
1584
1585         } while (retry < max_retry);
1586
1587         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1588
1589 read_byte_out:
1590         return status;
1591 }
1592
1593 /**
1594  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1595  *  @hw: pointer to hardware structure
1596  *  @byte_offset: byte offset to write
1597  *  @data: value to write
1598  *
1599  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1600  *  a specified device address.
1601  **/
1602 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1603                                  u8 dev_addr, u8 data)
1604 {
1605         s32 status = IXGBE_SUCCESS;
1606         u32 max_retry = 1;
1607         u32 retry = 0;
1608         u16 swfw_mask = 0;
1609
1610         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1611
1612         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1613                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1614         else
1615                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1616
1617         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1618                 status = IXGBE_ERR_SWFW_SYNC;
1619                 goto write_byte_out;
1620         }
1621
1622         do {
1623                 ixgbe_i2c_start(hw);
1624
1625                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1626                 if (status != IXGBE_SUCCESS)
1627                         goto fail;
1628
1629                 status = ixgbe_get_i2c_ack(hw);
1630                 if (status != IXGBE_SUCCESS)
1631                         goto fail;
1632
1633                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1634                 if (status != IXGBE_SUCCESS)
1635                         goto fail;
1636
1637                 status = ixgbe_get_i2c_ack(hw);
1638                 if (status != IXGBE_SUCCESS)
1639                         goto fail;
1640
1641                 status = ixgbe_clock_out_i2c_byte(hw, data);
1642                 if (status != IXGBE_SUCCESS)
1643                         goto fail;
1644
1645                 status = ixgbe_get_i2c_ack(hw);
1646                 if (status != IXGBE_SUCCESS)
1647                         goto fail;
1648
1649                 ixgbe_i2c_stop(hw);
1650                 break;
1651
1652 fail:
1653                 ixgbe_i2c_bus_clear(hw);
1654                 retry++;
1655                 if (retry < max_retry)
1656                         DEBUGOUT("I2C byte write error - Retrying.\n");
1657                 else
1658                         DEBUGOUT("I2C byte write error.\n");
1659         } while (retry < max_retry);
1660
1661         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1662
1663 write_byte_out:
1664         return status;
1665 }
1666
1667 /**
1668  *  ixgbe_i2c_start - Sets I2C start condition
1669  *  @hw: pointer to hardware structure
1670  *
1671  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1672  **/
1673 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
1674 {
1675         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1676
1677         DEBUGFUNC("ixgbe_i2c_start");
1678
1679         /* Start condition must begin with data and clock high */
1680         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1681         ixgbe_raise_i2c_clk(hw, &i2cctl);
1682
1683         /* Setup time for start condition (4.7us) */
1684         usec_delay(IXGBE_I2C_T_SU_STA);
1685
1686         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1687
1688         /* Hold time for start condition (4us) */
1689         usec_delay(IXGBE_I2C_T_HD_STA);
1690
1691         ixgbe_lower_i2c_clk(hw, &i2cctl);
1692
1693         /* Minimum low period of clock is 4.7 us */
1694         usec_delay(IXGBE_I2C_T_LOW);
1695
1696 }
1697
1698 /**
1699  *  ixgbe_i2c_stop - Sets I2C stop condition
1700  *  @hw: pointer to hardware structure
1701  *
1702  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1703  **/
1704 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1705 {
1706         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1707
1708         DEBUGFUNC("ixgbe_i2c_stop");
1709
1710         /* Stop condition must begin with data low and clock high */
1711         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1712         ixgbe_raise_i2c_clk(hw, &i2cctl);
1713
1714         /* Setup time for stop condition (4us) */
1715         usec_delay(IXGBE_I2C_T_SU_STO);
1716
1717         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1718
1719         /* bus free time between stop and start (4.7us)*/
1720         usec_delay(IXGBE_I2C_T_BUF);
1721 }
1722
1723 /**
1724  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1725  *  @hw: pointer to hardware structure
1726  *  @data: data byte to clock in
1727  *
1728  *  Clocks in one byte data via I2C data/clock
1729  **/
1730 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1731 {
1732         s32 i;
1733         bool bit = 0;
1734
1735         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1736
1737         for (i = 7; i >= 0; i--) {
1738                 ixgbe_clock_in_i2c_bit(hw, &bit);
1739                 *data |= bit << i;
1740         }
1741
1742         return IXGBE_SUCCESS;
1743 }
1744
1745 /**
1746  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1747  *  @hw: pointer to hardware structure
1748  *  @data: data byte clocked out
1749  *
1750  *  Clocks out one byte data via I2C data/clock
1751  **/
1752 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1753 {
1754         s32 status = IXGBE_SUCCESS;
1755         s32 i;
1756         u32 i2cctl;
1757         bool bit;
1758
1759         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1760
1761         for (i = 7; i >= 0; i--) {
1762                 bit = (data >> i) & 0x1;
1763                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1764
1765                 if (status != IXGBE_SUCCESS)
1766                         break;
1767         }
1768
1769         /* Release SDA line (set high) */
1770         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1771         i2cctl |= IXGBE_I2C_DATA_OUT;
1772         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1773         IXGBE_WRITE_FLUSH(hw);
1774
1775         return status;
1776 }
1777
1778 /**
1779  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1780  *  @hw: pointer to hardware structure
1781  *
1782  *  Clocks in/out one bit via I2C data/clock
1783  **/
1784 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1785 {
1786         s32 status = IXGBE_SUCCESS;
1787         u32 i = 0;
1788         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1789         u32 timeout = 10;
1790         bool ack = 1;
1791
1792         DEBUGFUNC("ixgbe_get_i2c_ack");
1793
1794         ixgbe_raise_i2c_clk(hw, &i2cctl);
1795
1796
1797         /* Minimum high period of clock is 4us */
1798         usec_delay(IXGBE_I2C_T_HIGH);
1799
1800         /* Poll for ACK.  Note that ACK in I2C spec is
1801          * transition from 1 to 0 */
1802         for (i = 0; i < timeout; i++) {
1803                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1804                 ack = ixgbe_get_i2c_data(&i2cctl);
1805
1806                 usec_delay(1);
1807                 if (ack == 0)
1808                         break;
1809         }
1810
1811         if (ack == 1) {
1812                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1813                              "I2C ack was not received.\n");
1814                 status = IXGBE_ERR_I2C;
1815         }
1816
1817         ixgbe_lower_i2c_clk(hw, &i2cctl);
1818
1819         /* Minimum low period of clock is 4.7 us */
1820         usec_delay(IXGBE_I2C_T_LOW);
1821
1822         return status;
1823 }
1824
1825 /**
1826  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1827  *  @hw: pointer to hardware structure
1828  *  @data: read data value
1829  *
1830  *  Clocks in one bit via I2C data/clock
1831  **/
1832 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1833 {
1834         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1835
1836         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1837
1838         ixgbe_raise_i2c_clk(hw, &i2cctl);
1839
1840         /* Minimum high period of clock is 4us */
1841         usec_delay(IXGBE_I2C_T_HIGH);
1842
1843         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1844         *data = ixgbe_get_i2c_data(&i2cctl);
1845
1846         ixgbe_lower_i2c_clk(hw, &i2cctl);
1847
1848         /* Minimum low period of clock is 4.7 us */
1849         usec_delay(IXGBE_I2C_T_LOW);
1850
1851         return IXGBE_SUCCESS;
1852 }
1853
1854 /**
1855  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1856  *  @hw: pointer to hardware structure
1857  *  @data: data value to write
1858  *
1859  *  Clocks out one bit via I2C data/clock
1860  **/
1861 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1862 {
1863         s32 status;
1864         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1865
1866         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1867
1868         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1869         if (status == IXGBE_SUCCESS) {
1870                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1871
1872                 /* Minimum high period of clock is 4us */
1873                 usec_delay(IXGBE_I2C_T_HIGH);
1874
1875                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1876
1877                 /* Minimum low period of clock is 4.7 us.
1878                  * This also takes care of the data hold time.
1879                  */
1880                 usec_delay(IXGBE_I2C_T_LOW);
1881         } else {
1882                 status = IXGBE_ERR_I2C;
1883                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1884                              "I2C data was not set to %X\n", data);
1885         }
1886
1887         return status;
1888 }
1889 /**
1890  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1891  *  @hw: pointer to hardware structure
1892  *  @i2cctl: Current value of I2CCTL register
1893  *
1894  *  Raises the I2C clock line '0'->'1'
1895  **/
1896 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1897 {
1898         u32 i = 0;
1899         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1900         u32 i2cctl_r = 0;
1901
1902         DEBUGFUNC("ixgbe_raise_i2c_clk");
1903
1904         for (i = 0; i < timeout; i++) {
1905                 *i2cctl |= IXGBE_I2C_CLK_OUT;
1906
1907                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1908                 IXGBE_WRITE_FLUSH(hw);
1909                 /* SCL rise time (1000ns) */
1910                 usec_delay(IXGBE_I2C_T_RISE);
1911
1912                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1913                 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1914                         break;
1915         }
1916 }
1917
1918 /**
1919  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1920  *  @hw: pointer to hardware structure
1921  *  @i2cctl: Current value of I2CCTL register
1922  *
1923  *  Lowers the I2C clock line '1'->'0'
1924  **/
1925 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1926 {
1927
1928         DEBUGFUNC("ixgbe_lower_i2c_clk");
1929
1930         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1931
1932         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1933         IXGBE_WRITE_FLUSH(hw);
1934
1935         /* SCL fall time (300ns) */
1936         usec_delay(IXGBE_I2C_T_FALL);
1937 }
1938
1939 /**
1940  *  ixgbe_set_i2c_data - Sets the I2C data bit
1941  *  @hw: pointer to hardware structure
1942  *  @i2cctl: Current value of I2CCTL register
1943  *  @data: I2C data value (0 or 1) to set
1944  *
1945  *  Sets the I2C data bit
1946  **/
1947 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1948 {
1949         s32 status = IXGBE_SUCCESS;
1950
1951         DEBUGFUNC("ixgbe_set_i2c_data");
1952
1953         if (data)
1954                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1955         else
1956                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1957
1958         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1959         IXGBE_WRITE_FLUSH(hw);
1960
1961         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1962         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1963
1964         /* Verify data was set correctly */
1965         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1966         if (data != ixgbe_get_i2c_data(i2cctl)) {
1967                 status = IXGBE_ERR_I2C;
1968                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1969                              "Error - I2C data was not set to %X.\n",
1970                              data);
1971         }
1972
1973         return status;
1974 }
1975
1976 /**
1977  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1978  *  @hw: pointer to hardware structure
1979  *  @i2cctl: Current value of I2CCTL register
1980  *
1981  *  Returns the I2C data bit value
1982  **/
1983 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl)
1984 {
1985         bool data;
1986
1987         DEBUGFUNC("ixgbe_get_i2c_data");
1988
1989         if (*i2cctl & IXGBE_I2C_DATA_IN)
1990                 data = 1;
1991         else
1992                 data = 0;
1993
1994         return data;
1995 }
1996
1997 /**
1998  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1999  *  @hw: pointer to hardware structure
2000  *
2001  *  Clears the I2C bus by sending nine clock pulses.
2002  *  Used when data line is stuck low.
2003  **/
2004 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2005 {
2006         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
2007         u32 i;
2008
2009         DEBUGFUNC("ixgbe_i2c_bus_clear");
2010
2011         ixgbe_i2c_start(hw);
2012
2013         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2014
2015         for (i = 0; i < 9; i++) {
2016                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2017
2018                 /* Min high period of clock is 4us */
2019                 usec_delay(IXGBE_I2C_T_HIGH);
2020
2021                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2022
2023                 /* Min low period of clock is 4.7us*/
2024                 usec_delay(IXGBE_I2C_T_LOW);
2025         }
2026
2027         ixgbe_i2c_start(hw);
2028
2029         /* Put the i2c bus back to default state */
2030         ixgbe_i2c_stop(hw);
2031 }
2032
2033 /**
2034  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2035  *  @hw: pointer to hardware structure
2036  *
2037  *  Checks if the LASI temp alarm status was triggered due to overtemp
2038  **/
2039 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2040 {
2041         s32 status = IXGBE_SUCCESS;
2042         u16 phy_data = 0;
2043
2044         DEBUGFUNC("ixgbe_tn_check_overtemp");
2045
2046         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2047                 goto out;
2048
2049         /* Check that the LASI temp alarm status was triggered */
2050         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2051                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2052
2053         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2054                 goto out;
2055
2056         status = IXGBE_ERR_OVERTEMP;
2057         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2058 out:
2059         return status;
2060 }