lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37 #ident "$Id: ixgbe_phy.c,v 1.139 2012/05/24 23:36:12 jtkirshe Exp $"
  38
  39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
  40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  49 static bool ixgbe_get_i2c_data(u32 *i2cctl);
  50
  51 /**
  52  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
  53  *  @hw: pointer to the hardware structure
  54  *
  55  *  Initialize the function pointers.
  56  **/
  57 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
  58 {
  59         struct ixgbe_phy_info *phy = &hw->phy;
  60
  61         DEBUGFUNC("ixgbe_init_phy_ops_generic");
  62
  63         /* PHY */
  64         phy->ops.identify = &ixgbe_identify_phy_generic;
  65         phy->ops.reset = &ixgbe_reset_phy_generic;
  66         phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
  67         phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
  68         phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
  69         phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
  70         phy->ops.check_link = NULL;
  71         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
  72         phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
  73         phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
  74         phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
  75         phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
  76         phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
  77         phy->ops.identify_sfp = &ixgbe_identify_module_generic;
  78         phy->sfp_type = ixgbe_sfp_type_unknown;
  79         phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
  80         return IXGBE_SUCCESS;
  81 }
  82
  83 /**
  84  *  ixgbe_identify_phy_generic - Get physical layer module
  85  *  @hw: pointer to hardware structure
  86  *
  87  *  Determines the physical layer module found on the current adapter.
  88  **/
  89 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  90 {
  91         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  92         u32 phy_addr;
  93         u16 ext_ability = 0;
  94
  95         DEBUGFUNC("ixgbe_identify_phy_generic");
  96
  97         if (hw->phy.type == ixgbe_phy_unknown) {
  98                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  99                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 100                                 hw->phy.addr = phy_addr;
 101                                 ixgbe_get_phy_id(hw);
 102                                 hw->phy.type =
 103                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 104
 105                                 if (hw->phy.type == ixgbe_phy_unknown) {
 106                                         hw->phy.ops.read_reg(hw,
 107                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 108                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 109                                                   &ext_ability);
 110                                         if (ext_ability &
 111                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 112                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 113                                                 hw->phy.type =
 114                                                          ixgbe_phy_cu_unknown;
 115                                         else
 116                                                 hw->phy.type =
 117                                                          ixgbe_phy_generic;
 118                                 }
 119
 120                                 status = IXGBE_SUCCESS;
 121                                 break;
 122                         }
 123                 }
 124                 /* clear value if nothing found */
 125                 if (status != IXGBE_SUCCESS)
 126                         hw->phy.addr = 0;
 127         } else {
 128                 status = IXGBE_SUCCESS;
 129         }
 130
 131         return status;
 132 }
 133
 134 /**
 135  *  ixgbe_validate_phy_addr - Determines phy address is valid
 136  *  @hw: pointer to hardware structure
 137  *
 138  **/
 139 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 140 {
 141         u16 phy_id = 0;
 142         bool valid = false;
 143
 144         DEBUGFUNC("ixgbe_validate_phy_addr");
 145
 146         hw->phy.addr = phy_addr;
 147         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 148                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 149
 150         if (phy_id != 0xFFFF && phy_id != 0x0)
 151                 valid = true;
 152
 153         return valid;
 154 }
 155
 156 /**
 157  *  ixgbe_get_phy_id - Get the phy type
 158  *  @hw: pointer to hardware structure
 159  *
 160  **/
 161 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 162 {
 163         u32 status;
 164         u16 phy_id_high = 0;
 165         u16 phy_id_low = 0;
 166
 167         DEBUGFUNC("ixgbe_get_phy_id");
 168
 169         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 170                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 171                                       &phy_id_high);
 172
 173         if (status == IXGBE_SUCCESS) {
 174                 hw->phy.id = (u32)(phy_id_high << 16);
 175                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 176                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 177                                               &phy_id_low);
 178                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 179                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 180         }
 181         return status;
 182 }
 183
 184 /**
 185  *  ixgbe_get_phy_type_from_id - Get the phy type
 186  *  @hw: pointer to hardware structure
 187  *
 188  **/
 189 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 190 {
 191         enum ixgbe_phy_type phy_type;
 192
 193         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 194
 195         switch (phy_id) {
 196         case TN1010_PHY_ID:
 197                 phy_type = ixgbe_phy_tn;
 198                 break;
 199         case X540_PHY_ID:
 200                 phy_type = ixgbe_phy_aq;
 201                 break;
 202         case QT2022_PHY_ID:
 203                 phy_type = ixgbe_phy_qt;
 204                 break;
 205         case ATH_PHY_ID:
 206                 phy_type = ixgbe_phy_nl;
 207                 break;
 208         default:
 209                 phy_type = ixgbe_phy_unknown;
 210                 break;
 211         }
 212
 213         DEBUGOUT1("phy type found is %d\n", phy_type);
 214         return phy_type;
 215 }
 216
 217 /**
 218  *  ixgbe_reset_phy_generic - Performs a PHY reset
 219  *  @hw: pointer to hardware structure
 220  **/
 221 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 222 {
 223         u32 i;
 224         u16 ctrl = 0;
 225         s32 status = IXGBE_SUCCESS;
 226
 227         DEBUGFUNC("ixgbe_reset_phy_generic");
 228
 229         if (hw->phy.type == ixgbe_phy_unknown)
 230                 status = ixgbe_identify_phy_generic(hw);
 231
 232         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 233                 goto out;
 234
 235         /* Don't reset PHY if it's shut down due to overtemp. */
 236         if (!hw->phy.reset_if_overtemp &&
 237             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 238                 goto out;
 239
 240         /*
 241          * Perform soft PHY reset to the PHY_XS.
 242          * This will cause a soft reset to the PHY
 243          */
 244         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 245                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 246                               IXGBE_MDIO_PHY_XS_RESET);
 247
 248         /*
 249          * Poll for reset bit to self-clear indicating reset is complete.
 250          * Some PHYs could take up to 3 seconds to complete and need about
 251          * 1.7 usec delay after the reset is complete.
 252          */
 253         for (i = 0; i < 30; i++) {
 254                 msec_delay(100);
 255                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 256                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 257                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 258                         usec_delay(2);
 259                         break;
 260                 }
 261         }
 262
 263         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 264                 status = IXGBE_ERR_RESET_FAILED;
 265                 DEBUGOUT("PHY reset polling failed to complete.\n");
 266         }
 267
 268 out:
 269         return status;
 270 }
 271
 272 /**
 273  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 274  *  @hw: pointer to hardware structure
 275  *  @reg_addr: 32 bit address of PHY register to read
 276  *  @phy_data: Pointer to read data from PHY register
 277  **/
 278 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 279                                u32 device_type, u16 *phy_data)
 280 {
 281         u32 command;
 282         u32 i;
 283         u32 data;
 284         s32 status = IXGBE_SUCCESS;
 285         u16 gssr;
 286
 287         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 288
 289         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 290                 gssr = IXGBE_GSSR_PHY1_SM;
 291         else
 292                 gssr = IXGBE_GSSR_PHY0_SM;
 293
 294         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
 295                 status = IXGBE_ERR_SWFW_SYNC;
 296
 297         if (status == IXGBE_SUCCESS) {
 298                 /* Setup and write the address cycle command */
 299                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 300                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 301                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 302                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 303
 304                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 305
 306                 /*
 307                  * Check every 10 usec to see if the address cycle completed.
 308                  * The MDI Command bit will clear when the operation is
 309                  * complete
 310                  */
 311                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 312                         usec_delay(10);
 313
 314                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 315
 316                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 317                                 break;
 318                 }
 319
 320                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 321                         DEBUGOUT("PHY address command did not complete.\n");
 322                         status = IXGBE_ERR_PHY;
 323                 }
 324
 325                 if (status == IXGBE_SUCCESS) {
 326                         /*
 327                          * Address cycle complete, setup and write the read
 328                          * command
 329                          */
 330                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 331                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 332                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 333                                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 334
 335                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 336
 337                         /*
 338                          * Check every 10 usec to see if the address cycle
 339                          * completed. The MDI Command bit will clear when the
 340                          * operation is complete
 341                          */
 342                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 343                                 usec_delay(10);
 344
 345                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 346
 347                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 348                                         break;
 349                         }
 350
 351                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 352                                 DEBUGOUT("PHY read command didn't complete\n");
 353                                 status = IXGBE_ERR_PHY;
 354                         } else {
 355                                 /*
 356                                  * Read operation is complete.  Get the data
 357                                  * from MSRWD
 358                                  */
 359                                 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 360                                 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 361                                 *phy_data = (u16)(data);
 362                         }
 363                 }
 364
 365                 hw->mac.ops.release_swfw_sync(hw, gssr);
 366         }
 367
 368         return status;
 369 }
 370
 371 /**
 372  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 373  *  @hw: pointer to hardware structure
 374  *  @reg_addr: 32 bit PHY register to write
 375  *  @device_type: 5 bit device type
 376  *  @phy_data: Data to write to the PHY register
 377  **/
 378 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 379                                 u32 device_type, u16 phy_data)
 380 {
 381         u32 command;
 382         u32 i;
 383         s32 status = IXGBE_SUCCESS;
 384         u16 gssr;
 385
 386         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 387
 388         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 389                 gssr = IXGBE_GSSR_PHY1_SM;
 390         else
 391                 gssr = IXGBE_GSSR_PHY0_SM;
 392
 393         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
 394                 status = IXGBE_ERR_SWFW_SYNC;
 395
 396         if (status == IXGBE_SUCCESS) {
 397                 /* Put the data in the MDI single read and write data register*/
 398                 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 399
 400                 /* Setup and write the address cycle command */
 401                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 402                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 403                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 404                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 405
 406                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 407
 408                 /*
 409                  * Check every 10 usec to see if the address cycle completed.
 410                  * The MDI Command bit will clear when the operation is
 411                  * complete
 412                  */
 413                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 414                         usec_delay(10);
 415
 416                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 417
 418                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 419                                 break;
 420                 }
 421
 422                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 423                         DEBUGOUT("PHY address cmd didn't complete\n");
 424                         status = IXGBE_ERR_PHY;
 425                 }
 426
 427                 if (status == IXGBE_SUCCESS) {
 428                         /*
 429                          * Address cycle complete, setup and write the write
 430                          * command
 431                          */
 432                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 433                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 434                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 435                                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 436
 437                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 438
 439                         /*
 440                          * Check every 10 usec to see if the address cycle
 441                          * completed. The MDI Command bit will clear when the
 442                          * operation is complete
 443                          */
 444                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 445                                 usec_delay(10);
 446
 447                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 448
 449                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 450                                         break;
 451                         }
 452
 453                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 454                                 DEBUGOUT("PHY address cmd didn't complete\n");
 455                                 status = IXGBE_ERR_PHY;
 456                         }
 457                 }
 458
 459                 hw->mac.ops.release_swfw_sync(hw, gssr);
 460         }
 461
 462         return status;
 463 }
 464
 465 /**
 466  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 467  *  @hw: pointer to hardware structure
 468  *
 469  *  Restart autonegotiation and PHY and waits for completion.
 470  **/
 471 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 472 {
 473         s32 status = IXGBE_SUCCESS;
 474         u32 time_out;
 475         u32 max_time_out = 10;
 476         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 477         bool autoneg = false;
 478         ixgbe_link_speed speed;
 479
 480         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 481
 482         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 483
 484         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 485                 /* Set or unset auto-negotiation 10G advertisement */
 486                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 487                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 488                                      &autoneg_reg);
 489
 490                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 491                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 492                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 493
 494                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 495                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 496                                       autoneg_reg);
 497         }
 498
 499         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 500                 /* Set or unset auto-negotiation 1G advertisement */
 501                 hw->phy.ops.read_reg(hw,
 502                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 503                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 504                                      &autoneg_reg);
 505
 506                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 507                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 508                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 509
 510                 hw->phy.ops.write_reg(hw,
 511                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 512                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 513                                       autoneg_reg);
 514         }
 515
 516         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 517                 /* Set or unset auto-negotiation 100M advertisement */
 518                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 519                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 520                                      &autoneg_reg);
 521
 522                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 523                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 524                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 525                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 526
 527                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 528                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 529                                       autoneg_reg);
 530         }
 531
 532         /* Restart PHY autonegotiation and wait for completion */
 533         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 534                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 535
 536         autoneg_reg |= IXGBE_MII_RESTART;
 537
 538         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 539                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 540
 541         /* Wait for autonegotiation to finish */
 542         for (time_out = 0; time_out < max_time_out; time_out++) {
 543                 usec_delay(10);
 544                 /* Restart PHY autonegotiation and wait for completion */
 545                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 546                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 547                                               &autoneg_reg);
 548
 549                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 550                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
 551                         break;
 552         }
 553
 554         if (time_out == max_time_out) {
 555                 status = IXGBE_ERR_LINK_SETUP;
 556                 DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
 557         }
 558
 559         return status;
 560 }
 561
 562 /**
 563  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 564  *  @hw: pointer to hardware structure
 565  *  @speed: new link speed
 566  *  @autoneg: true if autonegotiation enabled
 567  **/
 568 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 569                                        ixgbe_link_speed speed,
 570                                        bool autoneg,
 571                                        bool autoneg_wait_to_complete)
 572 {
 573
 574         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 575
 576         /*
 577          * Clear autoneg_advertised and set new values based on input link
 578          * speed.
 579          */
 580         hw->phy.autoneg_advertised = 0;
 581
 582         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 583                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 584
 585         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 586                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 587
 588         if (speed & IXGBE_LINK_SPEED_100_FULL)
 589                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 590
 591         /* Setup link based on the new speed settings */
 592         hw->phy.ops.setup_link(hw);
 593
 594         return IXGBE_SUCCESS;
 595 }
 596
 597 /**
 598  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 599  *  @hw: pointer to hardware structure
 600  *  @speed: pointer to link speed
 601  *  @autoneg: boolean auto-negotiation value
 602  *
 603  *  Determines the link capabilities by reading the AUTOC register.
 604  **/
 605 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 606                                                ixgbe_link_speed *speed,
 607                                                bool *autoneg)
 608 {
 609         s32 status = IXGBE_ERR_LINK_SETUP;
 610         u16 speed_ability;
 611
 612         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 613
 614         *speed = 0;
 615         *autoneg = true;
 616
 617         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 618                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 619                                       &speed_ability);
 620
 621         if (status == IXGBE_SUCCESS) {
 622                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 623                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 624                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 625                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 626                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 627                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 628         }
 629
 630         return status;
 631 }
 632
 633 /**
 634  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 635  *  @hw: pointer to hardware structure
 636  *
 637  *  Reads the VS1 register to determine if link is up and the current speed for
 638  *  the PHY.
 639  **/
 640 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 641                              bool *link_up)
 642 {
 643         s32 status = IXGBE_SUCCESS;
 644         u32 time_out;
 645         u32 max_time_out = 10;
 646         u16 phy_link = 0;
 647         u16 phy_speed = 0;
 648         u16 phy_data = 0;
 649
 650         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 651
 652         /* Initialize speed and link to default case */
 653         *link_up = false;
 654         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 655
 656         /*
 657          * Check current speed and link status of the PHY register.
 658          * This is a vendor specific register and may have to
 659          * be changed for other copper PHYs.
 660          */
 661         for (time_out = 0; time_out < max_time_out; time_out++) {
 662                 usec_delay(10);
 663                 status = hw->phy.ops.read_reg(hw,
 664                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 665                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 666                                         &phy_data);
 667                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 668                 phy_speed = phy_data &
 669                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 670                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 671                         *link_up = true;
 672                         if (phy_speed ==
 673                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 674                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 675                         break;
 676                 }
 677         }
 678
 679         return status;
 680 }
 681
 682 /**
 683  *      ixgbe_setup_phy_link_tnx - Set and restart autoneg
 684  *      @hw: pointer to hardware structure
 685  *
 686  *      Restart autonegotiation and PHY and waits for completion.
 687  **/
 688 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 689 {
 690         s32 status = IXGBE_SUCCESS;
 691         u32 time_out;
 692         u32 max_time_out = 10;
 693         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 694         bool autoneg = false;
 695         ixgbe_link_speed speed;
 696
 697         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
 698
 699         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 700
 701         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 702                 /* Set or unset auto-negotiation 10G advertisement */
 703                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 704                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 705                                      &autoneg_reg);
 706
 707                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 708                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 709                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 710
 711                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 712                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 713                                       autoneg_reg);
 714         }
 715
 716         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 717                 /* Set or unset auto-negotiation 1G advertisement */
 718                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 719                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 720                                      &autoneg_reg);
 721
 722                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 723                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 724                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 725
 726                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 727                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 728                                       autoneg_reg);
 729         }
 730
 731         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 732                 /* Set or unset auto-negotiation 100M advertisement */
 733                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 734                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 735                                      &autoneg_reg);
 736
 737                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
 738                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 739                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 740
 741                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 742                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 743                                       autoneg_reg);
 744         }
 745
 746         /* Restart PHY autonegotiation and wait for completion */
 747         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 748                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 749
 750         autoneg_reg |= IXGBE_MII_RESTART;
 751
 752         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 753                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 754
 755         /* Wait for autonegotiation to finish */
 756         for (time_out = 0; time_out < max_time_out; time_out++) {
 757                 usec_delay(10);
 758                 /* Restart PHY autonegotiation and wait for completion */
 759                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 760                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 761                                               &autoneg_reg);
 762
 763                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 764                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
 765                         break;
 766         }
 767
 768         if (time_out == max_time_out) {
 769                 status = IXGBE_ERR_LINK_SETUP;
 770                 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
 771         }
 772
 773         return status;
 774 }
 775
 776 /**
 777  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 778  *  @hw: pointer to hardware structure
 779  *  @firmware_version: pointer to the PHY Firmware Version
 780  **/
 781 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 782                                        u16 *firmware_version)
 783 {
 784         s32 status = IXGBE_SUCCESS;
 785
 786         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
 787
 788         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 789                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 790                                       firmware_version);
 791
 792         return status;
 793 }
 794
 795 /**
 796  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 797  *  @hw: pointer to hardware structure
 798  *  @firmware_version: pointer to the PHY Firmware Version
 799  **/
 800 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 801                                            u16 *firmware_version)
 802 {
 803         s32 status = IXGBE_SUCCESS;
 804
 805         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
 806
 807         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 808                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 809                                       firmware_version);
 810
 811         return status;
 812 }
 813
 814 /**
 815  *  ixgbe_reset_phy_nl - Performs a PHY reset
 816  *  @hw: pointer to hardware structure
 817  **/
 818 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 819 {
 820         u16 phy_offset, control, eword, edata, block_crc;
 821         bool end_data = false;
 822         u16 list_offset, data_offset;
 823         u16 phy_data = 0;
 824         s32 ret_val = IXGBE_SUCCESS;
 825         u32 i;
 826
 827         DEBUGFUNC("ixgbe_reset_phy_nl");
 828
 829         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 830                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 831
 832         /* reset the PHY and poll for completion */
 833         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 834                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 835                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
 836
 837         for (i = 0; i < 100; i++) {
 838                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 839                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 840                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
 841                         break;
 842                 msec_delay(10);
 843         }
 844
 845         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
 846                 DEBUGOUT("PHY reset did not complete.\n");
 847                 ret_val = IXGBE_ERR_PHY;
 848                 goto out;
 849         }
 850
 851         /* Get init offsets */
 852         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 853                                                       &data_offset);
 854         if (ret_val != IXGBE_SUCCESS)
 855                 goto out;
 856
 857         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 858         data_offset++;
 859         while (!end_data) {
 860                 /*
 861                  * Read control word from PHY init contents offset
 862                  */
 863                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 864                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 865                            IXGBE_CONTROL_SHIFT_NL;
 866                 edata = eword & IXGBE_DATA_MASK_NL;
 867                 switch (control) {
 868                 case IXGBE_DELAY_NL:
 869                         data_offset++;
 870                         DEBUGOUT1("DELAY: %d MS\n", edata);
 871                         msec_delay(edata);
 872                         break;
 873                 case IXGBE_DATA_NL:
 874                         DEBUGOUT("DATA:\n");
 875                         data_offset++;
 876                         hw->eeprom.ops.read(hw, data_offset++,
 877                                             &phy_offset);
 878                         for (i = 0; i < edata; i++) {
 879                                 hw->eeprom.ops.read(hw, data_offset, &eword);
 880                                 hw->phy.ops.write_reg(hw, phy_offset,
 881                                                       IXGBE_TWINAX_DEV, eword);
 882                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
 883                                           phy_offset);
 884                                 data_offset++;
 885                                 phy_offset++;
 886                         }
 887                         break;
 888                 case IXGBE_CONTROL_NL:
 889                         data_offset++;
 890                         DEBUGOUT("CONTROL:\n");
 891                         if (edata == IXGBE_CONTROL_EOL_NL) {
 892                                 DEBUGOUT("EOL\n");
 893                                 end_data = true;
 894                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 895                                 DEBUGOUT("SOL\n");
 896                         } else {
 897                                 DEBUGOUT("Bad control value\n");
 898                                 ret_val = IXGBE_ERR_PHY;
 899                                 goto out;
 900                         }
 901                         break;
 902                 default:
 903                         DEBUGOUT("Bad control type\n");
 904                         ret_val = IXGBE_ERR_PHY;
 905                         goto out;
 906                 }
 907         }
 908
 909 out:
 910         return ret_val;
 911 }
 912
 913 /**
 914  *  ixgbe_identify_module_generic - Identifies module type
 915  *  @hw: pointer to hardware structure
 916  *
 917  *  Determines HW type and calls appropriate function.
 918  **/
 919 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
 920 {
 921         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
 922
 923         DEBUGFUNC("ixgbe_identify_module_generic");
 924
 925         switch (hw->mac.ops.get_media_type(hw)) {
 926         case ixgbe_media_type_fiber:
 927                 status = ixgbe_identify_sfp_module_generic(hw);
 928                 break;
 929
 930
 931         default:
 932                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 933                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 934                 break;
 935         }
 936
 937         return status;
 938 }
 939
 940 /**
 941  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
 942  *  @hw: pointer to hardware structure
 943  *
 944  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
 945  **/
 946 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 947 {
 948         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 949         u32 vendor_oui = 0;
 950         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
 951         u8 identifier = 0;
 952         u8 comp_codes_1g = 0;
 953         u8 comp_codes_10g = 0;
 954         u8 oui_bytes[3] = {0, 0, 0};
 955         u8 cable_tech = 0;
 956         u8 cable_spec = 0;
 957         u16 enforce_sfp = 0;
 958
 959         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
 960
 961         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
 962                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 963                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 964                 goto out;
 965         }
 966
 967         status = hw->phy.ops.read_i2c_eeprom(hw,
 968                                              IXGBE_SFF_IDENTIFIER,
 969                                              &identifier);
 970
 971         if (status == IXGBE_ERR_SWFW_SYNC ||
 972             status == IXGBE_ERR_I2C ||
 973             status == IXGBE_ERR_SFP_NOT_PRESENT)
 974                 goto err_read_i2c_eeprom;
 975
 976         /* LAN ID is needed for sfp_type determination */
 977         hw->mac.ops.set_lan_id(hw);
 978
 979         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
 980                 hw->phy.type = ixgbe_phy_sfp_unsupported;
 981                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
 982         } else {
 983                 status = hw->phy.ops.read_i2c_eeprom(hw,
 984                                                      IXGBE_SFF_1GBE_COMP_CODES,
 985                                                      &comp_codes_1g);
 986
 987                 if (status == IXGBE_ERR_SWFW_SYNC ||
 988                     status == IXGBE_ERR_I2C ||
 989                     status == IXGBE_ERR_SFP_NOT_PRESENT)
 990                         goto err_read_i2c_eeprom;
 991
 992                 status = hw->phy.ops.read_i2c_eeprom(hw,
 993                                                      IXGBE_SFF_10GBE_COMP_CODES,
 994                                                      &comp_codes_10g);
 995
 996                 if (status == IXGBE_ERR_SWFW_SYNC ||
 997                     status == IXGBE_ERR_I2C ||
 998                     status == IXGBE_ERR_SFP_NOT_PRESENT)
 999                         goto err_read_i2c_eeprom;
1000                 status = hw->phy.ops.read_i2c_eeprom(hw,
1001                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1002                                                      &cable_tech);
1003
1004                 if (status == IXGBE_ERR_SWFW_SYNC ||
1005                     status == IXGBE_ERR_I2C ||
1006                     status == IXGBE_ERR_SFP_NOT_PRESENT)
1007                         goto err_read_i2c_eeprom;
1008
1009                  /* ID Module
1010                   * =========
1011                   * 0   SFP_DA_CU
1012                   * 1   SFP_SR
1013                   * 2   SFP_LR
1014                   * 3   SFP_DA_CORE0 - 82599-specific
1015                   * 4   SFP_DA_CORE1 - 82599-specific
1016                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1017                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1018                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1019                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1020                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1021                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1022                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1023                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1024                   */
1025                 if (hw->mac.type == ixgbe_mac_82598EB) {
1026                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1027                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1028                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1029                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1030                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1031                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1032                         else
1033                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1034                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1035                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1036                                 if (hw->bus.lan_id == 0)
1037                                         hw->phy.sfp_type =
1038                                                      ixgbe_sfp_type_da_cu_core0;
1039                                 else
1040                                         hw->phy.sfp_type =
1041                                                      ixgbe_sfp_type_da_cu_core1;
1042                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1043                                 hw->phy.ops.read_i2c_eeprom(
1044                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1045                                                 &cable_spec);
1046                                 if (cable_spec &
1047                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1048                                         if (hw->bus.lan_id == 0)
1049                                                 hw->phy.sfp_type =
1050                                                 ixgbe_sfp_type_da_act_lmt_core0;
1051                                         else
1052                                                 hw->phy.sfp_type =
1053                                                 ixgbe_sfp_type_da_act_lmt_core1;
1054                                 } else {
1055                                         hw->phy.sfp_type =
1056                                                         ixgbe_sfp_type_unknown;
1057                                 }
1058                         } else if (comp_codes_10g &
1059                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1060                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1061                                 if (hw->bus.lan_id == 0)
1062                                         hw->phy.sfp_type =
1063                                                       ixgbe_sfp_type_srlr_core0;
1064                                 else
1065                                         hw->phy.sfp_type =
1066                                                       ixgbe_sfp_type_srlr_core1;
1067                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1068                                 if (hw->bus.lan_id == 0)
1069                                         hw->phy.sfp_type =
1070                                                 ixgbe_sfp_type_1g_cu_core0;
1071                                 else
1072                                         hw->phy.sfp_type =
1073                                                 ixgbe_sfp_type_1g_cu_core1;
1074                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1075                                 if (hw->bus.lan_id == 0)
1076                                         hw->phy.sfp_type =
1077                                                 ixgbe_sfp_type_1g_sx_core0;
1078                                 else
1079                                         hw->phy.sfp_type =
1080                                                 ixgbe_sfp_type_1g_sx_core1;
1081                         } else {
1082                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1083                         }
1084                 }
1085
1086                 if (hw->phy.sfp_type != stored_sfp_type)
1087                         hw->phy.sfp_setup_needed = true;
1088
1089                 /* Determine if the SFP+ PHY is dual speed or not. */
1090                 hw->phy.multispeed_fiber = false;
1091                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1092                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1093                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1094                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1095                         hw->phy.multispeed_fiber = true;
1096
1097                 /* Determine PHY vendor */
1098                 if (hw->phy.type != ixgbe_phy_nl) {
1099                         hw->phy.id = identifier;
1100                         status = hw->phy.ops.read_i2c_eeprom(hw,
1101                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1102                                                     &oui_bytes[0]);
1103
1104                         if (status == IXGBE_ERR_SWFW_SYNC ||
1105                             status == IXGBE_ERR_I2C ||
1106                             status == IXGBE_ERR_SFP_NOT_PRESENT)
1107                                 goto err_read_i2c_eeprom;
1108
1109                         status = hw->phy.ops.read_i2c_eeprom(hw,
1110                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1111                                                     &oui_bytes[1]);
1112
1113                         if (status == IXGBE_ERR_SWFW_SYNC ||
1114                             status == IXGBE_ERR_I2C ||
1115                             status == IXGBE_ERR_SFP_NOT_PRESENT)
1116                                 goto err_read_i2c_eeprom;
1117
1118                         status = hw->phy.ops.read_i2c_eeprom(hw,
1119                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1120                                                     &oui_bytes[2]);
1121
1122                         if (status == IXGBE_ERR_SWFW_SYNC ||
1123                             status == IXGBE_ERR_I2C ||
1124                             status == IXGBE_ERR_SFP_NOT_PRESENT)
1125                                 goto err_read_i2c_eeprom;
1126
1127                         vendor_oui =
1128                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1129                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1130                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1131
1132                         switch (vendor_oui) {
1133                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1134                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1135                                         hw->phy.type =
1136                                                     ixgbe_phy_sfp_passive_tyco;
1137                                 break;
1138                         case IXGBE_SFF_VENDOR_OUI_FTL:
1139                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1140                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1141                                 else
1142                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1143                                 break;
1144                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1145                                 hw->phy.type = ixgbe_phy_sfp_avago;
1146                                 break;
1147                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1148                                 hw->phy.type = ixgbe_phy_sfp_intel;
1149                                 break;
1150                         default:
1151                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1152                                         hw->phy.type =
1153                                                  ixgbe_phy_sfp_passive_unknown;
1154                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1155                                         hw->phy.type =
1156                                                 ixgbe_phy_sfp_active_unknown;
1157                                 else
1158                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1159                                 break;
1160                         }
1161                 }
1162
1163                 /* Allow any DA cable vendor */
1164                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1165                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1166                         status = IXGBE_SUCCESS;
1167                         goto out;
1168                 }
1169
1170                 /* Verify supported 1G SFP modules */
1171                 if (comp_codes_10g == 0 &&
1172                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1173                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1174                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0  ||
1175                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1176                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1177                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1178                         goto out;
1179                 }
1180
1181                 /* Anything else 82598-based is supported */
1182                 if (hw->mac.type == ixgbe_mac_82598EB) {
1183                         status = IXGBE_SUCCESS;
1184                         goto out;
1185                 }
1186
1187                 ixgbe_get_device_caps(hw, &enforce_sfp);
1188                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1189                     !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1190                       (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) ||
1191                       (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0)  ||
1192                       (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) {
1193                         /* Make sure we're a supported PHY type */
1194                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1195                                 status = IXGBE_SUCCESS;
1196                         } else {
1197                                 if (hw->allow_unsupported_sfp == true) {
1198                                         EWARN(hw, "WARNING: Intel (R) Network "
1199                                               "Connections are quality tested "
1200                                               "using Intel (R) Ethernet Optics."
1201                                               " Using untested modules is not "
1202                                               "supported and may cause unstable"
1203                                               " operation or damage to the "
1204                                               "module or the adapter. Intel "
1205                                               "Corporation is not responsible "
1206                                               "for any harm caused by using "
1207                                               "untested modules.\n", status);
1208                                         status = IXGBE_SUCCESS;
1209                                 } else {
1210                                         DEBUGOUT("SFP+ module not supported\n");
1211                                         hw->phy.type =
1212                                                 ixgbe_phy_sfp_unsupported;
1213                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1214                                 }
1215                         }
1216                 } else {
1217                         status = IXGBE_SUCCESS;
1218                 }
1219         }
1220
1221 out:
1222         return status;
1223
1224 err_read_i2c_eeprom:
1225         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1226         if (hw->phy.type != ixgbe_phy_nl) {
1227                 hw->phy.id = 0;
1228                 hw->phy.type = ixgbe_phy_unknown;
1229         }
1230         return IXGBE_ERR_SFP_NOT_PRESENT;
1231 }
1232
1233
1234
1235 /**
1236  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1237  *  @hw: pointer to hardware structure
1238  *  @list_offset: offset to the SFP ID list
1239  *  @data_offset: offset to the SFP data block
1240  *
1241  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1242  *  so it returns the offsets to the phy init sequence block.
1243  **/
1244 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1245                                         u16 *list_offset,
1246                                         u16 *data_offset)
1247 {
1248         u16 sfp_id;
1249         u16 sfp_type = hw->phy.sfp_type;
1250
1251         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1252
1253         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1254                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1255
1256         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1257                 return IXGBE_ERR_SFP_NOT_PRESENT;
1258
1259         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1260             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1261                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1262
1263         /*
1264          * Limiting active cables and 1G Phys must be initialized as
1265          * SR modules
1266          */
1267         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1268             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1269             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1270                 sfp_type = ixgbe_sfp_type_srlr_core0;
1271         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1272                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1273                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1274                 sfp_type = ixgbe_sfp_type_srlr_core1;
1275
1276         /* Read offset to PHY init contents */
1277         hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1278
1279         if ((!*list_offset) || (*list_offset == 0xFFFF))
1280                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1281
1282         /* Shift offset to first ID word */
1283         (*list_offset)++;
1284
1285         /*
1286          * Find the matching SFP ID in the EEPROM
1287          * and program the init sequence
1288          */
1289         hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1290
1291         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1292                 if (sfp_id == sfp_type) {
1293                         (*list_offset)++;
1294                         hw->eeprom.ops.read(hw, *list_offset, data_offset);
1295                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1296                                 DEBUGOUT("SFP+ module not supported\n");
1297                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1298                         } else {
1299                                 break;
1300                         }
1301                 } else {
1302                         (*list_offset) += 2;
1303                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1304                                 return IXGBE_ERR_PHY;
1305                 }
1306         }
1307
1308         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1309                 DEBUGOUT("No matching SFP+ module found\n");
1310                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1311         }
1312
1313         return IXGBE_SUCCESS;
1314 }
1315
1316 /**
1317  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1318  *  @hw: pointer to hardware structure
1319  *  @byte_offset: EEPROM byte offset to read
1320  *  @eeprom_data: value read
1321  *
1322  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1323  **/
1324 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1325                                   u8 *eeprom_data)
1326 {
1327         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1328
1329         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1330                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1331                                          eeprom_data);
1332 }
1333
1334 /**
1335  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1336  *  @hw: pointer to hardware structure
1337  *  @byte_offset: EEPROM byte offset to write
1338  *  @eeprom_data: value to write
1339  *
1340  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1341  **/
1342 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1343                                    u8 eeprom_data)
1344 {
1345         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1346
1347         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1348                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1349                                           eeprom_data);
1350 }
1351
1352 /**
1353  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1354  *  @hw: pointer to hardware structure
1355  *  @byte_offset: byte offset to read
1356  *  @data: value read
1357  *
1358  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1359  *  a specified device address.
1360  **/
1361 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1362                                 u8 dev_addr, u8 *data)
1363 {
1364         s32 status = IXGBE_SUCCESS;
1365         u32 max_retry = 10;
1366         u32 retry = 0;
1367         u16 swfw_mask = 0;
1368         bool nack = 1;
1369         *data = 0;
1370
1371         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1372
1373         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1374                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1375         else
1376                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1377
1378         do {
1379                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1380                     != IXGBE_SUCCESS) {
1381                         status = IXGBE_ERR_SWFW_SYNC;
1382                         goto read_byte_out;
1383                 }
1384
1385                 ixgbe_i2c_start(hw);
1386
1387                 /* Device Address and write indication */
1388                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1389                 if (status != IXGBE_SUCCESS)
1390                         goto fail;
1391
1392                 status = ixgbe_get_i2c_ack(hw);
1393                 if (status != IXGBE_SUCCESS)
1394                         goto fail;
1395
1396                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1397                 if (status != IXGBE_SUCCESS)
1398                         goto fail;
1399
1400                 status = ixgbe_get_i2c_ack(hw);
1401                 if (status != IXGBE_SUCCESS)
1402                         goto fail;
1403
1404                 ixgbe_i2c_start(hw);
1405
1406                 /* Device Address and read indication */
1407                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1408                 if (status != IXGBE_SUCCESS)
1409                         goto fail;
1410
1411                 status = ixgbe_get_i2c_ack(hw);
1412                 if (status != IXGBE_SUCCESS)
1413                         goto fail;
1414
1415                 status = ixgbe_clock_in_i2c_byte(hw, data);
1416                 if (status != IXGBE_SUCCESS)
1417                         goto fail;
1418
1419                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1420                 if (status != IXGBE_SUCCESS)
1421                         goto fail;
1422
1423                 ixgbe_i2c_stop(hw);
1424                 break;
1425
1426 fail:
1427                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1428                 msec_delay(100);
1429                 ixgbe_i2c_bus_clear(hw);
1430                 retry++;
1431                 if (retry < max_retry)
1432                         DEBUGOUT("I2C byte read error - Retrying.\n");
1433                 else
1434                         DEBUGOUT("I2C byte read error.\n");
1435
1436         } while (retry < max_retry);
1437
1438         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1439
1440 read_byte_out:
1441         return status;
1442 }
1443
1444 /**
1445  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1446  *  @hw: pointer to hardware structure
1447  *  @byte_offset: byte offset to write
1448  *  @data: value to write
1449  *
1450  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1451  *  a specified device address.
1452  **/
1453 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1454                                  u8 dev_addr, u8 data)
1455 {
1456         s32 status = IXGBE_SUCCESS;
1457         u32 max_retry = 1;
1458         u32 retry = 0;
1459         u16 swfw_mask = 0;
1460
1461         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1462
1463         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1464                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1465         else
1466                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1467
1468         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1469                 status = IXGBE_ERR_SWFW_SYNC;
1470                 goto write_byte_out;
1471         }
1472
1473         do {
1474                 ixgbe_i2c_start(hw);
1475
1476                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1477                 if (status != IXGBE_SUCCESS)
1478                         goto fail;
1479
1480                 status = ixgbe_get_i2c_ack(hw);
1481                 if (status != IXGBE_SUCCESS)
1482                         goto fail;
1483
1484                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1485                 if (status != IXGBE_SUCCESS)
1486                         goto fail;
1487
1488                 status = ixgbe_get_i2c_ack(hw);
1489                 if (status != IXGBE_SUCCESS)
1490                         goto fail;
1491
1492                 status = ixgbe_clock_out_i2c_byte(hw, data);
1493                 if (status != IXGBE_SUCCESS)
1494                         goto fail;
1495
1496                 status = ixgbe_get_i2c_ack(hw);
1497                 if (status != IXGBE_SUCCESS)
1498                         goto fail;
1499
1500                 ixgbe_i2c_stop(hw);
1501                 break;
1502
1503 fail:
1504                 ixgbe_i2c_bus_clear(hw);
1505                 retry++;
1506                 if (retry < max_retry)
1507                         DEBUGOUT("I2C byte write error - Retrying.\n");
1508                 else
1509                         DEBUGOUT("I2C byte write error.\n");
1510         } while (retry < max_retry);
1511
1512         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1513
1514 write_byte_out:
1515         return status;
1516 }
1517
1518 /**
1519  *  ixgbe_i2c_start - Sets I2C start condition
1520  *  @hw: pointer to hardware structure
1521  *
1522  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1523  **/
1524 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1525 {
1526         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1527
1528         DEBUGFUNC("ixgbe_i2c_start");
1529
1530         /* Start condition must begin with data and clock high */
1531         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1532         ixgbe_raise_i2c_clk(hw, &i2cctl);
1533
1534         /* Setup time for start condition (4.7us) */
1535         usec_delay(IXGBE_I2C_T_SU_STA);
1536
1537         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1538
1539         /* Hold time for start condition (4us) */
1540         usec_delay(IXGBE_I2C_T_HD_STA);
1541
1542         ixgbe_lower_i2c_clk(hw, &i2cctl);
1543
1544         /* Minimum low period of clock is 4.7 us */
1545         usec_delay(IXGBE_I2C_T_LOW);
1546
1547 }
1548
1549 /**
1550  *  ixgbe_i2c_stop - Sets I2C stop condition
1551  *  @hw: pointer to hardware structure
1552  *
1553  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1554  **/
1555 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1556 {
1557         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1558
1559         DEBUGFUNC("ixgbe_i2c_stop");
1560
1561         /* Stop condition must begin with data low and clock high */
1562         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1563         ixgbe_raise_i2c_clk(hw, &i2cctl);
1564
1565         /* Setup time for stop condition (4us) */
1566         usec_delay(IXGBE_I2C_T_SU_STO);
1567
1568         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1569
1570         /* bus free time between stop and start (4.7us)*/
1571         usec_delay(IXGBE_I2C_T_BUF);
1572 }
1573
1574 /**
1575  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1576  *  @hw: pointer to hardware structure
1577  *  @data: data byte to clock in
1578  *
1579  *  Clocks in one byte data via I2C data/clock
1580  **/
1581 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1582 {
1583         s32 i;
1584         bool bit = 0;
1585
1586         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1587
1588         for (i = 7; i >= 0; i--) {
1589                 ixgbe_clock_in_i2c_bit(hw, &bit);
1590                 *data |= bit << i;
1591         }
1592
1593         return IXGBE_SUCCESS;
1594 }
1595
1596 /**
1597  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1598  *  @hw: pointer to hardware structure
1599  *  @data: data byte clocked out
1600  *
1601  *  Clocks out one byte data via I2C data/clock
1602  **/
1603 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1604 {
1605         s32 status = IXGBE_SUCCESS;
1606         s32 i;
1607         u32 i2cctl;
1608         bool bit = 0;
1609
1610         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1611
1612         for (i = 7; i >= 0; i--) {
1613                 bit = (data >> i) & 0x1;
1614                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1615
1616                 if (status != IXGBE_SUCCESS)
1617                         break;
1618         }
1619
1620         /* Release SDA line (set high) */
1621         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1622         i2cctl |= IXGBE_I2C_DATA_OUT;
1623         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1624         IXGBE_WRITE_FLUSH(hw);
1625
1626         return status;
1627 }
1628
1629 /**
1630  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1631  *  @hw: pointer to hardware structure
1632  *
1633  *  Clocks in/out one bit via I2C data/clock
1634  **/
1635 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1636 {
1637         s32 status = IXGBE_SUCCESS;
1638         u32 i = 0;
1639         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1640         u32 timeout = 10;
1641         bool ack = 1;
1642
1643         DEBUGFUNC("ixgbe_get_i2c_ack");
1644
1645         ixgbe_raise_i2c_clk(hw, &i2cctl);
1646
1647
1648         /* Minimum high period of clock is 4us */
1649         usec_delay(IXGBE_I2C_T_HIGH);
1650
1651         /* Poll for ACK.  Note that ACK in I2C spec is
1652          * transition from 1 to 0 */
1653         for (i = 0; i < timeout; i++) {
1654                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1655                 ack = ixgbe_get_i2c_data(&i2cctl);
1656
1657                 usec_delay(1);
1658                 if (ack == 0)
1659                         break;
1660         }
1661
1662         if (ack == 1) {
1663                 DEBUGOUT("I2C ack was not received.\n");
1664                 status = IXGBE_ERR_I2C;
1665         }
1666
1667         ixgbe_lower_i2c_clk(hw, &i2cctl);
1668
1669         /* Minimum low period of clock is 4.7 us */
1670         usec_delay(IXGBE_I2C_T_LOW);
1671
1672         return status;
1673 }
1674
1675 /**
1676  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1677  *  @hw: pointer to hardware structure
1678  *  @data: read data value
1679  *
1680  *  Clocks in one bit via I2C data/clock
1681  **/
1682 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1683 {
1684         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1685
1686         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1687
1688         ixgbe_raise_i2c_clk(hw, &i2cctl);
1689
1690         /* Minimum high period of clock is 4us */
1691         usec_delay(IXGBE_I2C_T_HIGH);
1692
1693         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1694         *data = ixgbe_get_i2c_data(&i2cctl);
1695
1696         ixgbe_lower_i2c_clk(hw, &i2cctl);
1697
1698         /* Minimum low period of clock is 4.7 us */
1699         usec_delay(IXGBE_I2C_T_LOW);
1700
1701         return IXGBE_SUCCESS;
1702 }
1703
1704 /**
1705  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1706  *  @hw: pointer to hardware structure
1707  *  @data: data value to write
1708  *
1709  *  Clocks out one bit via I2C data/clock
1710  **/
1711 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1712 {
1713         s32 status;
1714         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1715
1716         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1717
1718         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1719         if (status == IXGBE_SUCCESS) {
1720                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1721
1722                 /* Minimum high period of clock is 4us */
1723                 usec_delay(IXGBE_I2C_T_HIGH);
1724
1725                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1726
1727                 /* Minimum low period of clock is 4.7 us.
1728                  * This also takes care of the data hold time.
1729                  */
1730                 usec_delay(IXGBE_I2C_T_LOW);
1731         } else {
1732                 status = IXGBE_ERR_I2C;
1733                 DEBUGOUT1("I2C data was not set to %X\n", data);
1734         }
1735
1736         return status;
1737 }
1738 /**
1739  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1740  *  @hw: pointer to hardware structure
1741  *  @i2cctl: Current value of I2CCTL register
1742  *
1743  *  Raises the I2C clock line '0'->'1'
1744  **/
1745 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1746 {
1747         u32 i = 0;
1748         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1749         u32 i2cctl_r = 0;
1750
1751         DEBUGFUNC("ixgbe_raise_i2c_clk");
1752
1753         for (i = 0; i < timeout; i++) {
1754                 *i2cctl |= IXGBE_I2C_CLK_OUT;
1755
1756                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1757                 IXGBE_WRITE_FLUSH(hw);
1758                 /* SCL rise time (1000ns) */
1759                 usec_delay(IXGBE_I2C_T_RISE);
1760
1761                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1762                 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1763                         break;
1764         }
1765 }
1766
1767 /**
1768  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1769  *  @hw: pointer to hardware structure
1770  *  @i2cctl: Current value of I2CCTL register
1771  *
1772  *  Lowers the I2C clock line '1'->'0'
1773  **/
1774 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1775 {
1776
1777         DEBUGFUNC("ixgbe_lower_i2c_clk");
1778
1779         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1780
1781         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1782         IXGBE_WRITE_FLUSH(hw);
1783
1784         /* SCL fall time (300ns) */
1785         usec_delay(IXGBE_I2C_T_FALL);
1786 }
1787
1788 /**
1789  *  ixgbe_set_i2c_data - Sets the I2C data bit
1790  *  @hw: pointer to hardware structure
1791  *  @i2cctl: Current value of I2CCTL register
1792  *  @data: I2C data value (0 or 1) to set
1793  *
1794  *  Sets the I2C data bit
1795  **/
1796 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1797 {
1798         s32 status = IXGBE_SUCCESS;
1799
1800         DEBUGFUNC("ixgbe_set_i2c_data");
1801
1802         if (data)
1803                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1804         else
1805                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1806
1807         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1808         IXGBE_WRITE_FLUSH(hw);
1809
1810         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1811         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1812
1813         /* Verify data was set correctly */
1814         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1815         if (data != ixgbe_get_i2c_data(i2cctl)) {
1816                 status = IXGBE_ERR_I2C;
1817                 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
1818         }
1819
1820         return status;
1821 }
1822
1823 /**
1824  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1825  *  @hw: pointer to hardware structure
1826  *  @i2cctl: Current value of I2CCTL register
1827  *
1828  *  Returns the I2C data bit value
1829  **/
1830 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1831 {
1832         bool data;
1833
1834         DEBUGFUNC("ixgbe_get_i2c_data");
1835
1836         if (*i2cctl & IXGBE_I2C_DATA_IN)
1837                 data = 1;
1838         else
1839                 data = 0;
1840
1841         return data;
1842 }
1843
1844 /**
1845  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1846  *  @hw: pointer to hardware structure
1847  *
1848  *  Clears the I2C bus by sending nine clock pulses.
1849  *  Used when data line is stuck low.
1850  **/
1851 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1852 {
1853         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1854         u32 i;
1855
1856         DEBUGFUNC("ixgbe_i2c_bus_clear");
1857
1858         ixgbe_i2c_start(hw);
1859
1860         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1861
1862         for (i = 0; i < 9; i++) {
1863                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1864
1865                 /* Min high period of clock is 4us */
1866                 usec_delay(IXGBE_I2C_T_HIGH);
1867
1868                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1869
1870                 /* Min low period of clock is 4.7us*/
1871                 usec_delay(IXGBE_I2C_T_LOW);
1872         }
1873
1874         ixgbe_i2c_start(hw);
1875
1876         /* Put the i2c bus back to default state */
1877         ixgbe_i2c_stop(hw);
1878 }
1879
1880 /**
1881  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1882  *  @hw: pointer to hardware structure
1883  *
1884  *  Checks if the LASI temp alarm status was triggered due to overtemp
1885  **/
1886 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1887 {
1888         s32 status = IXGBE_SUCCESS;
1889         u16 phy_data = 0;
1890
1891         DEBUGFUNC("ixgbe_tn_check_overtemp");
1892
1893         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1894                 goto out;
1895
1896         /* Check that the LASI temp alarm status was triggered */
1897         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1898                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1899
1900         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1901                 goto out;
1902
1903         status = IXGBE_ERR_OVERTEMP;
1904 out:
1905         return status;
1906 }