1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_api.h"
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
54 * @hw: pointer to the hardware structure
57 * Returns an error code on error.
59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
63 status = ixgbe_clock_out_i2c_byte(hw, byte);
66 return ixgbe_get_i2c_ack(hw);
70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
71 * @hw: pointer to the hardware structure
72 * @byte: pointer to a u8 to receive the byte
74 * Returns an error code on error.
76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
80 status = ixgbe_clock_in_i2c_byte(hw, byte);
84 return ixgbe_clock_out_i2c_bit(hw, false);
88 * ixgbe_ones_comp_byte_add - Perform one's complement addition
92 * Returns one's complement 8-bit sum.
94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
96 u16 sum = add1 + add2;
98 sum = (sum & 0xFF) + (sum >> 8);
103 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
104 * @hw: pointer to the hardware structure
105 * @addr: I2C bus address to read from
106 * @reg: I2C device register to read from
107 * @val: pointer to location to receive read value
109 * Returns an error code on error.
111 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
114 u32 swfw_mask = hw->phy.phy_semaphore_mask;
123 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
124 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
127 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
128 return IXGBE_ERR_SWFW_SYNC;
130 /* Device Address and write indication */
131 if (ixgbe_out_i2c_byte_ack(hw, addr))
133 /* Write bits 14:8 */
134 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
137 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
140 if (ixgbe_out_i2c_byte_ack(hw, csum))
142 /* Re-start condition */
144 /* Device Address and read indication */
145 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
148 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
151 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
154 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
157 if (ixgbe_clock_out_i2c_bit(hw, false))
160 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
161 *val = (high_bits << 8) | low_bits;
165 ixgbe_i2c_bus_clear(hw);
166 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
168 if (retry < max_retry)
169 DEBUGOUT("I2C byte read combined error - Retrying.\n");
171 DEBUGOUT("I2C byte read combined error.\n");
172 } while (retry < max_retry);
174 return IXGBE_ERR_I2C;
178 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
179 * @hw: pointer to the hardware structure
180 * @addr: I2C bus address to write to
181 * @reg: I2C device register to write to
182 * @val: value to write
184 * Returns an error code on error.
186 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
187 u8 addr, u16 reg, u16 val)
194 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
195 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
196 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
197 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
201 /* Device Address and write indication */
202 if (ixgbe_out_i2c_byte_ack(hw, addr))
204 /* Write bits 14:8 */
205 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
208 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
210 /* Write data 15:8 */
211 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
214 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
217 if (ixgbe_out_i2c_byte_ack(hw, csum))
223 ixgbe_i2c_bus_clear(hw);
225 if (retry < max_retry)
226 DEBUGOUT("I2C byte write combined error - Retrying.\n");
228 DEBUGOUT("I2C byte write combined error.\n");
229 } while (retry < max_retry);
231 return IXGBE_ERR_I2C;
235 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
236 * @hw: pointer to the hardware structure
238 * Initialize the function pointers.
240 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
242 struct ixgbe_phy_info *phy = &hw->phy;
244 DEBUGFUNC("ixgbe_init_phy_ops_generic");
247 phy->ops.identify = ixgbe_identify_phy_generic;
248 phy->ops.reset = ixgbe_reset_phy_generic;
249 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
250 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
251 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
252 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
253 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
254 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
255 phy->ops.check_link = NULL;
256 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
257 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
258 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
259 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
260 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
261 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
262 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
263 phy->ops.identify_sfp = ixgbe_identify_module_generic;
264 phy->sfp_type = ixgbe_sfp_type_unknown;
265 phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic;
266 phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic;
267 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
268 return IXGBE_SUCCESS;
272 * ixgbe_identify_phy_generic - Get physical layer module
273 * @hw: pointer to hardware structure
275 * Determines the physical layer module found on the current adapter.
277 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
279 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
283 DEBUGFUNC("ixgbe_identify_phy_generic");
285 if (!hw->phy.phy_semaphore_mask) {
286 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
287 IXGBE_STATUS_LAN_ID_1;
289 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
291 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
294 if (hw->phy.type == ixgbe_phy_unknown) {
295 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
296 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
297 hw->phy.addr = phy_addr;
298 ixgbe_get_phy_id(hw);
300 ixgbe_get_phy_type_from_id(hw->phy.id);
302 if (hw->phy.type == ixgbe_phy_unknown) {
303 hw->phy.ops.read_reg(hw,
304 IXGBE_MDIO_PHY_EXT_ABILITY,
305 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
308 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
309 IXGBE_MDIO_PHY_1000BASET_ABILITY))
311 ixgbe_phy_cu_unknown;
317 status = IXGBE_SUCCESS;
322 /* Certain media types do not have a phy so an address will not
323 * be found and the code will take this path. Caller has to
324 * decide if it is an error or not.
326 if (status != IXGBE_SUCCESS) {
330 status = IXGBE_SUCCESS;
337 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
338 * @hw: pointer to the hardware structure
340 * This function checks the MMNGC.MNG_VETO bit to see if there are
341 * any constraints on link from manageability. For MAC's that don't
342 * have this bit just return faluse since the link can not be blocked
345 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
349 DEBUGFUNC("ixgbe_check_reset_blocked");
351 /* If we don't have this bit, it can't be blocking */
352 if (hw->mac.type == ixgbe_mac_82598EB)
355 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
356 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
357 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
358 "MNG_VETO bit detected.\n");
366 * ixgbe_validate_phy_addr - Determines phy address is valid
367 * @hw: pointer to hardware structure
370 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
375 DEBUGFUNC("ixgbe_validate_phy_addr");
377 hw->phy.addr = phy_addr;
378 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
379 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
381 if (phy_id != 0xFFFF && phy_id != 0x0)
388 * ixgbe_get_phy_id - Get the phy type
389 * @hw: pointer to hardware structure
392 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
398 DEBUGFUNC("ixgbe_get_phy_id");
400 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
401 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
404 if (status == IXGBE_SUCCESS) {
405 hw->phy.id = (u32)(phy_id_high << 16);
406 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
407 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
409 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
410 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
416 * ixgbe_get_phy_type_from_id - Get the phy type
417 * @hw: pointer to hardware structure
420 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
422 enum ixgbe_phy_type phy_type;
424 DEBUGFUNC("ixgbe_get_phy_type_from_id");
428 phy_type = ixgbe_phy_tn;
432 phy_type = ixgbe_phy_aq;
435 phy_type = ixgbe_phy_qt;
438 phy_type = ixgbe_phy_nl;
441 phy_type = ixgbe_phy_unknown;
445 DEBUGOUT1("phy type found is %d\n", phy_type);
450 * ixgbe_reset_phy_generic - Performs a PHY reset
451 * @hw: pointer to hardware structure
453 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
457 s32 status = IXGBE_SUCCESS;
459 DEBUGFUNC("ixgbe_reset_phy_generic");
461 if (hw->phy.type == ixgbe_phy_unknown)
462 status = ixgbe_identify_phy_generic(hw);
464 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
467 /* Don't reset PHY if it's shut down due to overtemp. */
468 if (!hw->phy.reset_if_overtemp &&
469 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
472 /* Blocked by MNG FW so bail */
473 if (ixgbe_check_reset_blocked(hw))
477 * Perform soft PHY reset to the PHY_XS.
478 * This will cause a soft reset to the PHY
480 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
481 IXGBE_MDIO_PHY_XS_DEV_TYPE,
482 IXGBE_MDIO_PHY_XS_RESET);
485 * Poll for reset bit to self-clear indicating reset is complete.
486 * Some PHYs could take up to 3 seconds to complete and need about
487 * 1.7 usec delay after the reset is complete.
489 for (i = 0; i < 30; i++) {
491 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
492 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
493 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
499 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
500 status = IXGBE_ERR_RESET_FAILED;
501 ERROR_REPORT1(IXGBE_ERROR_POLLING,
502 "PHY reset polling failed to complete.\n");
510 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
512 * @hw: pointer to hardware structure
513 * @reg_addr: 32 bit address of PHY register to read
514 * @phy_data: Pointer to read data from PHY register
516 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
519 u32 i, data, command;
521 /* Setup and write the address cycle command */
522 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
523 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
524 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
525 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
527 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
530 * Check every 10 usec to see if the address cycle completed.
531 * The MDI Command bit will clear when the operation is
534 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
537 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
538 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
543 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
544 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
545 return IXGBE_ERR_PHY;
549 * Address cycle complete, setup and write the read
552 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
553 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
554 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
555 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
557 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
560 * Check every 10 usec to see if the address cycle
561 * completed. The MDI Command bit will clear when the
562 * operation is complete
564 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
567 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
568 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
572 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
573 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
574 return IXGBE_ERR_PHY;
578 * Read operation is complete. Get the data
581 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
582 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
583 *phy_data = (u16)(data);
585 return IXGBE_SUCCESS;
589 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
590 * using the SWFW lock - this function is needed in most cases
591 * @hw: pointer to hardware structure
592 * @reg_addr: 32 bit address of PHY register to read
593 * @phy_data: Pointer to read data from PHY register
595 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
596 u32 device_type, u16 *phy_data)
599 u32 gssr = hw->phy.phy_semaphore_mask;
601 DEBUGFUNC("ixgbe_read_phy_reg_generic");
603 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
604 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
606 hw->mac.ops.release_swfw_sync(hw, gssr);
608 status = IXGBE_ERR_SWFW_SYNC;
615 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
617 * @hw: pointer to hardware structure
618 * @reg_addr: 32 bit PHY register to write
619 * @device_type: 5 bit device type
620 * @phy_data: Data to write to the PHY register
622 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
623 u32 device_type, u16 phy_data)
627 /* Put the data in the MDI single read and write data register*/
628 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
630 /* Setup and write the address cycle command */
631 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
632 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
633 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
634 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
636 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
639 * Check every 10 usec to see if the address cycle completed.
640 * The MDI Command bit will clear when the operation is
643 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
646 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
647 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
651 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
652 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
653 return IXGBE_ERR_PHY;
657 * Address cycle complete, setup and write the write
660 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
661 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
662 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
663 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
665 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
668 * Check every 10 usec to see if the address cycle
669 * completed. The MDI Command bit will clear when the
670 * operation is complete
672 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
675 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
676 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
680 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
681 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
682 return IXGBE_ERR_PHY;
685 return IXGBE_SUCCESS;
689 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
690 * using SWFW lock- this function is needed in most cases
691 * @hw: pointer to hardware structure
692 * @reg_addr: 32 bit PHY register to write
693 * @device_type: 5 bit device type
694 * @phy_data: Data to write to the PHY register
696 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
697 u32 device_type, u16 phy_data)
700 u32 gssr = hw->phy.phy_semaphore_mask;
702 DEBUGFUNC("ixgbe_write_phy_reg_generic");
704 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
705 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
707 hw->mac.ops.release_swfw_sync(hw, gssr);
709 status = IXGBE_ERR_SWFW_SYNC;
716 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
717 * @hw: pointer to hardware structure
719 * Restart auto-negotiation and PHY and waits for completion.
721 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
723 s32 status = IXGBE_SUCCESS;
724 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
725 bool autoneg = false;
726 ixgbe_link_speed speed;
728 DEBUGFUNC("ixgbe_setup_phy_link_generic");
730 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
732 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
733 /* Set or unset auto-negotiation 10G advertisement */
734 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
735 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
738 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
739 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
740 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
742 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
743 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
747 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
748 /* Set or unset auto-negotiation 1G advertisement */
749 hw->phy.ops.read_reg(hw,
750 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
751 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
754 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
755 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
756 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
758 hw->phy.ops.write_reg(hw,
759 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
760 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
764 if (speed & IXGBE_LINK_SPEED_100_FULL) {
765 /* Set or unset auto-negotiation 100M advertisement */
766 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
767 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
770 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
771 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
772 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
773 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
775 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
776 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
780 /* Blocked by MNG FW so don't reset PHY */
781 if (ixgbe_check_reset_blocked(hw))
784 /* Restart PHY auto-negotiation. */
785 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
786 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
788 autoneg_reg |= IXGBE_MII_RESTART;
790 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
791 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
797 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
798 * @hw: pointer to hardware structure
799 * @speed: new link speed
801 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
802 ixgbe_link_speed speed,
803 bool autoneg_wait_to_complete)
805 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
807 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
810 * Clear autoneg_advertised and set new values based on input link
813 hw->phy.autoneg_advertised = 0;
815 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
816 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
818 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
819 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
821 if (speed & IXGBE_LINK_SPEED_100_FULL)
822 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
824 /* Setup link based on the new speed settings */
825 hw->phy.ops.setup_link(hw);
827 return IXGBE_SUCCESS;
831 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
832 * @hw: pointer to hardware structure
833 * @speed: pointer to link speed
834 * @autoneg: boolean auto-negotiation value
836 * Determines the link capabilities by reading the AUTOC register.
838 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
839 ixgbe_link_speed *speed,
845 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
850 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
851 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
854 if (status == IXGBE_SUCCESS) {
855 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
856 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
857 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
858 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
859 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
860 *speed |= IXGBE_LINK_SPEED_100_FULL;
867 * ixgbe_check_phy_link_tnx - Determine link and speed status
868 * @hw: pointer to hardware structure
870 * Reads the VS1 register to determine if link is up and the current speed for
873 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
876 s32 status = IXGBE_SUCCESS;
878 u32 max_time_out = 10;
883 DEBUGFUNC("ixgbe_check_phy_link_tnx");
885 /* Initialize speed and link to default case */
887 *speed = IXGBE_LINK_SPEED_10GB_FULL;
890 * Check current speed and link status of the PHY register.
891 * This is a vendor specific register and may have to
892 * be changed for other copper PHYs.
894 for (time_out = 0; time_out < max_time_out; time_out++) {
896 status = hw->phy.ops.read_reg(hw,
897 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
898 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
900 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
901 phy_speed = phy_data &
902 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
903 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
906 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
907 *speed = IXGBE_LINK_SPEED_1GB_FULL;
916 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
917 * @hw: pointer to hardware structure
919 * Restart auto-negotiation and PHY and waits for completion.
921 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
923 s32 status = IXGBE_SUCCESS;
924 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
925 bool autoneg = false;
926 ixgbe_link_speed speed;
928 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
930 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
932 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
933 /* Set or unset auto-negotiation 10G advertisement */
934 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
935 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
938 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
939 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
940 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
942 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
943 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
947 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
948 /* Set or unset auto-negotiation 1G advertisement */
949 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
950 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
953 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
954 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
955 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
957 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
958 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
962 if (speed & IXGBE_LINK_SPEED_100_FULL) {
963 /* Set or unset auto-negotiation 100M advertisement */
964 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
965 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
968 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
969 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
970 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
972 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
973 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
977 /* Blocked by MNG FW so don't reset PHY */
978 if (ixgbe_check_reset_blocked(hw))
981 /* Restart PHY auto-negotiation. */
982 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
983 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
985 autoneg_reg |= IXGBE_MII_RESTART;
987 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
988 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
994 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
995 * @hw: pointer to hardware structure
996 * @firmware_version: pointer to the PHY Firmware Version
998 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
999 u16 *firmware_version)
1003 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1005 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1006 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1013 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1014 * @hw: pointer to hardware structure
1015 * @firmware_version: pointer to the PHY Firmware Version
1017 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1018 u16 *firmware_version)
1022 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1024 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1025 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1032 * ixgbe_reset_phy_nl - Performs a PHY reset
1033 * @hw: pointer to hardware structure
1035 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1037 u16 phy_offset, control, eword, edata, block_crc;
1038 bool end_data = false;
1039 u16 list_offset, data_offset;
1041 s32 ret_val = IXGBE_SUCCESS;
1044 DEBUGFUNC("ixgbe_reset_phy_nl");
1046 /* Blocked by MNG FW so bail */
1047 if (ixgbe_check_reset_blocked(hw))
1050 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1051 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1053 /* reset the PHY and poll for completion */
1054 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1055 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1056 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1058 for (i = 0; i < 100; i++) {
1059 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1060 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1061 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1066 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1067 DEBUGOUT("PHY reset did not complete.\n");
1068 ret_val = IXGBE_ERR_PHY;
1072 /* Get init offsets */
1073 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1075 if (ret_val != IXGBE_SUCCESS)
1078 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1082 * Read control word from PHY init contents offset
1084 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1087 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1088 IXGBE_CONTROL_SHIFT_NL;
1089 edata = eword & IXGBE_DATA_MASK_NL;
1091 case IXGBE_DELAY_NL:
1093 DEBUGOUT1("DELAY: %d MS\n", edata);
1097 DEBUGOUT("DATA:\n");
1099 ret_val = hw->eeprom.ops.read(hw, data_offset,
1104 for (i = 0; i < edata; i++) {
1105 ret_val = hw->eeprom.ops.read(hw, data_offset,
1109 hw->phy.ops.write_reg(hw, phy_offset,
1110 IXGBE_TWINAX_DEV, eword);
1111 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1117 case IXGBE_CONTROL_NL:
1119 DEBUGOUT("CONTROL:\n");
1120 if (edata == IXGBE_CONTROL_EOL_NL) {
1123 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1126 DEBUGOUT("Bad control value\n");
1127 ret_val = IXGBE_ERR_PHY;
1132 DEBUGOUT("Bad control type\n");
1133 ret_val = IXGBE_ERR_PHY;
1142 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1143 "eeprom read at offset %d failed", data_offset);
1144 return IXGBE_ERR_PHY;
1148 * ixgbe_identify_module_generic - Identifies module type
1149 * @hw: pointer to hardware structure
1151 * Determines HW type and calls appropriate function.
1153 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1155 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1157 DEBUGFUNC("ixgbe_identify_module_generic");
1159 switch (hw->mac.ops.get_media_type(hw)) {
1160 case ixgbe_media_type_fiber:
1161 status = ixgbe_identify_sfp_module_generic(hw);
1164 case ixgbe_media_type_fiber_qsfp:
1165 status = ixgbe_identify_qsfp_module_generic(hw);
1169 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1170 status = IXGBE_ERR_SFP_NOT_PRESENT;
1178 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1179 * @hw: pointer to hardware structure
1181 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1183 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1185 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1187 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1189 u8 comp_codes_1g = 0;
1190 u8 comp_codes_10g = 0;
1191 u8 oui_bytes[3] = {0, 0, 0};
1194 u16 enforce_sfp = 0;
1196 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1198 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1199 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1200 status = IXGBE_ERR_SFP_NOT_PRESENT;
1204 status = hw->phy.ops.read_i2c_eeprom(hw,
1205 IXGBE_SFF_IDENTIFIER,
1208 if (status != IXGBE_SUCCESS)
1209 goto err_read_i2c_eeprom;
1211 /* LAN ID is needed for sfp_type determination */
1212 hw->mac.ops.set_lan_id(hw);
1214 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1215 hw->phy.type = ixgbe_phy_sfp_unsupported;
1216 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1218 status = hw->phy.ops.read_i2c_eeprom(hw,
1219 IXGBE_SFF_1GBE_COMP_CODES,
1222 if (status != IXGBE_SUCCESS)
1223 goto err_read_i2c_eeprom;
1225 status = hw->phy.ops.read_i2c_eeprom(hw,
1226 IXGBE_SFF_10GBE_COMP_CODES,
1229 if (status != IXGBE_SUCCESS)
1230 goto err_read_i2c_eeprom;
1231 status = hw->phy.ops.read_i2c_eeprom(hw,
1232 IXGBE_SFF_CABLE_TECHNOLOGY,
1235 if (status != IXGBE_SUCCESS)
1236 goto err_read_i2c_eeprom;
1243 * 3 SFP_DA_CORE0 - 82599-specific
1244 * 4 SFP_DA_CORE1 - 82599-specific
1245 * 5 SFP_SR/LR_CORE0 - 82599-specific
1246 * 6 SFP_SR/LR_CORE1 - 82599-specific
1247 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1248 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1249 * 9 SFP_1g_cu_CORE0 - 82599-specific
1250 * 10 SFP_1g_cu_CORE1 - 82599-specific
1251 * 11 SFP_1g_sx_CORE0 - 82599-specific
1252 * 12 SFP_1g_sx_CORE1 - 82599-specific
1254 if (hw->mac.type == ixgbe_mac_82598EB) {
1255 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1256 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1257 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1258 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1259 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1260 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1262 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1264 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1265 if (hw->bus.lan_id == 0)
1267 ixgbe_sfp_type_da_cu_core0;
1270 ixgbe_sfp_type_da_cu_core1;
1271 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1272 hw->phy.ops.read_i2c_eeprom(
1273 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1276 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1277 if (hw->bus.lan_id == 0)
1279 ixgbe_sfp_type_da_act_lmt_core0;
1282 ixgbe_sfp_type_da_act_lmt_core1;
1285 ixgbe_sfp_type_unknown;
1287 } else if (comp_codes_10g &
1288 (IXGBE_SFF_10GBASESR_CAPABLE |
1289 IXGBE_SFF_10GBASELR_CAPABLE)) {
1290 if (hw->bus.lan_id == 0)
1292 ixgbe_sfp_type_srlr_core0;
1295 ixgbe_sfp_type_srlr_core1;
1296 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1297 if (hw->bus.lan_id == 0)
1299 ixgbe_sfp_type_1g_cu_core0;
1302 ixgbe_sfp_type_1g_cu_core1;
1303 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1304 if (hw->bus.lan_id == 0)
1306 ixgbe_sfp_type_1g_sx_core0;
1309 ixgbe_sfp_type_1g_sx_core1;
1310 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1311 if (hw->bus.lan_id == 0)
1313 ixgbe_sfp_type_1g_lx_core0;
1316 ixgbe_sfp_type_1g_lx_core1;
1318 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1322 if (hw->phy.sfp_type != stored_sfp_type)
1323 hw->phy.sfp_setup_needed = true;
1325 /* Determine if the SFP+ PHY is dual speed or not. */
1326 hw->phy.multispeed_fiber = false;
1327 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1328 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1329 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1330 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1331 hw->phy.multispeed_fiber = true;
1333 /* Determine PHY vendor */
1334 if (hw->phy.type != ixgbe_phy_nl) {
1335 hw->phy.id = identifier;
1336 status = hw->phy.ops.read_i2c_eeprom(hw,
1337 IXGBE_SFF_VENDOR_OUI_BYTE0,
1340 if (status != IXGBE_SUCCESS)
1341 goto err_read_i2c_eeprom;
1343 status = hw->phy.ops.read_i2c_eeprom(hw,
1344 IXGBE_SFF_VENDOR_OUI_BYTE1,
1347 if (status != IXGBE_SUCCESS)
1348 goto err_read_i2c_eeprom;
1350 status = hw->phy.ops.read_i2c_eeprom(hw,
1351 IXGBE_SFF_VENDOR_OUI_BYTE2,
1354 if (status != IXGBE_SUCCESS)
1355 goto err_read_i2c_eeprom;
1358 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1359 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1360 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1362 switch (vendor_oui) {
1363 case IXGBE_SFF_VENDOR_OUI_TYCO:
1364 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1366 ixgbe_phy_sfp_passive_tyco;
1368 case IXGBE_SFF_VENDOR_OUI_FTL:
1369 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1370 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1372 hw->phy.type = ixgbe_phy_sfp_ftl;
1374 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1375 hw->phy.type = ixgbe_phy_sfp_avago;
1377 case IXGBE_SFF_VENDOR_OUI_INTEL:
1378 hw->phy.type = ixgbe_phy_sfp_intel;
1381 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1383 ixgbe_phy_sfp_passive_unknown;
1384 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1386 ixgbe_phy_sfp_active_unknown;
1388 hw->phy.type = ixgbe_phy_sfp_unknown;
1393 /* Allow any DA cable vendor */
1394 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1395 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1396 status = IXGBE_SUCCESS;
1400 /* Verify supported 1G SFP modules */
1401 if (comp_codes_10g == 0 &&
1402 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1403 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1404 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1405 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1406 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1407 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1408 hw->phy.type = ixgbe_phy_sfp_unsupported;
1409 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1413 /* Anything else 82598-based is supported */
1414 if (hw->mac.type == ixgbe_mac_82598EB) {
1415 status = IXGBE_SUCCESS;
1419 ixgbe_get_device_caps(hw, &enforce_sfp);
1420 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1421 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1422 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1423 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1424 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1425 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1426 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1427 /* Make sure we're a supported PHY type */
1428 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1429 status = IXGBE_SUCCESS;
1431 if (hw->allow_unsupported_sfp == true) {
1432 EWARN(hw, "WARNING: Intel (R) Network "
1433 "Connections are quality tested "
1434 "using Intel (R) Ethernet Optics."
1435 " Using untested modules is not "
1436 "supported and may cause unstable"
1437 " operation or damage to the "
1438 "module or the adapter. Intel "
1439 "Corporation is not responsible "
1440 "for any harm caused by using "
1441 "untested modules.\n", status);
1442 status = IXGBE_SUCCESS;
1444 DEBUGOUT("SFP+ module not supported\n");
1446 ixgbe_phy_sfp_unsupported;
1447 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1451 status = IXGBE_SUCCESS;
1458 err_read_i2c_eeprom:
1459 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1460 if (hw->phy.type != ixgbe_phy_nl) {
1462 hw->phy.type = ixgbe_phy_unknown;
1464 return IXGBE_ERR_SFP_NOT_PRESENT;
1468 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1469 * @hw: pointer to hardware structure
1471 * Determines physical layer capabilities of the current SFP.
1473 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1475 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1476 u8 comp_codes_10g = 0;
1477 u8 comp_codes_1g = 0;
1479 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1481 hw->phy.ops.identify_sfp(hw);
1482 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1483 return physical_layer;
1485 switch (hw->phy.type) {
1486 case ixgbe_phy_sfp_passive_tyco:
1487 case ixgbe_phy_sfp_passive_unknown:
1488 case ixgbe_phy_qsfp_passive_unknown:
1489 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1491 case ixgbe_phy_sfp_ftl_active:
1492 case ixgbe_phy_sfp_active_unknown:
1493 case ixgbe_phy_qsfp_active_unknown:
1494 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1496 case ixgbe_phy_sfp_avago:
1497 case ixgbe_phy_sfp_ftl:
1498 case ixgbe_phy_sfp_intel:
1499 case ixgbe_phy_sfp_unknown:
1500 hw->phy.ops.read_i2c_eeprom(hw,
1501 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1502 hw->phy.ops.read_i2c_eeprom(hw,
1503 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1504 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1505 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1506 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1507 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1508 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1509 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1510 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1511 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1513 case ixgbe_phy_qsfp_intel:
1514 case ixgbe_phy_qsfp_unknown:
1515 hw->phy.ops.read_i2c_eeprom(hw,
1516 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1517 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1518 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1519 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1520 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1526 return physical_layer;
1530 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1531 * @hw: pointer to hardware structure
1533 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1535 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1537 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1539 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1541 u8 comp_codes_1g = 0;
1542 u8 comp_codes_10g = 0;
1543 u8 oui_bytes[3] = {0, 0, 0};
1544 u16 enforce_sfp = 0;
1546 u8 cable_length = 0;
1548 bool active_cable = false;
1550 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1552 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1553 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1554 status = IXGBE_ERR_SFP_NOT_PRESENT;
1558 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1561 if (status != IXGBE_SUCCESS)
1562 goto err_read_i2c_eeprom;
1564 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1565 hw->phy.type = ixgbe_phy_sfp_unsupported;
1566 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1570 hw->phy.id = identifier;
1572 /* LAN ID is needed for sfp_type determination */
1573 hw->mac.ops.set_lan_id(hw);
1575 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1578 if (status != IXGBE_SUCCESS)
1579 goto err_read_i2c_eeprom;
1581 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1584 if (status != IXGBE_SUCCESS)
1585 goto err_read_i2c_eeprom;
1587 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1588 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1589 if (hw->bus.lan_id == 0)
1590 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1592 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1593 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1594 IXGBE_SFF_10GBASELR_CAPABLE)) {
1595 if (hw->bus.lan_id == 0)
1596 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1598 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1600 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1601 active_cable = true;
1603 if (!active_cable) {
1604 /* check for active DA cables that pre-date
1606 hw->phy.ops.read_i2c_eeprom(hw,
1607 IXGBE_SFF_QSFP_CONNECTOR,
1610 hw->phy.ops.read_i2c_eeprom(hw,
1611 IXGBE_SFF_QSFP_CABLE_LENGTH,
1614 hw->phy.ops.read_i2c_eeprom(hw,
1615 IXGBE_SFF_QSFP_DEVICE_TECH,
1619 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1620 (cable_length > 0) &&
1621 ((device_tech >> 4) ==
1622 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1623 active_cable = true;
1627 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1628 if (hw->bus.lan_id == 0)
1630 ixgbe_sfp_type_da_act_lmt_core0;
1633 ixgbe_sfp_type_da_act_lmt_core1;
1635 /* unsupported module type */
1636 hw->phy.type = ixgbe_phy_sfp_unsupported;
1637 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1642 if (hw->phy.sfp_type != stored_sfp_type)
1643 hw->phy.sfp_setup_needed = true;
1645 /* Determine if the QSFP+ PHY is dual speed or not. */
1646 hw->phy.multispeed_fiber = false;
1647 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1648 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1649 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1650 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1651 hw->phy.multispeed_fiber = true;
1653 /* Determine PHY vendor for optical modules */
1654 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1655 IXGBE_SFF_10GBASELR_CAPABLE)) {
1656 status = hw->phy.ops.read_i2c_eeprom(hw,
1657 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1660 if (status != IXGBE_SUCCESS)
1661 goto err_read_i2c_eeprom;
1663 status = hw->phy.ops.read_i2c_eeprom(hw,
1664 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1667 if (status != IXGBE_SUCCESS)
1668 goto err_read_i2c_eeprom;
1670 status = hw->phy.ops.read_i2c_eeprom(hw,
1671 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1674 if (status != IXGBE_SUCCESS)
1675 goto err_read_i2c_eeprom;
1678 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1679 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1680 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1682 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1683 hw->phy.type = ixgbe_phy_qsfp_intel;
1685 hw->phy.type = ixgbe_phy_qsfp_unknown;
1687 ixgbe_get_device_caps(hw, &enforce_sfp);
1688 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1689 /* Make sure we're a supported PHY type */
1690 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1691 status = IXGBE_SUCCESS;
1693 if (hw->allow_unsupported_sfp == true) {
1694 EWARN(hw, "WARNING: Intel (R) Network "
1695 "Connections are quality tested "
1696 "using Intel (R) Ethernet Optics."
1697 " Using untested modules is not "
1698 "supported and may cause unstable"
1699 " operation or damage to the "
1700 "module or the adapter. Intel "
1701 "Corporation is not responsible "
1702 "for any harm caused by using "
1703 "untested modules.\n", status);
1704 status = IXGBE_SUCCESS;
1706 DEBUGOUT("QSFP module not supported\n");
1708 ixgbe_phy_sfp_unsupported;
1709 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1713 status = IXGBE_SUCCESS;
1720 err_read_i2c_eeprom:
1721 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1723 hw->phy.type = ixgbe_phy_unknown;
1725 return IXGBE_ERR_SFP_NOT_PRESENT;
1730 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1731 * @hw: pointer to hardware structure
1732 * @list_offset: offset to the SFP ID list
1733 * @data_offset: offset to the SFP data block
1735 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1736 * so it returns the offsets to the phy init sequence block.
1738 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1743 u16 sfp_type = hw->phy.sfp_type;
1745 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1747 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1748 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1750 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1751 return IXGBE_ERR_SFP_NOT_PRESENT;
1753 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1754 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1755 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1758 * Limiting active cables and 1G Phys must be initialized as
1761 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1762 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1763 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1764 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1765 sfp_type = ixgbe_sfp_type_srlr_core0;
1766 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1767 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1768 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1769 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1770 sfp_type = ixgbe_sfp_type_srlr_core1;
1772 /* Read offset to PHY init contents */
1773 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1774 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1775 "eeprom read at offset %d failed",
1776 IXGBE_PHY_INIT_OFFSET_NL);
1777 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1780 if ((!*list_offset) || (*list_offset == 0xFFFF))
1781 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1783 /* Shift offset to first ID word */
1787 * Find the matching SFP ID in the EEPROM
1788 * and program the init sequence
1790 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1793 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1794 if (sfp_id == sfp_type) {
1796 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1798 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1799 DEBUGOUT("SFP+ module not supported\n");
1800 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1805 (*list_offset) += 2;
1806 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1811 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1812 DEBUGOUT("No matching SFP+ module found\n");
1813 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1816 return IXGBE_SUCCESS;
1819 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1820 "eeprom read at offset %d failed", *list_offset);
1821 return IXGBE_ERR_PHY;
1825 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1826 * @hw: pointer to hardware structure
1827 * @byte_offset: EEPROM byte offset to read
1828 * @eeprom_data: value read
1830 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1832 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1835 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1837 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1838 IXGBE_I2C_EEPROM_DEV_ADDR,
1843 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1844 * @hw: pointer to hardware structure
1845 * @byte_offset: byte offset at address 0xA2
1846 * @eeprom_data: value read
1848 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1850 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1853 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1854 IXGBE_I2C_EEPROM_DEV_ADDR2,
1859 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1860 * @hw: pointer to hardware structure
1861 * @byte_offset: EEPROM byte offset to write
1862 * @eeprom_data: value to write
1864 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1866 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1869 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1871 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1872 IXGBE_I2C_EEPROM_DEV_ADDR,
1877 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1878 * @hw: pointer to hardware structure
1879 * @byte_offset: byte offset to read
1882 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1883 * a specified device address.
1885 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1886 u8 dev_addr, u8 *data)
1891 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1895 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1898 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1899 return IXGBE_ERR_SWFW_SYNC;
1901 ixgbe_i2c_start(hw);
1903 /* Device Address and write indication */
1904 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1905 if (status != IXGBE_SUCCESS)
1908 status = ixgbe_get_i2c_ack(hw);
1909 if (status != IXGBE_SUCCESS)
1912 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1913 if (status != IXGBE_SUCCESS)
1916 status = ixgbe_get_i2c_ack(hw);
1917 if (status != IXGBE_SUCCESS)
1920 ixgbe_i2c_start(hw);
1922 /* Device Address and read indication */
1923 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1924 if (status != IXGBE_SUCCESS)
1927 status = ixgbe_get_i2c_ack(hw);
1928 if (status != IXGBE_SUCCESS)
1931 status = ixgbe_clock_in_i2c_byte(hw, data);
1932 if (status != IXGBE_SUCCESS)
1935 status = ixgbe_clock_out_i2c_bit(hw, nack);
1936 if (status != IXGBE_SUCCESS)
1940 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1941 return IXGBE_SUCCESS;
1944 ixgbe_i2c_bus_clear(hw);
1945 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1948 if (retry < max_retry)
1949 DEBUGOUT("I2C byte read error - Retrying.\n");
1951 DEBUGOUT("I2C byte read error.\n");
1953 } while (retry < max_retry);
1959 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1960 * @hw: pointer to hardware structure
1961 * @byte_offset: byte offset to write
1962 * @data: value to write
1964 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1965 * a specified device address.
1967 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1968 u8 dev_addr, u8 data)
1970 s32 status = IXGBE_SUCCESS;
1973 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1975 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1977 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1978 status = IXGBE_ERR_SWFW_SYNC;
1979 goto write_byte_out;
1983 ixgbe_i2c_start(hw);
1985 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1986 if (status != IXGBE_SUCCESS)
1989 status = ixgbe_get_i2c_ack(hw);
1990 if (status != IXGBE_SUCCESS)
1993 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1994 if (status != IXGBE_SUCCESS)
1997 status = ixgbe_get_i2c_ack(hw);
1998 if (status != IXGBE_SUCCESS)
2001 status = ixgbe_clock_out_i2c_byte(hw, data);
2002 if (status != IXGBE_SUCCESS)
2005 status = ixgbe_get_i2c_ack(hw);
2006 if (status != IXGBE_SUCCESS)
2010 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2011 return IXGBE_SUCCESS;
2014 ixgbe_i2c_bus_clear(hw);
2016 if (retry < max_retry)
2017 DEBUGOUT("I2C byte write error - Retrying.\n");
2019 DEBUGOUT("I2C byte write error.\n");
2020 } while (retry < max_retry);
2022 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2029 * ixgbe_i2c_start - Sets I2C start condition
2030 * @hw: pointer to hardware structure
2032 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2033 * Set bit-bang mode on X550 hardware.
2035 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2037 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2039 DEBUGFUNC("ixgbe_i2c_start");
2041 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2043 /* Start condition must begin with data and clock high */
2044 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2045 ixgbe_raise_i2c_clk(hw, &i2cctl);
2047 /* Setup time for start condition (4.7us) */
2048 usec_delay(IXGBE_I2C_T_SU_STA);
2050 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2052 /* Hold time for start condition (4us) */
2053 usec_delay(IXGBE_I2C_T_HD_STA);
2055 ixgbe_lower_i2c_clk(hw, &i2cctl);
2057 /* Minimum low period of clock is 4.7 us */
2058 usec_delay(IXGBE_I2C_T_LOW);
2063 * ixgbe_i2c_stop - Sets I2C stop condition
2064 * @hw: pointer to hardware structure
2066 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2067 * Disables bit-bang mode and negates data output enable on X550
2070 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2072 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2073 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2074 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2075 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2077 DEBUGFUNC("ixgbe_i2c_stop");
2079 /* Stop condition must begin with data low and clock high */
2080 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2081 ixgbe_raise_i2c_clk(hw, &i2cctl);
2083 /* Setup time for stop condition (4us) */
2084 usec_delay(IXGBE_I2C_T_SU_STO);
2086 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2088 /* bus free time between stop and start (4.7us)*/
2089 usec_delay(IXGBE_I2C_T_BUF);
2091 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2092 i2cctl &= ~bb_en_bit;
2093 i2cctl |= data_oe_bit | clk_oe_bit;
2094 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2095 IXGBE_WRITE_FLUSH(hw);
2100 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2101 * @hw: pointer to hardware structure
2102 * @data: data byte to clock in
2104 * Clocks in one byte data via I2C data/clock
2106 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2111 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2114 for (i = 7; i >= 0; i--) {
2115 ixgbe_clock_in_i2c_bit(hw, &bit);
2119 return IXGBE_SUCCESS;
2123 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2124 * @hw: pointer to hardware structure
2125 * @data: data byte clocked out
2127 * Clocks out one byte data via I2C data/clock
2129 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2131 s32 status = IXGBE_SUCCESS;
2136 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2138 for (i = 7; i >= 0; i--) {
2139 bit = (data >> i) & 0x1;
2140 status = ixgbe_clock_out_i2c_bit(hw, bit);
2142 if (status != IXGBE_SUCCESS)
2146 /* Release SDA line (set high) */
2147 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2148 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2149 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2150 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2151 IXGBE_WRITE_FLUSH(hw);
2157 * ixgbe_get_i2c_ack - Polls for I2C ACK
2158 * @hw: pointer to hardware structure
2160 * Clocks in/out one bit via I2C data/clock
2162 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2164 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2165 s32 status = IXGBE_SUCCESS;
2167 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2171 DEBUGFUNC("ixgbe_get_i2c_ack");
2174 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2175 i2cctl |= data_oe_bit;
2176 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2177 IXGBE_WRITE_FLUSH(hw);
2179 ixgbe_raise_i2c_clk(hw, &i2cctl);
2181 /* Minimum high period of clock is 4us */
2182 usec_delay(IXGBE_I2C_T_HIGH);
2184 /* Poll for ACK. Note that ACK in I2C spec is
2185 * transition from 1 to 0 */
2186 for (i = 0; i < timeout; i++) {
2187 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2188 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2196 DEBUGOUT("I2C ack was not received.\n");
2197 status = IXGBE_ERR_I2C;
2200 ixgbe_lower_i2c_clk(hw, &i2cctl);
2202 /* Minimum low period of clock is 4.7 us */
2203 usec_delay(IXGBE_I2C_T_LOW);
2209 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2210 * @hw: pointer to hardware structure
2211 * @data: read data value
2213 * Clocks in one bit via I2C data/clock
2215 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2217 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2218 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2220 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2223 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2224 i2cctl |= data_oe_bit;
2225 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2226 IXGBE_WRITE_FLUSH(hw);
2228 ixgbe_raise_i2c_clk(hw, &i2cctl);
2230 /* Minimum high period of clock is 4us */
2231 usec_delay(IXGBE_I2C_T_HIGH);
2233 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2234 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2236 ixgbe_lower_i2c_clk(hw, &i2cctl);
2238 /* Minimum low period of clock is 4.7 us */
2239 usec_delay(IXGBE_I2C_T_LOW);
2241 return IXGBE_SUCCESS;
2245 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2246 * @hw: pointer to hardware structure
2247 * @data: data value to write
2249 * Clocks out one bit via I2C data/clock
2251 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2254 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2256 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2258 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2259 if (status == IXGBE_SUCCESS) {
2260 ixgbe_raise_i2c_clk(hw, &i2cctl);
2262 /* Minimum high period of clock is 4us */
2263 usec_delay(IXGBE_I2C_T_HIGH);
2265 ixgbe_lower_i2c_clk(hw, &i2cctl);
2267 /* Minimum low period of clock is 4.7 us.
2268 * This also takes care of the data hold time.
2270 usec_delay(IXGBE_I2C_T_LOW);
2272 status = IXGBE_ERR_I2C;
2273 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2274 "I2C data was not set to %X\n", data);
2281 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2282 * @hw: pointer to hardware structure
2283 * @i2cctl: Current value of I2CCTL register
2285 * Raises the I2C clock line '0'->'1'
2286 * Negates the I2C clock output enable on X550 hardware.
2288 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2290 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2292 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2295 DEBUGFUNC("ixgbe_raise_i2c_clk");
2298 *i2cctl |= clk_oe_bit;
2299 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2302 for (i = 0; i < timeout; i++) {
2303 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2305 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2306 IXGBE_WRITE_FLUSH(hw);
2307 /* SCL rise time (1000ns) */
2308 usec_delay(IXGBE_I2C_T_RISE);
2310 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2311 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2317 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2318 * @hw: pointer to hardware structure
2319 * @i2cctl: Current value of I2CCTL register
2321 * Lowers the I2C clock line '1'->'0'
2322 * Asserts the I2C clock output enable on X550 hardware.
2324 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2326 DEBUGFUNC("ixgbe_lower_i2c_clk");
2328 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2329 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2331 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2332 IXGBE_WRITE_FLUSH(hw);
2334 /* SCL fall time (300ns) */
2335 usec_delay(IXGBE_I2C_T_FALL);
2339 * ixgbe_set_i2c_data - Sets the I2C data bit
2340 * @hw: pointer to hardware structure
2341 * @i2cctl: Current value of I2CCTL register
2342 * @data: I2C data value (0 or 1) to set
2344 * Sets the I2C data bit
2345 * Asserts the I2C data output enable on X550 hardware.
2347 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2349 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2350 s32 status = IXGBE_SUCCESS;
2352 DEBUGFUNC("ixgbe_set_i2c_data");
2355 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2357 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2358 *i2cctl &= ~data_oe_bit;
2360 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2361 IXGBE_WRITE_FLUSH(hw);
2363 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2364 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2366 if (!data) /* Can't verify data in this case */
2367 return IXGBE_SUCCESS;
2369 *i2cctl |= data_oe_bit;
2370 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2371 IXGBE_WRITE_FLUSH(hw);
2374 /* Verify data was set correctly */
2375 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2376 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2377 status = IXGBE_ERR_I2C;
2378 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2379 "Error - I2C data was not set to %X.\n",
2387 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2388 * @hw: pointer to hardware structure
2389 * @i2cctl: Current value of I2CCTL register
2391 * Returns the I2C data bit value
2392 * Negates the I2C data output enable on X550 hardware.
2394 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2396 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2399 DEBUGFUNC("ixgbe_get_i2c_data");
2402 *i2cctl |= data_oe_bit;
2403 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2404 IXGBE_WRITE_FLUSH(hw);
2405 usec_delay(IXGBE_I2C_T_FALL);
2408 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2417 * ixgbe_i2c_bus_clear - Clears the I2C bus
2418 * @hw: pointer to hardware structure
2420 * Clears the I2C bus by sending nine clock pulses.
2421 * Used when data line is stuck low.
2423 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2428 DEBUGFUNC("ixgbe_i2c_bus_clear");
2430 ixgbe_i2c_start(hw);
2431 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2433 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2435 for (i = 0; i < 9; i++) {
2436 ixgbe_raise_i2c_clk(hw, &i2cctl);
2438 /* Min high period of clock is 4us */
2439 usec_delay(IXGBE_I2C_T_HIGH);
2441 ixgbe_lower_i2c_clk(hw, &i2cctl);
2443 /* Min low period of clock is 4.7us*/
2444 usec_delay(IXGBE_I2C_T_LOW);
2447 ixgbe_i2c_start(hw);
2449 /* Put the i2c bus back to default state */
2454 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2455 * @hw: pointer to hardware structure
2457 * Checks if the LASI temp alarm status was triggered due to overtemp
2459 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2461 s32 status = IXGBE_SUCCESS;
2464 DEBUGFUNC("ixgbe_tn_check_overtemp");
2466 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2469 /* Check that the LASI temp alarm status was triggered */
2470 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2471 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2473 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2476 status = IXGBE_ERR_OVERTEMP;
2477 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");