lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37 #ident "$Id: ixgbe_phy.c,v 1.155 2013/08/14 22:34:03 jtkirshe Exp $"
  38
  39 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  40 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  41 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  42 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  43 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  44 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  45 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  46 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  48 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  49 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
  50 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  51                                           u8 *sff8472_data);
  52
  53 /**
  54  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
  55  * @hw: pointer to the hardware structure
  56  * @byte: byte to send
  57  *
  58  * Returns an error code on error.
  59  */
  60 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
  61 {
  62         s32 status;
  63
  64         status = ixgbe_clock_out_i2c_byte(hw, byte);
  65         if (status)
  66                 return status;
  67         return ixgbe_get_i2c_ack(hw);
  68 }
  69
  70 /**
  71  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
  72  * @hw: pointer to the hardware structure
  73  * @byte: pointer to a u8 to receive the byte
  74  *
  75  * Returns an error code on error.
  76  */
  77 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
  78 {
  79         s32 status;
  80
  81         status = ixgbe_clock_in_i2c_byte(hw, byte);
  82         if (status)
  83                 return status;
  84         /* ACK */
  85         return ixgbe_clock_out_i2c_bit(hw, false);
  86 }
  87
  88 /**
  89  * ixgbe_ones_comp_byte_add - Perform one's complement addition
  90  * @add1 - addend 1
  91  * @add2 - addend 2
  92  *
  93  * Returns one's complement 8-bit sum.
  94  */
  95 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
  96 {
  97         u16 sum = add1 + add2;
  98
  99         sum = (sum & 0xFF) + (sum >> 8);
 100         return sum & 0xFF;
 101 }
 102
 103 /**
 104  * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
 105  * @hw: pointer to the hardware structure
 106  * @addr: I2C bus address to read from
 107  * @reg: I2C device register to read from
 108  * @val: pointer to location to receive read value
 109  *
 110  * Returns an error code on error.
 111  */
 112 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
 113                                            u16 reg, u16 *val)
 114 {
 115         u32 swfw_mask = hw->phy.phy_semaphore_mask;
 116         int max_retry = 10;
 117         int retry = 0;
 118         u8 csum_byte;
 119         u8 high_bits;
 120         u8 low_bits;
 121         u8 reg_high;
 122         u8 csum;
 123
 124         reg_high = ((reg >> 7) & 0xFE) | 1;     /* Indicate read combined */
 125         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 126         csum = ~csum;
 127         do {
 128                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
 129                         return IXGBE_ERR_SWFW_SYNC;
 130                 ixgbe_i2c_start(hw);
 131                 /* Device Address and write indication */
 132                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 133                         goto fail;
 134                 /* Write bits 14:8 */
 135                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 136                         goto fail;
 137                 /* Write bits 7:0 */
 138                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 139                         goto fail;
 140                 /* Write csum */
 141                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 142                         goto fail;
 143                 /* Re-start condition */
 144                 ixgbe_i2c_start(hw);
 145                 /* Device Address and read indication */
 146                 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
 147                         goto fail;
 148                 /* Get upper bits */
 149                 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
 150                         goto fail;
 151                 /* Get low bits */
 152                 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
 153                         goto fail;
 154                 /* Get csum */
 155                 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
 156                         goto fail;
 157                 /* NACK */
 158                 if (ixgbe_clock_out_i2c_bit(hw, false))
 159                         goto fail;
 160                 ixgbe_i2c_stop(hw);
 161                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 162                 *val = (high_bits << 8) | low_bits;
 163                 return 0;
 164
 165 fail:
 166                 ixgbe_i2c_bus_clear(hw);
 167                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
 168                 retry++;
 169                 if (retry < max_retry)
 170                         DEBUGOUT("I2C byte read combined error - Retrying.\n");
 171                 else
 172                         DEBUGOUT("I2C byte read combined error.\n");
 173         } while (retry < max_retry);
 174
 175         return IXGBE_ERR_I2C;
 176 }
 177
 178 /**
 179  * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
 180  * @hw: pointer to the hardware structure
 181  * @addr: I2C bus address to write to
 182  * @reg: I2C device register to write to
 183  * @val: value to write
 184  *
 185  * Returns an error code on error.
 186  */
 187 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
 188                                             u8 addr, u16 reg, u16 val)
 189 {
 190         int max_retry = 1;
 191         int retry = 0;
 192         u8 reg_high;
 193         u8 csum;
 194
 195         reg_high = (reg >> 7) & 0xFE;   /* Indicate write combined */
 196         csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
 197         csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
 198         csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
 199         csum = ~csum;
 200         do {
 201                 ixgbe_i2c_start(hw);
 202                 /* Device Address and write indication */
 203                 if (ixgbe_out_i2c_byte_ack(hw, addr))
 204                         goto fail;
 205                 /* Write bits 14:8 */
 206                 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
 207                         goto fail;
 208                 /* Write bits 7:0 */
 209                 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
 210                         goto fail;
 211                 /* Write data 15:8 */
 212                 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
 213                         goto fail;
 214                 /* Write data 7:0 */
 215                 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
 216                         goto fail;
 217                 /* Write csum */
 218                 if (ixgbe_out_i2c_byte_ack(hw, csum))
 219                         goto fail;
 220                 ixgbe_i2c_stop(hw);
 221                 return 0;
 222
 223 fail:
 224                 ixgbe_i2c_bus_clear(hw);
 225                 retry++;
 226                 if (retry < max_retry)
 227                         DEBUGOUT("I2C byte write combined error - Retrying.\n");
 228                 else
 229                         DEBUGOUT("I2C byte write combined error.\n");
 230         } while (retry < max_retry);
 231
 232         return IXGBE_ERR_I2C;
 233 }
 234
 235 /**
 236  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
 237  *  @hw: pointer to the hardware structure
 238  *
 239  *  Initialize the function pointers.
 240  **/
 241 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
 242 {
 243         struct ixgbe_phy_info *phy = &hw->phy;
 244
 245         DEBUGFUNC("ixgbe_init_phy_ops_generic");
 246
 247         /* PHY */
 248         phy->ops.identify = &ixgbe_identify_phy_generic;
 249         phy->ops.reset = &ixgbe_reset_phy_generic;
 250         phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
 251         phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
 252         phy->ops.read_reg_mdi = &ixgbe_read_phy_reg_mdi;
 253         phy->ops.write_reg_mdi = &ixgbe_write_phy_reg_mdi;
 254         phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
 255         phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
 256         phy->ops.check_link = NULL;
 257         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
 258         phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
 259         phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
 260         phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic;
 261         phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
 262         phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
 263         phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
 264         phy->ops.identify_sfp = &ixgbe_identify_module_generic;
 265         phy->sfp_type = ixgbe_sfp_type_unknown;
 266         phy->ops.read_i2c_combined = &ixgbe_read_i2c_combined_generic;
 267         phy->ops.write_i2c_combined = &ixgbe_write_i2c_combined_generic;
 268         phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
 269         return IXGBE_SUCCESS;
 270 }
 271
 272 /**
 273  *  ixgbe_identify_phy_generic - Get physical layer module
 274  *  @hw: pointer to hardware structure
 275  *
 276  *  Determines the physical layer module found on the current adapter.
 277  **/
 278 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
 279 {
 280         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
 281         u32 phy_addr;
 282         u16 ext_ability = 0;
 283
 284         DEBUGFUNC("ixgbe_identify_phy_generic");
 285
 286         if (!hw->phy.phy_semaphore_mask) {
 287                 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
 288                                                 IXGBE_STATUS_LAN_ID_1;
 289                 if (hw->phy.lan_id)
 290                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
 291                 else
 292                         hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
 293         }
 294
 295         if (hw->phy.type == ixgbe_phy_unknown) {
 296                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 297                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 298                                 hw->phy.addr = phy_addr;
 299                                 ixgbe_get_phy_id(hw);
 300                                 hw->phy.type =
 301                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 302
 303                                 if (hw->phy.type == ixgbe_phy_unknown) {
 304                                         hw->phy.ops.read_reg(hw,
 305                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 306                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 307                                                   &ext_ability);
 308                                         if (ext_ability &
 309                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 310                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 311                                                 hw->phy.type =
 312                                                          ixgbe_phy_cu_unknown;
 313                                         else
 314                                                 hw->phy.type =
 315                                                          ixgbe_phy_generic;
 316                                 }
 317
 318                                 status = IXGBE_SUCCESS;
 319                                 break;
 320                         }
 321                 }
 322
 323                 /* Certain media types do not have a phy so an address will not
 324                  * be found and the code will take this path.  Caller has to
 325                  * decide if it is an error or not.
 326                  */
 327                 if (status != IXGBE_SUCCESS) {
 328                         hw->phy.addr = 0;
 329                 }
 330         } else {
 331                 status = IXGBE_SUCCESS;
 332         }
 333
 334         return status;
 335 }
 336
 337 /**
 338  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 339  * @hw: pointer to the hardware structure
 340  *
 341  * This function checks the MMNGC.MNG_VETO bit to see if there are
 342  * any constraints on link from manageability.  For MAC's that don't
 343  * have this bit just return faluse since the link can not be blocked
 344  * via this method.
 345  **/
 346 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 347 {
 348         u32 mmngc;
 349
 350         DEBUGFUNC("ixgbe_check_reset_blocked");
 351
 352         /* If we don't have this bit, it can't be blocking */
 353         if (hw->mac.type == ixgbe_mac_82598EB)
 354                 return false;
 355
 356         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 357         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 358                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 359                               "MNG_VETO bit detected.\n");
 360                 return true;
 361         }
 362
 363         return false;
 364 }
 365
 366 /**
 367  *  ixgbe_validate_phy_addr - Determines phy address is valid
 368  *  @hw: pointer to hardware structure
 369  *
 370  **/
 371 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 372 {
 373         u16 phy_id = 0;
 374         bool valid = false;
 375
 376         DEBUGFUNC("ixgbe_validate_phy_addr");
 377
 378         hw->phy.addr = phy_addr;
 379         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 380                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 381
 382         if (phy_id != 0xFFFF && phy_id != 0x0)
 383                 valid = true;
 384
 385         return valid;
 386 }
 387
 388 /**
 389  *  ixgbe_get_phy_id - Get the phy type
 390  *  @hw: pointer to hardware structure
 391  *
 392  **/
 393 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 394 {
 395         u32 status;
 396         u16 phy_id_high = 0;
 397         u16 phy_id_low = 0;
 398
 399         DEBUGFUNC("ixgbe_get_phy_id");
 400
 401         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 402                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 403                                       &phy_id_high);
 404
 405         if (status == IXGBE_SUCCESS) {
 406                 hw->phy.id = (u32)(phy_id_high << 16);
 407                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 408                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 409                                               &phy_id_low);
 410                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 411                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 412         }
 413         return status;
 414 }
 415
 416 /**
 417  *  ixgbe_get_phy_type_from_id - Get the phy type
 418  *  @hw: pointer to hardware structure
 419  *
 420  **/
 421 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 422 {
 423         enum ixgbe_phy_type phy_type;
 424
 425         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 426
 427         switch (phy_id) {
 428         case TN1010_PHY_ID:
 429                 phy_type = ixgbe_phy_tn;
 430                 break;
 431         case X550_PHY_ID:
 432         case X540_PHY_ID:
 433                 phy_type = ixgbe_phy_aq;
 434                 break;
 435         case QT2022_PHY_ID:
 436                 phy_type = ixgbe_phy_qt;
 437                 break;
 438         case ATH_PHY_ID:
 439                 phy_type = ixgbe_phy_nl;
 440                 break;
 441         default:
 442                 phy_type = ixgbe_phy_unknown;
 443                 break;
 444         }
 445
 446         DEBUGOUT1("phy type found is %d\n", phy_type);
 447         return phy_type;
 448 }
 449
 450 /**
 451  *  ixgbe_reset_phy_generic - Performs a PHY reset
 452  *  @hw: pointer to hardware structure
 453  **/
 454 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 455 {
 456         u32 i;
 457         u16 ctrl = 0;
 458         s32 status = IXGBE_SUCCESS;
 459
 460         DEBUGFUNC("ixgbe_reset_phy_generic");
 461
 462         if (hw->phy.type == ixgbe_phy_unknown)
 463                 status = ixgbe_identify_phy_generic(hw);
 464
 465         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 466                 goto out;
 467
 468         /* Don't reset PHY if it's shut down due to overtemp. */
 469         if (!hw->phy.reset_if_overtemp &&
 470             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 471                 goto out;
 472
 473         /* Blocked by MNG FW so bail */
 474         if (ixgbe_check_reset_blocked(hw))
 475                 goto out;
 476
 477         /*
 478          * Perform soft PHY reset to the PHY_XS.
 479          * This will cause a soft reset to the PHY
 480          */
 481         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 482                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 483                               IXGBE_MDIO_PHY_XS_RESET);
 484
 485         /*
 486          * Poll for reset bit to self-clear indicating reset is complete.
 487          * Some PHYs could take up to 3 seconds to complete and need about
 488          * 1.7 usec delay after the reset is complete.
 489          */
 490         for (i = 0; i < 30; i++) {
 491                 msec_delay(100);
 492                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 493                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 494                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 495                         usec_delay(2);
 496                         break;
 497                 }
 498         }
 499
 500         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 501                 status = IXGBE_ERR_RESET_FAILED;
 502                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 503                              "PHY reset polling failed to complete.\n");
 504         }
 505
 506 out:
 507         return status;
 508 }
 509
 510 /**
 511  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 512  *  the SWFW lock
 513  *  @hw: pointer to hardware structure
 514  *  @reg_addr: 32 bit address of PHY register to read
 515  *  @phy_data: Pointer to read data from PHY register
 516  **/
 517 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 518                        u16 *phy_data)
 519 {
 520         u32 i, data, command;
 521
 522         /* Setup and write the address cycle command */
 523         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 524                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 525                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 526                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 527
 528         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 529
 530         /*
 531          * Check every 10 usec to see if the address cycle completed.
 532          * The MDI Command bit will clear when the operation is
 533          * complete
 534          */
 535         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 536                 usec_delay(10);
 537
 538                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 539                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 540                                 break;
 541         }
 542
 543
 544         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 545                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 546                 return IXGBE_ERR_PHY;
 547         }
 548
 549         /*
 550          * Address cycle complete, setup and write the read
 551          * command
 552          */
 553         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 554                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 555                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 556                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 557
 558         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 559
 560         /*
 561          * Check every 10 usec to see if the address cycle
 562          * completed. The MDI Command bit will clear when the
 563          * operation is complete
 564          */
 565         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 566                 usec_delay(10);
 567
 568                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 569                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 570                         break;
 571         }
 572
 573         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 574                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 575                 return IXGBE_ERR_PHY;
 576         }
 577
 578         /*
 579          * Read operation is complete.  Get the data
 580          * from MSRWD
 581          */
 582         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 583         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 584         *phy_data = (u16)(data);
 585
 586         return IXGBE_SUCCESS;
 587 }
 588
 589 /**
 590  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 591  *  using the SWFW lock - this function is needed in most cases
 592  *  @hw: pointer to hardware structure
 593  *  @reg_addr: 32 bit address of PHY register to read
 594  *  @phy_data: Pointer to read data from PHY register
 595  **/
 596 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 597                                u32 device_type, u16 *phy_data)
 598 {
 599         s32 status;
 600         u32 gssr = hw->phy.phy_semaphore_mask;
 601
 602         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 603
 604         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 605                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 606                                                 phy_data);
 607                 hw->mac.ops.release_swfw_sync(hw, gssr);
 608         } else {
 609                 status = IXGBE_ERR_SWFW_SYNC;
 610         }
 611
 612         return status;
 613 }
 614
 615 /**
 616  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 617  *  without SWFW lock
 618  *  @hw: pointer to hardware structure
 619  *  @reg_addr: 32 bit PHY register to write
 620  *  @device_type: 5 bit device type
 621  *  @phy_data: Data to write to the PHY register
 622  **/
 623 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 624                                 u32 device_type, u16 phy_data)
 625 {
 626         u32 i, command;
 627
 628         /* Put the data in the MDI single read and write data register*/
 629         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 630
 631         /* Setup and write the address cycle command */
 632         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 633                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 634                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 635                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 636
 637         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 638
 639         /*
 640          * Check every 10 usec to see if the address cycle completed.
 641          * The MDI Command bit will clear when the operation is
 642          * complete
 643          */
 644         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 645                 usec_delay(10);
 646
 647                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 648                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 649                         break;
 650         }
 651
 652         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 653                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 654                 return IXGBE_ERR_PHY;
 655         }
 656
 657         /*
 658          * Address cycle complete, setup and write the write
 659          * command
 660          */
 661         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 662                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 663                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 664                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 665
 666         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 667
 668         /*
 669          * Check every 10 usec to see if the address cycle
 670          * completed. The MDI Command bit will clear when the
 671          * operation is complete
 672          */
 673         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 674                 usec_delay(10);
 675
 676                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 677                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 678                         break;
 679         }
 680
 681         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 682                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 683                 return IXGBE_ERR_PHY;
 684         }
 685
 686         return IXGBE_SUCCESS;
 687 }
 688
 689 /**
 690  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 691  *  using SWFW lock- this function is needed in most cases
 692  *  @hw: pointer to hardware structure
 693  *  @reg_addr: 32 bit PHY register to write
 694  *  @device_type: 5 bit device type
 695  *  @phy_data: Data to write to the PHY register
 696  **/
 697 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 698                                 u32 device_type, u16 phy_data)
 699 {
 700         s32 status;
 701         u32 gssr = hw->phy.phy_semaphore_mask;
 702
 703         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 704
 705         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 706                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 707                                                  phy_data);
 708                 hw->mac.ops.release_swfw_sync(hw, gssr);
 709         } else {
 710                 status = IXGBE_ERR_SWFW_SYNC;
 711         }
 712
 713         return status;
 714 }
 715
 716 /**
 717  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 718  *  @hw: pointer to hardware structure
 719  *
 720  *  Restart auto-negotiation and PHY and waits for completion.
 721  **/
 722 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 723 {
 724         s32 status = IXGBE_SUCCESS;
 725         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 726         bool autoneg = false;
 727         ixgbe_link_speed speed;
 728
 729         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 730
 731         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 732
 733         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 734                 /* Set or unset auto-negotiation 10G advertisement */
 735                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 736                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 737                                      &autoneg_reg);
 738
 739                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 740                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 741                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 742
 743                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 744                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 745                                       autoneg_reg);
 746         }
 747
 748         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 749                 /* Set or unset auto-negotiation 1G advertisement */
 750                 hw->phy.ops.read_reg(hw,
 751                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 752                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 753                                      &autoneg_reg);
 754
 755                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 756                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 757                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 758
 759                 hw->phy.ops.write_reg(hw,
 760                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 761                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 762                                       autoneg_reg);
 763         }
 764
 765         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 766                 /* Set or unset auto-negotiation 100M advertisement */
 767                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 768                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 769                                      &autoneg_reg);
 770
 771                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 772                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 773                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 774                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 775
 776                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 777                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 778                                       autoneg_reg);
 779         }
 780
 781         /* Blocked by MNG FW so don't reset PHY */
 782         if (ixgbe_check_reset_blocked(hw))
 783                 return status;
 784
 785         /* Restart PHY auto-negotiation. */
 786         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 787                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 788
 789         autoneg_reg |= IXGBE_MII_RESTART;
 790
 791         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 792                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 793
 794         return status;
 795 }
 796
 797 /**
 798  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 799  *  @hw: pointer to hardware structure
 800  *  @speed: new link speed
 801  **/
 802 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 803                                        ixgbe_link_speed speed,
 804                                        bool autoneg_wait_to_complete)
 805 {
 806         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 807
 808         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 809
 810         /*
 811          * Clear autoneg_advertised and set new values based on input link
 812          * speed.
 813          */
 814         hw->phy.autoneg_advertised = 0;
 815
 816         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 817                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 818
 819         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 820                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 821
 822         if (speed & IXGBE_LINK_SPEED_100_FULL)
 823                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 824
 825         /* Setup link based on the new speed settings */
 826         hw->phy.ops.setup_link(hw);
 827
 828         return IXGBE_SUCCESS;
 829 }
 830
 831 /**
 832  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 833  *  @hw: pointer to hardware structure
 834  *  @speed: pointer to link speed
 835  *  @autoneg: boolean auto-negotiation value
 836  *
 837  *  Determines the link capabilities by reading the AUTOC register.
 838  **/
 839 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 840                                                ixgbe_link_speed *speed,
 841                                                bool *autoneg)
 842 {
 843         s32 status;
 844         u16 speed_ability;
 845
 846         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 847
 848         *speed = 0;
 849         *autoneg = true;
 850
 851         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 852                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 853                                       &speed_ability);
 854
 855         if (status == IXGBE_SUCCESS) {
 856                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 857                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 858                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 859                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 860                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 861                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 862         }
 863
 864         return status;
 865 }
 866
 867 /**
 868  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 869  *  @hw: pointer to hardware structure
 870  *
 871  *  Reads the VS1 register to determine if link is up and the current speed for
 872  *  the PHY.
 873  **/
 874 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 875                              bool *link_up)
 876 {
 877         s32 status = IXGBE_SUCCESS;
 878         u32 time_out;
 879         u32 max_time_out = 10;
 880         u16 phy_link = 0;
 881         u16 phy_speed = 0;
 882         u16 phy_data = 0;
 883
 884         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 885
 886         /* Initialize speed and link to default case */
 887         *link_up = false;
 888         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 889
 890         /*
 891          * Check current speed and link status of the PHY register.
 892          * This is a vendor specific register and may have to
 893          * be changed for other copper PHYs.
 894          */
 895         for (time_out = 0; time_out < max_time_out; time_out++) {
 896                 usec_delay(10);
 897                 status = hw->phy.ops.read_reg(hw,
 898                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 899                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 900                                         &phy_data);
 901                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 902                 phy_speed = phy_data &
 903                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 904                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 905                         *link_up = true;
 906                         if (phy_speed ==
 907                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 908                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 909                         break;
 910                 }
 911         }
 912
 913         return status;
 914 }
 915
 916 /**
 917  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
 918  *      @hw: pointer to hardware structure
 919  *
 920  *      Restart auto-negotiation and PHY and waits for completion.
 921  **/
 922 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 923 {
 924         s32 status = IXGBE_SUCCESS;
 925         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 926         bool autoneg = false;
 927         ixgbe_link_speed speed;
 928
 929         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
 930
 931         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 932
 933         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 934                 /* Set or unset auto-negotiation 10G advertisement */
 935                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 936                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 937                                      &autoneg_reg);
 938
 939                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 940                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 941                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 942
 943                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 944                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 945                                       autoneg_reg);
 946         }
 947
 948         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 949                 /* Set or unset auto-negotiation 1G advertisement */
 950                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 951                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 952                                      &autoneg_reg);
 953
 954                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 955                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 956                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 957
 958                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 959                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 960                                       autoneg_reg);
 961         }
 962
 963         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 964                 /* Set or unset auto-negotiation 100M advertisement */
 965                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 966                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 967                                      &autoneg_reg);
 968
 969                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
 970                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 971                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 972
 973                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 974                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 975                                       autoneg_reg);
 976         }
 977
 978         /* Blocked by MNG FW so don't reset PHY */
 979         if (ixgbe_check_reset_blocked(hw))
 980                 return status;
 981
 982         /* Restart PHY auto-negotiation. */
 983         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 984                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 985
 986         autoneg_reg |= IXGBE_MII_RESTART;
 987
 988         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 989                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 990
 991         return status;
 992 }
 993
 994 /**
 995  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 996  *  @hw: pointer to hardware structure
 997  *  @firmware_version: pointer to the PHY Firmware Version
 998  **/
 999 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1000                                        u16 *firmware_version)
1001 {
1002         s32 status;
1003
1004         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1005
1006         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1007                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1008                                       firmware_version);
1009
1010         return status;
1011 }
1012
1013 /**
1014  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1015  *  @hw: pointer to hardware structure
1016  *  @firmware_version: pointer to the PHY Firmware Version
1017  **/
1018 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1019                                            u16 *firmware_version)
1020 {
1021         s32 status;
1022
1023         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1024
1025         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1026                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1027                                       firmware_version);
1028
1029         return status;
1030 }
1031
1032 /**
1033  *  ixgbe_reset_phy_nl - Performs a PHY reset
1034  *  @hw: pointer to hardware structure
1035  **/
1036 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1037 {
1038         u16 phy_offset, control, eword, edata, block_crc;
1039         bool end_data = false;
1040         u16 list_offset, data_offset;
1041         u16 phy_data = 0;
1042         s32 ret_val = IXGBE_SUCCESS;
1043         u32 i;
1044
1045         DEBUGFUNC("ixgbe_reset_phy_nl");
1046
1047         /* Blocked by MNG FW so bail */
1048         if (ixgbe_check_reset_blocked(hw))
1049                 goto out;
1050
1051         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1052                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1053
1054         /* reset the PHY and poll for completion */
1055         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1056                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
1057                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1058
1059         for (i = 0; i < 100; i++) {
1060                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1061                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1062                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1063                         break;
1064                 msec_delay(10);
1065         }
1066
1067         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1068                 DEBUGOUT("PHY reset did not complete.\n");
1069                 ret_val = IXGBE_ERR_PHY;
1070                 goto out;
1071         }
1072
1073         /* Get init offsets */
1074         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1075                                                       &data_offset);
1076         if (ret_val != IXGBE_SUCCESS)
1077                 goto out;
1078
1079         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1080         data_offset++;
1081         while (!end_data) {
1082                 /*
1083                  * Read control word from PHY init contents offset
1084                  */
1085                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1086                 if (ret_val)
1087                         goto err_eeprom;
1088                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1089                            IXGBE_CONTROL_SHIFT_NL;
1090                 edata = eword & IXGBE_DATA_MASK_NL;
1091                 switch (control) {
1092                 case IXGBE_DELAY_NL:
1093                         data_offset++;
1094                         DEBUGOUT1("DELAY: %d MS\n", edata);
1095                         msec_delay(edata);
1096                         break;
1097                 case IXGBE_DATA_NL:
1098                         DEBUGOUT("DATA:\n");
1099                         data_offset++;
1100                         ret_val = hw->eeprom.ops.read(hw, data_offset,
1101                                                       &phy_offset);
1102                         if (ret_val)
1103                                 goto err_eeprom;
1104                         data_offset++;
1105                         for (i = 0; i < edata; i++) {
1106                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
1107                                                               &eword);
1108                                 if (ret_val)
1109                                         goto err_eeprom;
1110                                 hw->phy.ops.write_reg(hw, phy_offset,
1111                                                       IXGBE_TWINAX_DEV, eword);
1112                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1113                                           phy_offset);
1114                                 data_offset++;
1115                                 phy_offset++;
1116                         }
1117                         break;
1118                 case IXGBE_CONTROL_NL:
1119                         data_offset++;
1120                         DEBUGOUT("CONTROL:\n");
1121                         if (edata == IXGBE_CONTROL_EOL_NL) {
1122                                 DEBUGOUT("EOL\n");
1123                                 end_data = true;
1124                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
1125                                 DEBUGOUT("SOL\n");
1126                         } else {
1127                                 DEBUGOUT("Bad control value\n");
1128                                 ret_val = IXGBE_ERR_PHY;
1129                                 goto out;
1130                         }
1131                         break;
1132                 default:
1133                         DEBUGOUT("Bad control type\n");
1134                         ret_val = IXGBE_ERR_PHY;
1135                         goto out;
1136                 }
1137         }
1138
1139 out:
1140         return ret_val;
1141
1142 err_eeprom:
1143         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1144                       "eeprom read at offset %d failed", data_offset);
1145         return IXGBE_ERR_PHY;
1146 }
1147
1148 /**
1149  *  ixgbe_identify_module_generic - Identifies module type
1150  *  @hw: pointer to hardware structure
1151  *
1152  *  Determines HW type and calls appropriate function.
1153  **/
1154 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1155 {
1156         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1157
1158         DEBUGFUNC("ixgbe_identify_module_generic");
1159
1160         switch (hw->mac.ops.get_media_type(hw)) {
1161         case ixgbe_media_type_fiber:
1162                 status = ixgbe_identify_sfp_module_generic(hw);
1163                 break;
1164
1165         case ixgbe_media_type_fiber_qsfp:
1166                 status = ixgbe_identify_qsfp_module_generic(hw);
1167                 break;
1168
1169         default:
1170                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1171                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1172                 break;
1173         }
1174
1175         return status;
1176 }
1177
1178 /**
1179  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1180  *  @hw: pointer to hardware structure
1181  *
1182  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1183  **/
1184 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1185 {
1186         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1187         u32 vendor_oui = 0;
1188         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1189         u8 identifier = 0;
1190         u8 comp_codes_1g = 0;
1191         u8 comp_codes_10g = 0;
1192         u8 oui_bytes[3] = {0, 0, 0};
1193         u8 cable_tech = 0;
1194         u8 cable_spec = 0;
1195         u16 enforce_sfp = 0;
1196
1197         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1198
1199         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1200                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1201                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1202                 goto out;
1203         }
1204
1205         status = hw->phy.ops.read_i2c_eeprom(hw,
1206                                              IXGBE_SFF_IDENTIFIER,
1207                                              &identifier);
1208
1209         if (status != IXGBE_SUCCESS)
1210                 goto err_read_i2c_eeprom;
1211
1212         /* LAN ID is needed for sfp_type determination */
1213         hw->mac.ops.set_lan_id(hw);
1214
1215         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1216                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1217                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1218         } else {
1219                 status = hw->phy.ops.read_i2c_eeprom(hw,
1220                                                      IXGBE_SFF_1GBE_COMP_CODES,
1221                                                      &comp_codes_1g);
1222
1223                 if (status != IXGBE_SUCCESS)
1224                         goto err_read_i2c_eeprom;
1225
1226                 status = hw->phy.ops.read_i2c_eeprom(hw,
1227                                                      IXGBE_SFF_10GBE_COMP_CODES,
1228                                                      &comp_codes_10g);
1229
1230                 if (status != IXGBE_SUCCESS)
1231                         goto err_read_i2c_eeprom;
1232                 status = hw->phy.ops.read_i2c_eeprom(hw,
1233                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1234                                                      &cable_tech);
1235
1236                 if (status != IXGBE_SUCCESS)
1237                         goto err_read_i2c_eeprom;
1238
1239                  /* ID Module
1240                   * =========
1241                   * 0   SFP_DA_CU
1242                   * 1   SFP_SR
1243                   * 2   SFP_LR
1244                   * 3   SFP_DA_CORE0 - 82599-specific
1245                   * 4   SFP_DA_CORE1 - 82599-specific
1246                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1247                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1248                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1249                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1250                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1251                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1252                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1253                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1254                   */
1255                 if (hw->mac.type == ixgbe_mac_82598EB) {
1256                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1257                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1258                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1259                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1260                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1261                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1262                         else
1263                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1264                 } else {
1265                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1266                                 if (hw->bus.lan_id == 0)
1267                                         hw->phy.sfp_type =
1268                                                      ixgbe_sfp_type_da_cu_core0;
1269                                 else
1270                                         hw->phy.sfp_type =
1271                                                      ixgbe_sfp_type_da_cu_core1;
1272                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1273                                 hw->phy.ops.read_i2c_eeprom(
1274                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1275                                                 &cable_spec);
1276                                 if (cable_spec &
1277                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1278                                         if (hw->bus.lan_id == 0)
1279                                                 hw->phy.sfp_type =
1280                                                 ixgbe_sfp_type_da_act_lmt_core0;
1281                                         else
1282                                                 hw->phy.sfp_type =
1283                                                 ixgbe_sfp_type_da_act_lmt_core1;
1284                                 } else {
1285                                         hw->phy.sfp_type =
1286                                                         ixgbe_sfp_type_unknown;
1287                                 }
1288                         } else if (comp_codes_10g &
1289                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1290                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1291                                 if (hw->bus.lan_id == 0)
1292                                         hw->phy.sfp_type =
1293                                                       ixgbe_sfp_type_srlr_core0;
1294                                 else
1295                                         hw->phy.sfp_type =
1296                                                       ixgbe_sfp_type_srlr_core1;
1297                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1298                                 if (hw->bus.lan_id == 0)
1299                                         hw->phy.sfp_type =
1300                                                 ixgbe_sfp_type_1g_cu_core0;
1301                                 else
1302                                         hw->phy.sfp_type =
1303                                                 ixgbe_sfp_type_1g_cu_core1;
1304                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1305                                 if (hw->bus.lan_id == 0)
1306                                         hw->phy.sfp_type =
1307                                                 ixgbe_sfp_type_1g_sx_core0;
1308                                 else
1309                                         hw->phy.sfp_type =
1310                                                 ixgbe_sfp_type_1g_sx_core1;
1311                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1312                                 if (hw->bus.lan_id == 0)
1313                                         hw->phy.sfp_type =
1314                                                 ixgbe_sfp_type_1g_lx_core0;
1315                                 else
1316                                         hw->phy.sfp_type =
1317                                                 ixgbe_sfp_type_1g_lx_core1;
1318                         } else {
1319                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1320                         }
1321                 }
1322
1323                 if (hw->phy.sfp_type != stored_sfp_type)
1324                         hw->phy.sfp_setup_needed = true;
1325
1326                 /* Determine if the SFP+ PHY is dual speed or not. */
1327                 hw->phy.multispeed_fiber = false;
1328                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1329                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1330                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1331                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1332                         hw->phy.multispeed_fiber = true;
1333
1334                 /* Determine PHY vendor */
1335                 if (hw->phy.type != ixgbe_phy_nl) {
1336                         hw->phy.id = identifier;
1337                         status = hw->phy.ops.read_i2c_eeprom(hw,
1338                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1339                                                     &oui_bytes[0]);
1340
1341                         if (status != IXGBE_SUCCESS)
1342                                 goto err_read_i2c_eeprom;
1343
1344                         status = hw->phy.ops.read_i2c_eeprom(hw,
1345                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1346                                                     &oui_bytes[1]);
1347
1348                         if (status != IXGBE_SUCCESS)
1349                                 goto err_read_i2c_eeprom;
1350
1351                         status = hw->phy.ops.read_i2c_eeprom(hw,
1352                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1353                                                     &oui_bytes[2]);
1354
1355                         if (status != IXGBE_SUCCESS)
1356                                 goto err_read_i2c_eeprom;
1357
1358                         vendor_oui =
1359                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1360                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1361                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1362
1363                         switch (vendor_oui) {
1364                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1365                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1366                                         hw->phy.type =
1367                                                     ixgbe_phy_sfp_passive_tyco;
1368                                 break;
1369                         case IXGBE_SFF_VENDOR_OUI_FTL:
1370                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1371                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1372                                 else
1373                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1374                                 break;
1375                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1376                                 hw->phy.type = ixgbe_phy_sfp_avago;
1377                                 break;
1378                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1379                                 hw->phy.type = ixgbe_phy_sfp_intel;
1380                                 break;
1381                         default:
1382                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1383                                         hw->phy.type =
1384                                                  ixgbe_phy_sfp_passive_unknown;
1385                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1386                                         hw->phy.type =
1387                                                 ixgbe_phy_sfp_active_unknown;
1388                                 else
1389                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1390                                 break;
1391                         }
1392                 }
1393
1394                 /* Allow any DA cable vendor */
1395                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1396                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1397                         status = IXGBE_SUCCESS;
1398                         goto out;
1399                 }
1400
1401                 /* Verify supported 1G SFP modules */
1402                 if (comp_codes_10g == 0 &&
1403                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1404                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1405                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1406                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1407                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1408                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1409                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1410                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1411                         goto out;
1412                 }
1413
1414                 /* Anything else 82598-based is supported */
1415                 if (hw->mac.type == ixgbe_mac_82598EB) {
1416                         status = IXGBE_SUCCESS;
1417                         goto out;
1418                 }
1419
1420                 ixgbe_get_device_caps(hw, &enforce_sfp);
1421                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1422                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1423                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1424                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1425                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1426                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1427                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1428                         /* Make sure we're a supported PHY type */
1429                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1430                                 status = IXGBE_SUCCESS;
1431                         } else {
1432                                 if (hw->allow_unsupported_sfp == true) {
1433                                         EWARN(hw, "WARNING: Intel (R) Network "
1434                                               "Connections are quality tested "
1435                                               "using Intel (R) Ethernet Optics."
1436                                               " Using untested modules is not "
1437                                               "supported and may cause unstable"
1438                                               " operation or damage to the "
1439                                               "module or the adapter. Intel "
1440                                               "Corporation is not responsible "
1441                                               "for any harm caused by using "
1442                                               "untested modules.\n", status);
1443                                         status = IXGBE_SUCCESS;
1444                                 } else {
1445                                         DEBUGOUT("SFP+ module not supported\n");
1446                                         hw->phy.type =
1447                                                 ixgbe_phy_sfp_unsupported;
1448                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1449                                 }
1450                         }
1451                 } else {
1452                         status = IXGBE_SUCCESS;
1453                 }
1454         }
1455
1456 out:
1457         return status;
1458
1459 err_read_i2c_eeprom:
1460         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1461         if (hw->phy.type != ixgbe_phy_nl) {
1462                 hw->phy.id = 0;
1463                 hw->phy.type = ixgbe_phy_unknown;
1464         }
1465         return IXGBE_ERR_SFP_NOT_PRESENT;
1466 }
1467
1468 /**
1469  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1470  *  @hw: pointer to hardware structure
1471  *
1472  *  Determines physical layer capabilities of the current SFP.
1473  */
1474 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1475 {
1476         u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1477         u8 comp_codes_10g = 0;
1478         u8 comp_codes_1g = 0;
1479
1480         DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1481
1482         hw->phy.ops.identify_sfp(hw);
1483         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1484                 return physical_layer;
1485
1486         switch (hw->phy.type) {
1487         case ixgbe_phy_sfp_passive_tyco:
1488         case ixgbe_phy_sfp_passive_unknown:
1489         case ixgbe_phy_qsfp_passive_unknown:
1490                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1491                 break;
1492         case ixgbe_phy_sfp_ftl_active:
1493         case ixgbe_phy_sfp_active_unknown:
1494         case ixgbe_phy_qsfp_active_unknown:
1495                 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1496                 break;
1497         case ixgbe_phy_sfp_avago:
1498         case ixgbe_phy_sfp_ftl:
1499         case ixgbe_phy_sfp_intel:
1500         case ixgbe_phy_sfp_unknown:
1501                 hw->phy.ops.read_i2c_eeprom(hw,
1502                       IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1503                 hw->phy.ops.read_i2c_eeprom(hw,
1504                       IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1505                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1506                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1507                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1508                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1509                 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1510                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1511                 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1512                         physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1513                 break;
1514         case ixgbe_phy_qsfp_intel:
1515         case ixgbe_phy_qsfp_unknown:
1516                 hw->phy.ops.read_i2c_eeprom(hw,
1517                       IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1518                 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1519                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1520                 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1521                         physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1522                 break;
1523         default:
1524                 break;
1525         }
1526
1527         return physical_layer;
1528 }
1529
1530 /**
1531  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1532  *  @hw: pointer to hardware structure
1533  *
1534  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1535  **/
1536 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1537 {
1538         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1539         u32 vendor_oui = 0;
1540         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1541         u8 identifier = 0;
1542         u8 comp_codes_1g = 0;
1543         u8 comp_codes_10g = 0;
1544         u8 oui_bytes[3] = {0, 0, 0};
1545         u16 enforce_sfp = 0;
1546         u8 connector = 0;
1547         u8 cable_length = 0;
1548         u8 device_tech = 0;
1549         bool active_cable = false;
1550
1551         DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1552
1553         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1554                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1555                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1556                 goto out;
1557         }
1558
1559         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1560                                              &identifier);
1561
1562         if (status != IXGBE_SUCCESS)
1563                 goto err_read_i2c_eeprom;
1564
1565         if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1566                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1567                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1568                 goto out;
1569         }
1570
1571         hw->phy.id = identifier;
1572
1573         /* LAN ID is needed for sfp_type determination */
1574         hw->mac.ops.set_lan_id(hw);
1575
1576         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1577                                              &comp_codes_10g);
1578
1579         if (status != IXGBE_SUCCESS)
1580                 goto err_read_i2c_eeprom;
1581
1582         status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1583                                              &comp_codes_1g);
1584
1585         if (status != IXGBE_SUCCESS)
1586                 goto err_read_i2c_eeprom;
1587
1588         if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1589                 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1590                 if (hw->bus.lan_id == 0)
1591                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1592                 else
1593                         hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1594         } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1595                                      IXGBE_SFF_10GBASELR_CAPABLE)) {
1596                 if (hw->bus.lan_id == 0)
1597                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1598                 else
1599                         hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1600         } else {
1601                 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1602                         active_cable = true;
1603
1604                 if (!active_cable) {
1605                         /* check for active DA cables that pre-date
1606                          * SFF-8436 v3.6 */
1607                         hw->phy.ops.read_i2c_eeprom(hw,
1608                                         IXGBE_SFF_QSFP_CONNECTOR,
1609                                         &connector);
1610
1611                         hw->phy.ops.read_i2c_eeprom(hw,
1612                                         IXGBE_SFF_QSFP_CABLE_LENGTH,
1613                                         &cable_length);
1614
1615                         hw->phy.ops.read_i2c_eeprom(hw,
1616                                         IXGBE_SFF_QSFP_DEVICE_TECH,
1617                                         &device_tech);
1618
1619                         if ((connector ==
1620                                      IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1621                             (cable_length > 0) &&
1622                             ((device_tech >> 4) ==
1623                                      IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1624                                 active_cable = true;
1625                 }
1626
1627                 if (active_cable) {
1628                         hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1629                         if (hw->bus.lan_id == 0)
1630                                 hw->phy.sfp_type =
1631                                                 ixgbe_sfp_type_da_act_lmt_core0;
1632                         else
1633                                 hw->phy.sfp_type =
1634                                                 ixgbe_sfp_type_da_act_lmt_core1;
1635                 } else {
1636                         /* unsupported module type */
1637                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1638                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1639                         goto out;
1640                 }
1641         }
1642
1643         if (hw->phy.sfp_type != stored_sfp_type)
1644                 hw->phy.sfp_setup_needed = true;
1645
1646         /* Determine if the QSFP+ PHY is dual speed or not. */
1647         hw->phy.multispeed_fiber = false;
1648         if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1649            (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1650            ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1651            (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1652                 hw->phy.multispeed_fiber = true;
1653
1654         /* Determine PHY vendor for optical modules */
1655         if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1656                               IXGBE_SFF_10GBASELR_CAPABLE))  {
1657                 status = hw->phy.ops.read_i2c_eeprom(hw,
1658                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1659                                             &oui_bytes[0]);
1660
1661                 if (status != IXGBE_SUCCESS)
1662                         goto err_read_i2c_eeprom;
1663
1664                 status = hw->phy.ops.read_i2c_eeprom(hw,
1665                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1666                                             &oui_bytes[1]);
1667
1668                 if (status != IXGBE_SUCCESS)
1669                         goto err_read_i2c_eeprom;
1670
1671                 status = hw->phy.ops.read_i2c_eeprom(hw,
1672                                             IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1673                                             &oui_bytes[2]);
1674
1675                 if (status != IXGBE_SUCCESS)
1676                         goto err_read_i2c_eeprom;
1677
1678                 vendor_oui =
1679                   ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1680                    (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1681                    (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1682
1683                 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1684                         hw->phy.type = ixgbe_phy_qsfp_intel;
1685                 else
1686                         hw->phy.type = ixgbe_phy_qsfp_unknown;
1687
1688                 ixgbe_get_device_caps(hw, &enforce_sfp);
1689                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1690                         /* Make sure we're a supported PHY type */
1691                         if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1692                                 status = IXGBE_SUCCESS;
1693                         } else {
1694                                 if (hw->allow_unsupported_sfp == true) {
1695                                         EWARN(hw, "WARNING: Intel (R) Network "
1696                                               "Connections are quality tested "
1697                                               "using Intel (R) Ethernet Optics."
1698                                               " Using untested modules is not "
1699                                               "supported and may cause unstable"
1700                                               " operation or damage to the "
1701                                               "module or the adapter. Intel "
1702                                               "Corporation is not responsible "
1703                                               "for any harm caused by using "
1704                                               "untested modules.\n", status);
1705                                         status = IXGBE_SUCCESS;
1706                                 } else {
1707                                         DEBUGOUT("QSFP module not supported\n");
1708                                         hw->phy.type =
1709                                                 ixgbe_phy_sfp_unsupported;
1710                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1711                                 }
1712                         }
1713                 } else {
1714                         status = IXGBE_SUCCESS;
1715                 }
1716         }
1717
1718 out:
1719         return status;
1720
1721 err_read_i2c_eeprom:
1722         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1723         hw->phy.id = 0;
1724         hw->phy.type = ixgbe_phy_unknown;
1725
1726         return IXGBE_ERR_SFP_NOT_PRESENT;
1727 }
1728
1729
1730 /**
1731  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1732  *  @hw: pointer to hardware structure
1733  *  @list_offset: offset to the SFP ID list
1734  *  @data_offset: offset to the SFP data block
1735  *
1736  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1737  *  so it returns the offsets to the phy init sequence block.
1738  **/
1739 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1740                                         u16 *list_offset,
1741                                         u16 *data_offset)
1742 {
1743         u16 sfp_id;
1744         u16 sfp_type = hw->phy.sfp_type;
1745
1746         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1747
1748         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1749                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1750
1751         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1752                 return IXGBE_ERR_SFP_NOT_PRESENT;
1753
1754         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1755             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1756                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1757
1758         /*
1759          * Limiting active cables and 1G Phys must be initialized as
1760          * SR modules
1761          */
1762         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1763             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1764             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1765             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1766                 sfp_type = ixgbe_sfp_type_srlr_core0;
1767         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1768                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1769                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1770                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1771                 sfp_type = ixgbe_sfp_type_srlr_core1;
1772
1773         /* Read offset to PHY init contents */
1774         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1775                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1776                               "eeprom read at offset %d failed",
1777                               IXGBE_PHY_INIT_OFFSET_NL);
1778                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1779         }
1780
1781         if ((!*list_offset) || (*list_offset == 0xFFFF))
1782                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1783
1784         /* Shift offset to first ID word */
1785         (*list_offset)++;
1786
1787         /*
1788          * Find the matching SFP ID in the EEPROM
1789          * and program the init sequence
1790          */
1791         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1792                 goto err_phy;
1793
1794         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1795                 if (sfp_id == sfp_type) {
1796                         (*list_offset)++;
1797                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1798                                 goto err_phy;
1799                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1800                                 DEBUGOUT("SFP+ module not supported\n");
1801                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1802                         } else {
1803                                 break;
1804                         }
1805                 } else {
1806                         (*list_offset) += 2;
1807                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1808                                 goto err_phy;
1809                 }
1810         }
1811
1812         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1813                 DEBUGOUT("No matching SFP+ module found\n");
1814                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1815         }
1816
1817         return IXGBE_SUCCESS;
1818
1819 err_phy:
1820         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1821                       "eeprom read at offset %d failed", *list_offset);
1822         return IXGBE_ERR_PHY;
1823 }
1824
1825 /**
1826  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1827  *  @hw: pointer to hardware structure
1828  *  @byte_offset: EEPROM byte offset to read
1829  *  @eeprom_data: value read
1830  *
1831  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1832  **/
1833 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1834                                   u8 *eeprom_data)
1835 {
1836         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1837
1838         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1839                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1840                                          eeprom_data);
1841 }
1842
1843 /**
1844  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1845  *  @hw: pointer to hardware structure
1846  *  @byte_offset: byte offset at address 0xA2
1847  *  @eeprom_data: value read
1848  *
1849  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1850  **/
1851 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1852                                           u8 *sff8472_data)
1853 {
1854         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1855                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1856                                          sff8472_data);
1857 }
1858
1859 /**
1860  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1861  *  @hw: pointer to hardware structure
1862  *  @byte_offset: EEPROM byte offset to write
1863  *  @eeprom_data: value to write
1864  *
1865  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1866  **/
1867 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1868                                    u8 eeprom_data)
1869 {
1870         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1871
1872         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1873                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1874                                           eeprom_data);
1875 }
1876
1877 /**
1878  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1879  *  @hw: pointer to hardware structure
1880  *  @byte_offset: byte offset to read
1881  *  @data: value read
1882  *
1883  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1884  *  a specified device address.
1885  **/
1886 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1887                                 u8 dev_addr, u8 *data)
1888 {
1889         s32 status;
1890         u32 max_retry = 10;
1891         u32 retry = 0;
1892         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1893         bool nack = 1;
1894         *data = 0;
1895
1896         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1897
1898         do {
1899                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1900                         return IXGBE_ERR_SWFW_SYNC;
1901
1902                 ixgbe_i2c_start(hw);
1903
1904                 /* Device Address and write indication */
1905                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1906                 if (status != IXGBE_SUCCESS)
1907                         goto fail;
1908
1909                 status = ixgbe_get_i2c_ack(hw);
1910                 if (status != IXGBE_SUCCESS)
1911                         goto fail;
1912
1913                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1914                 if (status != IXGBE_SUCCESS)
1915                         goto fail;
1916
1917                 status = ixgbe_get_i2c_ack(hw);
1918                 if (status != IXGBE_SUCCESS)
1919                         goto fail;
1920
1921                 ixgbe_i2c_start(hw);
1922
1923                 /* Device Address and read indication */
1924                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1925                 if (status != IXGBE_SUCCESS)
1926                         goto fail;
1927
1928                 status = ixgbe_get_i2c_ack(hw);
1929                 if (status != IXGBE_SUCCESS)
1930                         goto fail;
1931
1932                 status = ixgbe_clock_in_i2c_byte(hw, data);
1933                 if (status != IXGBE_SUCCESS)
1934                         goto fail;
1935
1936                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1937                 if (status != IXGBE_SUCCESS)
1938                         goto fail;
1939
1940                 ixgbe_i2c_stop(hw);
1941                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1942                 return IXGBE_SUCCESS;
1943
1944 fail:
1945                 ixgbe_i2c_bus_clear(hw);
1946                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1947                 msec_delay(100);
1948                 retry++;
1949                 if (retry < max_retry)
1950                         DEBUGOUT("I2C byte read error - Retrying.\n");
1951                 else
1952                         DEBUGOUT("I2C byte read error.\n");
1953
1954         } while (retry < max_retry);
1955
1956         return status;
1957 }
1958
1959 /**
1960  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1961  *  @hw: pointer to hardware structure
1962  *  @byte_offset: byte offset to write
1963  *  @data: value to write
1964  *
1965  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1966  *  a specified device address.
1967  **/
1968 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1969                                  u8 dev_addr, u8 data)
1970 {
1971         s32 status = IXGBE_SUCCESS;
1972         u32 max_retry = 1;
1973         u32 retry = 0;
1974         u32 swfw_mask = hw->phy.phy_semaphore_mask;
1975
1976         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1977
1978         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1979                 status = IXGBE_ERR_SWFW_SYNC;
1980                 goto write_byte_out;
1981         }
1982
1983         do {
1984                 ixgbe_i2c_start(hw);
1985
1986                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1987                 if (status != IXGBE_SUCCESS)
1988                         goto fail;
1989
1990                 status = ixgbe_get_i2c_ack(hw);
1991                 if (status != IXGBE_SUCCESS)
1992                         goto fail;
1993
1994                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1995                 if (status != IXGBE_SUCCESS)
1996                         goto fail;
1997
1998                 status = ixgbe_get_i2c_ack(hw);
1999                 if (status != IXGBE_SUCCESS)
2000                         goto fail;
2001
2002                 status = ixgbe_clock_out_i2c_byte(hw, data);
2003                 if (status != IXGBE_SUCCESS)
2004                         goto fail;
2005
2006                 status = ixgbe_get_i2c_ack(hw);
2007                 if (status != IXGBE_SUCCESS)
2008                         goto fail;
2009
2010                 ixgbe_i2c_stop(hw);
2011                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2012                 return IXGBE_SUCCESS;
2013
2014 fail:
2015                 ixgbe_i2c_bus_clear(hw);
2016                 retry++;
2017                 if (retry < max_retry)
2018                         DEBUGOUT("I2C byte write error - Retrying.\n");
2019                 else
2020                         DEBUGOUT("I2C byte write error.\n");
2021         } while (retry < max_retry);
2022
2023         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2024
2025 write_byte_out:
2026         return status;
2027 }
2028
2029 /**
2030  *  ixgbe_i2c_start - Sets I2C start condition
2031  *  @hw: pointer to hardware structure
2032  *
2033  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2034  **/
2035 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2036 {
2037         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2038
2039         DEBUGFUNC("ixgbe_i2c_start");
2040
2041         /* Start condition must begin with data and clock high */
2042         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2043         ixgbe_raise_i2c_clk(hw, &i2cctl);
2044
2045         /* Setup time for start condition (4.7us) */
2046         usec_delay(IXGBE_I2C_T_SU_STA);
2047
2048         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2049
2050         /* Hold time for start condition (4us) */
2051         usec_delay(IXGBE_I2C_T_HD_STA);
2052
2053         ixgbe_lower_i2c_clk(hw, &i2cctl);
2054
2055         /* Minimum low period of clock is 4.7 us */
2056         usec_delay(IXGBE_I2C_T_LOW);
2057
2058 }
2059
2060 /**
2061  *  ixgbe_i2c_stop - Sets I2C stop condition
2062  *  @hw: pointer to hardware structure
2063  *
2064  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2065  **/
2066 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2067 {
2068         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2069
2070         DEBUGFUNC("ixgbe_i2c_stop");
2071
2072         /* Stop condition must begin with data low and clock high */
2073         ixgbe_set_i2c_data(hw, &i2cctl, 0);
2074         ixgbe_raise_i2c_clk(hw, &i2cctl);
2075
2076         /* Setup time for stop condition (4us) */
2077         usec_delay(IXGBE_I2C_T_SU_STO);
2078
2079         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2080
2081         /* bus free time between stop and start (4.7us)*/
2082         usec_delay(IXGBE_I2C_T_BUF);
2083 }
2084
2085 /**
2086  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2087  *  @hw: pointer to hardware structure
2088  *  @data: data byte to clock in
2089  *
2090  *  Clocks in one byte data via I2C data/clock
2091  **/
2092 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2093 {
2094         s32 i;
2095         bool bit = 0;
2096
2097         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2098
2099         for (i = 7; i >= 0; i--) {
2100                 ixgbe_clock_in_i2c_bit(hw, &bit);
2101                 *data |= bit << i;
2102         }
2103
2104         return IXGBE_SUCCESS;
2105 }
2106
2107 /**
2108  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2109  *  @hw: pointer to hardware structure
2110  *  @data: data byte clocked out
2111  *
2112  *  Clocks out one byte data via I2C data/clock
2113  **/
2114 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2115 {
2116         s32 status = IXGBE_SUCCESS;
2117         s32 i;
2118         u32 i2cctl;
2119         bool bit;
2120
2121         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2122
2123         for (i = 7; i >= 0; i--) {
2124                 bit = (data >> i) & 0x1;
2125                 status = ixgbe_clock_out_i2c_bit(hw, bit);
2126
2127                 if (status != IXGBE_SUCCESS)
2128                         break;
2129         }
2130
2131         /* Release SDA line (set high) */
2132         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2133         i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2134         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2135         IXGBE_WRITE_FLUSH(hw);
2136
2137         return status;
2138 }
2139
2140 /**
2141  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2142  *  @hw: pointer to hardware structure
2143  *
2144  *  Clocks in/out one bit via I2C data/clock
2145  **/
2146 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2147 {
2148         s32 status = IXGBE_SUCCESS;
2149         u32 i = 0;
2150         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2151         u32 timeout = 10;
2152         bool ack = 1;
2153
2154         DEBUGFUNC("ixgbe_get_i2c_ack");
2155
2156         ixgbe_raise_i2c_clk(hw, &i2cctl);
2157
2158
2159         /* Minimum high period of clock is 4us */
2160         usec_delay(IXGBE_I2C_T_HIGH);
2161
2162         /* Poll for ACK.  Note that ACK in I2C spec is
2163          * transition from 1 to 0 */
2164         for (i = 0; i < timeout; i++) {
2165                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2166                 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2167
2168                 usec_delay(1);
2169                 if (!ack)
2170                         break;
2171         }
2172
2173         if (ack) {
2174                 DEBUGOUT("I2C ack was not received.\n");
2175                 status = IXGBE_ERR_I2C;
2176         }
2177
2178         ixgbe_lower_i2c_clk(hw, &i2cctl);
2179
2180         /* Minimum low period of clock is 4.7 us */
2181         usec_delay(IXGBE_I2C_T_LOW);
2182
2183         return status;
2184 }
2185
2186 /**
2187  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2188  *  @hw: pointer to hardware structure
2189  *  @data: read data value
2190  *
2191  *  Clocks in one bit via I2C data/clock
2192  **/
2193 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2194 {
2195         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2196
2197         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2198
2199         ixgbe_raise_i2c_clk(hw, &i2cctl);
2200
2201         /* Minimum high period of clock is 4us */
2202         usec_delay(IXGBE_I2C_T_HIGH);
2203
2204         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2205         *data = ixgbe_get_i2c_data(hw, &i2cctl);
2206
2207         ixgbe_lower_i2c_clk(hw, &i2cctl);
2208
2209         /* Minimum low period of clock is 4.7 us */
2210         usec_delay(IXGBE_I2C_T_LOW);
2211
2212         return IXGBE_SUCCESS;
2213 }
2214
2215 /**
2216  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2217  *  @hw: pointer to hardware structure
2218  *  @data: data value to write
2219  *
2220  *  Clocks out one bit via I2C data/clock
2221  **/
2222 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2223 {
2224         s32 status;
2225         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2226
2227         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2228
2229         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2230         if (status == IXGBE_SUCCESS) {
2231                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2232
2233                 /* Minimum high period of clock is 4us */
2234                 usec_delay(IXGBE_I2C_T_HIGH);
2235
2236                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2237
2238                 /* Minimum low period of clock is 4.7 us.
2239                  * This also takes care of the data hold time.
2240                  */
2241                 usec_delay(IXGBE_I2C_T_LOW);
2242         } else {
2243                 status = IXGBE_ERR_I2C;
2244                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2245                              "I2C data was not set to %X\n", data);
2246         }
2247
2248         return status;
2249 }
2250
2251 /**
2252  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2253  *  @hw: pointer to hardware structure
2254  *  @i2cctl: Current value of I2CCTL register
2255  *
2256  *  Raises the I2C clock line '0'->'1'
2257  **/
2258 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2259 {
2260         u32 i = 0;
2261         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2262         u32 i2cctl_r = 0;
2263
2264         DEBUGFUNC("ixgbe_raise_i2c_clk");
2265
2266         for (i = 0; i < timeout; i++) {
2267                 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2268
2269                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2270                 IXGBE_WRITE_FLUSH(hw);
2271                 /* SCL rise time (1000ns) */
2272                 usec_delay(IXGBE_I2C_T_RISE);
2273
2274                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2275                 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2276                         break;
2277         }
2278 }
2279
2280 /**
2281  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2282  *  @hw: pointer to hardware structure
2283  *  @i2cctl: Current value of I2CCTL register
2284  *
2285  *  Lowers the I2C clock line '1'->'0'
2286  **/
2287 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2288 {
2289
2290         DEBUGFUNC("ixgbe_lower_i2c_clk");
2291
2292         *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2293
2294         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2295         IXGBE_WRITE_FLUSH(hw);
2296
2297         /* SCL fall time (300ns) */
2298         usec_delay(IXGBE_I2C_T_FALL);
2299 }
2300
2301 /**
2302  *  ixgbe_set_i2c_data - Sets the I2C data bit
2303  *  @hw: pointer to hardware structure
2304  *  @i2cctl: Current value of I2CCTL register
2305  *  @data: I2C data value (0 or 1) to set
2306  *
2307  *  Sets the I2C data bit
2308  **/
2309 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2310 {
2311         s32 status = IXGBE_SUCCESS;
2312
2313         DEBUGFUNC("ixgbe_set_i2c_data");
2314
2315         if (data)
2316                 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2317         else
2318                 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2319
2320         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2321         IXGBE_WRITE_FLUSH(hw);
2322
2323         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2324         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2325
2326         /* Verify data was set correctly */
2327         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2328         if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2329                 status = IXGBE_ERR_I2C;
2330                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2331                              "Error - I2C data was not set to %X.\n",
2332                              data);
2333         }
2334
2335         return status;
2336 }
2337
2338 /**
2339  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2340  *  @hw: pointer to hardware structure
2341  *  @i2cctl: Current value of I2CCTL register
2342  *
2343  *  Returns the I2C data bit value
2344  **/
2345 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2346 {
2347         bool data;
2348         UNREFERENCED_1PARAMETER(hw);
2349
2350         DEBUGFUNC("ixgbe_get_i2c_data");
2351
2352         if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2353                 data = 1;
2354         else
2355                 data = 0;
2356
2357         return data;
2358 }
2359
2360 /**
2361  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2362  *  @hw: pointer to hardware structure
2363  *
2364  *  Clears the I2C bus by sending nine clock pulses.
2365  *  Used when data line is stuck low.
2366  **/
2367 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2368 {
2369         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2370         u32 i;
2371
2372         DEBUGFUNC("ixgbe_i2c_bus_clear");
2373
2374         ixgbe_i2c_start(hw);
2375
2376         ixgbe_set_i2c_data(hw, &i2cctl, 1);
2377
2378         for (i = 0; i < 9; i++) {
2379                 ixgbe_raise_i2c_clk(hw, &i2cctl);
2380
2381                 /* Min high period of clock is 4us */
2382                 usec_delay(IXGBE_I2C_T_HIGH);
2383
2384                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2385
2386                 /* Min low period of clock is 4.7us*/
2387                 usec_delay(IXGBE_I2C_T_LOW);
2388         }
2389
2390         ixgbe_i2c_start(hw);
2391
2392         /* Put the i2c bus back to default state */
2393         ixgbe_i2c_stop(hw);
2394 }
2395
2396 /**
2397  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2398  *  @hw: pointer to hardware structure
2399  *
2400  *  Checks if the LASI temp alarm status was triggered due to overtemp
2401  **/
2402 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2403 {
2404         s32 status = IXGBE_SUCCESS;
2405         u16 phy_data = 0;
2406
2407         DEBUGFUNC("ixgbe_tn_check_overtemp");
2408
2409         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2410                 goto out;
2411
2412         /* Check that the LASI temp alarm status was triggered */
2413         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2414                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2415
2416         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2417                 goto out;
2418
2419         status = IXGBE_ERR_OVERTEMP;
2420         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2421 out:
2422         return status;
2423 }