lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37 #ident "$Id: ixgbe_phy.c,v 1.139 2012/05/24 23:36:12 jtkirshe Exp $"
  38
  39 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  40 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  41 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  42 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  43 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  44 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  45 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  46 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  48 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  49 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl);
  50
  51 /**
  52  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
  53  *  @hw: pointer to the hardware structure
  54  *
  55  *  Initialize the function pointers.
  56  **/
  57 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
  58 {
  59         struct ixgbe_phy_info *phy = &hw->phy;
  60
  61         DEBUGFUNC("ixgbe_init_phy_ops_generic");
  62
  63         /* PHY */
  64         phy->ops.identify = &ixgbe_identify_phy_generic;
  65         phy->ops.reset = &ixgbe_reset_phy_generic;
  66         phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
  67         phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
  68         phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
  69         phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
  70         phy->ops.check_link = NULL;
  71         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
  72         phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
  73         phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
  74         phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
  75         phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
  76         phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
  77         phy->ops.identify_sfp = &ixgbe_identify_module_generic;
  78         phy->sfp_type = ixgbe_sfp_type_unknown;
  79         phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
  80         return IXGBE_SUCCESS;
  81 }
  82
  83 /**
  84  *  ixgbe_identify_phy_generic - Get physical layer module
  85  *  @hw: pointer to hardware structure
  86  *
  87  *  Determines the physical layer module found on the current adapter.
  88  **/
  89 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  90 {
  91         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  92         u32 phy_addr;
  93         u16 ext_ability = 0;
  94
  95         DEBUGFUNC("ixgbe_identify_phy_generic");
  96
  97         if (hw->phy.type == ixgbe_phy_unknown) {
  98                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
  99                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 100                                 hw->phy.addr = phy_addr;
 101                                 ixgbe_get_phy_id(hw);
 102                                 hw->phy.type =
 103                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 104
 105                                 if (hw->phy.type == ixgbe_phy_unknown) {
 106                                         hw->phy.ops.read_reg(hw,
 107                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 108                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 109                                                   &ext_ability);
 110                                         if (ext_ability &
 111                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 112                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 113                                                 hw->phy.type =
 114                                                          ixgbe_phy_cu_unknown;
 115                                         else
 116                                                 hw->phy.type =
 117                                                          ixgbe_phy_generic;
 118                                 }
 119
 120                                 status = IXGBE_SUCCESS;
 121                                 break;
 122                         }
 123                 }
 124
 125                 /* Certain media types do not have a phy so an address will not
 126                  * be found and the code will take this path.  Caller has to
 127                  * decide if it is an error or not.
 128                  */
 129                 if (status != IXGBE_SUCCESS) {
 130                         hw->phy.addr = 0;
 131                 }
 132         } else {
 133                 status = IXGBE_SUCCESS;
 134         }
 135
 136         return status;
 137 }
 138
 139 /**
 140  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 141  * @hw: pointer to the hardware structure
 142  *
 143  * This function checks the MMNGC.MNG_VETO bit to see if there are
 144  * any constraints on link from manageability.  For MAC's that don't
 145  * have this bit just return faluse since the link can not be blocked
 146  * via this method.
 147  **/
 148 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 149 {
 150         u32 mmngc;
 151
 152         DEBUGFUNC("ixgbe_check_reset_blocked");
 153
 154         /* If we don't have this bit, it can't be blocking */
 155         if (hw->mac.type == ixgbe_mac_82598EB)
 156                 return false;
 157
 158         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 159         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 160                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 161                               "MNG_VETO bit detected.\n");
 162                 return true;
 163         }
 164
 165         return false;
 166 }
 167
 168 /**
 169  *  ixgbe_validate_phy_addr - Determines phy address is valid
 170  *  @hw: pointer to hardware structure
 171  *
 172  **/
 173 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 174 {
 175         u16 phy_id = 0;
 176         bool valid = false;
 177
 178         DEBUGFUNC("ixgbe_validate_phy_addr");
 179
 180         hw->phy.addr = phy_addr;
 181         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 182                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 183
 184         if (phy_id != 0xFFFF && phy_id != 0x0)
 185                 valid = true;
 186
 187         return valid;
 188 }
 189
 190 /**
 191  *  ixgbe_get_phy_id - Get the phy type
 192  *  @hw: pointer to hardware structure
 193  *
 194  **/
 195 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 196 {
 197         u32 status;
 198         u16 phy_id_high = 0;
 199         u16 phy_id_low = 0;
 200
 201         DEBUGFUNC("ixgbe_get_phy_id");
 202
 203         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 204                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 205                                       &phy_id_high);
 206
 207         if (status == IXGBE_SUCCESS) {
 208                 hw->phy.id = (u32)(phy_id_high << 16);
 209                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 210                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 211                                               &phy_id_low);
 212                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 213                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 214         }
 215         return status;
 216 }
 217
 218 /**
 219  *  ixgbe_get_phy_type_from_id - Get the phy type
 220  *  @hw: pointer to hardware structure
 221  *
 222  **/
 223 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 224 {
 225         enum ixgbe_phy_type phy_type;
 226
 227         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 228
 229         switch (phy_id) {
 230         case TN1010_PHY_ID:
 231                 phy_type = ixgbe_phy_tn;
 232                 break;
 233         case X540_PHY_ID:
 234                 phy_type = ixgbe_phy_aq;
 235                 break;
 236         case QT2022_PHY_ID:
 237                 phy_type = ixgbe_phy_qt;
 238                 break;
 239         case ATH_PHY_ID:
 240                 phy_type = ixgbe_phy_nl;
 241                 break;
 242         default:
 243                 phy_type = ixgbe_phy_unknown;
 244                 break;
 245         }
 246
 247         DEBUGOUT1("phy type found is %d\n", phy_type);
 248         return phy_type;
 249 }
 250
 251 /**
 252  *  ixgbe_reset_phy_generic - Performs a PHY reset
 253  *  @hw: pointer to hardware structure
 254  **/
 255 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 256 {
 257         u32 i;
 258         u16 ctrl = 0;
 259         s32 status = IXGBE_SUCCESS;
 260
 261         DEBUGFUNC("ixgbe_reset_phy_generic");
 262
 263         if (hw->phy.type == ixgbe_phy_unknown)
 264                 status = ixgbe_identify_phy_generic(hw);
 265
 266         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 267                 goto out;
 268
 269         /* Don't reset PHY if it's shut down due to overtemp. */
 270         if (!hw->phy.reset_if_overtemp &&
 271             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 272                 goto out;
 273
 274         /* Blocked by MNG FW so bail */
 275         if (ixgbe_check_reset_blocked(hw))
 276                 goto out;
 277
 278         /*
 279          * Perform soft PHY reset to the PHY_XS.
 280          * This will cause a soft reset to the PHY
 281          */
 282         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 283                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 284                               IXGBE_MDIO_PHY_XS_RESET);
 285
 286         /*
 287          * Poll for reset bit to self-clear indicating reset is complete.
 288          * Some PHYs could take up to 3 seconds to complete and need about
 289          * 1.7 usec delay after the reset is complete.
 290          */
 291         for (i = 0; i < 30; i++) {
 292                 msec_delay(100);
 293                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 294                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 295                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 296                         usec_delay(2);
 297                         break;
 298                 }
 299         }
 300
 301         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 302                 status = IXGBE_ERR_RESET_FAILED;
 303                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 304                              "PHY reset polling failed to complete.\n");
 305         }
 306
 307 out:
 308         return status;
 309 }
 310
 311 /**
 312  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 313  *  @hw: pointer to hardware structure
 314  *  @reg_addr: 32 bit address of PHY register to read
 315  *  @phy_data: Pointer to read data from PHY register
 316  **/
 317 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 318                                u32 device_type, u16 *phy_data)
 319 {
 320         u32 command;
 321         u32 i;
 322         u32 data;
 323         s32 status = IXGBE_SUCCESS;
 324         u16 gssr;
 325
 326         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 327
 328         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 329                 gssr = IXGBE_GSSR_PHY1_SM;
 330         else
 331                 gssr = IXGBE_GSSR_PHY0_SM;
 332
 333         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
 334                 status = IXGBE_ERR_SWFW_SYNC;
 335
 336         if (status == IXGBE_SUCCESS) {
 337                 /* Setup and write the address cycle command */
 338                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 339                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 340                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 341                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 342
 343                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 344
 345                 /*
 346                  * Check every 10 usec to see if the address cycle completed.
 347                  * The MDI Command bit will clear when the operation is
 348                  * complete
 349                  */
 350                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 351                         usec_delay(10);
 352
 353                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 354
 355                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 356                                 break;
 357                 }
 358
 359                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 360                         DEBUGOUT("PHY address command did not complete.\n");
 361                         status = IXGBE_ERR_PHY;
 362                 }
 363
 364                 if (status == IXGBE_SUCCESS) {
 365                         /*
 366                          * Address cycle complete, setup and write the read
 367                          * command
 368                          */
 369                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 370                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 371                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 372                                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 373
 374                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 375
 376                         /*
 377                          * Check every 10 usec to see if the address cycle
 378                          * completed. The MDI Command bit will clear when the
 379                          * operation is complete
 380                          */
 381                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 382                                 usec_delay(10);
 383
 384                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 385
 386                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 387                                         break;
 388                         }
 389
 390                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 391                                 DEBUGOUT("PHY read command didn't complete\n");
 392                                 status = IXGBE_ERR_PHY;
 393                         } else {
 394                                 /*
 395                                  * Read operation is complete.  Get the data
 396                                  * from MSRWD
 397                                  */
 398                                 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 399                                 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 400                                 *phy_data = (u16)(data);
 401                         }
 402                 }
 403
 404                 hw->mac.ops.release_swfw_sync(hw, gssr);
 405         }
 406
 407         return status;
 408 }
 409
 410 /**
 411  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 412  *  @hw: pointer to hardware structure
 413  *  @reg_addr: 32 bit PHY register to write
 414  *  @device_type: 5 bit device type
 415  *  @phy_data: Data to write to the PHY register
 416  **/
 417 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 418                                 u32 device_type, u16 phy_data)
 419 {
 420         u32 command;
 421         u32 i;
 422         s32 status = IXGBE_SUCCESS;
 423         u16 gssr;
 424
 425         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 426
 427         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 428                 gssr = IXGBE_GSSR_PHY1_SM;
 429         else
 430                 gssr = IXGBE_GSSR_PHY0_SM;
 431
 432         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
 433                 status = IXGBE_ERR_SWFW_SYNC;
 434
 435         if (status == IXGBE_SUCCESS) {
 436                 /* Put the data in the MDI single read and write data register*/
 437                 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 438
 439                 /* Setup and write the address cycle command */
 440                 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 441                            (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 442                            (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 443                            (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 444
 445                 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 446
 447                 /*
 448                  * Check every 10 usec to see if the address cycle completed.
 449                  * The MDI Command bit will clear when the operation is
 450                  * complete
 451                  */
 452                 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 453                         usec_delay(10);
 454
 455                         command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 456
 457                         if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 458                                 break;
 459                 }
 460
 461                 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 462                         DEBUGOUT("PHY address cmd didn't complete\n");
 463                         status = IXGBE_ERR_PHY;
 464                 }
 465
 466                 if (status == IXGBE_SUCCESS) {
 467                         /*
 468                          * Address cycle complete, setup and write the write
 469                          * command
 470                          */
 471                         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 472                                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 473                                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 474                                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 475
 476                         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 477
 478                         /*
 479                          * Check every 10 usec to see if the address cycle
 480                          * completed. The MDI Command bit will clear when the
 481                          * operation is complete
 482                          */
 483                         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 484                                 usec_delay(10);
 485
 486                                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 487
 488                                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 489                                         break;
 490                         }
 491
 492                         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 493                                 DEBUGOUT("PHY address cmd didn't complete\n");
 494                                 status = IXGBE_ERR_PHY;
 495                         }
 496                 }
 497
 498                 hw->mac.ops.release_swfw_sync(hw, gssr);
 499         }
 500
 501         return status;
 502 }
 503
 504 /**
 505  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 506  *  @hw: pointer to hardware structure
 507  *
 508  *  Restart autonegotiation and PHY and waits for completion.
 509  **/
 510 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 511 {
 512         s32 status = IXGBE_SUCCESS;
 513         u32 time_out;
 514         u32 max_time_out = 10;
 515         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 516         bool autoneg = false;
 517         ixgbe_link_speed speed;
 518
 519         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 520
 521         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 522
 523         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 524                 /* Set or unset auto-negotiation 10G advertisement */
 525                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 526                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 527                                      &autoneg_reg);
 528
 529                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 530                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 531                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 532
 533                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 534                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 535                                       autoneg_reg);
 536         }
 537
 538         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 539                 /* Set or unset auto-negotiation 1G advertisement */
 540                 hw->phy.ops.read_reg(hw,
 541                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 542                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 543                                      &autoneg_reg);
 544
 545                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 546                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 547                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 548
 549                 hw->phy.ops.write_reg(hw,
 550                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 551                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 552                                       autoneg_reg);
 553         }
 554
 555         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 556                 /* Set or unset auto-negotiation 100M advertisement */
 557                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 558                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 559                                      &autoneg_reg);
 560
 561                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 562                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 563                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 564                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 565
 566                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 567                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 568                                       autoneg_reg);
 569         }
 570
 571         /* Blocked by MNG FW so don't reset PHY */
 572         if (ixgbe_check_reset_blocked(hw))
 573                 return status;
 574
 575         /* Restart PHY autonegotiation and wait for completion */
 576         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 577                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 578
 579         autoneg_reg |= IXGBE_MII_RESTART;
 580
 581         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 582                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 583
 584         /* Wait for autonegotiation to finish */
 585         for (time_out = 0; time_out < max_time_out; time_out++) {
 586                 usec_delay(10);
 587                 /* Restart PHY autonegotiation and wait for completion */
 588                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 589                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 590                                               &autoneg_reg);
 591
 592                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 593                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
 594                         break;
 595         }
 596
 597         if (time_out == max_time_out) {
 598                 status = IXGBE_ERR_LINK_SETUP;
 599                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 600                              "PHY autonegotiation time out");
 601         }
 602
 603         return status;
 604 }
 605
 606 /**
 607  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 608  *  @hw: pointer to hardware structure
 609  *  @speed: new link speed
 610  **/
 611 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 612                                        ixgbe_link_speed speed,
 613                                        bool autoneg_wait_to_complete)
 614 {
 615         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 616
 617         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 618
 619         /*
 620          * Clear autoneg_advertised and set new values based on input link
 621          * speed.
 622          */
 623         hw->phy.autoneg_advertised = 0;
 624
 625         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 626                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 627
 628         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 629                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 630
 631         if (speed & IXGBE_LINK_SPEED_100_FULL)
 632                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 633
 634         /* Setup link based on the new speed settings */
 635         hw->phy.ops.setup_link(hw);
 636
 637         return IXGBE_SUCCESS;
 638 }
 639
 640 /**
 641  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 642  *  @hw: pointer to hardware structure
 643  *  @speed: pointer to link speed
 644  *  @autoneg: boolean auto-negotiation value
 645  *
 646  *  Determines the link capabilities by reading the AUTOC register.
 647  **/
 648 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 649                                                ixgbe_link_speed *speed,
 650                                                bool *autoneg)
 651 {
 652         s32 status;
 653         u16 speed_ability;
 654
 655         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 656
 657         *speed = 0;
 658         *autoneg = true;
 659
 660         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 661                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 662                                       &speed_ability);
 663
 664         if (status == IXGBE_SUCCESS) {
 665                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 666                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 667                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 668                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 669                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 670                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 671         }
 672
 673         return status;
 674 }
 675
 676 /**
 677  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 678  *  @hw: pointer to hardware structure
 679  *
 680  *  Reads the VS1 register to determine if link is up and the current speed for
 681  *  the PHY.
 682  **/
 683 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 684                              bool *link_up)
 685 {
 686         s32 status = IXGBE_SUCCESS;
 687         u32 time_out;
 688         u32 max_time_out = 10;
 689         u16 phy_link = 0;
 690         u16 phy_speed = 0;
 691         u16 phy_data = 0;
 692
 693         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 694
 695         /* Initialize speed and link to default case */
 696         *link_up = false;
 697         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 698
 699         /*
 700          * Check current speed and link status of the PHY register.
 701          * This is a vendor specific register and may have to
 702          * be changed for other copper PHYs.
 703          */
 704         for (time_out = 0; time_out < max_time_out; time_out++) {
 705                 usec_delay(10);
 706                 status = hw->phy.ops.read_reg(hw,
 707                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 708                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 709                                         &phy_data);
 710                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 711                 phy_speed = phy_data &
 712                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 713                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 714                         *link_up = true;
 715                         if (phy_speed ==
 716                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 717                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 718                         break;
 719                 }
 720         }
 721
 722         return status;
 723 }
 724
 725 /**
 726  *      ixgbe_setup_phy_link_tnx - Set and restart autoneg
 727  *      @hw: pointer to hardware structure
 728  *
 729  *      Restart autonegotiation and PHY and waits for completion.
 730  **/
 731 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 732 {
 733         s32 status = IXGBE_SUCCESS;
 734         u32 time_out;
 735         u32 max_time_out = 10;
 736         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 737         bool autoneg = false;
 738         ixgbe_link_speed speed;
 739
 740         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
 741
 742         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 743
 744         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 745                 /* Set or unset auto-negotiation 10G advertisement */
 746                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 747                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 748                                      &autoneg_reg);
 749
 750                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 751                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 752                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 753
 754                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 755                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 756                                       autoneg_reg);
 757         }
 758
 759         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 760                 /* Set or unset auto-negotiation 1G advertisement */
 761                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 762                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 763                                      &autoneg_reg);
 764
 765                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 766                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 767                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 768
 769                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 770                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 771                                       autoneg_reg);
 772         }
 773
 774         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 775                 /* Set or unset auto-negotiation 100M advertisement */
 776                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 777                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 778                                      &autoneg_reg);
 779
 780                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
 781                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 782                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 783
 784                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 785                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 786                                       autoneg_reg);
 787         }
 788
 789         /* Blocked by MNG FW so don't reset PHY */
 790         if (ixgbe_check_reset_blocked(hw))
 791                 return status;
 792
 793         /* Restart PHY autonegotiation and wait for completion */
 794         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 795                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 796
 797         autoneg_reg |= IXGBE_MII_RESTART;
 798
 799         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 800                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 801
 802         /* Wait for autonegotiation to finish */
 803         for (time_out = 0; time_out < max_time_out; time_out++) {
 804                 usec_delay(10);
 805                 /* Restart PHY autonegotiation and wait for completion */
 806                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 807                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 808                                               &autoneg_reg);
 809
 810                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 811                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
 812                         break;
 813         }
 814
 815         if (time_out == max_time_out) {
 816                 status = IXGBE_ERR_LINK_SETUP;
 817                 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
 818         }
 819
 820         return status;
 821 }
 822
 823 /**
 824  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 825  *  @hw: pointer to hardware structure
 826  *  @firmware_version: pointer to the PHY Firmware Version
 827  **/
 828 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 829                                        u16 *firmware_version)
 830 {
 831         s32 status;
 832
 833         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
 834
 835         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 836                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 837                                       firmware_version);
 838
 839         return status;
 840 }
 841
 842 /**
 843  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 844  *  @hw: pointer to hardware structure
 845  *  @firmware_version: pointer to the PHY Firmware Version
 846  **/
 847 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 848                                            u16 *firmware_version)
 849 {
 850         s32 status;
 851
 852         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
 853
 854         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 855                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 856                                       firmware_version);
 857
 858         return status;
 859 }
 860
 861 /**
 862  *  ixgbe_reset_phy_nl - Performs a PHY reset
 863  *  @hw: pointer to hardware structure
 864  **/
 865 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 866 {
 867         u16 phy_offset, control, eword, edata, block_crc;
 868         bool end_data = false;
 869         u16 list_offset, data_offset;
 870         u16 phy_data = 0;
 871         s32 ret_val = IXGBE_SUCCESS;
 872         u32 i;
 873
 874         DEBUGFUNC("ixgbe_reset_phy_nl");
 875
 876         /* Blocked by MNG FW so bail */
 877         if (ixgbe_check_reset_blocked(hw))
 878                 goto out;
 879
 880         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 881                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 882
 883         /* reset the PHY and poll for completion */
 884         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 885                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 886                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
 887
 888         for (i = 0; i < 100; i++) {
 889                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 890                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 891                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
 892                         break;
 893                 msec_delay(10);
 894         }
 895
 896         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
 897                 DEBUGOUT("PHY reset did not complete.\n");
 898                 ret_val = IXGBE_ERR_PHY;
 899                 goto out;
 900         }
 901
 902         /* Get init offsets */
 903         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 904                                                       &data_offset);
 905         if (ret_val != IXGBE_SUCCESS)
 906                 goto out;
 907
 908         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 909         data_offset++;
 910         while (!end_data) {
 911                 /*
 912                  * Read control word from PHY init contents offset
 913                  */
 914                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 915                 if (ret_val)
 916                         goto err_eeprom;
 917                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 918                            IXGBE_CONTROL_SHIFT_NL;
 919                 edata = eword & IXGBE_DATA_MASK_NL;
 920                 switch (control) {
 921                 case IXGBE_DELAY_NL:
 922                         data_offset++;
 923                         DEBUGOUT1("DELAY: %d MS\n", edata);
 924                         msec_delay(edata);
 925                         break;
 926                 case IXGBE_DATA_NL:
 927                         DEBUGOUT("DATA:\n");
 928                         data_offset++;
 929                         ret_val = hw->eeprom.ops.read(hw, data_offset,
 930                                                       &phy_offset);
 931                         if (ret_val)
 932                                 goto err_eeprom;
 933                         data_offset++;
 934                         for (i = 0; i < edata; i++) {
 935                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
 936                                                               &eword);
 937                                 if (ret_val)
 938                                         goto err_eeprom;
 939                                 hw->phy.ops.write_reg(hw, phy_offset,
 940                                                       IXGBE_TWINAX_DEV, eword);
 941                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
 942                                           phy_offset);
 943                                 data_offset++;
 944                                 phy_offset++;
 945                         }
 946                         break;
 947                 case IXGBE_CONTROL_NL:
 948                         data_offset++;
 949                         DEBUGOUT("CONTROL:\n");
 950                         if (edata == IXGBE_CONTROL_EOL_NL) {
 951                                 DEBUGOUT("EOL\n");
 952                                 end_data = true;
 953                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 954                                 DEBUGOUT("SOL\n");
 955                         } else {
 956                                 DEBUGOUT("Bad control value\n");
 957                                 ret_val = IXGBE_ERR_PHY;
 958                                 goto out;
 959                         }
 960                         break;
 961                 default:
 962                         DEBUGOUT("Bad control type\n");
 963                         ret_val = IXGBE_ERR_PHY;
 964                         goto out;
 965                 }
 966         }
 967
 968 out:
 969         return ret_val;
 970
 971 err_eeprom:
 972         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 973                       "eeprom read at offset %d failed", data_offset);
 974         return IXGBE_ERR_PHY;
 975 }
 976
 977 /**
 978  *  ixgbe_identify_module_generic - Identifies module type
 979  *  @hw: pointer to hardware structure
 980  *
 981  *  Determines HW type and calls appropriate function.
 982  **/
 983 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
 984 {
 985         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
 986
 987         DEBUGFUNC("ixgbe_identify_module_generic");
 988
 989         switch (hw->mac.ops.get_media_type(hw)) {
 990         case ixgbe_media_type_fiber:
 991                 status = ixgbe_identify_sfp_module_generic(hw);
 992                 break;
 993
 994
 995         default:
 996                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 997                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 998                 break;
 999         }
1000
1001         return status;
1002 }
1003
1004 /**
1005  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1006  *  @hw: pointer to hardware structure
1007  *
1008  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1009  **/
1010 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1011 {
1012         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1013         u32 vendor_oui = 0;
1014         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1015         u8 identifier = 0;
1016         u8 comp_codes_1g = 0;
1017         u8 comp_codes_10g = 0;
1018         u8 oui_bytes[3] = {0, 0, 0};
1019         u8 cable_tech = 0;
1020         u8 cable_spec = 0;
1021         u16 enforce_sfp = 0;
1022
1023         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1024
1025         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1026                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1027                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1028                 goto out;
1029         }
1030
1031         status = hw->phy.ops.read_i2c_eeprom(hw,
1032                                              IXGBE_SFF_IDENTIFIER,
1033                                              &identifier);
1034
1035         if (status != IXGBE_SUCCESS)
1036                 goto err_read_i2c_eeprom;
1037
1038         /* LAN ID is needed for sfp_type determination */
1039         hw->mac.ops.set_lan_id(hw);
1040
1041         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1042                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1043                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1044         } else {
1045                 status = hw->phy.ops.read_i2c_eeprom(hw,
1046                                                      IXGBE_SFF_1GBE_COMP_CODES,
1047                                                      &comp_codes_1g);
1048
1049                 if (status != IXGBE_SUCCESS)
1050                         goto err_read_i2c_eeprom;
1051
1052                 status = hw->phy.ops.read_i2c_eeprom(hw,
1053                                                      IXGBE_SFF_10GBE_COMP_CODES,
1054                                                      &comp_codes_10g);
1055
1056                 if (status != IXGBE_SUCCESS)
1057                         goto err_read_i2c_eeprom;
1058                 status = hw->phy.ops.read_i2c_eeprom(hw,
1059                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1060                                                      &cable_tech);
1061
1062                 if (status != IXGBE_SUCCESS)
1063                         goto err_read_i2c_eeprom;
1064
1065                  /* ID Module
1066                   * =========
1067                   * 0   SFP_DA_CU
1068                   * 1   SFP_SR
1069                   * 2   SFP_LR
1070                   * 3   SFP_DA_CORE0 - 82599-specific
1071                   * 4   SFP_DA_CORE1 - 82599-specific
1072                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1073                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1074                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1075                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1076                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1077                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1078                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1079                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1080                   */
1081                 if (hw->mac.type == ixgbe_mac_82598EB) {
1082                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1083                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1084                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1085                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1086                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1087                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1088                         else
1089                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1090                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1091                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1092                                 if (hw->bus.lan_id == 0)
1093                                         hw->phy.sfp_type =
1094                                                      ixgbe_sfp_type_da_cu_core0;
1095                                 else
1096                                         hw->phy.sfp_type =
1097                                                      ixgbe_sfp_type_da_cu_core1;
1098                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1099                                 hw->phy.ops.read_i2c_eeprom(
1100                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1101                                                 &cable_spec);
1102                                 if (cable_spec &
1103                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1104                                         if (hw->bus.lan_id == 0)
1105                                                 hw->phy.sfp_type =
1106                                                 ixgbe_sfp_type_da_act_lmt_core0;
1107                                         else
1108                                                 hw->phy.sfp_type =
1109                                                 ixgbe_sfp_type_da_act_lmt_core1;
1110                                 } else {
1111                                         hw->phy.sfp_type =
1112                                                         ixgbe_sfp_type_unknown;
1113                                 }
1114                         } else if (comp_codes_10g &
1115                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1116                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1117                                 if (hw->bus.lan_id == 0)
1118                                         hw->phy.sfp_type =
1119                                                       ixgbe_sfp_type_srlr_core0;
1120                                 else
1121                                         hw->phy.sfp_type =
1122                                                       ixgbe_sfp_type_srlr_core1;
1123 #ifdef SUPPORT_10GBASE_ER
1124                         } else if (comp_codes_10g &
1125                                    IXGBE_SFF_10GBASEER_CAPABLE) {
1126                                 if (hw->bus.lan_id == 0)
1127                                         hw->phy.sfp_type =
1128                                                         ixgbe_sfp_type_er_core0;
1129                                 else
1130                                         hw->phy.sfp_type =
1131                                                         ixgbe_sfp_type_er_core1;
1132 #endif /* SUPPORT_10GBASE_ER */
1133                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1134                                 if (hw->bus.lan_id == 0)
1135                                         hw->phy.sfp_type =
1136                                                 ixgbe_sfp_type_1g_cu_core0;
1137                                 else
1138                                         hw->phy.sfp_type =
1139                                                 ixgbe_sfp_type_1g_cu_core1;
1140                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1141                                 if (hw->bus.lan_id == 0)
1142                                         hw->phy.sfp_type =
1143                                                 ixgbe_sfp_type_1g_sx_core0;
1144                                 else
1145                                         hw->phy.sfp_type =
1146                                                 ixgbe_sfp_type_1g_sx_core1;
1147 #ifdef SUPPORT_1000BASE_LX
1148                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1149                                 if (hw->bus.lan_id == 0)
1150                                         hw->phy.sfp_type =
1151                                                 ixgbe_sfp_type_1g_lx_core0;
1152                                 else
1153                                         hw->phy.sfp_type =
1154                                                 ixgbe_sfp_type_1g_lx_core1;
1155 #endif /* SUPPORT_1000BASE_LX */
1156                         } else {
1157                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1158                         }
1159                 }
1160
1161                 if (hw->phy.sfp_type != stored_sfp_type)
1162                         hw->phy.sfp_setup_needed = true;
1163
1164                 /* Determine if the SFP+ PHY is dual speed or not. */
1165                 hw->phy.multispeed_fiber = false;
1166                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1167                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1168                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1169                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1170                         hw->phy.multispeed_fiber = true;
1171
1172                 /* Determine PHY vendor */
1173                 if (hw->phy.type != ixgbe_phy_nl) {
1174                         hw->phy.id = identifier;
1175                         status = hw->phy.ops.read_i2c_eeprom(hw,
1176                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1177                                                     &oui_bytes[0]);
1178
1179                         if (status != IXGBE_SUCCESS)
1180                                 goto err_read_i2c_eeprom;
1181
1182                         status = hw->phy.ops.read_i2c_eeprom(hw,
1183                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1184                                                     &oui_bytes[1]);
1185
1186                         if (status != IXGBE_SUCCESS)
1187                                 goto err_read_i2c_eeprom;
1188
1189                         status = hw->phy.ops.read_i2c_eeprom(hw,
1190                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1191                                                     &oui_bytes[2]);
1192
1193                         if (status != IXGBE_SUCCESS)
1194                                 goto err_read_i2c_eeprom;
1195
1196                         vendor_oui =
1197                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1198                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1199                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1200
1201                         switch (vendor_oui) {
1202                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1203                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1204                                         hw->phy.type =
1205                                                     ixgbe_phy_sfp_passive_tyco;
1206                                 break;
1207                         case IXGBE_SFF_VENDOR_OUI_FTL:
1208                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1209                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1210                                 else
1211                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1212                                 break;
1213                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1214                                 hw->phy.type = ixgbe_phy_sfp_avago;
1215                                 break;
1216                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1217                                 hw->phy.type = ixgbe_phy_sfp_intel;
1218                                 break;
1219                         default:
1220                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1221                                         hw->phy.type =
1222                                                  ixgbe_phy_sfp_passive_unknown;
1223                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1224                                         hw->phy.type =
1225                                                 ixgbe_phy_sfp_active_unknown;
1226                                 else
1227                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1228                                 break;
1229                         }
1230                 }
1231
1232                 /* Allow any DA cable vendor */
1233                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1234                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1235                         status = IXGBE_SUCCESS;
1236                         goto out;
1237                 }
1238
1239                 /* Verify supported 1G SFP modules */
1240                 if (comp_codes_10g == 0 &&
1241                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1242                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1243 #ifdef SUPPORT_1000BASE_LX
1244                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1245                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1246 #endif
1247                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1248                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1249                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1250                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1251                         goto out;
1252                 }
1253
1254                 /* Anything else 82598-based is supported */
1255                 if (hw->mac.type == ixgbe_mac_82598EB) {
1256                         status = IXGBE_SUCCESS;
1257                         goto out;
1258                 }
1259
1260                 ixgbe_get_device_caps(hw, &enforce_sfp);
1261                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1262                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1263                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1264 #ifdef SUPPORT_1000BASE_LX
1265                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1266                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1267 #endif
1268 #ifdef SUPPORT_10GBASE_ER
1269                       hw->phy.sfp_type == ixgbe_sfp_type_er_core0 ||
1270                       hw->phy.sfp_type == ixgbe_sfp_type_er_core1 ||
1271 #endif
1272                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1273                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1274                         /* Make sure we're a supported PHY type */
1275                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1276                                 status = IXGBE_SUCCESS;
1277                         } else {
1278                                 if (hw->allow_unsupported_sfp == true) {
1279                                         EWARN(hw, "WARNING: Intel (R) Network "
1280                                               "Connections are quality tested "
1281                                               "using Intel (R) Ethernet Optics."
1282                                               " Using untested modules is not "
1283                                               "supported and may cause unstable"
1284                                               " operation or damage to the "
1285                                               "module or the adapter. Intel "
1286                                               "Corporation is not responsible "
1287                                               "for any harm caused by using "
1288                                               "untested modules.\n", status);
1289                                         status = IXGBE_SUCCESS;
1290                                 } else {
1291                                         DEBUGOUT("SFP+ module not supported\n");
1292                                         hw->phy.type =
1293                                                 ixgbe_phy_sfp_unsupported;
1294                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1295                                 }
1296                         }
1297                 } else {
1298                         status = IXGBE_SUCCESS;
1299                 }
1300         }
1301
1302 out:
1303         return status;
1304
1305 err_read_i2c_eeprom:
1306         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1307         if (hw->phy.type != ixgbe_phy_nl) {
1308                 hw->phy.id = 0;
1309                 hw->phy.type = ixgbe_phy_unknown;
1310         }
1311         return IXGBE_ERR_SFP_NOT_PRESENT;
1312 }
1313
1314
1315
1316 /**
1317  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1318  *  @hw: pointer to hardware structure
1319  *  @list_offset: offset to the SFP ID list
1320  *  @data_offset: offset to the SFP data block
1321  *
1322  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1323  *  so it returns the offsets to the phy init sequence block.
1324  **/
1325 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1326                                         u16 *list_offset,
1327                                         u16 *data_offset)
1328 {
1329         u16 sfp_id;
1330         u16 sfp_type = hw->phy.sfp_type;
1331
1332         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1333
1334         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1335                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1336
1337         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1338                 return IXGBE_ERR_SFP_NOT_PRESENT;
1339
1340         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1341             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1342                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1343
1344         /*
1345          * Limiting active cables and 1G Phys must be initialized as
1346          * SR modules
1347          */
1348         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1349 #ifdef SUPPORT_10GBASE_ER
1350             sfp_type == ixgbe_sfp_type_er_core0 ||
1351 #endif /* SUPPORT_10GBASE_ER */
1352 #ifdef SUPPORT_1000BASE_LX
1353             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1354 #endif /* SUPPORT_1000BASE_LX */
1355             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1356             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1357                 sfp_type = ixgbe_sfp_type_srlr_core0;
1358         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1359 #ifdef SUPPORT_10GBASE_ER
1360                  sfp_type == ixgbe_sfp_type_er_core1 ||
1361 #endif /* SUPPORT_10GBASE_ER */
1362 #ifdef SUPPORT_1000BASE_LX
1363                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1364 #endif /* SUPPORT_1000BASE_LX */
1365                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1366                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1367                 sfp_type = ixgbe_sfp_type_srlr_core1;
1368
1369         /* Read offset to PHY init contents */
1370         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1371                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1372                               "eeprom read at offset %d failed",
1373                               IXGBE_PHY_INIT_OFFSET_NL);
1374                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1375         }
1376
1377         if ((!*list_offset) || (*list_offset == 0xFFFF))
1378                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1379
1380         /* Shift offset to first ID word */
1381         (*list_offset)++;
1382
1383         /*
1384          * Find the matching SFP ID in the EEPROM
1385          * and program the init sequence
1386          */
1387         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1388                 goto err_phy;
1389
1390         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1391                 if (sfp_id == sfp_type) {
1392                         (*list_offset)++;
1393                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1394                                 goto err_phy;
1395                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1396                                 DEBUGOUT("SFP+ module not supported\n");
1397                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1398                         } else {
1399                                 break;
1400                         }
1401                 } else {
1402                         (*list_offset) += 2;
1403                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1404                                 goto err_phy;
1405                 }
1406         }
1407
1408         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1409                 DEBUGOUT("No matching SFP+ module found\n");
1410                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1411         }
1412
1413         return IXGBE_SUCCESS;
1414
1415 err_phy:
1416         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1417                       "eeprom read at offset %d failed", *list_offset);
1418         return IXGBE_ERR_PHY;
1419 }
1420
1421 /**
1422  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1423  *  @hw: pointer to hardware structure
1424  *  @byte_offset: EEPROM byte offset to read
1425  *  @eeprom_data: value read
1426  *
1427  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1428  **/
1429 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1430                                   u8 *eeprom_data)
1431 {
1432         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1433
1434         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1435                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1436                                          eeprom_data);
1437 }
1438
1439 /**
1440  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1441  *  @hw: pointer to hardware structure
1442  *  @byte_offset: EEPROM byte offset to write
1443  *  @eeprom_data: value to write
1444  *
1445  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1446  **/
1447 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1448                                    u8 eeprom_data)
1449 {
1450         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1451
1452         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1453                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1454                                           eeprom_data);
1455 }
1456
1457 /**
1458  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1459  *  @hw: pointer to hardware structure
1460  *  @byte_offset: byte offset to read
1461  *  @data: value read
1462  *
1463  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1464  *  a specified device address.
1465  **/
1466 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1467                                 u8 dev_addr, u8 *data)
1468 {
1469         s32 status = IXGBE_SUCCESS;
1470         u32 max_retry = 10;
1471         u32 retry = 0;
1472         u16 swfw_mask = 0;
1473         bool nack = 1;
1474         *data = 0;
1475
1476         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1477
1478         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1479                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1480         else
1481                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1482
1483         do {
1484                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1485                     != IXGBE_SUCCESS) {
1486                         status = IXGBE_ERR_SWFW_SYNC;
1487                         goto read_byte_out;
1488                 }
1489
1490                 ixgbe_i2c_start(hw);
1491
1492                 /* Device Address and write indication */
1493                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1494                 if (status != IXGBE_SUCCESS)
1495                         goto fail;
1496
1497                 status = ixgbe_get_i2c_ack(hw);
1498                 if (status != IXGBE_SUCCESS)
1499                         goto fail;
1500
1501                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1502                 if (status != IXGBE_SUCCESS)
1503                         goto fail;
1504
1505                 status = ixgbe_get_i2c_ack(hw);
1506                 if (status != IXGBE_SUCCESS)
1507                         goto fail;
1508
1509                 ixgbe_i2c_start(hw);
1510
1511                 /* Device Address and read indication */
1512                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1513                 if (status != IXGBE_SUCCESS)
1514                         goto fail;
1515
1516                 status = ixgbe_get_i2c_ack(hw);
1517                 if (status != IXGBE_SUCCESS)
1518                         goto fail;
1519
1520                 status = ixgbe_clock_in_i2c_byte(hw, data);
1521                 if (status != IXGBE_SUCCESS)
1522                         goto fail;
1523
1524                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1525                 if (status != IXGBE_SUCCESS)
1526                         goto fail;
1527
1528                 ixgbe_i2c_stop(hw);
1529                 break;
1530
1531 fail:
1532                 ixgbe_i2c_bus_clear(hw);
1533                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1534                 msec_delay(100);
1535                 retry++;
1536                 if (retry < max_retry)
1537                         DEBUGOUT("I2C byte read error - Retrying.\n");
1538                 else
1539                         DEBUGOUT("I2C byte read error.\n");
1540
1541         } while (retry < max_retry);
1542
1543         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1544
1545 read_byte_out:
1546         return status;
1547 }
1548
1549 /**
1550  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1551  *  @hw: pointer to hardware structure
1552  *  @byte_offset: byte offset to write
1553  *  @data: value to write
1554  *
1555  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1556  *  a specified device address.
1557  **/
1558 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1559                                  u8 dev_addr, u8 data)
1560 {
1561         s32 status = IXGBE_SUCCESS;
1562         u32 max_retry = 1;
1563         u32 retry = 0;
1564         u16 swfw_mask = 0;
1565
1566         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1567
1568         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1569                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1570         else
1571                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1572
1573         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1574                 status = IXGBE_ERR_SWFW_SYNC;
1575                 goto write_byte_out;
1576         }
1577
1578         do {
1579                 ixgbe_i2c_start(hw);
1580
1581                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1582                 if (status != IXGBE_SUCCESS)
1583                         goto fail;
1584
1585                 status = ixgbe_get_i2c_ack(hw);
1586                 if (status != IXGBE_SUCCESS)
1587                         goto fail;
1588
1589                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1590                 if (status != IXGBE_SUCCESS)
1591                         goto fail;
1592
1593                 status = ixgbe_get_i2c_ack(hw);
1594                 if (status != IXGBE_SUCCESS)
1595                         goto fail;
1596
1597                 status = ixgbe_clock_out_i2c_byte(hw, data);
1598                 if (status != IXGBE_SUCCESS)
1599                         goto fail;
1600
1601                 status = ixgbe_get_i2c_ack(hw);
1602                 if (status != IXGBE_SUCCESS)
1603                         goto fail;
1604
1605                 ixgbe_i2c_stop(hw);
1606                 break;
1607
1608 fail:
1609                 ixgbe_i2c_bus_clear(hw);
1610                 retry++;
1611                 if (retry < max_retry)
1612                         DEBUGOUT("I2C byte write error - Retrying.\n");
1613                 else
1614                         DEBUGOUT("I2C byte write error.\n");
1615         } while (retry < max_retry);
1616
1617         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1618
1619 write_byte_out:
1620         return status;
1621 }
1622
1623 /**
1624  *  ixgbe_i2c_start - Sets I2C start condition
1625  *  @hw: pointer to hardware structure
1626  *
1627  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1628  **/
1629 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
1630 {
1631         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1632
1633         DEBUGFUNC("ixgbe_i2c_start");
1634
1635         /* Start condition must begin with data and clock high */
1636         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1637         ixgbe_raise_i2c_clk(hw, &i2cctl);
1638
1639         /* Setup time for start condition (4.7us) */
1640         usec_delay(IXGBE_I2C_T_SU_STA);
1641
1642         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1643
1644         /* Hold time for start condition (4us) */
1645         usec_delay(IXGBE_I2C_T_HD_STA);
1646
1647         ixgbe_lower_i2c_clk(hw, &i2cctl);
1648
1649         /* Minimum low period of clock is 4.7 us */
1650         usec_delay(IXGBE_I2C_T_LOW);
1651
1652 }
1653
1654 /**
1655  *  ixgbe_i2c_stop - Sets I2C stop condition
1656  *  @hw: pointer to hardware structure
1657  *
1658  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1659  **/
1660 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1661 {
1662         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1663
1664         DEBUGFUNC("ixgbe_i2c_stop");
1665
1666         /* Stop condition must begin with data low and clock high */
1667         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1668         ixgbe_raise_i2c_clk(hw, &i2cctl);
1669
1670         /* Setup time for stop condition (4us) */
1671         usec_delay(IXGBE_I2C_T_SU_STO);
1672
1673         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1674
1675         /* bus free time between stop and start (4.7us)*/
1676         usec_delay(IXGBE_I2C_T_BUF);
1677 }
1678
1679 /**
1680  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1681  *  @hw: pointer to hardware structure
1682  *  @data: data byte to clock in
1683  *
1684  *  Clocks in one byte data via I2C data/clock
1685  **/
1686 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1687 {
1688         s32 i;
1689         bool bit = 0;
1690
1691         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1692
1693         for (i = 7; i >= 0; i--) {
1694                 ixgbe_clock_in_i2c_bit(hw, &bit);
1695                 *data |= bit << i;
1696         }
1697
1698         return IXGBE_SUCCESS;
1699 }
1700
1701 /**
1702  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1703  *  @hw: pointer to hardware structure
1704  *  @data: data byte clocked out
1705  *
1706  *  Clocks out one byte data via I2C data/clock
1707  **/
1708 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1709 {
1710         s32 status = IXGBE_SUCCESS;
1711         s32 i;
1712         u32 i2cctl;
1713         bool bit;
1714
1715         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1716
1717         for (i = 7; i >= 0; i--) {
1718                 bit = (data >> i) & 0x1;
1719                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1720
1721                 if (status != IXGBE_SUCCESS)
1722                         break;
1723         }
1724
1725         /* Release SDA line (set high) */
1726         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1727         i2cctl |= IXGBE_I2C_DATA_OUT;
1728         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1729         IXGBE_WRITE_FLUSH(hw);
1730
1731         return status;
1732 }
1733
1734 /**
1735  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1736  *  @hw: pointer to hardware structure
1737  *
1738  *  Clocks in/out one bit via I2C data/clock
1739  **/
1740 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1741 {
1742         s32 status = IXGBE_SUCCESS;
1743         u32 i = 0;
1744         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1745         u32 timeout = 10;
1746         bool ack = 1;
1747
1748         DEBUGFUNC("ixgbe_get_i2c_ack");
1749
1750         ixgbe_raise_i2c_clk(hw, &i2cctl);
1751
1752
1753         /* Minimum high period of clock is 4us */
1754         usec_delay(IXGBE_I2C_T_HIGH);
1755
1756         /* Poll for ACK.  Note that ACK in I2C spec is
1757          * transition from 1 to 0 */
1758         for (i = 0; i < timeout; i++) {
1759                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1760                 ack = ixgbe_get_i2c_data(&i2cctl);
1761
1762                 usec_delay(1);
1763                 if (ack == 0)
1764                         break;
1765         }
1766
1767         if (ack == 1) {
1768                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1769                              "I2C ack was not received.\n");
1770                 status = IXGBE_ERR_I2C;
1771         }
1772
1773         ixgbe_lower_i2c_clk(hw, &i2cctl);
1774
1775         /* Minimum low period of clock is 4.7 us */
1776         usec_delay(IXGBE_I2C_T_LOW);
1777
1778         return status;
1779 }
1780
1781 /**
1782  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1783  *  @hw: pointer to hardware structure
1784  *  @data: read data value
1785  *
1786  *  Clocks in one bit via I2C data/clock
1787  **/
1788 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1789 {
1790         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1791
1792         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1793
1794         ixgbe_raise_i2c_clk(hw, &i2cctl);
1795
1796         /* Minimum high period of clock is 4us */
1797         usec_delay(IXGBE_I2C_T_HIGH);
1798
1799         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1800         *data = ixgbe_get_i2c_data(&i2cctl);
1801
1802         ixgbe_lower_i2c_clk(hw, &i2cctl);
1803
1804         /* Minimum low period of clock is 4.7 us */
1805         usec_delay(IXGBE_I2C_T_LOW);
1806
1807         return IXGBE_SUCCESS;
1808 }
1809
1810 /**
1811  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1812  *  @hw: pointer to hardware structure
1813  *  @data: data value to write
1814  *
1815  *  Clocks out one bit via I2C data/clock
1816  **/
1817 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1818 {
1819         s32 status;
1820         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1821
1822         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1823
1824         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1825         if (status == IXGBE_SUCCESS) {
1826                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1827
1828                 /* Minimum high period of clock is 4us */
1829                 usec_delay(IXGBE_I2C_T_HIGH);
1830
1831                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1832
1833                 /* Minimum low period of clock is 4.7 us.
1834                  * This also takes care of the data hold time.
1835                  */
1836                 usec_delay(IXGBE_I2C_T_LOW);
1837         } else {
1838                 status = IXGBE_ERR_I2C;
1839                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1840                              "I2C data was not set to %X\n", data);
1841         }
1842
1843         return status;
1844 }
1845 /**
1846  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1847  *  @hw: pointer to hardware structure
1848  *  @i2cctl: Current value of I2CCTL register
1849  *
1850  *  Raises the I2C clock line '0'->'1'
1851  **/
1852 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1853 {
1854         u32 i = 0;
1855         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1856         u32 i2cctl_r = 0;
1857
1858         DEBUGFUNC("ixgbe_raise_i2c_clk");
1859
1860         for (i = 0; i < timeout; i++) {
1861                 *i2cctl |= IXGBE_I2C_CLK_OUT;
1862
1863                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1864                 IXGBE_WRITE_FLUSH(hw);
1865                 /* SCL rise time (1000ns) */
1866                 usec_delay(IXGBE_I2C_T_RISE);
1867
1868                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1869                 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1870                         break;
1871         }
1872 }
1873
1874 /**
1875  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1876  *  @hw: pointer to hardware structure
1877  *  @i2cctl: Current value of I2CCTL register
1878  *
1879  *  Lowers the I2C clock line '1'->'0'
1880  **/
1881 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1882 {
1883
1884         DEBUGFUNC("ixgbe_lower_i2c_clk");
1885
1886         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1887
1888         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1889         IXGBE_WRITE_FLUSH(hw);
1890
1891         /* SCL fall time (300ns) */
1892         usec_delay(IXGBE_I2C_T_FALL);
1893 }
1894
1895 /**
1896  *  ixgbe_set_i2c_data - Sets the I2C data bit
1897  *  @hw: pointer to hardware structure
1898  *  @i2cctl: Current value of I2CCTL register
1899  *  @data: I2C data value (0 or 1) to set
1900  *
1901  *  Sets the I2C data bit
1902  **/
1903 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1904 {
1905         s32 status = IXGBE_SUCCESS;
1906
1907         DEBUGFUNC("ixgbe_set_i2c_data");
1908
1909         if (data)
1910                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1911         else
1912                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1913
1914         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1915         IXGBE_WRITE_FLUSH(hw);
1916
1917         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1918         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1919
1920         /* Verify data was set correctly */
1921         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1922         if (data != ixgbe_get_i2c_data(i2cctl)) {
1923                 status = IXGBE_ERR_I2C;
1924                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1925                              "Error - I2C data was not set to %X.\n",
1926                              data);
1927         }
1928
1929         return status;
1930 }
1931
1932 /**
1933  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1934  *  @hw: pointer to hardware structure
1935  *  @i2cctl: Current value of I2CCTL register
1936  *
1937  *  Returns the I2C data bit value
1938  **/
1939 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl)
1940 {
1941         bool data;
1942
1943         DEBUGFUNC("ixgbe_get_i2c_data");
1944
1945         if (*i2cctl & IXGBE_I2C_DATA_IN)
1946                 data = 1;
1947         else
1948                 data = 0;
1949
1950         return data;
1951 }
1952
1953 /**
1954  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1955  *  @hw: pointer to hardware structure
1956  *
1957  *  Clears the I2C bus by sending nine clock pulses.
1958  *  Used when data line is stuck low.
1959  **/
1960 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1961 {
1962         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1963         u32 i;
1964
1965         DEBUGFUNC("ixgbe_i2c_bus_clear");
1966
1967         ixgbe_i2c_start(hw);
1968
1969         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1970
1971         for (i = 0; i < 9; i++) {
1972                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1973
1974                 /* Min high period of clock is 4us */
1975                 usec_delay(IXGBE_I2C_T_HIGH);
1976
1977                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1978
1979                 /* Min low period of clock is 4.7us*/
1980                 usec_delay(IXGBE_I2C_T_LOW);
1981         }
1982
1983         ixgbe_i2c_start(hw);
1984
1985         /* Put the i2c bus back to default state */
1986         ixgbe_i2c_stop(hw);
1987 }
1988
1989 /**
1990  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1991  *  @hw: pointer to hardware structure
1992  *
1993  *  Checks if the LASI temp alarm status was triggered due to overtemp
1994  **/
1995 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1996 {
1997         s32 status = IXGBE_SUCCESS;
1998         u16 phy_data = 0;
1999
2000         DEBUGFUNC("ixgbe_tn_check_overtemp");
2001
2002         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2003                 goto out;
2004
2005         /* Check that the LASI temp alarm status was triggered */
2006         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2007                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2008
2009         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2010                 goto out;
2011
2012         status = IXGBE_ERR_OVERTEMP;
2013         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2014 out:
2015         return status;
2016 }