lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2012, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37 #ident "$Id: ixgbe_phy.c,v 1.139 2012/05/24 23:36:12 jtkirshe Exp $"
  38
  39 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  40 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  41 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  42 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  43 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  44 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  45 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  46 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  48 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  49 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl);
  50
  51 /**
  52  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
  53  *  @hw: pointer to the hardware structure
  54  *
  55  *  Initialize the function pointers.
  56  **/
  57 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
  58 {
  59         struct ixgbe_phy_info *phy = &hw->phy;
  60
  61         DEBUGFUNC("ixgbe_init_phy_ops_generic");
  62
  63         /* PHY */
  64         phy->ops.identify = &ixgbe_identify_phy_generic;
  65         phy->ops.reset = &ixgbe_reset_phy_generic;
  66         phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
  67         phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
  68         phy->ops.read_reg_mdi = &ixgbe_read_phy_reg_mdi;
  69         phy->ops.write_reg_mdi = &ixgbe_write_phy_reg_mdi;
  70         phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
  71         phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
  72         phy->ops.check_link = NULL;
  73         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
  74         phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
  75         phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
  76         phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
  77         phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
  78         phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
  79         phy->ops.identify_sfp = &ixgbe_identify_module_generic;
  80         phy->sfp_type = ixgbe_sfp_type_unknown;
  81         phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
  82         return IXGBE_SUCCESS;
  83 }
  84
  85 /**
  86  *  ixgbe_identify_phy_generic - Get physical layer module
  87  *  @hw: pointer to hardware structure
  88  *
  89  *  Determines the physical layer module found on the current adapter.
  90  **/
  91 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  92 {
  93         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  94         u32 phy_addr;
  95         u16 ext_ability = 0;
  96
  97         DEBUGFUNC("ixgbe_identify_phy_generic");
  98
  99         if (hw->phy.type == ixgbe_phy_unknown) {
 100                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 101                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 102                                 hw->phy.addr = phy_addr;
 103                                 ixgbe_get_phy_id(hw);
 104                                 hw->phy.type =
 105                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 106
 107                                 if (hw->phy.type == ixgbe_phy_unknown) {
 108                                         hw->phy.ops.read_reg(hw,
 109                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 110                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 111                                                   &ext_ability);
 112                                         if (ext_ability &
 113                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 114                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 115                                                 hw->phy.type =
 116                                                          ixgbe_phy_cu_unknown;
 117                                         else
 118                                                 hw->phy.type =
 119                                                          ixgbe_phy_generic;
 120                                 }
 121
 122                                 status = IXGBE_SUCCESS;
 123                                 break;
 124                         }
 125                 }
 126
 127                 /* Certain media types do not have a phy so an address will not
 128                  * be found and the code will take this path.  Caller has to
 129                  * decide if it is an error or not.
 130                  */
 131                 if (status != IXGBE_SUCCESS) {
 132                         hw->phy.addr = 0;
 133                 }
 134         } else {
 135                 status = IXGBE_SUCCESS;
 136         }
 137
 138         return status;
 139 }
 140
 141 /**
 142  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 143  * @hw: pointer to the hardware structure
 144  *
 145  * This function checks the MMNGC.MNG_VETO bit to see if there are
 146  * any constraints on link from manageability.  For MAC's that don't
 147  * have this bit just return faluse since the link can not be blocked
 148  * via this method.
 149  **/
 150 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 151 {
 152         u32 mmngc;
 153
 154         DEBUGFUNC("ixgbe_check_reset_blocked");
 155
 156         /* If we don't have this bit, it can't be blocking */
 157         if (hw->mac.type == ixgbe_mac_82598EB)
 158                 return false;
 159
 160         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 161         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 162                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 163                               "MNG_VETO bit detected.\n");
 164                 return true;
 165         }
 166
 167         return false;
 168 }
 169
 170 /**
 171  *  ixgbe_validate_phy_addr - Determines phy address is valid
 172  *  @hw: pointer to hardware structure
 173  *
 174  **/
 175 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 176 {
 177         u16 phy_id = 0;
 178         bool valid = false;
 179
 180         DEBUGFUNC("ixgbe_validate_phy_addr");
 181
 182         hw->phy.addr = phy_addr;
 183         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 184                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 185
 186         if (phy_id != 0xFFFF && phy_id != 0x0)
 187                 valid = true;
 188
 189         return valid;
 190 }
 191
 192 /**
 193  *  ixgbe_get_phy_id - Get the phy type
 194  *  @hw: pointer to hardware structure
 195  *
 196  **/
 197 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 198 {
 199         u32 status;
 200         u16 phy_id_high = 0;
 201         u16 phy_id_low = 0;
 202
 203         DEBUGFUNC("ixgbe_get_phy_id");
 204
 205         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 206                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 207                                       &phy_id_high);
 208
 209         if (status == IXGBE_SUCCESS) {
 210                 hw->phy.id = (u32)(phy_id_high << 16);
 211                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 212                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 213                                               &phy_id_low);
 214                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 215                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 216         }
 217         return status;
 218 }
 219
 220 /**
 221  *  ixgbe_get_phy_type_from_id - Get the phy type
 222  *  @hw: pointer to hardware structure
 223  *
 224  **/
 225 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 226 {
 227         enum ixgbe_phy_type phy_type;
 228
 229         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 230
 231         switch (phy_id) {
 232         case TN1010_PHY_ID:
 233                 phy_type = ixgbe_phy_tn;
 234                 break;
 235         case X540_PHY_ID:
 236                 phy_type = ixgbe_phy_aq;
 237                 break;
 238         case QT2022_PHY_ID:
 239                 phy_type = ixgbe_phy_qt;
 240                 break;
 241         case ATH_PHY_ID:
 242                 phy_type = ixgbe_phy_nl;
 243                 break;
 244         default:
 245                 phy_type = ixgbe_phy_unknown;
 246                 break;
 247         }
 248
 249         DEBUGOUT1("phy type found is %d\n", phy_type);
 250         return phy_type;
 251 }
 252
 253 /**
 254  *  ixgbe_reset_phy_generic - Performs a PHY reset
 255  *  @hw: pointer to hardware structure
 256  **/
 257 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 258 {
 259         u32 i;
 260         u16 ctrl = 0;
 261         s32 status = IXGBE_SUCCESS;
 262
 263         DEBUGFUNC("ixgbe_reset_phy_generic");
 264
 265         if (hw->phy.type == ixgbe_phy_unknown)
 266                 status = ixgbe_identify_phy_generic(hw);
 267
 268         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 269                 goto out;
 270
 271         /* Don't reset PHY if it's shut down due to overtemp. */
 272         if (!hw->phy.reset_if_overtemp &&
 273             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 274                 goto out;
 275
 276         /* Blocked by MNG FW so bail */
 277         if (ixgbe_check_reset_blocked(hw))
 278                 goto out;
 279
 280         /*
 281          * Perform soft PHY reset to the PHY_XS.
 282          * This will cause a soft reset to the PHY
 283          */
 284         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 285                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 286                               IXGBE_MDIO_PHY_XS_RESET);
 287
 288         /*
 289          * Poll for reset bit to self-clear indicating reset is complete.
 290          * Some PHYs could take up to 3 seconds to complete and need about
 291          * 1.7 usec delay after the reset is complete.
 292          */
 293         for (i = 0; i < 30; i++) {
 294                 msec_delay(100);
 295                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 296                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 297                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 298                         usec_delay(2);
 299                         break;
 300                 }
 301         }
 302
 303         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 304                 status = IXGBE_ERR_RESET_FAILED;
 305                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 306                              "PHY reset polling failed to complete.\n");
 307         }
 308
 309 out:
 310         return status;
 311 }
 312
 313 /**
 314  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 315  *  the SWFW lock
 316  *  @hw: pointer to hardware structure
 317  *  @reg_addr: 32 bit address of PHY register to read
 318  *  @phy_data: Pointer to read data from PHY register
 319  **/
 320 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 321                        u16 *phy_data)
 322 {
 323         u32 i, data, command;
 324
 325         /* Setup and write the address cycle command */
 326         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 327                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 328                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 329                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 330
 331         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 332
 333         /*
 334          * Check every 10 usec to see if the address cycle completed.
 335          * The MDI Command bit will clear when the operation is
 336          * complete
 337          */
 338         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 339                 usec_delay(10);
 340
 341                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 342                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 343                                 break;
 344         }
 345
 346
 347         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 348                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 349                 return IXGBE_ERR_PHY;
 350         }
 351
 352         /*
 353          * Address cycle complete, setup and write the read
 354          * command
 355          */
 356         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 357                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 358                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 359                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 360
 361         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 362
 363         /*
 364          * Check every 10 usec to see if the address cycle
 365          * completed. The MDI Command bit will clear when the
 366          * operation is complete
 367          */
 368         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 369                 usec_delay(10);
 370
 371                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 372                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 373                         break;
 374         }
 375
 376         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 377                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 378                 return IXGBE_ERR_PHY;
 379         }
 380
 381         /*
 382          * Read operation is complete.  Get the data
 383          * from MSRWD
 384          */
 385         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 386         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 387         *phy_data = (u16)(data);
 388
 389         return IXGBE_SUCCESS;
 390 }
 391
 392 /**
 393  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 394  *  using the SWFW lock - this function is needed in most cases
 395  *  @hw: pointer to hardware structure
 396  *  @reg_addr: 32 bit address of PHY register to read
 397  *  @phy_data: Pointer to read data from PHY register
 398  **/
 399 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 400                                u32 device_type, u16 *phy_data)
 401 {
 402         s32 status;
 403         u16 gssr;
 404
 405         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 406
 407         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 408                 gssr = IXGBE_GSSR_PHY1_SM;
 409         else
 410                 gssr = IXGBE_GSSR_PHY0_SM;
 411
 412         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 413                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 414                                                 phy_data);
 415                 hw->mac.ops.release_swfw_sync(hw, gssr);
 416         } else {
 417                 status = IXGBE_ERR_SWFW_SYNC;
 418         }
 419
 420         return status;
 421 }
 422
 423 /**
 424  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 425  *  without SWFW lock
 426  *  @hw: pointer to hardware structure
 427  *  @reg_addr: 32 bit PHY register to write
 428  *  @device_type: 5 bit device type
 429  *  @phy_data: Data to write to the PHY register
 430  **/
 431 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 432                                 u32 device_type, u16 phy_data)
 433 {
 434         u32 i, command;
 435
 436         /* Put the data in the MDI single read and write data register*/
 437         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 438
 439         /* Setup and write the address cycle command */
 440         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 441                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 442                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 443                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 444
 445         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 446
 447         /*
 448          * Check every 10 usec to see if the address cycle completed.
 449          * The MDI Command bit will clear when the operation is
 450          * complete
 451          */
 452         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 453                 usec_delay(10);
 454
 455                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 456                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 457                         break;
 458         }
 459
 460         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 461                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 462                 return IXGBE_ERR_PHY;
 463         }
 464
 465         /*
 466          * Address cycle complete, setup and write the write
 467          * command
 468          */
 469         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 470                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 471                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 472                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 473
 474         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 475
 476         /*
 477          * Check every 10 usec to see if the address cycle
 478          * completed. The MDI Command bit will clear when the
 479          * operation is complete
 480          */
 481         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 482                 usec_delay(10);
 483
 484                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 485                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 486                         break;
 487         }
 488
 489         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 490                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 491                 return IXGBE_ERR_PHY;
 492         }
 493
 494         return IXGBE_SUCCESS;
 495 }
 496
 497 /**
 498  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 499  *  using SWFW lock- this function is needed in most cases
 500  *  @hw: pointer to hardware structure
 501  *  @reg_addr: 32 bit PHY register to write
 502  *  @device_type: 5 bit device type
 503  *  @phy_data: Data to write to the PHY register
 504  **/
 505 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 506                                 u32 device_type, u16 phy_data)
 507 {
 508         s32 status;
 509         u16 gssr;
 510
 511         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 512
 513         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 514                 gssr = IXGBE_GSSR_PHY1_SM;
 515         else
 516                 gssr = IXGBE_GSSR_PHY0_SM;
 517
 518         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 519                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 520                                                  phy_data);
 521                 hw->mac.ops.release_swfw_sync(hw, gssr);
 522         } else {
 523                 status = IXGBE_ERR_SWFW_SYNC;
 524         }
 525
 526         return status;
 527 }
 528
 529 /**
 530  *  ixgbe_setup_phy_link_generic - Set and restart autoneg
 531  *  @hw: pointer to hardware structure
 532  *
 533  *  Restart autonegotiation and PHY and waits for completion.
 534  **/
 535 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 536 {
 537         s32 status = IXGBE_SUCCESS;
 538         u32 time_out;
 539         u32 max_time_out = 10;
 540         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 541         bool autoneg = false;
 542         ixgbe_link_speed speed;
 543
 544         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 545
 546         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 547
 548         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 549                 /* Set or unset auto-negotiation 10G advertisement */
 550                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 551                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 552                                      &autoneg_reg);
 553
 554                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 555                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 556                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 557
 558                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 559                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 560                                       autoneg_reg);
 561         }
 562
 563         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 564                 /* Set or unset auto-negotiation 1G advertisement */
 565                 hw->phy.ops.read_reg(hw,
 566                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 567                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 568                                      &autoneg_reg);
 569
 570                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 571                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 572                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 573
 574                 hw->phy.ops.write_reg(hw,
 575                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 576                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 577                                       autoneg_reg);
 578         }
 579
 580         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 581                 /* Set or unset auto-negotiation 100M advertisement */
 582                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 583                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 584                                      &autoneg_reg);
 585
 586                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 587                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 588                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 589                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 590
 591                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 592                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 593                                       autoneg_reg);
 594         }
 595
 596         /* Blocked by MNG FW so don't reset PHY */
 597         if (ixgbe_check_reset_blocked(hw))
 598                 return status;
 599
 600         /* Restart PHY autonegotiation and wait for completion */
 601         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 602                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 603
 604         autoneg_reg |= IXGBE_MII_RESTART;
 605
 606         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 607                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 608
 609         /* Wait for autonegotiation to finish */
 610         for (time_out = 0; time_out < max_time_out; time_out++) {
 611                 usec_delay(10);
 612                 /* Restart PHY autonegotiation and wait for completion */
 613                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 614                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 615                                               &autoneg_reg);
 616
 617                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 618                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
 619                         break;
 620         }
 621
 622         if (time_out == max_time_out) {
 623                 status = IXGBE_ERR_LINK_SETUP;
 624                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 625                              "PHY autonegotiation time out");
 626         }
 627
 628         return status;
 629 }
 630
 631 /**
 632  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 633  *  @hw: pointer to hardware structure
 634  *  @speed: new link speed
 635  **/
 636 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 637                                        ixgbe_link_speed speed,
 638                                        bool autoneg_wait_to_complete)
 639 {
 640         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 641
 642         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 643
 644         /*
 645          * Clear autoneg_advertised and set new values based on input link
 646          * speed.
 647          */
 648         hw->phy.autoneg_advertised = 0;
 649
 650         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 651                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 652
 653         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 654                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 655
 656         if (speed & IXGBE_LINK_SPEED_100_FULL)
 657                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 658
 659         /* Setup link based on the new speed settings */
 660         hw->phy.ops.setup_link(hw);
 661
 662         return IXGBE_SUCCESS;
 663 }
 664
 665 /**
 666  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 667  *  @hw: pointer to hardware structure
 668  *  @speed: pointer to link speed
 669  *  @autoneg: boolean auto-negotiation value
 670  *
 671  *  Determines the link capabilities by reading the AUTOC register.
 672  **/
 673 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 674                                                ixgbe_link_speed *speed,
 675                                                bool *autoneg)
 676 {
 677         s32 status;
 678         u16 speed_ability;
 679
 680         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 681
 682         *speed = 0;
 683         *autoneg = true;
 684
 685         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 686                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 687                                       &speed_ability);
 688
 689         if (status == IXGBE_SUCCESS) {
 690                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 691                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 692                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 693                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 694                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 695                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 696         }
 697
 698         return status;
 699 }
 700
 701 /**
 702  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 703  *  @hw: pointer to hardware structure
 704  *
 705  *  Reads the VS1 register to determine if link is up and the current speed for
 706  *  the PHY.
 707  **/
 708 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 709                              bool *link_up)
 710 {
 711         s32 status = IXGBE_SUCCESS;
 712         u32 time_out;
 713         u32 max_time_out = 10;
 714         u16 phy_link = 0;
 715         u16 phy_speed = 0;
 716         u16 phy_data = 0;
 717
 718         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 719
 720         /* Initialize speed and link to default case */
 721         *link_up = false;
 722         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 723
 724         /*
 725          * Check current speed and link status of the PHY register.
 726          * This is a vendor specific register and may have to
 727          * be changed for other copper PHYs.
 728          */
 729         for (time_out = 0; time_out < max_time_out; time_out++) {
 730                 usec_delay(10);
 731                 status = hw->phy.ops.read_reg(hw,
 732                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 733                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 734                                         &phy_data);
 735                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 736                 phy_speed = phy_data &
 737                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 738                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 739                         *link_up = true;
 740                         if (phy_speed ==
 741                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 742                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 743                         break;
 744                 }
 745         }
 746
 747         return status;
 748 }
 749
 750 /**
 751  *      ixgbe_setup_phy_link_tnx - Set and restart autoneg
 752  *      @hw: pointer to hardware structure
 753  *
 754  *      Restart autonegotiation and PHY and waits for completion.
 755  **/
 756 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 757 {
 758         s32 status = IXGBE_SUCCESS;
 759         u32 time_out;
 760         u32 max_time_out = 10;
 761         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 762         bool autoneg = false;
 763         ixgbe_link_speed speed;
 764
 765         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
 766
 767         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 768
 769         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 770                 /* Set or unset auto-negotiation 10G advertisement */
 771                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 772                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 773                                      &autoneg_reg);
 774
 775                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 776                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 777                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 778
 779                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 780                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 781                                       autoneg_reg);
 782         }
 783
 784         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 785                 /* Set or unset auto-negotiation 1G advertisement */
 786                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 787                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 788                                      &autoneg_reg);
 789
 790                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 791                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 792                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 793
 794                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 795                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 796                                       autoneg_reg);
 797         }
 798
 799         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 800                 /* Set or unset auto-negotiation 100M advertisement */
 801                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 802                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 803                                      &autoneg_reg);
 804
 805                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
 806                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 807                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 808
 809                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 810                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 811                                       autoneg_reg);
 812         }
 813
 814         /* Blocked by MNG FW so don't reset PHY */
 815         if (ixgbe_check_reset_blocked(hw))
 816                 return status;
 817
 818         /* Restart PHY autonegotiation and wait for completion */
 819         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 820                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 821
 822         autoneg_reg |= IXGBE_MII_RESTART;
 823
 824         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 825                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 826
 827         /* Wait for autonegotiation to finish */
 828         for (time_out = 0; time_out < max_time_out; time_out++) {
 829                 usec_delay(10);
 830                 /* Restart PHY autonegotiation and wait for completion */
 831                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
 832                                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 833                                               &autoneg_reg);
 834
 835                 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
 836                 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE)
 837                         break;
 838         }
 839
 840         if (time_out == max_time_out) {
 841                 status = IXGBE_ERR_LINK_SETUP;
 842                 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
 843         }
 844
 845         return status;
 846 }
 847
 848 /**
 849  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 850  *  @hw: pointer to hardware structure
 851  *  @firmware_version: pointer to the PHY Firmware Version
 852  **/
 853 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 854                                        u16 *firmware_version)
 855 {
 856         s32 status;
 857
 858         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
 859
 860         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 861                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 862                                       firmware_version);
 863
 864         return status;
 865 }
 866
 867 /**
 868  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 869  *  @hw: pointer to hardware structure
 870  *  @firmware_version: pointer to the PHY Firmware Version
 871  **/
 872 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 873                                            u16 *firmware_version)
 874 {
 875         s32 status;
 876
 877         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
 878
 879         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 880                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 881                                       firmware_version);
 882
 883         return status;
 884 }
 885
 886 /**
 887  *  ixgbe_reset_phy_nl - Performs a PHY reset
 888  *  @hw: pointer to hardware structure
 889  **/
 890 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 891 {
 892         u16 phy_offset, control, eword, edata, block_crc;
 893         bool end_data = false;
 894         u16 list_offset, data_offset;
 895         u16 phy_data = 0;
 896         s32 ret_val = IXGBE_SUCCESS;
 897         u32 i;
 898
 899         DEBUGFUNC("ixgbe_reset_phy_nl");
 900
 901         /* Blocked by MNG FW so bail */
 902         if (ixgbe_check_reset_blocked(hw))
 903                 goto out;
 904
 905         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 906                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 907
 908         /* reset the PHY and poll for completion */
 909         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 910                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 911                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
 912
 913         for (i = 0; i < 100; i++) {
 914                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 915                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 916                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
 917                         break;
 918                 msec_delay(10);
 919         }
 920
 921         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
 922                 DEBUGOUT("PHY reset did not complete.\n");
 923                 ret_val = IXGBE_ERR_PHY;
 924                 goto out;
 925         }
 926
 927         /* Get init offsets */
 928         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 929                                                       &data_offset);
 930         if (ret_val != IXGBE_SUCCESS)
 931                 goto out;
 932
 933         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 934         data_offset++;
 935         while (!end_data) {
 936                 /*
 937                  * Read control word from PHY init contents offset
 938                  */
 939                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 940                 if (ret_val)
 941                         goto err_eeprom;
 942                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 943                            IXGBE_CONTROL_SHIFT_NL;
 944                 edata = eword & IXGBE_DATA_MASK_NL;
 945                 switch (control) {
 946                 case IXGBE_DELAY_NL:
 947                         data_offset++;
 948                         DEBUGOUT1("DELAY: %d MS\n", edata);
 949                         msec_delay(edata);
 950                         break;
 951                 case IXGBE_DATA_NL:
 952                         DEBUGOUT("DATA:\n");
 953                         data_offset++;
 954                         ret_val = hw->eeprom.ops.read(hw, data_offset,
 955                                                       &phy_offset);
 956                         if (ret_val)
 957                                 goto err_eeprom;
 958                         data_offset++;
 959                         for (i = 0; i < edata; i++) {
 960                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
 961                                                               &eword);
 962                                 if (ret_val)
 963                                         goto err_eeprom;
 964                                 hw->phy.ops.write_reg(hw, phy_offset,
 965                                                       IXGBE_TWINAX_DEV, eword);
 966                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
 967                                           phy_offset);
 968                                 data_offset++;
 969                                 phy_offset++;
 970                         }
 971                         break;
 972                 case IXGBE_CONTROL_NL:
 973                         data_offset++;
 974                         DEBUGOUT("CONTROL:\n");
 975                         if (edata == IXGBE_CONTROL_EOL_NL) {
 976                                 DEBUGOUT("EOL\n");
 977                                 end_data = true;
 978                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 979                                 DEBUGOUT("SOL\n");
 980                         } else {
 981                                 DEBUGOUT("Bad control value\n");
 982                                 ret_val = IXGBE_ERR_PHY;
 983                                 goto out;
 984                         }
 985                         break;
 986                 default:
 987                         DEBUGOUT("Bad control type\n");
 988                         ret_val = IXGBE_ERR_PHY;
 989                         goto out;
 990                 }
 991         }
 992
 993 out:
 994         return ret_val;
 995
 996 err_eeprom:
 997         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 998                       "eeprom read at offset %d failed", data_offset);
 999         return IXGBE_ERR_PHY;
1000 }
1001
1002 /**
1003  *  ixgbe_identify_module_generic - Identifies module type
1004  *  @hw: pointer to hardware structure
1005  *
1006  *  Determines HW type and calls appropriate function.
1007  **/
1008 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1009 {
1010         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1011
1012         DEBUGFUNC("ixgbe_identify_module_generic");
1013
1014         switch (hw->mac.ops.get_media_type(hw)) {
1015         case ixgbe_media_type_fiber:
1016                 status = ixgbe_identify_sfp_module_generic(hw);
1017                 break;
1018
1019
1020         default:
1021                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1022                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1023                 break;
1024         }
1025
1026         return status;
1027 }
1028
1029 /**
1030  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1031  *  @hw: pointer to hardware structure
1032  *
1033  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1034  **/
1035 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1036 {
1037         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1038         u32 vendor_oui = 0;
1039         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1040         u8 identifier = 0;
1041         u8 comp_codes_1g = 0;
1042         u8 comp_codes_10g = 0;
1043         u8 oui_bytes[3] = {0, 0, 0};
1044         u8 cable_tech = 0;
1045         u8 cable_spec = 0;
1046         u16 enforce_sfp = 0;
1047
1048         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1049
1050         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1051                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1052                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1053                 goto out;
1054         }
1055
1056         status = hw->phy.ops.read_i2c_eeprom(hw,
1057                                              IXGBE_SFF_IDENTIFIER,
1058                                              &identifier);
1059
1060         if (status != IXGBE_SUCCESS)
1061                 goto err_read_i2c_eeprom;
1062
1063         /* LAN ID is needed for sfp_type determination */
1064         hw->mac.ops.set_lan_id(hw);
1065
1066         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1067                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1068                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1069         } else {
1070                 status = hw->phy.ops.read_i2c_eeprom(hw,
1071                                                      IXGBE_SFF_1GBE_COMP_CODES,
1072                                                      &comp_codes_1g);
1073
1074                 if (status != IXGBE_SUCCESS)
1075                         goto err_read_i2c_eeprom;
1076
1077                 status = hw->phy.ops.read_i2c_eeprom(hw,
1078                                                      IXGBE_SFF_10GBE_COMP_CODES,
1079                                                      &comp_codes_10g);
1080
1081                 if (status != IXGBE_SUCCESS)
1082                         goto err_read_i2c_eeprom;
1083                 status = hw->phy.ops.read_i2c_eeprom(hw,
1084                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1085                                                      &cable_tech);
1086
1087                 if (status != IXGBE_SUCCESS)
1088                         goto err_read_i2c_eeprom;
1089
1090                  /* ID Module
1091                   * =========
1092                   * 0   SFP_DA_CU
1093                   * 1   SFP_SR
1094                   * 2   SFP_LR
1095                   * 3   SFP_DA_CORE0 - 82599-specific
1096                   * 4   SFP_DA_CORE1 - 82599-specific
1097                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1098                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1099                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1100                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1101                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1102                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1103                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1104                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1105                   */
1106                 if (hw->mac.type == ixgbe_mac_82598EB) {
1107                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1108                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1109                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1110                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1111                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1112                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1113                         else
1114                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1115                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1116                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1117                                 if (hw->bus.lan_id == 0)
1118                                         hw->phy.sfp_type =
1119                                                      ixgbe_sfp_type_da_cu_core0;
1120                                 else
1121                                         hw->phy.sfp_type =
1122                                                      ixgbe_sfp_type_da_cu_core1;
1123                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1124                                 hw->phy.ops.read_i2c_eeprom(
1125                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1126                                                 &cable_spec);
1127                                 if (cable_spec &
1128                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1129                                         if (hw->bus.lan_id == 0)
1130                                                 hw->phy.sfp_type =
1131                                                 ixgbe_sfp_type_da_act_lmt_core0;
1132                                         else
1133                                                 hw->phy.sfp_type =
1134                                                 ixgbe_sfp_type_da_act_lmt_core1;
1135                                 } else {
1136                                         hw->phy.sfp_type =
1137                                                         ixgbe_sfp_type_unknown;
1138                                 }
1139                         } else if (comp_codes_10g &
1140                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1141                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1142                                 if (hw->bus.lan_id == 0)
1143                                         hw->phy.sfp_type =
1144                                                       ixgbe_sfp_type_srlr_core0;
1145                                 else
1146                                         hw->phy.sfp_type =
1147                                                       ixgbe_sfp_type_srlr_core1;
1148 #ifdef SUPPORT_10GBASE_ER
1149                         } else if (comp_codes_10g &
1150                                    IXGBE_SFF_10GBASEER_CAPABLE) {
1151                                 if (hw->bus.lan_id == 0)
1152                                         hw->phy.sfp_type =
1153                                                         ixgbe_sfp_type_er_core0;
1154                                 else
1155                                         hw->phy.sfp_type =
1156                                                         ixgbe_sfp_type_er_core1;
1157 #endif /* SUPPORT_10GBASE_ER */
1158                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1159                                 if (hw->bus.lan_id == 0)
1160                                         hw->phy.sfp_type =
1161                                                 ixgbe_sfp_type_1g_cu_core0;
1162                                 else
1163                                         hw->phy.sfp_type =
1164                                                 ixgbe_sfp_type_1g_cu_core1;
1165                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1166                                 if (hw->bus.lan_id == 0)
1167                                         hw->phy.sfp_type =
1168                                                 ixgbe_sfp_type_1g_sx_core0;
1169                                 else
1170                                         hw->phy.sfp_type =
1171                                                 ixgbe_sfp_type_1g_sx_core1;
1172 #ifdef SUPPORT_1000BASE_LX
1173                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1174                                 if (hw->bus.lan_id == 0)
1175                                         hw->phy.sfp_type =
1176                                                 ixgbe_sfp_type_1g_lx_core0;
1177                                 else
1178                                         hw->phy.sfp_type =
1179                                                 ixgbe_sfp_type_1g_lx_core1;
1180 #endif /* SUPPORT_1000BASE_LX */
1181                         } else {
1182                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1183                         }
1184                 }
1185
1186                 if (hw->phy.sfp_type != stored_sfp_type)
1187                         hw->phy.sfp_setup_needed = true;
1188
1189                 /* Determine if the SFP+ PHY is dual speed or not. */
1190                 hw->phy.multispeed_fiber = false;
1191                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1192                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1193                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1194                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1195                         hw->phy.multispeed_fiber = true;
1196
1197                 /* Determine PHY vendor */
1198                 if (hw->phy.type != ixgbe_phy_nl) {
1199                         hw->phy.id = identifier;
1200                         status = hw->phy.ops.read_i2c_eeprom(hw,
1201                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1202                                                     &oui_bytes[0]);
1203
1204                         if (status != IXGBE_SUCCESS)
1205                                 goto err_read_i2c_eeprom;
1206
1207                         status = hw->phy.ops.read_i2c_eeprom(hw,
1208                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1209                                                     &oui_bytes[1]);
1210
1211                         if (status != IXGBE_SUCCESS)
1212                                 goto err_read_i2c_eeprom;
1213
1214                         status = hw->phy.ops.read_i2c_eeprom(hw,
1215                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1216                                                     &oui_bytes[2]);
1217
1218                         if (status != IXGBE_SUCCESS)
1219                                 goto err_read_i2c_eeprom;
1220
1221                         vendor_oui =
1222                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1223                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1224                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1225
1226                         switch (vendor_oui) {
1227                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1228                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1229                                         hw->phy.type =
1230                                                     ixgbe_phy_sfp_passive_tyco;
1231                                 break;
1232                         case IXGBE_SFF_VENDOR_OUI_FTL:
1233                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1234                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1235                                 else
1236                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1237                                 break;
1238                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1239                                 hw->phy.type = ixgbe_phy_sfp_avago;
1240                                 break;
1241                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1242                                 hw->phy.type = ixgbe_phy_sfp_intel;
1243                                 break;
1244                         default:
1245                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1246                                         hw->phy.type =
1247                                                  ixgbe_phy_sfp_passive_unknown;
1248                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1249                                         hw->phy.type =
1250                                                 ixgbe_phy_sfp_active_unknown;
1251                                 else
1252                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1253                                 break;
1254                         }
1255                 }
1256
1257                 /* Allow any DA cable vendor */
1258                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1259                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1260                         status = IXGBE_SUCCESS;
1261                         goto out;
1262                 }
1263
1264                 /* Verify supported 1G SFP modules */
1265                 if (comp_codes_10g == 0 &&
1266                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1267                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1268 #ifdef SUPPORT_1000BASE_LX
1269                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1270                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1271 #endif
1272                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1273                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1274                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1275                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1276                         goto out;
1277                 }
1278
1279                 /* Anything else 82598-based is supported */
1280                 if (hw->mac.type == ixgbe_mac_82598EB) {
1281                         status = IXGBE_SUCCESS;
1282                         goto out;
1283                 }
1284
1285                 ixgbe_get_device_caps(hw, &enforce_sfp);
1286                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1287                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1288                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1289 #ifdef SUPPORT_1000BASE_LX
1290                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1291                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1292 #endif
1293 #ifdef SUPPORT_10GBASE_ER
1294                       hw->phy.sfp_type == ixgbe_sfp_type_er_core0 ||
1295                       hw->phy.sfp_type == ixgbe_sfp_type_er_core1 ||
1296 #endif
1297                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1298                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1299                         /* Make sure we're a supported PHY type */
1300                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1301                                 status = IXGBE_SUCCESS;
1302                         } else {
1303                                 if (hw->allow_unsupported_sfp == true) {
1304                                         EWARN(hw, "WARNING: Intel (R) Network "
1305                                               "Connections are quality tested "
1306                                               "using Intel (R) Ethernet Optics."
1307                                               " Using untested modules is not "
1308                                               "supported and may cause unstable"
1309                                               " operation or damage to the "
1310                                               "module or the adapter. Intel "
1311                                               "Corporation is not responsible "
1312                                               "for any harm caused by using "
1313                                               "untested modules.\n", status);
1314                                         status = IXGBE_SUCCESS;
1315                                 } else {
1316                                         DEBUGOUT("SFP+ module not supported\n");
1317                                         hw->phy.type =
1318                                                 ixgbe_phy_sfp_unsupported;
1319                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1320                                 }
1321                         }
1322                 } else {
1323                         status = IXGBE_SUCCESS;
1324                 }
1325         }
1326
1327 out:
1328         return status;
1329
1330 err_read_i2c_eeprom:
1331         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1332         if (hw->phy.type != ixgbe_phy_nl) {
1333                 hw->phy.id = 0;
1334                 hw->phy.type = ixgbe_phy_unknown;
1335         }
1336         return IXGBE_ERR_SFP_NOT_PRESENT;
1337 }
1338
1339
1340
1341 /**
1342  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1343  *  @hw: pointer to hardware structure
1344  *  @list_offset: offset to the SFP ID list
1345  *  @data_offset: offset to the SFP data block
1346  *
1347  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1348  *  so it returns the offsets to the phy init sequence block.
1349  **/
1350 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1351                                         u16 *list_offset,
1352                                         u16 *data_offset)
1353 {
1354         u16 sfp_id;
1355         u16 sfp_type = hw->phy.sfp_type;
1356
1357         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1358
1359         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1360                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1361
1362         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1363                 return IXGBE_ERR_SFP_NOT_PRESENT;
1364
1365         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1366             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1367                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1368
1369         /*
1370          * Limiting active cables and 1G Phys must be initialized as
1371          * SR modules
1372          */
1373         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1374 #ifdef SUPPORT_10GBASE_ER
1375             sfp_type == ixgbe_sfp_type_er_core0 ||
1376 #endif /* SUPPORT_10GBASE_ER */
1377 #ifdef SUPPORT_1000BASE_LX
1378             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1379 #endif /* SUPPORT_1000BASE_LX */
1380             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1381             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1382                 sfp_type = ixgbe_sfp_type_srlr_core0;
1383         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1384 #ifdef SUPPORT_10GBASE_ER
1385                  sfp_type == ixgbe_sfp_type_er_core1 ||
1386 #endif /* SUPPORT_10GBASE_ER */
1387 #ifdef SUPPORT_1000BASE_LX
1388                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1389 #endif /* SUPPORT_1000BASE_LX */
1390                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1391                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1392                 sfp_type = ixgbe_sfp_type_srlr_core1;
1393
1394         /* Read offset to PHY init contents */
1395         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1396                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1397                               "eeprom read at offset %d failed",
1398                               IXGBE_PHY_INIT_OFFSET_NL);
1399                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1400         }
1401
1402         if ((!*list_offset) || (*list_offset == 0xFFFF))
1403                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1404
1405         /* Shift offset to first ID word */
1406         (*list_offset)++;
1407
1408         /*
1409          * Find the matching SFP ID in the EEPROM
1410          * and program the init sequence
1411          */
1412         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1413                 goto err_phy;
1414
1415         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1416                 if (sfp_id == sfp_type) {
1417                         (*list_offset)++;
1418                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1419                                 goto err_phy;
1420                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1421                                 DEBUGOUT("SFP+ module not supported\n");
1422                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1423                         } else {
1424                                 break;
1425                         }
1426                 } else {
1427                         (*list_offset) += 2;
1428                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1429                                 goto err_phy;
1430                 }
1431         }
1432
1433         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1434                 DEBUGOUT("No matching SFP+ module found\n");
1435                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1436         }
1437
1438         return IXGBE_SUCCESS;
1439
1440 err_phy:
1441         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1442                       "eeprom read at offset %d failed", *list_offset);
1443         return IXGBE_ERR_PHY;
1444 }
1445
1446 /**
1447  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1448  *  @hw: pointer to hardware structure
1449  *  @byte_offset: EEPROM byte offset to read
1450  *  @eeprom_data: value read
1451  *
1452  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1453  **/
1454 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1455                                   u8 *eeprom_data)
1456 {
1457         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1458
1459         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1460                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1461                                          eeprom_data);
1462 }
1463
1464 /**
1465  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1466  *  @hw: pointer to hardware structure
1467  *  @byte_offset: EEPROM byte offset to write
1468  *  @eeprom_data: value to write
1469  *
1470  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1471  **/
1472 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1473                                    u8 eeprom_data)
1474 {
1475         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1476
1477         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1478                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1479                                           eeprom_data);
1480 }
1481
1482 /**
1483  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1484  *  @hw: pointer to hardware structure
1485  *  @byte_offset: byte offset to read
1486  *  @data: value read
1487  *
1488  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1489  *  a specified device address.
1490  **/
1491 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1492                                 u8 dev_addr, u8 *data)
1493 {
1494         s32 status = IXGBE_SUCCESS;
1495         u32 max_retry = 10;
1496         u32 retry = 0;
1497         u16 swfw_mask = 0;
1498         bool nack = 1;
1499         *data = 0;
1500
1501         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1502
1503         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1504                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1505         else
1506                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1507
1508         do {
1509                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1510                     != IXGBE_SUCCESS) {
1511                         status = IXGBE_ERR_SWFW_SYNC;
1512                         goto read_byte_out;
1513                 }
1514
1515                 ixgbe_i2c_start(hw);
1516
1517                 /* Device Address and write indication */
1518                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1519                 if (status != IXGBE_SUCCESS)
1520                         goto fail;
1521
1522                 status = ixgbe_get_i2c_ack(hw);
1523                 if (status != IXGBE_SUCCESS)
1524                         goto fail;
1525
1526                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1527                 if (status != IXGBE_SUCCESS)
1528                         goto fail;
1529
1530                 status = ixgbe_get_i2c_ack(hw);
1531                 if (status != IXGBE_SUCCESS)
1532                         goto fail;
1533
1534                 ixgbe_i2c_start(hw);
1535
1536                 /* Device Address and read indication */
1537                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1538                 if (status != IXGBE_SUCCESS)
1539                         goto fail;
1540
1541                 status = ixgbe_get_i2c_ack(hw);
1542                 if (status != IXGBE_SUCCESS)
1543                         goto fail;
1544
1545                 status = ixgbe_clock_in_i2c_byte(hw, data);
1546                 if (status != IXGBE_SUCCESS)
1547                         goto fail;
1548
1549                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1550                 if (status != IXGBE_SUCCESS)
1551                         goto fail;
1552
1553                 ixgbe_i2c_stop(hw);
1554                 break;
1555
1556 fail:
1557                 ixgbe_i2c_bus_clear(hw);
1558                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1559                 msec_delay(100);
1560                 retry++;
1561                 if (retry < max_retry)
1562                         DEBUGOUT("I2C byte read error - Retrying.\n");
1563                 else
1564                         DEBUGOUT("I2C byte read error.\n");
1565
1566         } while (retry < max_retry);
1567
1568         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1569
1570 read_byte_out:
1571         return status;
1572 }
1573
1574 /**
1575  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1576  *  @hw: pointer to hardware structure
1577  *  @byte_offset: byte offset to write
1578  *  @data: value to write
1579  *
1580  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1581  *  a specified device address.
1582  **/
1583 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1584                                  u8 dev_addr, u8 data)
1585 {
1586         s32 status = IXGBE_SUCCESS;
1587         u32 max_retry = 1;
1588         u32 retry = 0;
1589         u16 swfw_mask = 0;
1590
1591         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1592
1593         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1594                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1595         else
1596                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1597
1598         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1599                 status = IXGBE_ERR_SWFW_SYNC;
1600                 goto write_byte_out;
1601         }
1602
1603         do {
1604                 ixgbe_i2c_start(hw);
1605
1606                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1607                 if (status != IXGBE_SUCCESS)
1608                         goto fail;
1609
1610                 status = ixgbe_get_i2c_ack(hw);
1611                 if (status != IXGBE_SUCCESS)
1612                         goto fail;
1613
1614                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1615                 if (status != IXGBE_SUCCESS)
1616                         goto fail;
1617
1618                 status = ixgbe_get_i2c_ack(hw);
1619                 if (status != IXGBE_SUCCESS)
1620                         goto fail;
1621
1622                 status = ixgbe_clock_out_i2c_byte(hw, data);
1623                 if (status != IXGBE_SUCCESS)
1624                         goto fail;
1625
1626                 status = ixgbe_get_i2c_ack(hw);
1627                 if (status != IXGBE_SUCCESS)
1628                         goto fail;
1629
1630                 ixgbe_i2c_stop(hw);
1631                 break;
1632
1633 fail:
1634                 ixgbe_i2c_bus_clear(hw);
1635                 retry++;
1636                 if (retry < max_retry)
1637                         DEBUGOUT("I2C byte write error - Retrying.\n");
1638                 else
1639                         DEBUGOUT("I2C byte write error.\n");
1640         } while (retry < max_retry);
1641
1642         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1643
1644 write_byte_out:
1645         return status;
1646 }
1647
1648 /**
1649  *  ixgbe_i2c_start - Sets I2C start condition
1650  *  @hw: pointer to hardware structure
1651  *
1652  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1653  **/
1654 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
1655 {
1656         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1657
1658         DEBUGFUNC("ixgbe_i2c_start");
1659
1660         /* Start condition must begin with data and clock high */
1661         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1662         ixgbe_raise_i2c_clk(hw, &i2cctl);
1663
1664         /* Setup time for start condition (4.7us) */
1665         usec_delay(IXGBE_I2C_T_SU_STA);
1666
1667         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1668
1669         /* Hold time for start condition (4us) */
1670         usec_delay(IXGBE_I2C_T_HD_STA);
1671
1672         ixgbe_lower_i2c_clk(hw, &i2cctl);
1673
1674         /* Minimum low period of clock is 4.7 us */
1675         usec_delay(IXGBE_I2C_T_LOW);
1676
1677 }
1678
1679 /**
1680  *  ixgbe_i2c_stop - Sets I2C stop condition
1681  *  @hw: pointer to hardware structure
1682  *
1683  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1684  **/
1685 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1686 {
1687         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1688
1689         DEBUGFUNC("ixgbe_i2c_stop");
1690
1691         /* Stop condition must begin with data low and clock high */
1692         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1693         ixgbe_raise_i2c_clk(hw, &i2cctl);
1694
1695         /* Setup time for stop condition (4us) */
1696         usec_delay(IXGBE_I2C_T_SU_STO);
1697
1698         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1699
1700         /* bus free time between stop and start (4.7us)*/
1701         usec_delay(IXGBE_I2C_T_BUF);
1702 }
1703
1704 /**
1705  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1706  *  @hw: pointer to hardware structure
1707  *  @data: data byte to clock in
1708  *
1709  *  Clocks in one byte data via I2C data/clock
1710  **/
1711 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1712 {
1713         s32 i;
1714         bool bit = 0;
1715
1716         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1717
1718         for (i = 7; i >= 0; i--) {
1719                 ixgbe_clock_in_i2c_bit(hw, &bit);
1720                 *data |= bit << i;
1721         }
1722
1723         return IXGBE_SUCCESS;
1724 }
1725
1726 /**
1727  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1728  *  @hw: pointer to hardware structure
1729  *  @data: data byte clocked out
1730  *
1731  *  Clocks out one byte data via I2C data/clock
1732  **/
1733 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1734 {
1735         s32 status = IXGBE_SUCCESS;
1736         s32 i;
1737         u32 i2cctl;
1738         bool bit;
1739
1740         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1741
1742         for (i = 7; i >= 0; i--) {
1743                 bit = (data >> i) & 0x1;
1744                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1745
1746                 if (status != IXGBE_SUCCESS)
1747                         break;
1748         }
1749
1750         /* Release SDA line (set high) */
1751         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1752         i2cctl |= IXGBE_I2C_DATA_OUT;
1753         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1754         IXGBE_WRITE_FLUSH(hw);
1755
1756         return status;
1757 }
1758
1759 /**
1760  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1761  *  @hw: pointer to hardware structure
1762  *
1763  *  Clocks in/out one bit via I2C data/clock
1764  **/
1765 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1766 {
1767         s32 status = IXGBE_SUCCESS;
1768         u32 i = 0;
1769         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1770         u32 timeout = 10;
1771         bool ack = 1;
1772
1773         DEBUGFUNC("ixgbe_get_i2c_ack");
1774
1775         ixgbe_raise_i2c_clk(hw, &i2cctl);
1776
1777
1778         /* Minimum high period of clock is 4us */
1779         usec_delay(IXGBE_I2C_T_HIGH);
1780
1781         /* Poll for ACK.  Note that ACK in I2C spec is
1782          * transition from 1 to 0 */
1783         for (i = 0; i < timeout; i++) {
1784                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1785                 ack = ixgbe_get_i2c_data(&i2cctl);
1786
1787                 usec_delay(1);
1788                 if (ack == 0)
1789                         break;
1790         }
1791
1792         if (ack == 1) {
1793                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1794                              "I2C ack was not received.\n");
1795                 status = IXGBE_ERR_I2C;
1796         }
1797
1798         ixgbe_lower_i2c_clk(hw, &i2cctl);
1799
1800         /* Minimum low period of clock is 4.7 us */
1801         usec_delay(IXGBE_I2C_T_LOW);
1802
1803         return status;
1804 }
1805
1806 /**
1807  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1808  *  @hw: pointer to hardware structure
1809  *  @data: read data value
1810  *
1811  *  Clocks in one bit via I2C data/clock
1812  **/
1813 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1814 {
1815         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1816
1817         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1818
1819         ixgbe_raise_i2c_clk(hw, &i2cctl);
1820
1821         /* Minimum high period of clock is 4us */
1822         usec_delay(IXGBE_I2C_T_HIGH);
1823
1824         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1825         *data = ixgbe_get_i2c_data(&i2cctl);
1826
1827         ixgbe_lower_i2c_clk(hw, &i2cctl);
1828
1829         /* Minimum low period of clock is 4.7 us */
1830         usec_delay(IXGBE_I2C_T_LOW);
1831
1832         return IXGBE_SUCCESS;
1833 }
1834
1835 /**
1836  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1837  *  @hw: pointer to hardware structure
1838  *  @data: data value to write
1839  *
1840  *  Clocks out one bit via I2C data/clock
1841  **/
1842 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1843 {
1844         s32 status;
1845         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1846
1847         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1848
1849         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1850         if (status == IXGBE_SUCCESS) {
1851                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1852
1853                 /* Minimum high period of clock is 4us */
1854                 usec_delay(IXGBE_I2C_T_HIGH);
1855
1856                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1857
1858                 /* Minimum low period of clock is 4.7 us.
1859                  * This also takes care of the data hold time.
1860                  */
1861                 usec_delay(IXGBE_I2C_T_LOW);
1862         } else {
1863                 status = IXGBE_ERR_I2C;
1864                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1865                              "I2C data was not set to %X\n", data);
1866         }
1867
1868         return status;
1869 }
1870 /**
1871  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1872  *  @hw: pointer to hardware structure
1873  *  @i2cctl: Current value of I2CCTL register
1874  *
1875  *  Raises the I2C clock line '0'->'1'
1876  **/
1877 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1878 {
1879         u32 i = 0;
1880         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1881         u32 i2cctl_r = 0;
1882
1883         DEBUGFUNC("ixgbe_raise_i2c_clk");
1884
1885         for (i = 0; i < timeout; i++) {
1886                 *i2cctl |= IXGBE_I2C_CLK_OUT;
1887
1888                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1889                 IXGBE_WRITE_FLUSH(hw);
1890                 /* SCL rise time (1000ns) */
1891                 usec_delay(IXGBE_I2C_T_RISE);
1892
1893                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1894                 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1895                         break;
1896         }
1897 }
1898
1899 /**
1900  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1901  *  @hw: pointer to hardware structure
1902  *  @i2cctl: Current value of I2CCTL register
1903  *
1904  *  Lowers the I2C clock line '1'->'0'
1905  **/
1906 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1907 {
1908
1909         DEBUGFUNC("ixgbe_lower_i2c_clk");
1910
1911         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1912
1913         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1914         IXGBE_WRITE_FLUSH(hw);
1915
1916         /* SCL fall time (300ns) */
1917         usec_delay(IXGBE_I2C_T_FALL);
1918 }
1919
1920 /**
1921  *  ixgbe_set_i2c_data - Sets the I2C data bit
1922  *  @hw: pointer to hardware structure
1923  *  @i2cctl: Current value of I2CCTL register
1924  *  @data: I2C data value (0 or 1) to set
1925  *
1926  *  Sets the I2C data bit
1927  **/
1928 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1929 {
1930         s32 status = IXGBE_SUCCESS;
1931
1932         DEBUGFUNC("ixgbe_set_i2c_data");
1933
1934         if (data)
1935                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1936         else
1937                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1938
1939         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1940         IXGBE_WRITE_FLUSH(hw);
1941
1942         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1943         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1944
1945         /* Verify data was set correctly */
1946         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1947         if (data != ixgbe_get_i2c_data(i2cctl)) {
1948                 status = IXGBE_ERR_I2C;
1949                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1950                              "Error - I2C data was not set to %X.\n",
1951                              data);
1952         }
1953
1954         return status;
1955 }
1956
1957 /**
1958  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1959  *  @hw: pointer to hardware structure
1960  *  @i2cctl: Current value of I2CCTL register
1961  *
1962  *  Returns the I2C data bit value
1963  **/
1964 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl)
1965 {
1966         bool data;
1967
1968         DEBUGFUNC("ixgbe_get_i2c_data");
1969
1970         if (*i2cctl & IXGBE_I2C_DATA_IN)
1971                 data = 1;
1972         else
1973                 data = 0;
1974
1975         return data;
1976 }
1977
1978 /**
1979  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1980  *  @hw: pointer to hardware structure
1981  *
1982  *  Clears the I2C bus by sending nine clock pulses.
1983  *  Used when data line is stuck low.
1984  **/
1985 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1986 {
1987         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1988         u32 i;
1989
1990         DEBUGFUNC("ixgbe_i2c_bus_clear");
1991
1992         ixgbe_i2c_start(hw);
1993
1994         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1995
1996         for (i = 0; i < 9; i++) {
1997                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1998
1999                 /* Min high period of clock is 4us */
2000                 usec_delay(IXGBE_I2C_T_HIGH);
2001
2002                 ixgbe_lower_i2c_clk(hw, &i2cctl);
2003
2004                 /* Min low period of clock is 4.7us*/
2005                 usec_delay(IXGBE_I2C_T_LOW);
2006         }
2007
2008         ixgbe_i2c_start(hw);
2009
2010         /* Put the i2c bus back to default state */
2011         ixgbe_i2c_stop(hw);
2012 }
2013
2014 /**
2015  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2016  *  @hw: pointer to hardware structure
2017  *
2018  *  Checks if the LASI temp alarm status was triggered due to overtemp
2019  **/
2020 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2021 {
2022         s32 status = IXGBE_SUCCESS;
2023         u16 phy_data = 0;
2024
2025         DEBUGFUNC("ixgbe_tn_check_overtemp");
2026
2027         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2028                 goto out;
2029
2030         /* Check that the LASI temp alarm status was triggered */
2031         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2032                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2033
2034         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2035                 goto out;
2036
2037         status = IXGBE_ERR_OVERTEMP;
2038         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2039 out:
2040         return status;
2041 }