1 /*******************************************************************************
3 Copyright (c) 2001-2014, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ***************************************************************************/
34 #include "ixgbe_api.h"
35 #include "ixgbe_common.h"
36 #include "ixgbe_phy.h"
38 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
39 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
40 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
41 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
42 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
43 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
44 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
45 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
46 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
48 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
49 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
53 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
54 * @hw: pointer to the hardware structure
57 * Returns an error code on error.
59 STATIC s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
63 status = ixgbe_clock_out_i2c_byte(hw, byte);
66 return ixgbe_get_i2c_ack(hw);
70 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
71 * @hw: pointer to the hardware structure
72 * @byte: pointer to a u8 to receive the byte
74 * Returns an error code on error.
76 STATIC s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
80 status = ixgbe_clock_in_i2c_byte(hw, byte);
84 return ixgbe_clock_out_i2c_bit(hw, false);
88 * ixgbe_ones_comp_byte_add - Perform one's complement addition
92 * Returns one's complement 8-bit sum.
94 STATIC u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
96 u16 sum = add1 + add2;
98 sum = (sum & 0xFF) + (sum >> 8);
103 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation
104 * @hw: pointer to the hardware structure
105 * @addr: I2C bus address to read from
106 * @reg: I2C device register to read from
107 * @val: pointer to location to receive read value
109 * Returns an error code on error.
111 STATIC s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr,
114 u32 swfw_mask = hw->phy.phy_semaphore_mask;
123 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */
124 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
127 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
128 return IXGBE_ERR_SWFW_SYNC;
130 /* Device Address and write indication */
131 if (ixgbe_out_i2c_byte_ack(hw, addr))
133 /* Write bits 14:8 */
134 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
137 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
140 if (ixgbe_out_i2c_byte_ack(hw, csum))
142 /* Re-start condition */
144 /* Device Address and read indication */
145 if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
148 if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
151 if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
154 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
157 if (ixgbe_clock_out_i2c_bit(hw, false))
160 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
161 *val = (high_bits << 8) | low_bits;
165 ixgbe_i2c_bus_clear(hw);
166 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
168 if (retry < max_retry)
169 DEBUGOUT("I2C byte read combined error - Retrying.\n");
171 DEBUGOUT("I2C byte read combined error.\n");
172 } while (retry < max_retry);
174 return IXGBE_ERR_I2C;
178 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation
179 * @hw: pointer to the hardware structure
180 * @addr: I2C bus address to write to
181 * @reg: I2C device register to write to
182 * @val: value to write
184 * Returns an error code on error.
186 STATIC s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw,
187 u8 addr, u16 reg, u16 val)
194 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */
195 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
196 csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
197 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
201 /* Device Address and write indication */
202 if (ixgbe_out_i2c_byte_ack(hw, addr))
204 /* Write bits 14:8 */
205 if (ixgbe_out_i2c_byte_ack(hw, reg_high))
208 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
210 /* Write data 15:8 */
211 if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
214 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
217 if (ixgbe_out_i2c_byte_ack(hw, csum))
223 ixgbe_i2c_bus_clear(hw);
225 if (retry < max_retry)
226 DEBUGOUT("I2C byte write combined error - Retrying.\n");
228 DEBUGOUT("I2C byte write combined error.\n");
229 } while (retry < max_retry);
231 return IXGBE_ERR_I2C;
235 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
236 * @hw: pointer to the hardware structure
238 * Initialize the function pointers.
240 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
242 struct ixgbe_phy_info *phy = &hw->phy;
244 DEBUGFUNC("ixgbe_init_phy_ops_generic");
247 phy->ops.identify = ixgbe_identify_phy_generic;
248 phy->ops.reset = ixgbe_reset_phy_generic;
249 phy->ops.read_reg = ixgbe_read_phy_reg_generic;
250 phy->ops.write_reg = ixgbe_write_phy_reg_generic;
251 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
252 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
253 phy->ops.setup_link = ixgbe_setup_phy_link_generic;
254 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
255 phy->ops.check_link = NULL;
256 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
257 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
258 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
259 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
260 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
261 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
262 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
263 phy->ops.identify_sfp = ixgbe_identify_module_generic;
264 phy->sfp_type = ixgbe_sfp_type_unknown;
265 phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic;
266 phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic;
267 phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
268 return IXGBE_SUCCESS;
272 * ixgbe_identify_phy_generic - Get physical layer module
273 * @hw: pointer to hardware structure
275 * Determines the physical layer module found on the current adapter.
277 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
279 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
283 DEBUGFUNC("ixgbe_identify_phy_generic");
285 if (!hw->phy.phy_semaphore_mask) {
286 hw->phy.lan_id = IXGBE_READ_REG(hw, IXGBE_STATUS) &
287 IXGBE_STATUS_LAN_ID_1;
289 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
291 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
294 if (hw->phy.type == ixgbe_phy_unknown) {
295 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
296 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
297 hw->phy.addr = phy_addr;
298 ixgbe_get_phy_id(hw);
300 ixgbe_get_phy_type_from_id(hw->phy.id);
302 if (hw->phy.type == ixgbe_phy_unknown) {
303 hw->phy.ops.read_reg(hw,
304 IXGBE_MDIO_PHY_EXT_ABILITY,
305 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
308 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
309 IXGBE_MDIO_PHY_1000BASET_ABILITY))
311 ixgbe_phy_cu_unknown;
317 status = IXGBE_SUCCESS;
322 /* Certain media types do not have a phy so an address will not
323 * be found and the code will take this path. Caller has to
324 * decide if it is an error or not.
326 if (status != IXGBE_SUCCESS) {
330 status = IXGBE_SUCCESS;
337 * ixgbe_check_reset_blocked - check status of MNG FW veto bit
338 * @hw: pointer to the hardware structure
340 * This function checks the MMNGC.MNG_VETO bit to see if there are
341 * any constraints on link from manageability. For MAC's that don't
342 * have this bit just return faluse since the link can not be blocked
345 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
349 DEBUGFUNC("ixgbe_check_reset_blocked");
351 /* If we don't have this bit, it can't be blocking */
352 if (hw->mac.type == ixgbe_mac_82598EB)
355 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
356 if (mmngc & IXGBE_MMNGC_MNG_VETO) {
357 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
358 "MNG_VETO bit detected.\n");
366 * ixgbe_validate_phy_addr - Determines phy address is valid
367 * @hw: pointer to hardware structure
370 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
375 DEBUGFUNC("ixgbe_validate_phy_addr");
377 hw->phy.addr = phy_addr;
378 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
379 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
381 if (phy_id != 0xFFFF && phy_id != 0x0)
388 * ixgbe_get_phy_id - Get the phy type
389 * @hw: pointer to hardware structure
392 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
398 DEBUGFUNC("ixgbe_get_phy_id");
400 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
401 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
404 if (status == IXGBE_SUCCESS) {
405 hw->phy.id = (u32)(phy_id_high << 16);
406 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
407 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
409 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
410 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
416 * ixgbe_get_phy_type_from_id - Get the phy type
417 * @hw: pointer to hardware structure
420 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
422 enum ixgbe_phy_type phy_type;
424 DEBUGFUNC("ixgbe_get_phy_type_from_id");
428 phy_type = ixgbe_phy_tn;
432 phy_type = ixgbe_phy_aq;
435 phy_type = ixgbe_phy_qt;
438 phy_type = ixgbe_phy_nl;
441 phy_type = ixgbe_phy_unknown;
445 DEBUGOUT1("phy type found is %d\n", phy_type);
450 * ixgbe_reset_phy_generic - Performs a PHY reset
451 * @hw: pointer to hardware structure
453 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
457 s32 status = IXGBE_SUCCESS;
459 DEBUGFUNC("ixgbe_reset_phy_generic");
461 if (hw->phy.type == ixgbe_phy_unknown)
462 status = ixgbe_identify_phy_generic(hw);
464 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
467 /* Don't reset PHY if it's shut down due to overtemp. */
468 if (!hw->phy.reset_if_overtemp &&
469 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
472 /* Blocked by MNG FW so bail */
473 if (ixgbe_check_reset_blocked(hw))
477 * Perform soft PHY reset to the PHY_XS.
478 * This will cause a soft reset to the PHY
480 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
481 IXGBE_MDIO_PHY_XS_DEV_TYPE,
482 IXGBE_MDIO_PHY_XS_RESET);
485 * Poll for reset bit to self-clear indicating reset is complete.
486 * Some PHYs could take up to 3 seconds to complete and need about
487 * 1.7 usec delay after the reset is complete.
489 for (i = 0; i < 30; i++) {
491 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
492 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
493 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
499 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
500 status = IXGBE_ERR_RESET_FAILED;
501 ERROR_REPORT1(IXGBE_ERROR_POLLING,
502 "PHY reset polling failed to complete.\n");
510 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
512 * @hw: pointer to hardware structure
513 * @reg_addr: 32 bit address of PHY register to read
514 * @phy_data: Pointer to read data from PHY register
516 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
519 u32 i, data, command;
521 /* Setup and write the address cycle command */
522 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
523 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
524 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
525 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
527 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
530 * Check every 10 usec to see if the address cycle completed.
531 * The MDI Command bit will clear when the operation is
534 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
537 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
538 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
543 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
544 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
545 return IXGBE_ERR_PHY;
549 * Address cycle complete, setup and write the read
552 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
553 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
554 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
555 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
557 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
560 * Check every 10 usec to see if the address cycle
561 * completed. The MDI Command bit will clear when the
562 * operation is complete
564 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
567 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
568 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
572 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
573 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
574 return IXGBE_ERR_PHY;
578 * Read operation is complete. Get the data
581 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
582 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
583 *phy_data = (u16)(data);
585 return IXGBE_SUCCESS;
589 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
590 * using the SWFW lock - this function is needed in most cases
591 * @hw: pointer to hardware structure
592 * @reg_addr: 32 bit address of PHY register to read
593 * @phy_data: Pointer to read data from PHY register
595 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
596 u32 device_type, u16 *phy_data)
599 u32 gssr = hw->phy.phy_semaphore_mask;
601 DEBUGFUNC("ixgbe_read_phy_reg_generic");
603 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
604 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
606 hw->mac.ops.release_swfw_sync(hw, gssr);
608 status = IXGBE_ERR_SWFW_SYNC;
615 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
617 * @hw: pointer to hardware structure
618 * @reg_addr: 32 bit PHY register to write
619 * @device_type: 5 bit device type
620 * @phy_data: Data to write to the PHY register
622 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
623 u32 device_type, u16 phy_data)
627 /* Put the data in the MDI single read and write data register*/
628 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
630 /* Setup and write the address cycle command */
631 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
632 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
633 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
634 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
636 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
639 * Check every 10 usec to see if the address cycle completed.
640 * The MDI Command bit will clear when the operation is
643 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
646 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
647 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
651 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
652 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
653 return IXGBE_ERR_PHY;
657 * Address cycle complete, setup and write the write
660 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
661 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
662 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
663 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
665 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
668 * Check every 10 usec to see if the address cycle
669 * completed. The MDI Command bit will clear when the
670 * operation is complete
672 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
675 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
676 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
680 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
681 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
682 return IXGBE_ERR_PHY;
685 return IXGBE_SUCCESS;
689 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
690 * using SWFW lock- this function is needed in most cases
691 * @hw: pointer to hardware structure
692 * @reg_addr: 32 bit PHY register to write
693 * @device_type: 5 bit device type
694 * @phy_data: Data to write to the PHY register
696 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
697 u32 device_type, u16 phy_data)
700 u32 gssr = hw->phy.phy_semaphore_mask;
702 DEBUGFUNC("ixgbe_write_phy_reg_generic");
704 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
705 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
707 hw->mac.ops.release_swfw_sync(hw, gssr);
709 status = IXGBE_ERR_SWFW_SYNC;
716 * ixgbe_setup_phy_link_generic - Set and restart auto-neg
717 * @hw: pointer to hardware structure
719 * Restart auto-negotiation and PHY and waits for completion.
721 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
723 s32 status = IXGBE_SUCCESS;
724 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
725 bool autoneg = false;
726 ixgbe_link_speed speed;
728 DEBUGFUNC("ixgbe_setup_phy_link_generic");
730 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
732 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
733 /* Set or unset auto-negotiation 10G advertisement */
734 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
735 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
738 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
739 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
740 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
742 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
743 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
747 if (hw->mac.type == ixgbe_mac_X550) {
748 if (speed & IXGBE_LINK_SPEED_5GB_FULL) {
749 /* Set or unset auto-negotiation 1G advertisement */
750 hw->phy.ops.read_reg(hw,
751 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
752 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
755 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
756 if (hw->phy.autoneg_advertised &
757 IXGBE_LINK_SPEED_5GB_FULL)
758 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
760 hw->phy.ops.write_reg(hw,
761 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
762 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
766 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) {
767 /* Set or unset auto-negotiation 1G advertisement */
768 hw->phy.ops.read_reg(hw,
769 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
770 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
773 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
774 if (hw->phy.autoneg_advertised &
775 IXGBE_LINK_SPEED_2_5GB_FULL)
776 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
778 hw->phy.ops.write_reg(hw,
779 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
780 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
785 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
786 /* Set or unset auto-negotiation 1G advertisement */
787 hw->phy.ops.read_reg(hw,
788 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
789 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
792 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
793 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
794 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
796 hw->phy.ops.write_reg(hw,
797 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
798 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
802 if (speed & IXGBE_LINK_SPEED_100_FULL) {
803 /* Set or unset auto-negotiation 100M advertisement */
804 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
805 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
808 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
809 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
810 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
811 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
813 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
814 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
818 /* Blocked by MNG FW so don't reset PHY */
819 if (ixgbe_check_reset_blocked(hw))
822 /* Restart PHY auto-negotiation. */
823 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
824 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
826 autoneg_reg |= IXGBE_MII_RESTART;
828 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
829 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
835 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
836 * @hw: pointer to hardware structure
837 * @speed: new link speed
839 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
840 ixgbe_link_speed speed,
841 bool autoneg_wait_to_complete)
843 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
845 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
848 * Clear autoneg_advertised and set new values based on input link
851 hw->phy.autoneg_advertised = 0;
853 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
854 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
856 if (speed & IXGBE_LINK_SPEED_5GB_FULL)
857 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
859 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
860 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
862 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
863 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
865 if (speed & IXGBE_LINK_SPEED_100_FULL)
866 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
868 /* Setup link based on the new speed settings */
869 hw->phy.ops.setup_link(hw);
871 return IXGBE_SUCCESS;
875 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
876 * @hw: pointer to hardware structure
877 * @speed: pointer to link speed
878 * @autoneg: boolean auto-negotiation value
880 * Determines the supported link capabilities by reading the PHY auto
881 * negotiation register.
883 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
884 ixgbe_link_speed *speed,
890 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
895 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
896 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
899 if (status == IXGBE_SUCCESS) {
900 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
901 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
902 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
903 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
904 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
905 *speed |= IXGBE_LINK_SPEED_100_FULL;
908 /* Internal PHY does not support 100 Mbps */
909 if (hw->mac.type == ixgbe_mac_X550EM_x)
910 *speed &= ~IXGBE_LINK_SPEED_100_FULL;
912 if (hw->mac.type == ixgbe_mac_X550) {
913 *speed |= IXGBE_LINK_SPEED_2_5GB_FULL;
914 *speed |= IXGBE_LINK_SPEED_5GB_FULL;
921 * ixgbe_check_phy_link_tnx - Determine link and speed status
922 * @hw: pointer to hardware structure
924 * Reads the VS1 register to determine if link is up and the current speed for
927 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
930 s32 status = IXGBE_SUCCESS;
932 u32 max_time_out = 10;
937 DEBUGFUNC("ixgbe_check_phy_link_tnx");
939 /* Initialize speed and link to default case */
941 *speed = IXGBE_LINK_SPEED_10GB_FULL;
944 * Check current speed and link status of the PHY register.
945 * This is a vendor specific register and may have to
946 * be changed for other copper PHYs.
948 for (time_out = 0; time_out < max_time_out; time_out++) {
950 status = hw->phy.ops.read_reg(hw,
951 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
952 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
954 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
955 phy_speed = phy_data &
956 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
957 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
960 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
961 *speed = IXGBE_LINK_SPEED_1GB_FULL;
970 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg
971 * @hw: pointer to hardware structure
973 * Restart auto-negotiation and PHY and waits for completion.
975 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
977 s32 status = IXGBE_SUCCESS;
978 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
979 bool autoneg = false;
980 ixgbe_link_speed speed;
982 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
984 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
986 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
987 /* Set or unset auto-negotiation 10G advertisement */
988 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
989 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
992 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
993 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
994 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
996 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
997 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1001 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1002 /* Set or unset auto-negotiation 1G advertisement */
1003 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1004 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1007 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1008 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1009 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1011 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1012 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1016 if (speed & IXGBE_LINK_SPEED_100_FULL) {
1017 /* Set or unset auto-negotiation 100M advertisement */
1018 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1019 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1022 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1023 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1024 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1026 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1027 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1031 /* Blocked by MNG FW so don't reset PHY */
1032 if (ixgbe_check_reset_blocked(hw))
1035 /* Restart PHY auto-negotiation. */
1036 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1037 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1039 autoneg_reg |= IXGBE_MII_RESTART;
1041 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1042 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1048 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1049 * @hw: pointer to hardware structure
1050 * @firmware_version: pointer to the PHY Firmware Version
1052 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1053 u16 *firmware_version)
1057 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1059 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1060 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1067 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1068 * @hw: pointer to hardware structure
1069 * @firmware_version: pointer to the PHY Firmware Version
1071 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1072 u16 *firmware_version)
1076 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1078 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1079 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1086 * ixgbe_reset_phy_nl - Performs a PHY reset
1087 * @hw: pointer to hardware structure
1089 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1091 u16 phy_offset, control, eword, edata, block_crc;
1092 bool end_data = false;
1093 u16 list_offset, data_offset;
1095 s32 ret_val = IXGBE_SUCCESS;
1098 DEBUGFUNC("ixgbe_reset_phy_nl");
1100 /* Blocked by MNG FW so bail */
1101 if (ixgbe_check_reset_blocked(hw))
1104 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1105 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1107 /* reset the PHY and poll for completion */
1108 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1109 IXGBE_MDIO_PHY_XS_DEV_TYPE,
1110 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1112 for (i = 0; i < 100; i++) {
1113 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1114 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1115 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1120 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1121 DEBUGOUT("PHY reset did not complete.\n");
1122 ret_val = IXGBE_ERR_PHY;
1126 /* Get init offsets */
1127 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1129 if (ret_val != IXGBE_SUCCESS)
1132 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1136 * Read control word from PHY init contents offset
1138 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1141 control = (eword & IXGBE_CONTROL_MASK_NL) >>
1142 IXGBE_CONTROL_SHIFT_NL;
1143 edata = eword & IXGBE_DATA_MASK_NL;
1145 case IXGBE_DELAY_NL:
1147 DEBUGOUT1("DELAY: %d MS\n", edata);
1151 DEBUGOUT("DATA:\n");
1153 ret_val = hw->eeprom.ops.read(hw, data_offset,
1158 for (i = 0; i < edata; i++) {
1159 ret_val = hw->eeprom.ops.read(hw, data_offset,
1163 hw->phy.ops.write_reg(hw, phy_offset,
1164 IXGBE_TWINAX_DEV, eword);
1165 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1171 case IXGBE_CONTROL_NL:
1173 DEBUGOUT("CONTROL:\n");
1174 if (edata == IXGBE_CONTROL_EOL_NL) {
1177 } else if (edata == IXGBE_CONTROL_SOL_NL) {
1180 DEBUGOUT("Bad control value\n");
1181 ret_val = IXGBE_ERR_PHY;
1186 DEBUGOUT("Bad control type\n");
1187 ret_val = IXGBE_ERR_PHY;
1196 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1197 "eeprom read at offset %d failed", data_offset);
1198 return IXGBE_ERR_PHY;
1202 * ixgbe_identify_module_generic - Identifies module type
1203 * @hw: pointer to hardware structure
1205 * Determines HW type and calls appropriate function.
1207 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1209 s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1211 DEBUGFUNC("ixgbe_identify_module_generic");
1213 switch (hw->mac.ops.get_media_type(hw)) {
1214 case ixgbe_media_type_fiber:
1215 status = ixgbe_identify_sfp_module_generic(hw);
1218 case ixgbe_media_type_fiber_qsfp:
1219 status = ixgbe_identify_qsfp_module_generic(hw);
1223 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1224 status = IXGBE_ERR_SFP_NOT_PRESENT;
1232 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
1233 * @hw: pointer to hardware structure
1235 * Searches for and identifies the SFP module and assigns appropriate PHY type.
1237 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1239 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1241 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1243 u8 comp_codes_1g = 0;
1244 u8 comp_codes_10g = 0;
1245 u8 oui_bytes[3] = {0, 0, 0};
1248 u16 enforce_sfp = 0;
1250 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1252 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1253 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1254 status = IXGBE_ERR_SFP_NOT_PRESENT;
1258 /* LAN ID is needed for I2C access */
1259 hw->mac.ops.set_lan_id(hw);
1261 status = hw->phy.ops.read_i2c_eeprom(hw,
1262 IXGBE_SFF_IDENTIFIER,
1265 if (status != IXGBE_SUCCESS)
1266 goto err_read_i2c_eeprom;
1268 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1269 hw->phy.type = ixgbe_phy_sfp_unsupported;
1270 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1272 status = hw->phy.ops.read_i2c_eeprom(hw,
1273 IXGBE_SFF_1GBE_COMP_CODES,
1276 if (status != IXGBE_SUCCESS)
1277 goto err_read_i2c_eeprom;
1279 status = hw->phy.ops.read_i2c_eeprom(hw,
1280 IXGBE_SFF_10GBE_COMP_CODES,
1283 if (status != IXGBE_SUCCESS)
1284 goto err_read_i2c_eeprom;
1285 status = hw->phy.ops.read_i2c_eeprom(hw,
1286 IXGBE_SFF_CABLE_TECHNOLOGY,
1289 if (status != IXGBE_SUCCESS)
1290 goto err_read_i2c_eeprom;
1297 * 3 SFP_DA_CORE0 - 82599-specific
1298 * 4 SFP_DA_CORE1 - 82599-specific
1299 * 5 SFP_SR/LR_CORE0 - 82599-specific
1300 * 6 SFP_SR/LR_CORE1 - 82599-specific
1301 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
1302 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
1303 * 9 SFP_1g_cu_CORE0 - 82599-specific
1304 * 10 SFP_1g_cu_CORE1 - 82599-specific
1305 * 11 SFP_1g_sx_CORE0 - 82599-specific
1306 * 12 SFP_1g_sx_CORE1 - 82599-specific
1308 if (hw->mac.type == ixgbe_mac_82598EB) {
1309 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1310 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1311 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1312 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1313 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1314 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1316 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1318 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1319 if (hw->bus.lan_id == 0)
1321 ixgbe_sfp_type_da_cu_core0;
1324 ixgbe_sfp_type_da_cu_core1;
1325 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1326 hw->phy.ops.read_i2c_eeprom(
1327 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1330 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1331 if (hw->bus.lan_id == 0)
1333 ixgbe_sfp_type_da_act_lmt_core0;
1336 ixgbe_sfp_type_da_act_lmt_core1;
1339 ixgbe_sfp_type_unknown;
1341 } else if (comp_codes_10g &
1342 (IXGBE_SFF_10GBASESR_CAPABLE |
1343 IXGBE_SFF_10GBASELR_CAPABLE)) {
1344 if (hw->bus.lan_id == 0)
1346 ixgbe_sfp_type_srlr_core0;
1349 ixgbe_sfp_type_srlr_core1;
1350 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1351 if (hw->bus.lan_id == 0)
1353 ixgbe_sfp_type_1g_cu_core0;
1356 ixgbe_sfp_type_1g_cu_core1;
1357 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1358 if (hw->bus.lan_id == 0)
1360 ixgbe_sfp_type_1g_sx_core0;
1363 ixgbe_sfp_type_1g_sx_core1;
1364 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1365 if (hw->bus.lan_id == 0)
1367 ixgbe_sfp_type_1g_lx_core0;
1370 ixgbe_sfp_type_1g_lx_core1;
1372 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1376 if (hw->phy.sfp_type != stored_sfp_type)
1377 hw->phy.sfp_setup_needed = true;
1379 /* Determine if the SFP+ PHY is dual speed or not. */
1380 hw->phy.multispeed_fiber = false;
1381 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1382 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1383 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1384 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1385 hw->phy.multispeed_fiber = true;
1387 /* Determine PHY vendor */
1388 if (hw->phy.type != ixgbe_phy_nl) {
1389 hw->phy.id = identifier;
1390 status = hw->phy.ops.read_i2c_eeprom(hw,
1391 IXGBE_SFF_VENDOR_OUI_BYTE0,
1394 if (status != IXGBE_SUCCESS)
1395 goto err_read_i2c_eeprom;
1397 status = hw->phy.ops.read_i2c_eeprom(hw,
1398 IXGBE_SFF_VENDOR_OUI_BYTE1,
1401 if (status != IXGBE_SUCCESS)
1402 goto err_read_i2c_eeprom;
1404 status = hw->phy.ops.read_i2c_eeprom(hw,
1405 IXGBE_SFF_VENDOR_OUI_BYTE2,
1408 if (status != IXGBE_SUCCESS)
1409 goto err_read_i2c_eeprom;
1412 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1413 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1414 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1416 switch (vendor_oui) {
1417 case IXGBE_SFF_VENDOR_OUI_TYCO:
1418 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1420 ixgbe_phy_sfp_passive_tyco;
1422 case IXGBE_SFF_VENDOR_OUI_FTL:
1423 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1424 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1426 hw->phy.type = ixgbe_phy_sfp_ftl;
1428 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1429 hw->phy.type = ixgbe_phy_sfp_avago;
1431 case IXGBE_SFF_VENDOR_OUI_INTEL:
1432 hw->phy.type = ixgbe_phy_sfp_intel;
1435 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1437 ixgbe_phy_sfp_passive_unknown;
1438 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1440 ixgbe_phy_sfp_active_unknown;
1442 hw->phy.type = ixgbe_phy_sfp_unknown;
1447 /* Allow any DA cable vendor */
1448 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1449 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1450 status = IXGBE_SUCCESS;
1454 /* Verify supported 1G SFP modules */
1455 if (comp_codes_10g == 0 &&
1456 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1457 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1458 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1459 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1460 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1461 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1462 hw->phy.type = ixgbe_phy_sfp_unsupported;
1463 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1467 /* Anything else 82598-based is supported */
1468 if (hw->mac.type == ixgbe_mac_82598EB) {
1469 status = IXGBE_SUCCESS;
1473 ixgbe_get_device_caps(hw, &enforce_sfp);
1474 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1475 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1476 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1477 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1478 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1479 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1480 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1481 /* Make sure we're a supported PHY type */
1482 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1483 status = IXGBE_SUCCESS;
1485 if (hw->allow_unsupported_sfp == true) {
1486 EWARN(hw, "WARNING: Intel (R) Network "
1487 "Connections are quality tested "
1488 "using Intel (R) Ethernet Optics."
1489 " Using untested modules is not "
1490 "supported and may cause unstable"
1491 " operation or damage to the "
1492 "module or the adapter. Intel "
1493 "Corporation is not responsible "
1494 "for any harm caused by using "
1495 "untested modules.\n", status);
1496 status = IXGBE_SUCCESS;
1498 DEBUGOUT("SFP+ module not supported\n");
1500 ixgbe_phy_sfp_unsupported;
1501 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1505 status = IXGBE_SUCCESS;
1512 err_read_i2c_eeprom:
1513 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1514 if (hw->phy.type != ixgbe_phy_nl) {
1516 hw->phy.type = ixgbe_phy_unknown;
1518 return IXGBE_ERR_SFP_NOT_PRESENT;
1522 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1523 * @hw: pointer to hardware structure
1525 * Determines physical layer capabilities of the current SFP.
1527 s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1529 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1530 u8 comp_codes_10g = 0;
1531 u8 comp_codes_1g = 0;
1533 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1535 hw->phy.ops.identify_sfp(hw);
1536 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1537 return physical_layer;
1539 switch (hw->phy.type) {
1540 case ixgbe_phy_sfp_passive_tyco:
1541 case ixgbe_phy_sfp_passive_unknown:
1542 case ixgbe_phy_qsfp_passive_unknown:
1543 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1545 case ixgbe_phy_sfp_ftl_active:
1546 case ixgbe_phy_sfp_active_unknown:
1547 case ixgbe_phy_qsfp_active_unknown:
1548 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1550 case ixgbe_phy_sfp_avago:
1551 case ixgbe_phy_sfp_ftl:
1552 case ixgbe_phy_sfp_intel:
1553 case ixgbe_phy_sfp_unknown:
1554 hw->phy.ops.read_i2c_eeprom(hw,
1555 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1556 hw->phy.ops.read_i2c_eeprom(hw,
1557 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1558 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1559 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1560 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1561 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1562 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1563 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1564 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1565 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1567 case ixgbe_phy_qsfp_intel:
1568 case ixgbe_phy_qsfp_unknown:
1569 hw->phy.ops.read_i2c_eeprom(hw,
1570 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1571 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1572 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1573 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1574 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1580 return physical_layer;
1584 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1585 * @hw: pointer to hardware structure
1587 * Searches for and identifies the QSFP module and assigns appropriate PHY type
1589 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1591 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1593 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1595 u8 comp_codes_1g = 0;
1596 u8 comp_codes_10g = 0;
1597 u8 oui_bytes[3] = {0, 0, 0};
1598 u16 enforce_sfp = 0;
1600 u8 cable_length = 0;
1602 bool active_cable = false;
1604 DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1606 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1607 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1608 status = IXGBE_ERR_SFP_NOT_PRESENT;
1612 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1615 if (status != IXGBE_SUCCESS)
1616 goto err_read_i2c_eeprom;
1618 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1619 hw->phy.type = ixgbe_phy_sfp_unsupported;
1620 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1624 hw->phy.id = identifier;
1626 /* LAN ID is needed for sfp_type determination */
1627 hw->mac.ops.set_lan_id(hw);
1629 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1632 if (status != IXGBE_SUCCESS)
1633 goto err_read_i2c_eeprom;
1635 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1638 if (status != IXGBE_SUCCESS)
1639 goto err_read_i2c_eeprom;
1641 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1642 hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1643 if (hw->bus.lan_id == 0)
1644 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1646 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1647 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1648 IXGBE_SFF_10GBASELR_CAPABLE)) {
1649 if (hw->bus.lan_id == 0)
1650 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1652 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1654 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1655 active_cable = true;
1657 if (!active_cable) {
1658 /* check for active DA cables that pre-date
1660 hw->phy.ops.read_i2c_eeprom(hw,
1661 IXGBE_SFF_QSFP_CONNECTOR,
1664 hw->phy.ops.read_i2c_eeprom(hw,
1665 IXGBE_SFF_QSFP_CABLE_LENGTH,
1668 hw->phy.ops.read_i2c_eeprom(hw,
1669 IXGBE_SFF_QSFP_DEVICE_TECH,
1673 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1674 (cable_length > 0) &&
1675 ((device_tech >> 4) ==
1676 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1677 active_cable = true;
1681 hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1682 if (hw->bus.lan_id == 0)
1684 ixgbe_sfp_type_da_act_lmt_core0;
1687 ixgbe_sfp_type_da_act_lmt_core1;
1689 /* unsupported module type */
1690 hw->phy.type = ixgbe_phy_sfp_unsupported;
1691 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1696 if (hw->phy.sfp_type != stored_sfp_type)
1697 hw->phy.sfp_setup_needed = true;
1699 /* Determine if the QSFP+ PHY is dual speed or not. */
1700 hw->phy.multispeed_fiber = false;
1701 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1702 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1703 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1704 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1705 hw->phy.multispeed_fiber = true;
1707 /* Determine PHY vendor for optical modules */
1708 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1709 IXGBE_SFF_10GBASELR_CAPABLE)) {
1710 status = hw->phy.ops.read_i2c_eeprom(hw,
1711 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1714 if (status != IXGBE_SUCCESS)
1715 goto err_read_i2c_eeprom;
1717 status = hw->phy.ops.read_i2c_eeprom(hw,
1718 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1721 if (status != IXGBE_SUCCESS)
1722 goto err_read_i2c_eeprom;
1724 status = hw->phy.ops.read_i2c_eeprom(hw,
1725 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1728 if (status != IXGBE_SUCCESS)
1729 goto err_read_i2c_eeprom;
1732 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1733 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1734 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1736 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1737 hw->phy.type = ixgbe_phy_qsfp_intel;
1739 hw->phy.type = ixgbe_phy_qsfp_unknown;
1741 ixgbe_get_device_caps(hw, &enforce_sfp);
1742 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1743 /* Make sure we're a supported PHY type */
1744 if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1745 status = IXGBE_SUCCESS;
1747 if (hw->allow_unsupported_sfp == true) {
1748 EWARN(hw, "WARNING: Intel (R) Network "
1749 "Connections are quality tested "
1750 "using Intel (R) Ethernet Optics."
1751 " Using untested modules is not "
1752 "supported and may cause unstable"
1753 " operation or damage to the "
1754 "module or the adapter. Intel "
1755 "Corporation is not responsible "
1756 "for any harm caused by using "
1757 "untested modules.\n", status);
1758 status = IXGBE_SUCCESS;
1760 DEBUGOUT("QSFP module not supported\n");
1762 ixgbe_phy_sfp_unsupported;
1763 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1767 status = IXGBE_SUCCESS;
1774 err_read_i2c_eeprom:
1775 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1777 hw->phy.type = ixgbe_phy_unknown;
1779 return IXGBE_ERR_SFP_NOT_PRESENT;
1784 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1785 * @hw: pointer to hardware structure
1786 * @list_offset: offset to the SFP ID list
1787 * @data_offset: offset to the SFP data block
1789 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1790 * so it returns the offsets to the phy init sequence block.
1792 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1797 u16 sfp_type = hw->phy.sfp_type;
1799 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1801 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1802 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1804 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1805 return IXGBE_ERR_SFP_NOT_PRESENT;
1807 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1808 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1809 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1812 * Limiting active cables and 1G Phys must be initialized as
1815 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1816 sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1817 sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1818 sfp_type == ixgbe_sfp_type_1g_sx_core0)
1819 sfp_type = ixgbe_sfp_type_srlr_core0;
1820 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1821 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1822 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1823 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1824 sfp_type = ixgbe_sfp_type_srlr_core1;
1826 /* Read offset to PHY init contents */
1827 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1828 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1829 "eeprom read at offset %d failed",
1830 IXGBE_PHY_INIT_OFFSET_NL);
1831 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1834 if ((!*list_offset) || (*list_offset == 0xFFFF))
1835 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1837 /* Shift offset to first ID word */
1841 * Find the matching SFP ID in the EEPROM
1842 * and program the init sequence
1844 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1847 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1848 if (sfp_id == sfp_type) {
1850 if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1852 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1853 DEBUGOUT("SFP+ module not supported\n");
1854 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1859 (*list_offset) += 2;
1860 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1865 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1866 DEBUGOUT("No matching SFP+ module found\n");
1867 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1870 return IXGBE_SUCCESS;
1873 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1874 "eeprom read at offset %d failed", *list_offset);
1875 return IXGBE_ERR_PHY;
1879 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1880 * @hw: pointer to hardware structure
1881 * @byte_offset: EEPROM byte offset to read
1882 * @eeprom_data: value read
1884 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1886 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1889 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1891 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1892 IXGBE_I2C_EEPROM_DEV_ADDR,
1897 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1898 * @hw: pointer to hardware structure
1899 * @byte_offset: byte offset at address 0xA2
1900 * @eeprom_data: value read
1902 * Performs byte read operation to SFP module's SFF-8472 data over I2C
1904 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1907 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1908 IXGBE_I2C_EEPROM_DEV_ADDR2,
1913 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1914 * @hw: pointer to hardware structure
1915 * @byte_offset: EEPROM byte offset to write
1916 * @eeprom_data: value to write
1918 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1920 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1923 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1925 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1926 IXGBE_I2C_EEPROM_DEV_ADDR,
1931 * ixgbe_is_sfp_probe - Returns true if SFP is being detected
1932 * @hw: pointer to hardware structure
1933 * @offset: eeprom offset to be read
1934 * @addr: I2C address to be read
1936 STATIC bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1938 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1939 offset == IXGBE_SFF_IDENTIFIER &&
1940 hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1946 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1947 * @hw: pointer to hardware structure
1948 * @byte_offset: byte offset to read
1951 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1952 * a specified device address.
1954 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1955 u8 dev_addr, u8 *data)
1960 u32 swfw_mask = hw->phy.phy_semaphore_mask;
1964 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1966 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
1967 max_retry = IXGBE_SFP_DETECT_RETRIES;
1970 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
1971 return IXGBE_ERR_SWFW_SYNC;
1973 ixgbe_i2c_start(hw);
1975 /* Device Address and write indication */
1976 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1977 if (status != IXGBE_SUCCESS)
1980 status = ixgbe_get_i2c_ack(hw);
1981 if (status != IXGBE_SUCCESS)
1984 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1985 if (status != IXGBE_SUCCESS)
1988 status = ixgbe_get_i2c_ack(hw);
1989 if (status != IXGBE_SUCCESS)
1992 ixgbe_i2c_start(hw);
1994 /* Device Address and read indication */
1995 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1996 if (status != IXGBE_SUCCESS)
1999 status = ixgbe_get_i2c_ack(hw);
2000 if (status != IXGBE_SUCCESS)
2003 status = ixgbe_clock_in_i2c_byte(hw, data);
2004 if (status != IXGBE_SUCCESS)
2007 status = ixgbe_clock_out_i2c_bit(hw, nack);
2008 if (status != IXGBE_SUCCESS)
2012 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2013 return IXGBE_SUCCESS;
2016 ixgbe_i2c_bus_clear(hw);
2017 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2020 if (retry < max_retry)
2021 DEBUGOUT("I2C byte read error - Retrying.\n");
2023 DEBUGOUT("I2C byte read error.\n");
2025 } while (retry < max_retry);
2031 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2032 * @hw: pointer to hardware structure
2033 * @byte_offset: byte offset to write
2034 * @data: value to write
2036 * Performs byte write operation to SFP module's EEPROM over I2C interface at
2037 * a specified device address.
2039 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2040 u8 dev_addr, u8 data)
2042 s32 status = IXGBE_SUCCESS;
2045 u32 swfw_mask = hw->phy.phy_semaphore_mask;
2047 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2049 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
2050 status = IXGBE_ERR_SWFW_SYNC;
2051 goto write_byte_out;
2055 ixgbe_i2c_start(hw);
2057 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2058 if (status != IXGBE_SUCCESS)
2061 status = ixgbe_get_i2c_ack(hw);
2062 if (status != IXGBE_SUCCESS)
2065 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2066 if (status != IXGBE_SUCCESS)
2069 status = ixgbe_get_i2c_ack(hw);
2070 if (status != IXGBE_SUCCESS)
2073 status = ixgbe_clock_out_i2c_byte(hw, data);
2074 if (status != IXGBE_SUCCESS)
2077 status = ixgbe_get_i2c_ack(hw);
2078 if (status != IXGBE_SUCCESS)
2082 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2083 return IXGBE_SUCCESS;
2086 ixgbe_i2c_bus_clear(hw);
2088 if (retry < max_retry)
2089 DEBUGOUT("I2C byte write error - Retrying.\n");
2091 DEBUGOUT("I2C byte write error.\n");
2092 } while (retry < max_retry);
2094 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2101 * ixgbe_i2c_start - Sets I2C start condition
2102 * @hw: pointer to hardware structure
2104 * Sets I2C start condition (High -> Low on SDA while SCL is High)
2105 * Set bit-bang mode on X550 hardware.
2107 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
2109 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2111 DEBUGFUNC("ixgbe_i2c_start");
2113 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2115 /* Start condition must begin with data and clock high */
2116 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2117 ixgbe_raise_i2c_clk(hw, &i2cctl);
2119 /* Setup time for start condition (4.7us) */
2120 usec_delay(IXGBE_I2C_T_SU_STA);
2122 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2124 /* Hold time for start condition (4us) */
2125 usec_delay(IXGBE_I2C_T_HD_STA);
2127 ixgbe_lower_i2c_clk(hw, &i2cctl);
2129 /* Minimum low period of clock is 4.7 us */
2130 usec_delay(IXGBE_I2C_T_LOW);
2135 * ixgbe_i2c_stop - Sets I2C stop condition
2136 * @hw: pointer to hardware structure
2138 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
2139 * Disables bit-bang mode and negates data output enable on X550
2142 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2144 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2145 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2146 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2147 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2149 DEBUGFUNC("ixgbe_i2c_stop");
2151 /* Stop condition must begin with data low and clock high */
2152 ixgbe_set_i2c_data(hw, &i2cctl, 0);
2153 ixgbe_raise_i2c_clk(hw, &i2cctl);
2155 /* Setup time for stop condition (4us) */
2156 usec_delay(IXGBE_I2C_T_SU_STO);
2158 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2160 /* bus free time between stop and start (4.7us)*/
2161 usec_delay(IXGBE_I2C_T_BUF);
2163 if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2164 i2cctl &= ~bb_en_bit;
2165 i2cctl |= data_oe_bit | clk_oe_bit;
2166 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2167 IXGBE_WRITE_FLUSH(hw);
2172 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2173 * @hw: pointer to hardware structure
2174 * @data: data byte to clock in
2176 * Clocks in one byte data via I2C data/clock
2178 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2183 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2186 for (i = 7; i >= 0; i--) {
2187 ixgbe_clock_in_i2c_bit(hw, &bit);
2191 return IXGBE_SUCCESS;
2195 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2196 * @hw: pointer to hardware structure
2197 * @data: data byte clocked out
2199 * Clocks out one byte data via I2C data/clock
2201 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2203 s32 status = IXGBE_SUCCESS;
2208 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2210 for (i = 7; i >= 0; i--) {
2211 bit = (data >> i) & 0x1;
2212 status = ixgbe_clock_out_i2c_bit(hw, bit);
2214 if (status != IXGBE_SUCCESS)
2218 /* Release SDA line (set high) */
2219 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2220 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2221 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2222 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2223 IXGBE_WRITE_FLUSH(hw);
2229 * ixgbe_get_i2c_ack - Polls for I2C ACK
2230 * @hw: pointer to hardware structure
2232 * Clocks in/out one bit via I2C data/clock
2234 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2236 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2237 s32 status = IXGBE_SUCCESS;
2239 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2243 DEBUGFUNC("ixgbe_get_i2c_ack");
2246 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2247 i2cctl |= data_oe_bit;
2248 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2249 IXGBE_WRITE_FLUSH(hw);
2251 ixgbe_raise_i2c_clk(hw, &i2cctl);
2253 /* Minimum high period of clock is 4us */
2254 usec_delay(IXGBE_I2C_T_HIGH);
2256 /* Poll for ACK. Note that ACK in I2C spec is
2257 * transition from 1 to 0 */
2258 for (i = 0; i < timeout; i++) {
2259 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2260 ack = ixgbe_get_i2c_data(hw, &i2cctl);
2268 DEBUGOUT("I2C ack was not received.\n");
2269 status = IXGBE_ERR_I2C;
2272 ixgbe_lower_i2c_clk(hw, &i2cctl);
2274 /* Minimum low period of clock is 4.7 us */
2275 usec_delay(IXGBE_I2C_T_LOW);
2281 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2282 * @hw: pointer to hardware structure
2283 * @data: read data value
2285 * Clocks in one bit via I2C data/clock
2287 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2289 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2290 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2292 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2295 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2296 i2cctl |= data_oe_bit;
2297 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2298 IXGBE_WRITE_FLUSH(hw);
2300 ixgbe_raise_i2c_clk(hw, &i2cctl);
2302 /* Minimum high period of clock is 4us */
2303 usec_delay(IXGBE_I2C_T_HIGH);
2305 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2306 *data = ixgbe_get_i2c_data(hw, &i2cctl);
2308 ixgbe_lower_i2c_clk(hw, &i2cctl);
2310 /* Minimum low period of clock is 4.7 us */
2311 usec_delay(IXGBE_I2C_T_LOW);
2313 return IXGBE_SUCCESS;
2317 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2318 * @hw: pointer to hardware structure
2319 * @data: data value to write
2321 * Clocks out one bit via I2C data/clock
2323 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2326 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2328 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2330 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2331 if (status == IXGBE_SUCCESS) {
2332 ixgbe_raise_i2c_clk(hw, &i2cctl);
2334 /* Minimum high period of clock is 4us */
2335 usec_delay(IXGBE_I2C_T_HIGH);
2337 ixgbe_lower_i2c_clk(hw, &i2cctl);
2339 /* Minimum low period of clock is 4.7 us.
2340 * This also takes care of the data hold time.
2342 usec_delay(IXGBE_I2C_T_LOW);
2344 status = IXGBE_ERR_I2C;
2345 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2346 "I2C data was not set to %X\n", data);
2353 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2354 * @hw: pointer to hardware structure
2355 * @i2cctl: Current value of I2CCTL register
2357 * Raises the I2C clock line '0'->'1'
2358 * Negates the I2C clock output enable on X550 hardware.
2360 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2362 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2364 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2367 DEBUGFUNC("ixgbe_raise_i2c_clk");
2370 *i2cctl |= clk_oe_bit;
2371 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2374 for (i = 0; i < timeout; i++) {
2375 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2377 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2378 IXGBE_WRITE_FLUSH(hw);
2379 /* SCL rise time (1000ns) */
2380 usec_delay(IXGBE_I2C_T_RISE);
2382 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2383 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2389 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2390 * @hw: pointer to hardware structure
2391 * @i2cctl: Current value of I2CCTL register
2393 * Lowers the I2C clock line '1'->'0'
2394 * Asserts the I2C clock output enable on X550 hardware.
2396 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2398 DEBUGFUNC("ixgbe_lower_i2c_clk");
2400 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2401 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2403 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2404 IXGBE_WRITE_FLUSH(hw);
2406 /* SCL fall time (300ns) */
2407 usec_delay(IXGBE_I2C_T_FALL);
2411 * ixgbe_set_i2c_data - Sets the I2C data bit
2412 * @hw: pointer to hardware structure
2413 * @i2cctl: Current value of I2CCTL register
2414 * @data: I2C data value (0 or 1) to set
2416 * Sets the I2C data bit
2417 * Asserts the I2C data output enable on X550 hardware.
2419 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2421 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2422 s32 status = IXGBE_SUCCESS;
2424 DEBUGFUNC("ixgbe_set_i2c_data");
2427 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2429 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2430 *i2cctl &= ~data_oe_bit;
2432 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2433 IXGBE_WRITE_FLUSH(hw);
2435 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2436 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2438 if (!data) /* Can't verify data in this case */
2439 return IXGBE_SUCCESS;
2441 *i2cctl |= data_oe_bit;
2442 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2443 IXGBE_WRITE_FLUSH(hw);
2446 /* Verify data was set correctly */
2447 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2448 if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2449 status = IXGBE_ERR_I2C;
2450 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2451 "Error - I2C data was not set to %X.\n",
2459 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
2460 * @hw: pointer to hardware structure
2461 * @i2cctl: Current value of I2CCTL register
2463 * Returns the I2C data bit value
2464 * Negates the I2C data output enable on X550 hardware.
2466 STATIC bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2468 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2471 DEBUGFUNC("ixgbe_get_i2c_data");
2474 *i2cctl |= data_oe_bit;
2475 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2476 IXGBE_WRITE_FLUSH(hw);
2477 usec_delay(IXGBE_I2C_T_FALL);
2480 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2489 * ixgbe_i2c_bus_clear - Clears the I2C bus
2490 * @hw: pointer to hardware structure
2492 * Clears the I2C bus by sending nine clock pulses.
2493 * Used when data line is stuck low.
2495 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2500 DEBUGFUNC("ixgbe_i2c_bus_clear");
2502 ixgbe_i2c_start(hw);
2503 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2505 ixgbe_set_i2c_data(hw, &i2cctl, 1);
2507 for (i = 0; i < 9; i++) {
2508 ixgbe_raise_i2c_clk(hw, &i2cctl);
2510 /* Min high period of clock is 4us */
2511 usec_delay(IXGBE_I2C_T_HIGH);
2513 ixgbe_lower_i2c_clk(hw, &i2cctl);
2515 /* Min low period of clock is 4.7us*/
2516 usec_delay(IXGBE_I2C_T_LOW);
2519 ixgbe_i2c_start(hw);
2521 /* Put the i2c bus back to default state */
2526 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2527 * @hw: pointer to hardware structure
2529 * Checks if the LASI temp alarm status was triggered due to overtemp
2531 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2533 s32 status = IXGBE_SUCCESS;
2536 DEBUGFUNC("ixgbe_tn_check_overtemp");
2538 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2541 /* Check that the LASI temp alarm status was triggered */
2542 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2543 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2545 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2548 status = IXGBE_ERR_OVERTEMP;
2549 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");