lib/librte_pmd_ixgbe/ixgbe/ixgbe_phy.c

   1 /*******************************************************************************
   2
   3 Copyright (c) 2001-2014, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #include "ixgbe_api.h"
  35 #include "ixgbe_common.h"
  36 #include "ixgbe_phy.h"
  37 #ident "$Id: ixgbe_phy.c,v 1.155 2013/08/14 22:34:03 jtkirshe Exp $"
  38
  39 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw);
  40 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw);
  41 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
  42 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
  43 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
  44 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
  45 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
  46 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  47 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
  48 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
  49 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl);
  50 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
  51                                           u8 *sff8472_data);
  52
  53 /**
  54  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
  55  *  @hw: pointer to the hardware structure
  56  *
  57  *  Initialize the function pointers.
  58  **/
  59 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
  60 {
  61         struct ixgbe_phy_info *phy = &hw->phy;
  62
  63         DEBUGFUNC("ixgbe_init_phy_ops_generic");
  64
  65         /* PHY */
  66         phy->ops.identify = &ixgbe_identify_phy_generic;
  67         phy->ops.reset = &ixgbe_reset_phy_generic;
  68         phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
  69         phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
  70         phy->ops.read_reg_mdi = &ixgbe_read_phy_reg_mdi;
  71         phy->ops.write_reg_mdi = &ixgbe_write_phy_reg_mdi;
  72         phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
  73         phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
  74         phy->ops.check_link = NULL;
  75         phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
  76         phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
  77         phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
  78         phy->ops.read_i2c_sff8472 = &ixgbe_read_i2c_sff8472_generic;
  79         phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
  80         phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
  81         phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
  82         phy->ops.identify_sfp = &ixgbe_identify_module_generic;
  83         phy->sfp_type = ixgbe_sfp_type_unknown;
  84         phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
  85         return IXGBE_SUCCESS;
  86 }
  87
  88 /**
  89  *  ixgbe_identify_phy_generic - Get physical layer module
  90  *  @hw: pointer to hardware structure
  91  *
  92  *  Determines the physical layer module found on the current adapter.
  93  **/
  94 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
  95 {
  96         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
  97         u32 phy_addr;
  98         u16 ext_ability = 0;
  99
 100         DEBUGFUNC("ixgbe_identify_phy_generic");
 101
 102         if (hw->phy.type == ixgbe_phy_unknown) {
 103                 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
 104                         if (ixgbe_validate_phy_addr(hw, phy_addr)) {
 105                                 hw->phy.addr = phy_addr;
 106                                 ixgbe_get_phy_id(hw);
 107                                 hw->phy.type =
 108                                         ixgbe_get_phy_type_from_id(hw->phy.id);
 109
 110                                 if (hw->phy.type == ixgbe_phy_unknown) {
 111                                         hw->phy.ops.read_reg(hw,
 112                                                   IXGBE_MDIO_PHY_EXT_ABILITY,
 113                                                   IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 114                                                   &ext_ability);
 115                                         if (ext_ability &
 116                                             (IXGBE_MDIO_PHY_10GBASET_ABILITY |
 117                                              IXGBE_MDIO_PHY_1000BASET_ABILITY))
 118                                                 hw->phy.type =
 119                                                          ixgbe_phy_cu_unknown;
 120                                         else
 121                                                 hw->phy.type =
 122                                                          ixgbe_phy_generic;
 123                                 }
 124
 125                                 status = IXGBE_SUCCESS;
 126                                 break;
 127                         }
 128                 }
 129
 130                 /* Certain media types do not have a phy so an address will not
 131                  * be found and the code will take this path.  Caller has to
 132                  * decide if it is an error or not.
 133                  */
 134                 if (status != IXGBE_SUCCESS) {
 135                         hw->phy.addr = 0;
 136                 }
 137         } else {
 138                 status = IXGBE_SUCCESS;
 139         }
 140
 141         return status;
 142 }
 143
 144 /**
 145  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
 146  * @hw: pointer to the hardware structure
 147  *
 148  * This function checks the MMNGC.MNG_VETO bit to see if there are
 149  * any constraints on link from manageability.  For MAC's that don't
 150  * have this bit just return faluse since the link can not be blocked
 151  * via this method.
 152  **/
 153 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
 154 {
 155         u32 mmngc;
 156
 157         DEBUGFUNC("ixgbe_check_reset_blocked");
 158
 159         /* If we don't have this bit, it can't be blocking */
 160         if (hw->mac.type == ixgbe_mac_82598EB)
 161                 return false;
 162
 163         mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
 164         if (mmngc & IXGBE_MMNGC_MNG_VETO) {
 165                 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
 166                               "MNG_VETO bit detected.\n");
 167                 return true;
 168         }
 169
 170         return false;
 171 }
 172
 173 /**
 174  *  ixgbe_validate_phy_addr - Determines phy address is valid
 175  *  @hw: pointer to hardware structure
 176  *
 177  **/
 178 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
 179 {
 180         u16 phy_id = 0;
 181         bool valid = false;
 182
 183         DEBUGFUNC("ixgbe_validate_phy_addr");
 184
 185         hw->phy.addr = phy_addr;
 186         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 187                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
 188
 189         if (phy_id != 0xFFFF && phy_id != 0x0)
 190                 valid = true;
 191
 192         return valid;
 193 }
 194
 195 /**
 196  *  ixgbe_get_phy_id - Get the phy type
 197  *  @hw: pointer to hardware structure
 198  *
 199  **/
 200 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
 201 {
 202         u32 status;
 203         u16 phy_id_high = 0;
 204         u16 phy_id_low = 0;
 205
 206         DEBUGFUNC("ixgbe_get_phy_id");
 207
 208         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
 209                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 210                                       &phy_id_high);
 211
 212         if (status == IXGBE_SUCCESS) {
 213                 hw->phy.id = (u32)(phy_id_high << 16);
 214                 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
 215                                               IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 216                                               &phy_id_low);
 217                 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
 218                 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
 219         }
 220         return status;
 221 }
 222
 223 /**
 224  *  ixgbe_get_phy_type_from_id - Get the phy type
 225  *  @hw: pointer to hardware structure
 226  *
 227  **/
 228 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
 229 {
 230         enum ixgbe_phy_type phy_type;
 231
 232         DEBUGFUNC("ixgbe_get_phy_type_from_id");
 233
 234         switch (phy_id) {
 235         case TN1010_PHY_ID:
 236                 phy_type = ixgbe_phy_tn;
 237                 break;
 238         case X540_PHY_ID:
 239                 phy_type = ixgbe_phy_aq;
 240                 break;
 241         case QT2022_PHY_ID:
 242                 phy_type = ixgbe_phy_qt;
 243                 break;
 244         case ATH_PHY_ID:
 245                 phy_type = ixgbe_phy_nl;
 246                 break;
 247         default:
 248                 phy_type = ixgbe_phy_unknown;
 249                 break;
 250         }
 251
 252         DEBUGOUT1("phy type found is %d\n", phy_type);
 253         return phy_type;
 254 }
 255
 256 /**
 257  *  ixgbe_reset_phy_generic - Performs a PHY reset
 258  *  @hw: pointer to hardware structure
 259  **/
 260 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
 261 {
 262         u32 i;
 263         u16 ctrl = 0;
 264         s32 status = IXGBE_SUCCESS;
 265
 266         DEBUGFUNC("ixgbe_reset_phy_generic");
 267
 268         if (hw->phy.type == ixgbe_phy_unknown)
 269                 status = ixgbe_identify_phy_generic(hw);
 270
 271         if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
 272                 goto out;
 273
 274         /* Don't reset PHY if it's shut down due to overtemp. */
 275         if (!hw->phy.reset_if_overtemp &&
 276             (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
 277                 goto out;
 278
 279         /* Blocked by MNG FW so bail */
 280         if (ixgbe_check_reset_blocked(hw))
 281                 goto out;
 282
 283         /*
 284          * Perform soft PHY reset to the PHY_XS.
 285          * This will cause a soft reset to the PHY
 286          */
 287         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 288                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 289                               IXGBE_MDIO_PHY_XS_RESET);
 290
 291         /*
 292          * Poll for reset bit to self-clear indicating reset is complete.
 293          * Some PHYs could take up to 3 seconds to complete and need about
 294          * 1.7 usec delay after the reset is complete.
 295          */
 296         for (i = 0; i < 30; i++) {
 297                 msec_delay(100);
 298                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 299                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
 300                 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
 301                         usec_delay(2);
 302                         break;
 303                 }
 304         }
 305
 306         if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
 307                 status = IXGBE_ERR_RESET_FAILED;
 308                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
 309                              "PHY reset polling failed to complete.\n");
 310         }
 311
 312 out:
 313         return status;
 314 }
 315
 316 /**
 317  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
 318  *  the SWFW lock
 319  *  @hw: pointer to hardware structure
 320  *  @reg_addr: 32 bit address of PHY register to read
 321  *  @phy_data: Pointer to read data from PHY register
 322  **/
 323 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
 324                        u16 *phy_data)
 325 {
 326         u32 i, data, command;
 327
 328         /* Setup and write the address cycle command */
 329         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 330                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 331                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 332                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 333
 334         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 335
 336         /*
 337          * Check every 10 usec to see if the address cycle completed.
 338          * The MDI Command bit will clear when the operation is
 339          * complete
 340          */
 341         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 342                 usec_delay(10);
 343
 344                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 345                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 346                                 break;
 347         }
 348
 349
 350         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 351                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
 352                 return IXGBE_ERR_PHY;
 353         }
 354
 355         /*
 356          * Address cycle complete, setup and write the read
 357          * command
 358          */
 359         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 360                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 361                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 362                    (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
 363
 364         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 365
 366         /*
 367          * Check every 10 usec to see if the address cycle
 368          * completed. The MDI Command bit will clear when the
 369          * operation is complete
 370          */
 371         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 372                 usec_delay(10);
 373
 374                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 375                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 376                         break;
 377         }
 378
 379         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 380                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
 381                 return IXGBE_ERR_PHY;
 382         }
 383
 384         /*
 385          * Read operation is complete.  Get the data
 386          * from MSRWD
 387          */
 388         data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
 389         data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
 390         *phy_data = (u16)(data);
 391
 392         return IXGBE_SUCCESS;
 393 }
 394
 395 /**
 396  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
 397  *  using the SWFW lock - this function is needed in most cases
 398  *  @hw: pointer to hardware structure
 399  *  @reg_addr: 32 bit address of PHY register to read
 400  *  @phy_data: Pointer to read data from PHY register
 401  **/
 402 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 403                                u32 device_type, u16 *phy_data)
 404 {
 405         s32 status;
 406         u16 gssr;
 407
 408         DEBUGFUNC("ixgbe_read_phy_reg_generic");
 409
 410         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 411                 gssr = IXGBE_GSSR_PHY1_SM;
 412         else
 413                 gssr = IXGBE_GSSR_PHY0_SM;
 414
 415         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 416                 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type,
 417                                                 phy_data);
 418                 hw->mac.ops.release_swfw_sync(hw, gssr);
 419         } else {
 420                 status = IXGBE_ERR_SWFW_SYNC;
 421         }
 422
 423         return status;
 424 }
 425
 426 /**
 427  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
 428  *  without SWFW lock
 429  *  @hw: pointer to hardware structure
 430  *  @reg_addr: 32 bit PHY register to write
 431  *  @device_type: 5 bit device type
 432  *  @phy_data: Data to write to the PHY register
 433  **/
 434 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
 435                                 u32 device_type, u16 phy_data)
 436 {
 437         u32 i, command;
 438
 439         /* Put the data in the MDI single read and write data register*/
 440         IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
 441
 442         /* Setup and write the address cycle command */
 443         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 444                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 445                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 446                    (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
 447
 448         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 449
 450         /*
 451          * Check every 10 usec to see if the address cycle completed.
 452          * The MDI Command bit will clear when the operation is
 453          * complete
 454          */
 455         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 456                 usec_delay(10);
 457
 458                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 459                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 460                         break;
 461         }
 462
 463         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 464                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
 465                 return IXGBE_ERR_PHY;
 466         }
 467
 468         /*
 469          * Address cycle complete, setup and write the write
 470          * command
 471          */
 472         command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
 473                    (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
 474                    (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
 475                    (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
 476
 477         IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
 478
 479         /*
 480          * Check every 10 usec to see if the address cycle
 481          * completed. The MDI Command bit will clear when the
 482          * operation is complete
 483          */
 484         for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
 485                 usec_delay(10);
 486
 487                 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
 488                 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
 489                         break;
 490         }
 491
 492         if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
 493                 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
 494                 return IXGBE_ERR_PHY;
 495         }
 496
 497         return IXGBE_SUCCESS;
 498 }
 499
 500 /**
 501  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
 502  *  using SWFW lock- this function is needed in most cases
 503  *  @hw: pointer to hardware structure
 504  *  @reg_addr: 32 bit PHY register to write
 505  *  @device_type: 5 bit device type
 506  *  @phy_data: Data to write to the PHY register
 507  **/
 508 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
 509                                 u32 device_type, u16 phy_data)
 510 {
 511         s32 status;
 512         u16 gssr;
 513
 514         DEBUGFUNC("ixgbe_write_phy_reg_generic");
 515
 516         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
 517                 gssr = IXGBE_GSSR_PHY1_SM;
 518         else
 519                 gssr = IXGBE_GSSR_PHY0_SM;
 520
 521         if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
 522                 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type,
 523                                                  phy_data);
 524                 hw->mac.ops.release_swfw_sync(hw, gssr);
 525         } else {
 526                 status = IXGBE_ERR_SWFW_SYNC;
 527         }
 528
 529         return status;
 530 }
 531
 532 /**
 533  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
 534  *  @hw: pointer to hardware structure
 535  *
 536  *  Restart auto-negotiation and PHY and waits for completion.
 537  **/
 538 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
 539 {
 540         s32 status = IXGBE_SUCCESS;
 541         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 542         bool autoneg = false;
 543         ixgbe_link_speed speed;
 544
 545         DEBUGFUNC("ixgbe_setup_phy_link_generic");
 546
 547         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 548
 549         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 550                 /* Set or unset auto-negotiation 10G advertisement */
 551                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 552                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 553                                      &autoneg_reg);
 554
 555                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 556                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 557                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 558
 559                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 560                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 561                                       autoneg_reg);
 562         }
 563
 564         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 565                 /* Set or unset auto-negotiation 1G advertisement */
 566                 hw->phy.ops.read_reg(hw,
 567                                      IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 568                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 569                                      &autoneg_reg);
 570
 571                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
 572                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 573                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
 574
 575                 hw->phy.ops.write_reg(hw,
 576                                       IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
 577                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 578                                       autoneg_reg);
 579         }
 580
 581         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 582                 /* Set or unset auto-negotiation 100M advertisement */
 583                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 584                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 585                                      &autoneg_reg);
 586
 587                 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
 588                                  IXGBE_MII_100BASE_T_ADVERTISE_HALF);
 589                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 590                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 591
 592                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 593                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 594                                       autoneg_reg);
 595         }
 596
 597         /* Blocked by MNG FW so don't reset PHY */
 598         if (ixgbe_check_reset_blocked(hw))
 599                 return status;
 600
 601         /* Restart PHY auto-negotiation. */
 602         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 603                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 604
 605         autoneg_reg |= IXGBE_MII_RESTART;
 606
 607         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 608                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 609
 610         return status;
 611 }
 612
 613 /**
 614  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
 615  *  @hw: pointer to hardware structure
 616  *  @speed: new link speed
 617  **/
 618 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
 619                                        ixgbe_link_speed speed,
 620                                        bool autoneg_wait_to_complete)
 621 {
 622         UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
 623
 624         DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
 625
 626         /*
 627          * Clear autoneg_advertised and set new values based on input link
 628          * speed.
 629          */
 630         hw->phy.autoneg_advertised = 0;
 631
 632         if (speed & IXGBE_LINK_SPEED_10GB_FULL)
 633                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
 634
 635         if (speed & IXGBE_LINK_SPEED_1GB_FULL)
 636                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
 637
 638         if (speed & IXGBE_LINK_SPEED_100_FULL)
 639                 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
 640
 641         /* Setup link based on the new speed settings */
 642         hw->phy.ops.setup_link(hw);
 643
 644         return IXGBE_SUCCESS;
 645 }
 646
 647 /**
 648  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
 649  *  @hw: pointer to hardware structure
 650  *  @speed: pointer to link speed
 651  *  @autoneg: boolean auto-negotiation value
 652  *
 653  *  Determines the link capabilities by reading the AUTOC register.
 654  **/
 655 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
 656                                                ixgbe_link_speed *speed,
 657                                                bool *autoneg)
 658 {
 659         s32 status;
 660         u16 speed_ability;
 661
 662         DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
 663
 664         *speed = 0;
 665         *autoneg = true;
 666
 667         status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
 668                                       IXGBE_MDIO_PMA_PMD_DEV_TYPE,
 669                                       &speed_ability);
 670
 671         if (status == IXGBE_SUCCESS) {
 672                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
 673                         *speed |= IXGBE_LINK_SPEED_10GB_FULL;
 674                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
 675                         *speed |= IXGBE_LINK_SPEED_1GB_FULL;
 676                 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
 677                         *speed |= IXGBE_LINK_SPEED_100_FULL;
 678         }
 679
 680         return status;
 681 }
 682
 683 /**
 684  *  ixgbe_check_phy_link_tnx - Determine link and speed status
 685  *  @hw: pointer to hardware structure
 686  *
 687  *  Reads the VS1 register to determine if link is up and the current speed for
 688  *  the PHY.
 689  **/
 690 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
 691                              bool *link_up)
 692 {
 693         s32 status = IXGBE_SUCCESS;
 694         u32 time_out;
 695         u32 max_time_out = 10;
 696         u16 phy_link = 0;
 697         u16 phy_speed = 0;
 698         u16 phy_data = 0;
 699
 700         DEBUGFUNC("ixgbe_check_phy_link_tnx");
 701
 702         /* Initialize speed and link to default case */
 703         *link_up = false;
 704         *speed = IXGBE_LINK_SPEED_10GB_FULL;
 705
 706         /*
 707          * Check current speed and link status of the PHY register.
 708          * This is a vendor specific register and may have to
 709          * be changed for other copper PHYs.
 710          */
 711         for (time_out = 0; time_out < max_time_out; time_out++) {
 712                 usec_delay(10);
 713                 status = hw->phy.ops.read_reg(hw,
 714                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
 715                                         IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 716                                         &phy_data);
 717                 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
 718                 phy_speed = phy_data &
 719                                  IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
 720                 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
 721                         *link_up = true;
 722                         if (phy_speed ==
 723                             IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
 724                                 *speed = IXGBE_LINK_SPEED_1GB_FULL;
 725                         break;
 726                 }
 727         }
 728
 729         return status;
 730 }
 731
 732 /**
 733  *      ixgbe_setup_phy_link_tnx - Set and restart auto-neg
 734  *      @hw: pointer to hardware structure
 735  *
 736  *      Restart auto-negotiation and PHY and waits for completion.
 737  **/
 738 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
 739 {
 740         s32 status = IXGBE_SUCCESS;
 741         u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
 742         bool autoneg = false;
 743         ixgbe_link_speed speed;
 744
 745         DEBUGFUNC("ixgbe_setup_phy_link_tnx");
 746
 747         ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
 748
 749         if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
 750                 /* Set or unset auto-negotiation 10G advertisement */
 751                 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 752                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 753                                      &autoneg_reg);
 754
 755                 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
 756                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
 757                         autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
 758
 759                 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
 760                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 761                                       autoneg_reg);
 762         }
 763
 764         if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
 765                 /* Set or unset auto-negotiation 1G advertisement */
 766                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 767                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 768                                      &autoneg_reg);
 769
 770                 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 771                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
 772                         autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
 773
 774                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
 775                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 776                                       autoneg_reg);
 777         }
 778
 779         if (speed & IXGBE_LINK_SPEED_100_FULL) {
 780                 /* Set or unset auto-negotiation 100M advertisement */
 781                 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 782                                      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 783                                      &autoneg_reg);
 784
 785                 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
 786                 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
 787                         autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
 788
 789                 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
 790                                       IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
 791                                       autoneg_reg);
 792         }
 793
 794         /* Blocked by MNG FW so don't reset PHY */
 795         if (ixgbe_check_reset_blocked(hw))
 796                 return status;
 797
 798         /* Restart PHY auto-negotiation. */
 799         hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 800                              IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
 801
 802         autoneg_reg |= IXGBE_MII_RESTART;
 803
 804         hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
 805                               IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
 806
 807         return status;
 808 }
 809
 810 /**
 811  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
 812  *  @hw: pointer to hardware structure
 813  *  @firmware_version: pointer to the PHY Firmware Version
 814  **/
 815 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 816                                        u16 *firmware_version)
 817 {
 818         s32 status;
 819
 820         DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
 821
 822         status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
 823                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 824                                       firmware_version);
 825
 826         return status;
 827 }
 828
 829 /**
 830  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
 831  *  @hw: pointer to hardware structure
 832  *  @firmware_version: pointer to the PHY Firmware Version
 833  **/
 834 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 835                                            u16 *firmware_version)
 836 {
 837         s32 status;
 838
 839         DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
 840
 841         status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
 842                                       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
 843                                       firmware_version);
 844
 845         return status;
 846 }
 847
 848 /**
 849  *  ixgbe_reset_phy_nl - Performs a PHY reset
 850  *  @hw: pointer to hardware structure
 851  **/
 852 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
 853 {
 854         u16 phy_offset, control, eword, edata, block_crc;
 855         bool end_data = false;
 856         u16 list_offset, data_offset;
 857         u16 phy_data = 0;
 858         s32 ret_val = IXGBE_SUCCESS;
 859         u32 i;
 860
 861         DEBUGFUNC("ixgbe_reset_phy_nl");
 862
 863         /* Blocked by MNG FW so bail */
 864         if (ixgbe_check_reset_blocked(hw))
 865                 goto out;
 866
 867         hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 868                              IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 869
 870         /* reset the PHY and poll for completion */
 871         hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 872                               IXGBE_MDIO_PHY_XS_DEV_TYPE,
 873                               (phy_data | IXGBE_MDIO_PHY_XS_RESET));
 874
 875         for (i = 0; i < 100; i++) {
 876                 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
 877                                      IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
 878                 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
 879                         break;
 880                 msec_delay(10);
 881         }
 882
 883         if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
 884                 DEBUGOUT("PHY reset did not complete.\n");
 885                 ret_val = IXGBE_ERR_PHY;
 886                 goto out;
 887         }
 888
 889         /* Get init offsets */
 890         ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
 891                                                       &data_offset);
 892         if (ret_val != IXGBE_SUCCESS)
 893                 goto out;
 894
 895         ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
 896         data_offset++;
 897         while (!end_data) {
 898                 /*
 899                  * Read control word from PHY init contents offset
 900                  */
 901                 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
 902                 if (ret_val)
 903                         goto err_eeprom;
 904                 control = (eword & IXGBE_CONTROL_MASK_NL) >>
 905                            IXGBE_CONTROL_SHIFT_NL;
 906                 edata = eword & IXGBE_DATA_MASK_NL;
 907                 switch (control) {
 908                 case IXGBE_DELAY_NL:
 909                         data_offset++;
 910                         DEBUGOUT1("DELAY: %d MS\n", edata);
 911                         msec_delay(edata);
 912                         break;
 913                 case IXGBE_DATA_NL:
 914                         DEBUGOUT("DATA:\n");
 915                         data_offset++;
 916                         ret_val = hw->eeprom.ops.read(hw, data_offset,
 917                                                       &phy_offset);
 918                         if (ret_val)
 919                                 goto err_eeprom;
 920                         data_offset++;
 921                         for (i = 0; i < edata; i++) {
 922                                 ret_val = hw->eeprom.ops.read(hw, data_offset,
 923                                                               &eword);
 924                                 if (ret_val)
 925                                         goto err_eeprom;
 926                                 hw->phy.ops.write_reg(hw, phy_offset,
 927                                                       IXGBE_TWINAX_DEV, eword);
 928                                 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
 929                                           phy_offset);
 930                                 data_offset++;
 931                                 phy_offset++;
 932                         }
 933                         break;
 934                 case IXGBE_CONTROL_NL:
 935                         data_offset++;
 936                         DEBUGOUT("CONTROL:\n");
 937                         if (edata == IXGBE_CONTROL_EOL_NL) {
 938                                 DEBUGOUT("EOL\n");
 939                                 end_data = true;
 940                         } else if (edata == IXGBE_CONTROL_SOL_NL) {
 941                                 DEBUGOUT("SOL\n");
 942                         } else {
 943                                 DEBUGOUT("Bad control value\n");
 944                                 ret_val = IXGBE_ERR_PHY;
 945                                 goto out;
 946                         }
 947                         break;
 948                 default:
 949                         DEBUGOUT("Bad control type\n");
 950                         ret_val = IXGBE_ERR_PHY;
 951                         goto out;
 952                 }
 953         }
 954
 955 out:
 956         return ret_val;
 957
 958 err_eeprom:
 959         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
 960                       "eeprom read at offset %d failed", data_offset);
 961         return IXGBE_ERR_PHY;
 962 }
 963
 964 /**
 965  *  ixgbe_identify_module_generic - Identifies module type
 966  *  @hw: pointer to hardware structure
 967  *
 968  *  Determines HW type and calls appropriate function.
 969  **/
 970 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
 971 {
 972         s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
 973
 974         DEBUGFUNC("ixgbe_identify_module_generic");
 975
 976         switch (hw->mac.ops.get_media_type(hw)) {
 977         case ixgbe_media_type_fiber:
 978                 status = ixgbe_identify_sfp_module_generic(hw);
 979                 break;
 980
 981
 982         default:
 983                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
 984                 status = IXGBE_ERR_SFP_NOT_PRESENT;
 985                 break;
 986         }
 987
 988         return status;
 989 }
 990
 991 /**
 992  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
 993  *  @hw: pointer to hardware structure
 994  *
 995  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
 996  **/
 997 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
 998 {
 999         s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1000         u32 vendor_oui = 0;
1001         enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1002         u8 identifier = 0;
1003         u8 comp_codes_1g = 0;
1004         u8 comp_codes_10g = 0;
1005         u8 oui_bytes[3] = {0, 0, 0};
1006         u8 cable_tech = 0;
1007         u8 cable_spec = 0;
1008         u16 enforce_sfp = 0;
1009
1010         DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1011
1012         if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1013                 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1014                 status = IXGBE_ERR_SFP_NOT_PRESENT;
1015                 goto out;
1016         }
1017
1018         status = hw->phy.ops.read_i2c_eeprom(hw,
1019                                              IXGBE_SFF_IDENTIFIER,
1020                                              &identifier);
1021
1022         if (status != IXGBE_SUCCESS)
1023                 goto err_read_i2c_eeprom;
1024
1025         /* LAN ID is needed for sfp_type determination */
1026         hw->mac.ops.set_lan_id(hw);
1027
1028         if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1029                 hw->phy.type = ixgbe_phy_sfp_unsupported;
1030                 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1031         } else {
1032                 status = hw->phy.ops.read_i2c_eeprom(hw,
1033                                                      IXGBE_SFF_1GBE_COMP_CODES,
1034                                                      &comp_codes_1g);
1035
1036                 if (status != IXGBE_SUCCESS)
1037                         goto err_read_i2c_eeprom;
1038
1039                 status = hw->phy.ops.read_i2c_eeprom(hw,
1040                                                      IXGBE_SFF_10GBE_COMP_CODES,
1041                                                      &comp_codes_10g);
1042
1043                 if (status != IXGBE_SUCCESS)
1044                         goto err_read_i2c_eeprom;
1045                 status = hw->phy.ops.read_i2c_eeprom(hw,
1046                                                      IXGBE_SFF_CABLE_TECHNOLOGY,
1047                                                      &cable_tech);
1048
1049                 if (status != IXGBE_SUCCESS)
1050                         goto err_read_i2c_eeprom;
1051
1052                  /* ID Module
1053                   * =========
1054                   * 0   SFP_DA_CU
1055                   * 1   SFP_SR
1056                   * 2   SFP_LR
1057                   * 3   SFP_DA_CORE0 - 82599-specific
1058                   * 4   SFP_DA_CORE1 - 82599-specific
1059                   * 5   SFP_SR/LR_CORE0 - 82599-specific
1060                   * 6   SFP_SR/LR_CORE1 - 82599-specific
1061                   * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1062                   * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1063                   * 9   SFP_1g_cu_CORE0 - 82599-specific
1064                   * 10  SFP_1g_cu_CORE1 - 82599-specific
1065                   * 11  SFP_1g_sx_CORE0 - 82599-specific
1066                   * 12  SFP_1g_sx_CORE1 - 82599-specific
1067                   */
1068                 if (hw->mac.type == ixgbe_mac_82598EB) {
1069                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1070                                 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1071                         else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1072                                 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1073                         else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1074                                 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1075                         else
1076                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1077                 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1078                         if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1079                                 if (hw->bus.lan_id == 0)
1080                                         hw->phy.sfp_type =
1081                                                      ixgbe_sfp_type_da_cu_core0;
1082                                 else
1083                                         hw->phy.sfp_type =
1084                                                      ixgbe_sfp_type_da_cu_core1;
1085                         } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1086                                 hw->phy.ops.read_i2c_eeprom(
1087                                                 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1088                                                 &cable_spec);
1089                                 if (cable_spec &
1090                                     IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1091                                         if (hw->bus.lan_id == 0)
1092                                                 hw->phy.sfp_type =
1093                                                 ixgbe_sfp_type_da_act_lmt_core0;
1094                                         else
1095                                                 hw->phy.sfp_type =
1096                                                 ixgbe_sfp_type_da_act_lmt_core1;
1097                                 } else {
1098                                         hw->phy.sfp_type =
1099                                                         ixgbe_sfp_type_unknown;
1100                                 }
1101                         } else if (comp_codes_10g &
1102                                    (IXGBE_SFF_10GBASESR_CAPABLE |
1103                                     IXGBE_SFF_10GBASELR_CAPABLE)) {
1104                                 if (hw->bus.lan_id == 0)
1105                                         hw->phy.sfp_type =
1106                                                       ixgbe_sfp_type_srlr_core0;
1107                                 else
1108                                         hw->phy.sfp_type =
1109                                                       ixgbe_sfp_type_srlr_core1;
1110 #ifdef SUPPORT_10GBASE_ER
1111                         } else if (comp_codes_10g &
1112                                    IXGBE_SFF_10GBASEER_CAPABLE) {
1113                                 if (hw->bus.lan_id == 0)
1114                                         hw->phy.sfp_type =
1115                                                         ixgbe_sfp_type_er_core0;
1116                                 else
1117                                         hw->phy.sfp_type =
1118                                                         ixgbe_sfp_type_er_core1;
1119 #endif /* SUPPORT_10GBASE_ER */
1120                         } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1121                                 if (hw->bus.lan_id == 0)
1122                                         hw->phy.sfp_type =
1123                                                 ixgbe_sfp_type_1g_cu_core0;
1124                                 else
1125                                         hw->phy.sfp_type =
1126                                                 ixgbe_sfp_type_1g_cu_core1;
1127                         } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1128                                 if (hw->bus.lan_id == 0)
1129                                         hw->phy.sfp_type =
1130                                                 ixgbe_sfp_type_1g_sx_core0;
1131                                 else
1132                                         hw->phy.sfp_type =
1133                                                 ixgbe_sfp_type_1g_sx_core1;
1134 #ifdef SUPPORT_1000BASE_LX
1135                         } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1136                                 if (hw->bus.lan_id == 0)
1137                                         hw->phy.sfp_type =
1138                                                 ixgbe_sfp_type_1g_lx_core0;
1139                                 else
1140                                         hw->phy.sfp_type =
1141                                                 ixgbe_sfp_type_1g_lx_core1;
1142 #endif /* SUPPORT_1000BASE_LX */
1143                         } else {
1144                                 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1145                         }
1146                 }
1147
1148                 if (hw->phy.sfp_type != stored_sfp_type)
1149                         hw->phy.sfp_setup_needed = true;
1150
1151                 /* Determine if the SFP+ PHY is dual speed or not. */
1152                 hw->phy.multispeed_fiber = false;
1153                 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1154                    (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1155                    ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1156                    (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1157                         hw->phy.multispeed_fiber = true;
1158
1159                 /* Determine PHY vendor */
1160                 if (hw->phy.type != ixgbe_phy_nl) {
1161                         hw->phy.id = identifier;
1162                         status = hw->phy.ops.read_i2c_eeprom(hw,
1163                                                     IXGBE_SFF_VENDOR_OUI_BYTE0,
1164                                                     &oui_bytes[0]);
1165
1166                         if (status != IXGBE_SUCCESS)
1167                                 goto err_read_i2c_eeprom;
1168
1169                         status = hw->phy.ops.read_i2c_eeprom(hw,
1170                                                     IXGBE_SFF_VENDOR_OUI_BYTE1,
1171                                                     &oui_bytes[1]);
1172
1173                         if (status != IXGBE_SUCCESS)
1174                                 goto err_read_i2c_eeprom;
1175
1176                         status = hw->phy.ops.read_i2c_eeprom(hw,
1177                                                     IXGBE_SFF_VENDOR_OUI_BYTE2,
1178                                                     &oui_bytes[2]);
1179
1180                         if (status != IXGBE_SUCCESS)
1181                                 goto err_read_i2c_eeprom;
1182
1183                         vendor_oui =
1184                           ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1185                            (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1186                            (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1187
1188                         switch (vendor_oui) {
1189                         case IXGBE_SFF_VENDOR_OUI_TYCO:
1190                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1191                                         hw->phy.type =
1192                                                     ixgbe_phy_sfp_passive_tyco;
1193                                 break;
1194                         case IXGBE_SFF_VENDOR_OUI_FTL:
1195                                 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1196                                         hw->phy.type = ixgbe_phy_sfp_ftl_active;
1197                                 else
1198                                         hw->phy.type = ixgbe_phy_sfp_ftl;
1199                                 break;
1200                         case IXGBE_SFF_VENDOR_OUI_AVAGO:
1201                                 hw->phy.type = ixgbe_phy_sfp_avago;
1202                                 break;
1203                         case IXGBE_SFF_VENDOR_OUI_INTEL:
1204                                 hw->phy.type = ixgbe_phy_sfp_intel;
1205                                 break;
1206                         default:
1207                                 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1208                                         hw->phy.type =
1209                                                  ixgbe_phy_sfp_passive_unknown;
1210                                 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1211                                         hw->phy.type =
1212                                                 ixgbe_phy_sfp_active_unknown;
1213                                 else
1214                                         hw->phy.type = ixgbe_phy_sfp_unknown;
1215                                 break;
1216                         }
1217                 }
1218
1219                 /* Allow any DA cable vendor */
1220                 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1221                     IXGBE_SFF_DA_ACTIVE_CABLE)) {
1222                         status = IXGBE_SUCCESS;
1223                         goto out;
1224                 }
1225
1226                 /* Verify supported 1G SFP modules */
1227                 if (comp_codes_10g == 0 &&
1228                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1229                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1230 #ifdef SUPPORT_1000BASE_LX
1231                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1232                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1233 #endif
1234                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1235                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1236                         hw->phy.type = ixgbe_phy_sfp_unsupported;
1237                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1238                         goto out;
1239                 }
1240
1241                 /* Anything else 82598-based is supported */
1242                 if (hw->mac.type == ixgbe_mac_82598EB) {
1243                         status = IXGBE_SUCCESS;
1244                         goto out;
1245                 }
1246
1247                 ixgbe_get_device_caps(hw, &enforce_sfp);
1248                 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1249                     !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1250                       hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1251 #ifdef SUPPORT_1000BASE_LX
1252                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1253                       hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1254 #endif
1255 #ifdef SUPPORT_10GBASE_ER
1256                       hw->phy.sfp_type == ixgbe_sfp_type_er_core0 ||
1257                       hw->phy.sfp_type == ixgbe_sfp_type_er_core1 ||
1258 #endif
1259                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1260                       hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1261                         /* Make sure we're a supported PHY type */
1262                         if (hw->phy.type == ixgbe_phy_sfp_intel) {
1263                                 status = IXGBE_SUCCESS;
1264                         } else {
1265                                 if (hw->allow_unsupported_sfp == true) {
1266                                         EWARN(hw, "WARNING: Intel (R) Network "
1267                                               "Connections are quality tested "
1268                                               "using Intel (R) Ethernet Optics."
1269                                               " Using untested modules is not "
1270                                               "supported and may cause unstable"
1271                                               " operation or damage to the "
1272                                               "module or the adapter. Intel "
1273                                               "Corporation is not responsible "
1274                                               "for any harm caused by using "
1275                                               "untested modules.\n", status);
1276                                         status = IXGBE_SUCCESS;
1277                                 } else {
1278                                         DEBUGOUT("SFP+ module not supported\n");
1279                                         hw->phy.type =
1280                                                 ixgbe_phy_sfp_unsupported;
1281                                         status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1282                                 }
1283                         }
1284                 } else {
1285                         status = IXGBE_SUCCESS;
1286                 }
1287         }
1288
1289 out:
1290         return status;
1291
1292 err_read_i2c_eeprom:
1293         hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1294         if (hw->phy.type != ixgbe_phy_nl) {
1295                 hw->phy.id = 0;
1296                 hw->phy.type = ixgbe_phy_unknown;
1297         }
1298         return IXGBE_ERR_SFP_NOT_PRESENT;
1299 }
1300
1301
1302
1303 /**
1304  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1305  *  @hw: pointer to hardware structure
1306  *  @list_offset: offset to the SFP ID list
1307  *  @data_offset: offset to the SFP data block
1308  *
1309  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1310  *  so it returns the offsets to the phy init sequence block.
1311  **/
1312 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1313                                         u16 *list_offset,
1314                                         u16 *data_offset)
1315 {
1316         u16 sfp_id;
1317         u16 sfp_type = hw->phy.sfp_type;
1318
1319         DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1320
1321         if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1322                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1323
1324         if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1325                 return IXGBE_ERR_SFP_NOT_PRESENT;
1326
1327         if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1328             (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1329                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1330
1331         /*
1332          * Limiting active cables and 1G Phys must be initialized as
1333          * SR modules
1334          */
1335         if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1336 #ifdef SUPPORT_10GBASE_ER
1337             sfp_type == ixgbe_sfp_type_er_core0 ||
1338 #endif /* SUPPORT_10GBASE_ER */
1339 #ifdef SUPPORT_1000BASE_LX
1340             sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1341 #endif /* SUPPORT_1000BASE_LX */
1342             sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1343             sfp_type == ixgbe_sfp_type_1g_sx_core0)
1344                 sfp_type = ixgbe_sfp_type_srlr_core0;
1345         else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1346 #ifdef SUPPORT_10GBASE_ER
1347                  sfp_type == ixgbe_sfp_type_er_core1 ||
1348 #endif /* SUPPORT_10GBASE_ER */
1349 #ifdef SUPPORT_1000BASE_LX
1350                  sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1351 #endif /* SUPPORT_1000BASE_LX */
1352                  sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1353                  sfp_type == ixgbe_sfp_type_1g_sx_core1)
1354                 sfp_type = ixgbe_sfp_type_srlr_core1;
1355
1356         /* Read offset to PHY init contents */
1357         if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1358                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1359                               "eeprom read at offset %d failed",
1360                               IXGBE_PHY_INIT_OFFSET_NL);
1361                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1362         }
1363
1364         if ((!*list_offset) || (*list_offset == 0xFFFF))
1365                 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1366
1367         /* Shift offset to first ID word */
1368         (*list_offset)++;
1369
1370         /*
1371          * Find the matching SFP ID in the EEPROM
1372          * and program the init sequence
1373          */
1374         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1375                 goto err_phy;
1376
1377         while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1378                 if (sfp_id == sfp_type) {
1379                         (*list_offset)++;
1380                         if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1381                                 goto err_phy;
1382                         if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1383                                 DEBUGOUT("SFP+ module not supported\n");
1384                                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1385                         } else {
1386                                 break;
1387                         }
1388                 } else {
1389                         (*list_offset) += 2;
1390                         if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1391                                 goto err_phy;
1392                 }
1393         }
1394
1395         if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1396                 DEBUGOUT("No matching SFP+ module found\n");
1397                 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1398         }
1399
1400         return IXGBE_SUCCESS;
1401
1402 err_phy:
1403         ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1404                       "eeprom read at offset %d failed", *list_offset);
1405         return IXGBE_ERR_PHY;
1406 }
1407
1408 /**
1409  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1410  *  @hw: pointer to hardware structure
1411  *  @byte_offset: EEPROM byte offset to read
1412  *  @eeprom_data: value read
1413  *
1414  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1415  **/
1416 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1417                                   u8 *eeprom_data)
1418 {
1419         DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1420
1421         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1422                                          IXGBE_I2C_EEPROM_DEV_ADDR,
1423                                          eeprom_data);
1424 }
1425
1426 /**
1427  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1428  *  @hw: pointer to hardware structure
1429  *  @byte_offset: byte offset at address 0xA2
1430  *  @eeprom_data: value read
1431  *
1432  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1433  **/
1434 STATIC s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1435                                           u8 *sff8472_data)
1436 {
1437         return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1438                                          IXGBE_I2C_EEPROM_DEV_ADDR2,
1439                                          sff8472_data);
1440 }
1441
1442 /**
1443  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1444  *  @hw: pointer to hardware structure
1445  *  @byte_offset: EEPROM byte offset to write
1446  *  @eeprom_data: value to write
1447  *
1448  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1449  **/
1450 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1451                                    u8 eeprom_data)
1452 {
1453         DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1454
1455         return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1456                                           IXGBE_I2C_EEPROM_DEV_ADDR,
1457                                           eeprom_data);
1458 }
1459
1460 /**
1461  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1462  *  @hw: pointer to hardware structure
1463  *  @byte_offset: byte offset to read
1464  *  @data: value read
1465  *
1466  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1467  *  a specified device address.
1468  **/
1469 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1470                                 u8 dev_addr, u8 *data)
1471 {
1472         s32 status = IXGBE_SUCCESS;
1473         u32 max_retry = 10;
1474         u32 retry = 0;
1475         u16 swfw_mask = 0;
1476         bool nack = 1;
1477         *data = 0;
1478
1479         DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1480
1481         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1482                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1483         else
1484                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1485
1486         do {
1487                 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1488                     != IXGBE_SUCCESS) {
1489                         status = IXGBE_ERR_SWFW_SYNC;
1490                         goto read_byte_out;
1491                 }
1492
1493                 ixgbe_i2c_start(hw);
1494
1495                 /* Device Address and write indication */
1496                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1497                 if (status != IXGBE_SUCCESS)
1498                         goto fail;
1499
1500                 status = ixgbe_get_i2c_ack(hw);
1501                 if (status != IXGBE_SUCCESS)
1502                         goto fail;
1503
1504                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1505                 if (status != IXGBE_SUCCESS)
1506                         goto fail;
1507
1508                 status = ixgbe_get_i2c_ack(hw);
1509                 if (status != IXGBE_SUCCESS)
1510                         goto fail;
1511
1512                 ixgbe_i2c_start(hw);
1513
1514                 /* Device Address and read indication */
1515                 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1516                 if (status != IXGBE_SUCCESS)
1517                         goto fail;
1518
1519                 status = ixgbe_get_i2c_ack(hw);
1520                 if (status != IXGBE_SUCCESS)
1521                         goto fail;
1522
1523                 status = ixgbe_clock_in_i2c_byte(hw, data);
1524                 if (status != IXGBE_SUCCESS)
1525                         goto fail;
1526
1527                 status = ixgbe_clock_out_i2c_bit(hw, nack);
1528                 if (status != IXGBE_SUCCESS)
1529                         goto fail;
1530
1531                 ixgbe_i2c_stop(hw);
1532                 break;
1533
1534 fail:
1535                 ixgbe_i2c_bus_clear(hw);
1536                 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1537                 msec_delay(100);
1538                 retry++;
1539                 if (retry < max_retry)
1540                         DEBUGOUT("I2C byte read error - Retrying.\n");
1541                 else
1542                         DEBUGOUT("I2C byte read error.\n");
1543
1544         } while (retry < max_retry);
1545
1546         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1547
1548 read_byte_out:
1549         return status;
1550 }
1551
1552 /**
1553  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1554  *  @hw: pointer to hardware structure
1555  *  @byte_offset: byte offset to write
1556  *  @data: value to write
1557  *
1558  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
1559  *  a specified device address.
1560  **/
1561 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1562                                  u8 dev_addr, u8 data)
1563 {
1564         s32 status = IXGBE_SUCCESS;
1565         u32 max_retry = 1;
1566         u32 retry = 0;
1567         u16 swfw_mask = 0;
1568
1569         DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1570
1571         if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1572                 swfw_mask = IXGBE_GSSR_PHY1_SM;
1573         else
1574                 swfw_mask = IXGBE_GSSR_PHY0_SM;
1575
1576         if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1577                 status = IXGBE_ERR_SWFW_SYNC;
1578                 goto write_byte_out;
1579         }
1580
1581         do {
1582                 ixgbe_i2c_start(hw);
1583
1584                 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1585                 if (status != IXGBE_SUCCESS)
1586                         goto fail;
1587
1588                 status = ixgbe_get_i2c_ack(hw);
1589                 if (status != IXGBE_SUCCESS)
1590                         goto fail;
1591
1592                 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1593                 if (status != IXGBE_SUCCESS)
1594                         goto fail;
1595
1596                 status = ixgbe_get_i2c_ack(hw);
1597                 if (status != IXGBE_SUCCESS)
1598                         goto fail;
1599
1600                 status = ixgbe_clock_out_i2c_byte(hw, data);
1601                 if (status != IXGBE_SUCCESS)
1602                         goto fail;
1603
1604                 status = ixgbe_get_i2c_ack(hw);
1605                 if (status != IXGBE_SUCCESS)
1606                         goto fail;
1607
1608                 ixgbe_i2c_stop(hw);
1609                 break;
1610
1611 fail:
1612                 ixgbe_i2c_bus_clear(hw);
1613                 retry++;
1614                 if (retry < max_retry)
1615                         DEBUGOUT("I2C byte write error - Retrying.\n");
1616                 else
1617                         DEBUGOUT("I2C byte write error.\n");
1618         } while (retry < max_retry);
1619
1620         hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1621
1622 write_byte_out:
1623         return status;
1624 }
1625
1626 /**
1627  *  ixgbe_i2c_start - Sets I2C start condition
1628  *  @hw: pointer to hardware structure
1629  *
1630  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
1631  **/
1632 STATIC void ixgbe_i2c_start(struct ixgbe_hw *hw)
1633 {
1634         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1635
1636         DEBUGFUNC("ixgbe_i2c_start");
1637
1638         /* Start condition must begin with data and clock high */
1639         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1640         ixgbe_raise_i2c_clk(hw, &i2cctl);
1641
1642         /* Setup time for start condition (4.7us) */
1643         usec_delay(IXGBE_I2C_T_SU_STA);
1644
1645         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1646
1647         /* Hold time for start condition (4us) */
1648         usec_delay(IXGBE_I2C_T_HD_STA);
1649
1650         ixgbe_lower_i2c_clk(hw, &i2cctl);
1651
1652         /* Minimum low period of clock is 4.7 us */
1653         usec_delay(IXGBE_I2C_T_LOW);
1654
1655 }
1656
1657 /**
1658  *  ixgbe_i2c_stop - Sets I2C stop condition
1659  *  @hw: pointer to hardware structure
1660  *
1661  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
1662  **/
1663 STATIC void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1664 {
1665         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1666
1667         DEBUGFUNC("ixgbe_i2c_stop");
1668
1669         /* Stop condition must begin with data low and clock high */
1670         ixgbe_set_i2c_data(hw, &i2cctl, 0);
1671         ixgbe_raise_i2c_clk(hw, &i2cctl);
1672
1673         /* Setup time for stop condition (4us) */
1674         usec_delay(IXGBE_I2C_T_SU_STO);
1675
1676         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1677
1678         /* bus free time between stop and start (4.7us)*/
1679         usec_delay(IXGBE_I2C_T_BUF);
1680 }
1681
1682 /**
1683  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1684  *  @hw: pointer to hardware structure
1685  *  @data: data byte to clock in
1686  *
1687  *  Clocks in one byte data via I2C data/clock
1688  **/
1689 STATIC s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1690 {
1691         s32 i;
1692         bool bit = 0;
1693
1694         DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1695
1696         for (i = 7; i >= 0; i--) {
1697                 ixgbe_clock_in_i2c_bit(hw, &bit);
1698                 *data |= bit << i;
1699         }
1700
1701         return IXGBE_SUCCESS;
1702 }
1703
1704 /**
1705  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1706  *  @hw: pointer to hardware structure
1707  *  @data: data byte clocked out
1708  *
1709  *  Clocks out one byte data via I2C data/clock
1710  **/
1711 STATIC s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1712 {
1713         s32 status = IXGBE_SUCCESS;
1714         s32 i;
1715         u32 i2cctl;
1716         bool bit;
1717
1718         DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1719
1720         for (i = 7; i >= 0; i--) {
1721                 bit = (data >> i) & 0x1;
1722                 status = ixgbe_clock_out_i2c_bit(hw, bit);
1723
1724                 if (status != IXGBE_SUCCESS)
1725                         break;
1726         }
1727
1728         /* Release SDA line (set high) */
1729         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1730         i2cctl |= IXGBE_I2C_DATA_OUT;
1731         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1732         IXGBE_WRITE_FLUSH(hw);
1733
1734         return status;
1735 }
1736
1737 /**
1738  *  ixgbe_get_i2c_ack - Polls for I2C ACK
1739  *  @hw: pointer to hardware structure
1740  *
1741  *  Clocks in/out one bit via I2C data/clock
1742  **/
1743 STATIC s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1744 {
1745         s32 status = IXGBE_SUCCESS;
1746         u32 i = 0;
1747         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1748         u32 timeout = 10;
1749         bool ack = 1;
1750
1751         DEBUGFUNC("ixgbe_get_i2c_ack");
1752
1753         ixgbe_raise_i2c_clk(hw, &i2cctl);
1754
1755
1756         /* Minimum high period of clock is 4us */
1757         usec_delay(IXGBE_I2C_T_HIGH);
1758
1759         /* Poll for ACK.  Note that ACK in I2C spec is
1760          * transition from 1 to 0 */
1761         for (i = 0; i < timeout; i++) {
1762                 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1763                 ack = ixgbe_get_i2c_data(&i2cctl);
1764
1765                 usec_delay(1);
1766                 if (!ack)
1767                         break;
1768         }
1769
1770         if (ack == 1) {
1771                 ERROR_REPORT1(IXGBE_ERROR_POLLING,
1772                              "I2C ack was not received.\n");
1773                 status = IXGBE_ERR_I2C;
1774         }
1775
1776         ixgbe_lower_i2c_clk(hw, &i2cctl);
1777
1778         /* Minimum low period of clock is 4.7 us */
1779         usec_delay(IXGBE_I2C_T_LOW);
1780
1781         return status;
1782 }
1783
1784 /**
1785  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1786  *  @hw: pointer to hardware structure
1787  *  @data: read data value
1788  *
1789  *  Clocks in one bit via I2C data/clock
1790  **/
1791 STATIC s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1792 {
1793         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1794
1795         DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1796
1797         ixgbe_raise_i2c_clk(hw, &i2cctl);
1798
1799         /* Minimum high period of clock is 4us */
1800         usec_delay(IXGBE_I2C_T_HIGH);
1801
1802         i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1803         *data = ixgbe_get_i2c_data(&i2cctl);
1804
1805         ixgbe_lower_i2c_clk(hw, &i2cctl);
1806
1807         /* Minimum low period of clock is 4.7 us */
1808         usec_delay(IXGBE_I2C_T_LOW);
1809
1810         return IXGBE_SUCCESS;
1811 }
1812
1813 /**
1814  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1815  *  @hw: pointer to hardware structure
1816  *  @data: data value to write
1817  *
1818  *  Clocks out one bit via I2C data/clock
1819  **/
1820 STATIC s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1821 {
1822         s32 status;
1823         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1824
1825         DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1826
1827         status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1828         if (status == IXGBE_SUCCESS) {
1829                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1830
1831                 /* Minimum high period of clock is 4us */
1832                 usec_delay(IXGBE_I2C_T_HIGH);
1833
1834                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1835
1836                 /* Minimum low period of clock is 4.7 us.
1837                  * This also takes care of the data hold time.
1838                  */
1839                 usec_delay(IXGBE_I2C_T_LOW);
1840         } else {
1841                 status = IXGBE_ERR_I2C;
1842                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1843                              "I2C data was not set to %X\n", data);
1844         }
1845
1846         return status;
1847 }
1848
1849 /**
1850  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1851  *  @hw: pointer to hardware structure
1852  *  @i2cctl: Current value of I2CCTL register
1853  *
1854  *  Raises the I2C clock line '0'->'1'
1855  **/
1856 STATIC void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1857 {
1858         u32 i = 0;
1859         u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
1860         u32 i2cctl_r = 0;
1861
1862         DEBUGFUNC("ixgbe_raise_i2c_clk");
1863
1864         for (i = 0; i < timeout; i++) {
1865                 *i2cctl |= IXGBE_I2C_CLK_OUT;
1866
1867                 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1868                 IXGBE_WRITE_FLUSH(hw);
1869                 /* SCL rise time (1000ns) */
1870                 usec_delay(IXGBE_I2C_T_RISE);
1871
1872                 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1873                 if (i2cctl_r & IXGBE_I2C_CLK_IN)
1874                         break;
1875         }
1876 }
1877
1878 /**
1879  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1880  *  @hw: pointer to hardware structure
1881  *  @i2cctl: Current value of I2CCTL register
1882  *
1883  *  Lowers the I2C clock line '1'->'0'
1884  **/
1885 STATIC void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1886 {
1887
1888         DEBUGFUNC("ixgbe_lower_i2c_clk");
1889
1890         *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1891
1892         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1893         IXGBE_WRITE_FLUSH(hw);
1894
1895         /* SCL fall time (300ns) */
1896         usec_delay(IXGBE_I2C_T_FALL);
1897 }
1898
1899 /**
1900  *  ixgbe_set_i2c_data - Sets the I2C data bit
1901  *  @hw: pointer to hardware structure
1902  *  @i2cctl: Current value of I2CCTL register
1903  *  @data: I2C data value (0 or 1) to set
1904  *
1905  *  Sets the I2C data bit
1906  **/
1907 STATIC s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1908 {
1909         s32 status = IXGBE_SUCCESS;
1910
1911         DEBUGFUNC("ixgbe_set_i2c_data");
1912
1913         if (data)
1914                 *i2cctl |= IXGBE_I2C_DATA_OUT;
1915         else
1916                 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1917
1918         IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1919         IXGBE_WRITE_FLUSH(hw);
1920
1921         /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1922         usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1923
1924         /* Verify data was set correctly */
1925         *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1926         if (data != ixgbe_get_i2c_data(i2cctl)) {
1927                 status = IXGBE_ERR_I2C;
1928                 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1929                              "Error - I2C data was not set to %X.\n",
1930                              data);
1931         }
1932
1933         return status;
1934 }
1935
1936 /**
1937  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
1938  *  @hw: pointer to hardware structure
1939  *  @i2cctl: Current value of I2CCTL register
1940  *
1941  *  Returns the I2C data bit value
1942  **/
1943 STATIC bool ixgbe_get_i2c_data(u32 *i2cctl)
1944 {
1945         bool data;
1946
1947         DEBUGFUNC("ixgbe_get_i2c_data");
1948
1949         if (*i2cctl & IXGBE_I2C_DATA_IN)
1950                 data = 1;
1951         else
1952                 data = 0;
1953
1954         return data;
1955 }
1956
1957 /**
1958  *  ixgbe_i2c_bus_clear - Clears the I2C bus
1959  *  @hw: pointer to hardware structure
1960  *
1961  *  Clears the I2C bus by sending nine clock pulses.
1962  *  Used when data line is stuck low.
1963  **/
1964 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1965 {
1966         u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1967         u32 i;
1968
1969         DEBUGFUNC("ixgbe_i2c_bus_clear");
1970
1971         ixgbe_i2c_start(hw);
1972
1973         ixgbe_set_i2c_data(hw, &i2cctl, 1);
1974
1975         for (i = 0; i < 9; i++) {
1976                 ixgbe_raise_i2c_clk(hw, &i2cctl);
1977
1978                 /* Min high period of clock is 4us */
1979                 usec_delay(IXGBE_I2C_T_HIGH);
1980
1981                 ixgbe_lower_i2c_clk(hw, &i2cctl);
1982
1983                 /* Min low period of clock is 4.7us*/
1984                 usec_delay(IXGBE_I2C_T_LOW);
1985         }
1986
1987         ixgbe_i2c_start(hw);
1988
1989         /* Put the i2c bus back to default state */
1990         ixgbe_i2c_stop(hw);
1991 }
1992
1993 /**
1994  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
1995  *  @hw: pointer to hardware structure
1996  *
1997  *  Checks if the LASI temp alarm status was triggered due to overtemp
1998  **/
1999 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2000 {
2001         s32 status = IXGBE_SUCCESS;
2002         u16 phy_data = 0;
2003
2004         DEBUGFUNC("ixgbe_tn_check_overtemp");
2005
2006         if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2007                 goto out;
2008
2009         /* Check that the LASI temp alarm status was triggered */
2010         hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2011                              IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2012
2013         if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2014                 goto out;
2015
2016         status = IXGBE_ERR_OVERTEMP;
2017         ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2018 out:
2019         return status;
2020 }