1 /******************************************************************************
3 Copyright (c) 2001-2010, Intel Corporation
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
32 ******************************************************************************/
35 #include "ixgbe_api.h"
36 #include "ixgbe_common.h"
37 #include "ixgbe_phy.h"
39 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
40 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
41 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
42 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
43 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
44 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
45 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
46 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
47 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
49 static bool ixgbe_get_i2c_data(u32 *i2cctl);
50 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
53 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs
54 * @hw: pointer to the hardware structure
56 * Initialize the function pointers.
58 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
60 struct ixgbe_phy_info *phy = &hw->phy;
62 DEBUGFUNC("ixgbe_init_phy_ops_generic");
65 phy->ops.identify = &ixgbe_identify_phy_generic;
66 phy->ops.reset = &ixgbe_reset_phy_generic;
67 phy->ops.read_reg = &ixgbe_read_phy_reg_generic;
68 phy->ops.write_reg = &ixgbe_write_phy_reg_generic;
69 phy->ops.setup_link = &ixgbe_setup_phy_link_generic;
70 phy->ops.setup_link_speed = &ixgbe_setup_phy_link_speed_generic;
71 phy->ops.check_link = NULL;
72 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
73 phy->ops.read_i2c_byte = &ixgbe_read_i2c_byte_generic;
74 phy->ops.write_i2c_byte = &ixgbe_write_i2c_byte_generic;
75 phy->ops.read_i2c_eeprom = &ixgbe_read_i2c_eeprom_generic;
76 phy->ops.write_i2c_eeprom = &ixgbe_write_i2c_eeprom_generic;
77 phy->ops.i2c_bus_clear = &ixgbe_i2c_bus_clear;
78 phy->ops.identify_sfp = &ixgbe_identify_sfp_module_generic;
79 phy->sfp_type = ixgbe_sfp_type_unknown;
80 phy->ops.check_overtemp = &ixgbe_tn_check_overtemp;
85 * ixgbe_identify_phy_generic - Get physical layer module
86 * @hw: pointer to hardware structure
88 * Determines the physical layer module found on the current adapter.
90 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
92 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
96 DEBUGFUNC("ixgbe_identify_phy_generic");
98 if (hw->phy.type == ixgbe_phy_unknown) {
99 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
100 if (ixgbe_validate_phy_addr(hw, phy_addr)) {
101 hw->phy.addr = phy_addr;
102 ixgbe_get_phy_id(hw);
104 ixgbe_get_phy_type_from_id(hw->phy.id);
106 if (hw->phy.type == ixgbe_phy_unknown) {
107 hw->phy.ops.read_reg(hw,
108 IXGBE_MDIO_PHY_EXT_ABILITY,
109 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
112 (IXGBE_MDIO_PHY_10GBASET_ABILITY |
113 IXGBE_MDIO_PHY_1000BASET_ABILITY))
115 ixgbe_phy_cu_unknown;
121 status = IXGBE_SUCCESS;
125 /* clear value if nothing found */
126 if (status != IXGBE_SUCCESS)
129 status = IXGBE_SUCCESS;
136 * ixgbe_validate_phy_addr - Determines phy address is valid
137 * @hw: pointer to hardware structure
140 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
145 DEBUGFUNC("ixgbe_validate_phy_addr");
147 hw->phy.addr = phy_addr;
148 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
149 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
151 if (phy_id != 0xFFFF && phy_id != 0x0)
158 * ixgbe_get_phy_id - Get the phy type
159 * @hw: pointer to hardware structure
162 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
168 DEBUGFUNC("ixgbe_get_phy_id");
170 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
171 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
174 if (status == IXGBE_SUCCESS) {
175 hw->phy.id = (u32)(phy_id_high << 16);
176 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
177 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
179 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
180 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
186 * ixgbe_get_phy_type_from_id - Get the phy type
187 * @hw: pointer to hardware structure
190 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
192 enum ixgbe_phy_type phy_type;
194 DEBUGFUNC("ixgbe_get_phy_type_from_id");
198 phy_type = ixgbe_phy_tn;
201 phy_type = ixgbe_phy_aq;
204 phy_type = ixgbe_phy_qt;
207 phy_type = ixgbe_phy_nl;
210 phy_type = ixgbe_phy_unknown;
214 DEBUGOUT1("phy type found is %d\n", phy_type);
219 * ixgbe_reset_phy_generic - Performs a PHY reset
220 * @hw: pointer to hardware structure
222 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
226 s32 status = IXGBE_SUCCESS;
228 DEBUGFUNC("ixgbe_reset_phy_generic");
230 if (hw->phy.type == ixgbe_phy_unknown)
231 status = ixgbe_identify_phy_generic(hw);
233 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
236 /* Don't reset PHY if it's shut down due to overtemp. */
237 if (!hw->phy.reset_if_overtemp &&
238 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
242 * Perform soft PHY reset to the PHY_XS.
243 * This will cause a soft reset to the PHY
245 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
246 IXGBE_MDIO_PHY_XS_DEV_TYPE,
247 IXGBE_MDIO_PHY_XS_RESET);
250 * Poll for reset bit to self-clear indicating reset is complete.
251 * Some PHYs could take up to 3 seconds to complete and need about
252 * 1.7 usec delay after the reset is complete.
254 for (i = 0; i < 30; i++) {
256 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
257 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl);
258 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
264 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
265 status = IXGBE_ERR_RESET_FAILED;
266 DEBUGOUT("PHY reset polling failed to complete.\n");
274 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
275 * @hw: pointer to hardware structure
276 * @reg_addr: 32 bit address of PHY register to read
277 * @phy_data: Pointer to read data from PHY register
279 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
280 u32 device_type, u16 *phy_data)
285 s32 status = IXGBE_SUCCESS;
288 DEBUGFUNC("ixgbe_read_phy_reg_generic");
290 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
291 gssr = IXGBE_GSSR_PHY1_SM;
293 gssr = IXGBE_GSSR_PHY0_SM;
295 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
296 status = IXGBE_ERR_SWFW_SYNC;
298 if (status == IXGBE_SUCCESS) {
299 /* Setup and write the address cycle command */
300 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
301 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
302 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
303 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
305 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
308 * Check every 10 usec to see if the address cycle completed.
309 * The MDI Command bit will clear when the operation is
312 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
315 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
317 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
321 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
322 DEBUGOUT("PHY address command did not complete.\n");
323 status = IXGBE_ERR_PHY;
326 if (status == IXGBE_SUCCESS) {
328 * Address cycle complete, setup and write the read
331 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
332 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
333 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
334 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
336 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
339 * Check every 10 usec to see if the address cycle
340 * completed. The MDI Command bit will clear when the
341 * operation is complete
343 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
346 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
348 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
352 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
353 DEBUGOUT("PHY read command didn't complete\n");
354 status = IXGBE_ERR_PHY;
357 * Read operation is complete. Get the data
360 data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
361 data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
362 *phy_data = (u16)(data);
366 hw->mac.ops.release_swfw_sync(hw, gssr);
373 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
374 * @hw: pointer to hardware structure
375 * @reg_addr: 32 bit PHY register to write
376 * @device_type: 5 bit device type
377 * @phy_data: Data to write to the PHY register
379 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
380 u32 device_type, u16 phy_data)
384 s32 status = IXGBE_SUCCESS;
387 DEBUGFUNC("ixgbe_write_phy_reg_generic");
389 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
390 gssr = IXGBE_GSSR_PHY1_SM;
392 gssr = IXGBE_GSSR_PHY0_SM;
394 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != IXGBE_SUCCESS)
395 status = IXGBE_ERR_SWFW_SYNC;
397 if (status == IXGBE_SUCCESS) {
398 /* Put the data in the MDI single read and write data register*/
399 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
401 /* Setup and write the address cycle command */
402 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
403 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
404 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
405 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
407 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
410 * Check every 10 usec to see if the address cycle completed.
411 * The MDI Command bit will clear when the operation is
414 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
417 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
419 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
423 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
424 DEBUGOUT("PHY address cmd didn't complete\n");
425 status = IXGBE_ERR_PHY;
428 if (status == IXGBE_SUCCESS) {
430 * Address cycle complete, setup and write the write
433 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) |
434 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
435 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
436 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
438 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
441 * Check every 10 usec to see if the address cycle
442 * completed. The MDI Command bit will clear when the
443 * operation is complete
445 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
448 command = IXGBE_READ_REG(hw, IXGBE_MSCA);
450 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
454 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
455 DEBUGOUT("PHY address cmd didn't complete\n");
456 status = IXGBE_ERR_PHY;
460 hw->mac.ops.release_swfw_sync(hw, gssr);
467 * ixgbe_setup_phy_link_generic - Set and restart autoneg
468 * @hw: pointer to hardware structure
470 * Restart autonegotiation and PHY and waits for completion.
472 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
474 s32 status = IXGBE_SUCCESS;
476 u32 max_time_out = 10;
477 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
478 bool autoneg = FALSE;
479 ixgbe_link_speed speed;
481 DEBUGFUNC("ixgbe_setup_phy_link_generic");
483 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
485 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
486 /* Set or unset auto-negotiation 10G advertisement */
487 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
488 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
491 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
492 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
493 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
495 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
496 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
500 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
501 /* Set or unset auto-negotiation 1G advertisement */
502 hw->phy.ops.read_reg(hw,
503 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
504 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
507 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
508 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
509 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
511 hw->phy.ops.write_reg(hw,
512 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
513 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
517 if (speed & IXGBE_LINK_SPEED_100_FULL) {
518 /* Set or unset auto-negotiation 100M advertisement */
519 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
520 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
523 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
524 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
525 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
526 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
528 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
529 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
533 /* Restart PHY autonegotiation and wait for completion */
534 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
535 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
537 autoneg_reg |= IXGBE_MII_RESTART;
539 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
540 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
542 /* Wait for autonegotiation to finish */
543 for (time_out = 0; time_out < max_time_out; time_out++) {
545 /* Restart PHY autonegotiation and wait for completion */
546 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
547 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
550 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
551 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
556 if (time_out == max_time_out) {
557 status = IXGBE_ERR_LINK_SETUP;
558 DEBUGOUT("ixgbe_setup_phy_link_generic: time out");
565 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
566 * @hw: pointer to hardware structure
567 * @speed: new link speed
568 * @autoneg: TRUE if autonegotiation enabled
570 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
571 ixgbe_link_speed speed,
573 bool autoneg_wait_to_complete)
575 UNREFERENCED_2PARAMETER(autoneg, autoneg_wait_to_complete);
577 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
580 * Clear autoneg_advertised and set new values based on input link
583 hw->phy.autoneg_advertised = 0;
585 if (speed & IXGBE_LINK_SPEED_10GB_FULL)
586 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
588 if (speed & IXGBE_LINK_SPEED_1GB_FULL)
589 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
591 if (speed & IXGBE_LINK_SPEED_100_FULL)
592 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
594 /* Setup link based on the new speed settings */
595 hw->phy.ops.setup_link(hw);
597 return IXGBE_SUCCESS;
601 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
602 * @hw: pointer to hardware structure
603 * @speed: pointer to link speed
604 * @autoneg: boolean auto-negotiation value
606 * Determines the link capabilities by reading the AUTOC register.
608 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
609 ixgbe_link_speed *speed,
612 s32 status = IXGBE_ERR_LINK_SETUP;
615 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
620 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
621 IXGBE_MDIO_PMA_PMD_DEV_TYPE,
624 if (status == IXGBE_SUCCESS) {
625 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
626 *speed |= IXGBE_LINK_SPEED_10GB_FULL;
627 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
628 *speed |= IXGBE_LINK_SPEED_1GB_FULL;
629 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
630 *speed |= IXGBE_LINK_SPEED_100_FULL;
637 * ixgbe_check_phy_link_tnx - Determine link and speed status
638 * @hw: pointer to hardware structure
640 * Reads the VS1 register to determine if link is up and the current speed for
643 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
646 s32 status = IXGBE_SUCCESS;
648 u32 max_time_out = 10;
653 DEBUGFUNC("ixgbe_check_phy_link_tnx");
655 /* Initialize speed and link to default case */
657 *speed = IXGBE_LINK_SPEED_10GB_FULL;
660 * Check current speed and link status of the PHY register.
661 * This is a vendor specific register and may have to
662 * be changed for other copper PHYs.
664 for (time_out = 0; time_out < max_time_out; time_out++) {
666 status = hw->phy.ops.read_reg(hw,
667 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
668 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
670 phy_link = phy_data &
671 IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
672 phy_speed = phy_data &
673 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
674 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
677 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
678 *speed = IXGBE_LINK_SPEED_1GB_FULL;
687 * ixgbe_setup_phy_link_tnx - Set and restart autoneg
688 * @hw: pointer to hardware structure
690 * Restart autonegotiation and PHY and waits for completion.
692 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
694 s32 status = IXGBE_SUCCESS;
696 u32 max_time_out = 10;
697 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
698 bool autoneg = FALSE;
699 ixgbe_link_speed speed;
701 DEBUGFUNC("ixgbe_setup_phy_link_tnx");
703 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
705 if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
706 /* Set or unset auto-negotiation 10G advertisement */
707 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
708 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
711 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
712 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
713 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
715 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
716 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
720 if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
721 /* Set or unset auto-negotiation 1G advertisement */
722 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
723 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
726 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
727 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
728 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
730 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
731 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
735 if (speed & IXGBE_LINK_SPEED_100_FULL) {
736 /* Set or unset auto-negotiation 100M advertisement */
737 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
738 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
741 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
742 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
743 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
745 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
746 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
750 /* Restart PHY autonegotiation and wait for completion */
751 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
752 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
754 autoneg_reg |= IXGBE_MII_RESTART;
756 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
757 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
759 /* Wait for autonegotiation to finish */
760 for (time_out = 0; time_out < max_time_out; time_out++) {
762 /* Restart PHY autonegotiation and wait for completion */
763 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS,
764 IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
767 autoneg_reg &= IXGBE_MII_AUTONEG_COMPLETE;
768 if (autoneg_reg == IXGBE_MII_AUTONEG_COMPLETE) {
773 if (time_out == max_time_out) {
774 status = IXGBE_ERR_LINK_SETUP;
775 DEBUGOUT("ixgbe_setup_phy_link_tnx: time out");
782 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
783 * @hw: pointer to hardware structure
784 * @firmware_version: pointer to the PHY Firmware Version
786 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
787 u16 *firmware_version)
789 s32 status = IXGBE_SUCCESS;
791 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
793 status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
794 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
801 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
802 * @hw: pointer to hardware structure
803 * @firmware_version: pointer to the PHY Firmware Version
805 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
806 u16 *firmware_version)
808 s32 status = IXGBE_SUCCESS;
810 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
812 status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
813 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
820 * ixgbe_reset_phy_nl - Performs a PHY reset
821 * @hw: pointer to hardware structure
823 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
825 u16 phy_offset, control, eword, edata, block_crc;
826 bool end_data = FALSE;
827 u16 list_offset, data_offset;
829 s32 ret_val = IXGBE_SUCCESS;
832 DEBUGFUNC("ixgbe_reset_phy_nl");
834 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
835 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
837 /* reset the PHY and poll for completion */
838 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
839 IXGBE_MDIO_PHY_XS_DEV_TYPE,
840 (phy_data | IXGBE_MDIO_PHY_XS_RESET));
842 for (i = 0; i < 100; i++) {
843 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
844 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
845 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
850 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
851 DEBUGOUT("PHY reset did not complete.\n");
852 ret_val = IXGBE_ERR_PHY;
856 /* Get init offsets */
857 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
859 if (ret_val != IXGBE_SUCCESS)
862 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
866 * Read control word from PHY init contents offset
868 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
869 control = (eword & IXGBE_CONTROL_MASK_NL) >>
870 IXGBE_CONTROL_SHIFT_NL;
871 edata = eword & IXGBE_DATA_MASK_NL;
875 DEBUGOUT1("DELAY: %d MS\n", edata);
879 DEBUGOUT("DATA: \n");
881 hw->eeprom.ops.read(hw, data_offset++,
883 for (i = 0; i < edata; i++) {
884 hw->eeprom.ops.read(hw, data_offset, &eword);
885 hw->phy.ops.write_reg(hw, phy_offset,
886 IXGBE_TWINAX_DEV, eword);
887 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
893 case IXGBE_CONTROL_NL:
895 DEBUGOUT("CONTROL: \n");
896 if (edata == IXGBE_CONTROL_EOL_NL) {
899 } else if (edata == IXGBE_CONTROL_SOL_NL) {
902 DEBUGOUT("Bad control value\n");
903 ret_val = IXGBE_ERR_PHY;
908 DEBUGOUT("Bad control type\n");
909 ret_val = IXGBE_ERR_PHY;
919 * ixgbe_identify_sfp_module_generic - Identifies SFP modules
920 * @hw: pointer to hardware structure
922 * Searches for and identifies the SFP module and assigns appropriate PHY type.
924 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
926 s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
928 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
930 u8 comp_codes_1g = 0;
931 u8 comp_codes_10g = 0;
932 u8 oui_bytes[3] = {0, 0, 0};
937 DEBUGFUNC("ixgbe_identify_sfp_module_generic");
939 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
940 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
941 status = IXGBE_ERR_SFP_NOT_PRESENT;
945 status = hw->phy.ops.read_i2c_eeprom(hw,
946 IXGBE_SFF_IDENTIFIER,
949 if (status == IXGBE_ERR_SWFW_SYNC ||
950 status == IXGBE_ERR_I2C ||
951 status == IXGBE_ERR_SFP_NOT_PRESENT)
952 goto err_read_i2c_eeprom;
954 /* LAN ID is needed for sfp_type determination */
955 hw->mac.ops.set_lan_id(hw);
957 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
958 hw->phy.type = ixgbe_phy_sfp_unsupported;
959 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
961 status = hw->phy.ops.read_i2c_eeprom(hw,
962 IXGBE_SFF_1GBE_COMP_CODES,
965 if (status == IXGBE_ERR_SWFW_SYNC ||
966 status == IXGBE_ERR_I2C ||
967 status == IXGBE_ERR_SFP_NOT_PRESENT)
968 goto err_read_i2c_eeprom;
970 status = hw->phy.ops.read_i2c_eeprom(hw,
971 IXGBE_SFF_10GBE_COMP_CODES,
974 if (status == IXGBE_ERR_SWFW_SYNC ||
975 status == IXGBE_ERR_I2C ||
976 status == IXGBE_ERR_SFP_NOT_PRESENT)
977 goto err_read_i2c_eeprom;
978 status = hw->phy.ops.read_i2c_eeprom(hw,
979 IXGBE_SFF_CABLE_TECHNOLOGY,
982 if (status == IXGBE_ERR_SWFW_SYNC ||
983 status == IXGBE_ERR_I2C ||
984 status == IXGBE_ERR_SFP_NOT_PRESENT)
985 goto err_read_i2c_eeprom;
992 * 3 SFP_DA_CORE0 - 82599-specific
993 * 4 SFP_DA_CORE1 - 82599-specific
994 * 5 SFP_SR/LR_CORE0 - 82599-specific
995 * 6 SFP_SR/LR_CORE1 - 82599-specific
996 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific
997 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific
998 * 9 SFP_1g_cu_CORE0 - 82599-specific
999 * 10 SFP_1g_cu_CORE1 - 82599-specific
1001 if (hw->mac.type == ixgbe_mac_82598EB) {
1002 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1003 hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1004 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1005 hw->phy.sfp_type = ixgbe_sfp_type_sr;
1006 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1007 hw->phy.sfp_type = ixgbe_sfp_type_lr;
1009 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1010 } else if (hw->mac.type == ixgbe_mac_82599EB) {
1011 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1012 if (hw->bus.lan_id == 0)
1014 ixgbe_sfp_type_da_cu_core0;
1017 ixgbe_sfp_type_da_cu_core1;
1018 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1019 hw->phy.ops.read_i2c_eeprom(
1020 hw, IXGBE_SFF_CABLE_SPEC_COMP,
1023 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1024 if (hw->bus.lan_id == 0)
1026 ixgbe_sfp_type_da_act_lmt_core0;
1029 ixgbe_sfp_type_da_act_lmt_core1;
1032 ixgbe_sfp_type_unknown;
1034 } else if (comp_codes_10g &
1035 (IXGBE_SFF_10GBASESR_CAPABLE |
1036 IXGBE_SFF_10GBASELR_CAPABLE)) {
1037 if (hw->bus.lan_id == 0)
1039 ixgbe_sfp_type_srlr_core0;
1042 ixgbe_sfp_type_srlr_core1;
1043 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1044 if (hw->bus.lan_id == 0)
1046 ixgbe_sfp_type_1g_cu_core0;
1049 ixgbe_sfp_type_1g_cu_core1;
1051 hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1055 if (hw->phy.sfp_type != stored_sfp_type)
1056 hw->phy.sfp_setup_needed = TRUE;
1058 /* Determine if the SFP+ PHY is dual speed or not. */
1059 hw->phy.multispeed_fiber = FALSE;
1060 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1061 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1062 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1063 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1064 hw->phy.multispeed_fiber = TRUE;
1066 /* Determine PHY vendor */
1067 if (hw->phy.type != ixgbe_phy_nl) {
1068 hw->phy.id = identifier;
1069 status = hw->phy.ops.read_i2c_eeprom(hw,
1070 IXGBE_SFF_VENDOR_OUI_BYTE0,
1073 if (status == IXGBE_ERR_SWFW_SYNC ||
1074 status == IXGBE_ERR_I2C ||
1075 status == IXGBE_ERR_SFP_NOT_PRESENT)
1076 goto err_read_i2c_eeprom;
1078 status = hw->phy.ops.read_i2c_eeprom(hw,
1079 IXGBE_SFF_VENDOR_OUI_BYTE1,
1082 if (status == IXGBE_ERR_SWFW_SYNC ||
1083 status == IXGBE_ERR_I2C ||
1084 status == IXGBE_ERR_SFP_NOT_PRESENT)
1085 goto err_read_i2c_eeprom;
1087 status = hw->phy.ops.read_i2c_eeprom(hw,
1088 IXGBE_SFF_VENDOR_OUI_BYTE2,
1091 if (status == IXGBE_ERR_SWFW_SYNC ||
1092 status == IXGBE_ERR_I2C ||
1093 status == IXGBE_ERR_SFP_NOT_PRESENT)
1094 goto err_read_i2c_eeprom;
1097 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1098 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1099 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1101 switch (vendor_oui) {
1102 case IXGBE_SFF_VENDOR_OUI_TYCO:
1103 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1105 ixgbe_phy_sfp_passive_tyco;
1107 case IXGBE_SFF_VENDOR_OUI_FTL:
1108 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1109 hw->phy.type = ixgbe_phy_sfp_ftl_active;
1111 hw->phy.type = ixgbe_phy_sfp_ftl;
1113 case IXGBE_SFF_VENDOR_OUI_AVAGO:
1114 hw->phy.type = ixgbe_phy_sfp_avago;
1116 case IXGBE_SFF_VENDOR_OUI_INTEL:
1117 hw->phy.type = ixgbe_phy_sfp_intel;
1120 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1122 ixgbe_phy_sfp_passive_unknown;
1123 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1125 ixgbe_phy_sfp_active_unknown;
1127 hw->phy.type = ixgbe_phy_sfp_unknown;
1132 /* Allow any DA cable vendor */
1133 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1134 IXGBE_SFF_DA_ACTIVE_CABLE)) {
1135 status = IXGBE_SUCCESS;
1139 /* Verify supported 1G SFP modules */
1140 if (comp_codes_10g == 0 &&
1141 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1142 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0)) {
1143 hw->phy.type = ixgbe_phy_sfp_unsupported;
1144 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1148 /* Anything else 82598-based is supported */
1149 if (hw->mac.type == ixgbe_mac_82598EB) {
1150 status = IXGBE_SUCCESS;
1154 ixgbe_get_device_caps(hw, &enforce_sfp);
1155 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1156 !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) ||
1157 (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1))) {
1158 /* Make sure we're a supported PHY type */
1159 if (hw->phy.type == ixgbe_phy_sfp_intel) {
1160 status = IXGBE_SUCCESS;
1162 DEBUGOUT("SFP+ module not supported\n");
1163 hw->phy.type = ixgbe_phy_sfp_unsupported;
1164 status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1167 status = IXGBE_SUCCESS;
1174 err_read_i2c_eeprom:
1175 hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1176 if (hw->phy.type != ixgbe_phy_nl) {
1178 hw->phy.type = ixgbe_phy_unknown;
1180 return IXGBE_ERR_SFP_NOT_PRESENT;
1184 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1185 * @hw: pointer to hardware structure
1186 * @list_offset: offset to the SFP ID list
1187 * @data_offset: offset to the SFP data block
1189 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1190 * so it returns the offsets to the phy init sequence block.
1192 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1197 u16 sfp_type = hw->phy.sfp_type;
1199 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1201 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1202 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1204 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1205 return IXGBE_ERR_SFP_NOT_PRESENT;
1207 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1208 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1209 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1212 * Limiting active cables and 1G Phys must be initialized as
1215 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1216 sfp_type == ixgbe_sfp_type_1g_cu_core0)
1217 sfp_type = ixgbe_sfp_type_srlr_core0;
1218 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1219 sfp_type == ixgbe_sfp_type_1g_cu_core1)
1220 sfp_type = ixgbe_sfp_type_srlr_core1;
1222 /* Read offset to PHY init contents */
1223 hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset);
1225 if ((!*list_offset) || (*list_offset == 0xFFFF))
1226 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1228 /* Shift offset to first ID word */
1232 * Find the matching SFP ID in the EEPROM
1233 * and program the init sequence
1235 hw->eeprom.ops.read(hw, *list_offset, &sfp_id);
1237 while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1238 if (sfp_id == sfp_type) {
1240 hw->eeprom.ops.read(hw, *list_offset, data_offset);
1241 if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1242 DEBUGOUT("SFP+ module not supported\n");
1243 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1248 (*list_offset) += 2;
1249 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1250 return IXGBE_ERR_PHY;
1254 if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1255 DEBUGOUT("No matching SFP+ module found\n");
1256 return IXGBE_ERR_SFP_NOT_SUPPORTED;
1259 return IXGBE_SUCCESS;
1263 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1264 * @hw: pointer to hardware structure
1265 * @byte_offset: EEPROM byte offset to read
1266 * @eeprom_data: value read
1268 * Performs byte read operation to SFP module's EEPROM over I2C interface.
1270 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1273 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1275 return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1276 IXGBE_I2C_EEPROM_DEV_ADDR,
1281 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1282 * @hw: pointer to hardware structure
1283 * @byte_offset: EEPROM byte offset to write
1284 * @eeprom_data: value to write
1286 * Performs byte write operation to SFP module's EEPROM over I2C interface.
1288 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1291 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1293 return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1294 IXGBE_I2C_EEPROM_DEV_ADDR,
1299 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
1300 * @hw: pointer to hardware structure
1301 * @byte_offset: byte offset to read
1304 * Performs byte read operation to SFP module's EEPROM over I2C interface at
1305 * a specified device address.
1307 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1308 u8 dev_addr, u8 *data)
1310 s32 status = IXGBE_SUCCESS;
1317 DEBUGFUNC("ixgbe_read_i2c_byte_generic");
1319 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1320 swfw_mask = IXGBE_GSSR_PHY1_SM;
1322 swfw_mask = IXGBE_GSSR_PHY0_SM;
1325 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
1327 status = IXGBE_ERR_SWFW_SYNC;
1331 ixgbe_i2c_start(hw);
1333 /* Device Address and write indication */
1334 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1335 if (status != IXGBE_SUCCESS)
1338 status = ixgbe_get_i2c_ack(hw);
1339 if (status != IXGBE_SUCCESS)
1342 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1343 if (status != IXGBE_SUCCESS)
1346 status = ixgbe_get_i2c_ack(hw);
1347 if (status != IXGBE_SUCCESS)
1350 ixgbe_i2c_start(hw);
1352 /* Device Address and read indication */
1353 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
1354 if (status != IXGBE_SUCCESS)
1357 status = ixgbe_get_i2c_ack(hw);
1358 if (status != IXGBE_SUCCESS)
1361 status = ixgbe_clock_in_i2c_byte(hw, data);
1362 if (status != IXGBE_SUCCESS)
1365 status = ixgbe_clock_out_i2c_bit(hw, nack);
1366 if (status != IXGBE_SUCCESS)
1373 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1375 ixgbe_i2c_bus_clear(hw);
1377 if (retry < max_retry)
1378 DEBUGOUT("I2C byte read error - Retrying.\n");
1380 DEBUGOUT("I2C byte read error.\n");
1382 } while (retry < max_retry);
1384 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1391 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
1392 * @hw: pointer to hardware structure
1393 * @byte_offset: byte offset to write
1394 * @data: value to write
1396 * Performs byte write operation to SFP module's EEPROM over I2C interface at
1397 * a specified device address.
1399 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
1400 u8 dev_addr, u8 data)
1402 s32 status = IXGBE_SUCCESS;
1407 DEBUGFUNC("ixgbe_write_i2c_byte_generic");
1409 if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1)
1410 swfw_mask = IXGBE_GSSR_PHY1_SM;
1412 swfw_mask = IXGBE_GSSR_PHY0_SM;
1414 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != IXGBE_SUCCESS) {
1415 status = IXGBE_ERR_SWFW_SYNC;
1416 goto write_byte_out;
1420 ixgbe_i2c_start(hw);
1422 status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
1423 if (status != IXGBE_SUCCESS)
1426 status = ixgbe_get_i2c_ack(hw);
1427 if (status != IXGBE_SUCCESS)
1430 status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
1431 if (status != IXGBE_SUCCESS)
1434 status = ixgbe_get_i2c_ack(hw);
1435 if (status != IXGBE_SUCCESS)
1438 status = ixgbe_clock_out_i2c_byte(hw, data);
1439 if (status != IXGBE_SUCCESS)
1442 status = ixgbe_get_i2c_ack(hw);
1443 if (status != IXGBE_SUCCESS)
1450 ixgbe_i2c_bus_clear(hw);
1452 if (retry < max_retry)
1453 DEBUGOUT("I2C byte write error - Retrying.\n");
1455 DEBUGOUT("I2C byte write error.\n");
1456 } while (retry < max_retry);
1458 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
1465 * ixgbe_i2c_start - Sets I2C start condition
1466 * @hw: pointer to hardware structure
1468 * Sets I2C start condition (High -> Low on SDA while SCL is High)
1470 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
1472 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1474 DEBUGFUNC("ixgbe_i2c_start");
1476 /* Start condition must begin with data and clock high */
1477 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1478 ixgbe_raise_i2c_clk(hw, &i2cctl);
1480 /* Setup time for start condition (4.7us) */
1481 usec_delay(IXGBE_I2C_T_SU_STA);
1483 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1485 /* Hold time for start condition (4us) */
1486 usec_delay(IXGBE_I2C_T_HD_STA);
1488 ixgbe_lower_i2c_clk(hw, &i2cctl);
1490 /* Minimum low period of clock is 4.7 us */
1491 usec_delay(IXGBE_I2C_T_LOW);
1496 * ixgbe_i2c_stop - Sets I2C stop condition
1497 * @hw: pointer to hardware structure
1499 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
1501 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
1503 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1505 DEBUGFUNC("ixgbe_i2c_stop");
1507 /* Stop condition must begin with data low and clock high */
1508 ixgbe_set_i2c_data(hw, &i2cctl, 0);
1509 ixgbe_raise_i2c_clk(hw, &i2cctl);
1511 /* Setup time for stop condition (4us) */
1512 usec_delay(IXGBE_I2C_T_SU_STO);
1514 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1516 /* bus free time between stop and start (4.7us)*/
1517 usec_delay(IXGBE_I2C_T_BUF);
1521 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
1522 * @hw: pointer to hardware structure
1523 * @data: data byte to clock in
1525 * Clocks in one byte data via I2C data/clock
1527 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
1532 DEBUGFUNC("ixgbe_clock_in_i2c_byte");
1534 for (i = 7; i >= 0; i--) {
1535 ixgbe_clock_in_i2c_bit(hw, &bit);
1539 return IXGBE_SUCCESS;
1543 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
1544 * @hw: pointer to hardware structure
1545 * @data: data byte clocked out
1547 * Clocks out one byte data via I2C data/clock
1549 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
1551 s32 status = IXGBE_SUCCESS;
1556 DEBUGFUNC("ixgbe_clock_out_i2c_byte");
1558 for (i = 7; i >= 0; i--) {
1559 bit = (data >> i) & 0x1;
1560 status = ixgbe_clock_out_i2c_bit(hw, bit);
1562 if (status != IXGBE_SUCCESS)
1566 /* Release SDA line (set high) */
1567 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1568 i2cctl |= IXGBE_I2C_DATA_OUT;
1569 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl);
1570 IXGBE_WRITE_FLUSH(hw);
1576 * ixgbe_get_i2c_ack - Polls for I2C ACK
1577 * @hw: pointer to hardware structure
1579 * Clocks in/out one bit via I2C data/clock
1581 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
1583 s32 status = IXGBE_SUCCESS;
1585 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1589 DEBUGFUNC("ixgbe_get_i2c_ack");
1591 ixgbe_raise_i2c_clk(hw, &i2cctl);
1594 /* Minimum high period of clock is 4us */
1595 usec_delay(IXGBE_I2C_T_HIGH);
1597 /* Poll for ACK. Note that ACK in I2C spec is
1598 * transition from 1 to 0 */
1599 for (i = 0; i < timeout; i++) {
1600 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1601 ack = ixgbe_get_i2c_data(&i2cctl);
1609 DEBUGOUT("I2C ack was not received.\n");
1610 status = IXGBE_ERR_I2C;
1613 ixgbe_lower_i2c_clk(hw, &i2cctl);
1615 /* Minimum low period of clock is 4.7 us */
1616 usec_delay(IXGBE_I2C_T_LOW);
1622 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
1623 * @hw: pointer to hardware structure
1624 * @data: read data value
1626 * Clocks in one bit via I2C data/clock
1628 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
1630 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1632 DEBUGFUNC("ixgbe_clock_in_i2c_bit");
1634 ixgbe_raise_i2c_clk(hw, &i2cctl);
1636 /* Minimum high period of clock is 4us */
1637 usec_delay(IXGBE_I2C_T_HIGH);
1639 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1640 *data = ixgbe_get_i2c_data(&i2cctl);
1642 ixgbe_lower_i2c_clk(hw, &i2cctl);
1644 /* Minimum low period of clock is 4.7 us */
1645 usec_delay(IXGBE_I2C_T_LOW);
1647 return IXGBE_SUCCESS;
1651 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
1652 * @hw: pointer to hardware structure
1653 * @data: data value to write
1655 * Clocks out one bit via I2C data/clock
1657 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
1660 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1662 DEBUGFUNC("ixgbe_clock_out_i2c_bit");
1664 status = ixgbe_set_i2c_data(hw, &i2cctl, data);
1665 if (status == IXGBE_SUCCESS) {
1666 ixgbe_raise_i2c_clk(hw, &i2cctl);
1668 /* Minimum high period of clock is 4us */
1669 usec_delay(IXGBE_I2C_T_HIGH);
1671 ixgbe_lower_i2c_clk(hw, &i2cctl);
1673 /* Minimum low period of clock is 4.7 us.
1674 * This also takes care of the data hold time.
1676 usec_delay(IXGBE_I2C_T_LOW);
1678 status = IXGBE_ERR_I2C;
1679 DEBUGOUT1("I2C data was not set to %X\n", data);
1685 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock
1686 * @hw: pointer to hardware structure
1687 * @i2cctl: Current value of I2CCTL register
1689 * Raises the I2C clock line '0'->'1'
1691 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1693 DEBUGFUNC("ixgbe_raise_i2c_clk");
1695 *i2cctl |= IXGBE_I2C_CLK_OUT;
1697 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1698 IXGBE_WRITE_FLUSH(hw);
1700 /* SCL rise time (1000ns) */
1701 usec_delay(IXGBE_I2C_T_RISE);
1705 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
1706 * @hw: pointer to hardware structure
1707 * @i2cctl: Current value of I2CCTL register
1709 * Lowers the I2C clock line '1'->'0'
1711 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
1714 DEBUGFUNC("ixgbe_lower_i2c_clk");
1716 *i2cctl &= ~IXGBE_I2C_CLK_OUT;
1718 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1719 IXGBE_WRITE_FLUSH(hw);
1721 /* SCL fall time (300ns) */
1722 usec_delay(IXGBE_I2C_T_FALL);
1726 * ixgbe_set_i2c_data - Sets the I2C data bit
1727 * @hw: pointer to hardware structure
1728 * @i2cctl: Current value of I2CCTL register
1729 * @data: I2C data value (0 or 1) to set
1731 * Sets the I2C data bit
1733 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
1735 s32 status = IXGBE_SUCCESS;
1737 DEBUGFUNC("ixgbe_set_i2c_data");
1740 *i2cctl |= IXGBE_I2C_DATA_OUT;
1742 *i2cctl &= ~IXGBE_I2C_DATA_OUT;
1744 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl);
1745 IXGBE_WRITE_FLUSH(hw);
1747 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
1748 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
1750 /* Verify data was set correctly */
1751 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1752 if (data != ixgbe_get_i2c_data(i2cctl)) {
1753 status = IXGBE_ERR_I2C;
1754 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
1761 * ixgbe_get_i2c_data - Reads the I2C SDA data bit
1762 * @hw: pointer to hardware structure
1763 * @i2cctl: Current value of I2CCTL register
1765 * Returns the I2C data bit value
1767 static bool ixgbe_get_i2c_data(u32 *i2cctl)
1771 DEBUGFUNC("ixgbe_get_i2c_data");
1773 if (*i2cctl & IXGBE_I2C_DATA_IN)
1782 * ixgbe_i2c_bus_clear - Clears the I2C bus
1783 * @hw: pointer to hardware structure
1785 * Clears the I2C bus by sending nine clock pulses.
1786 * Used when data line is stuck low.
1788 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
1790 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL);
1793 DEBUGFUNC("ixgbe_i2c_bus_clear");
1795 ixgbe_i2c_start(hw);
1797 ixgbe_set_i2c_data(hw, &i2cctl, 1);
1799 for (i = 0; i < 9; i++) {
1800 ixgbe_raise_i2c_clk(hw, &i2cctl);
1802 /* Min high period of clock is 4us */
1803 usec_delay(IXGBE_I2C_T_HIGH);
1805 ixgbe_lower_i2c_clk(hw, &i2cctl);
1807 /* Min low period of clock is 4.7us*/
1808 usec_delay(IXGBE_I2C_T_LOW);
1811 ixgbe_i2c_start(hw);
1813 /* Put the i2c bus back to default state */
1818 * ixgbe_tn_check_overtemp - Checks if an overtemp occured.
1819 * @hw: pointer to hardware structure
1821 * Checks if the LASI temp alarm status was triggered due to overtemp
1823 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
1825 s32 status = IXGBE_SUCCESS;
1828 DEBUGFUNC("ixgbe_tn_check_overtemp");
1830 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
1833 /* Check that the LASI temp alarm status was triggered */
1834 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
1835 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
1837 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
1840 status = IXGBE_ERR_OVERTEMP;